Power transformer and method of transforming power

Abstract

A power transformer and a power transformation method. The power transformer includes a power stage circuit, a ramp generation circuit, a calculation circuit and a control circuit. The power stage circuit generates an output signal according to an input signal and a control signal. The ramp generation circuit generates a ramp signal according to the control signal, the input signal and the output signal. The calculation circuit generates a calculation signal according to the output signal and a reference signal. When the power transformer operates in a light load state, the calculation circuit operates in a first mode. When the power transformer operates in a normal state, the calculation circuit operates in a second mode. The control circuit generates the control signal according to the calculation signal and the ramp signal. The control circuit includes a comparison circuit and a control signal generator. The comparison circuit generates a comparison signal according to the calculation signal and the ramp signal. The control signal generator generates the control signal according to the comparison signal. Thus, fast seamless transition can be achieved without the aforementioned additional switching circuit, thereby reducing circuit cost and circuit size.

Description

TECHNICAL FIELD

[0001] Embodiments described herein relate to power conversion technology, and more particularly, to a power transformer and a method of transforming power. BACKGROUND

[0002] With the development of technology, various power transformers have been applied to various circuit systems. In some related arts, a power transformer includes an additional switching circuit. The switching circuit is designed to switch the circuit to an additional low-power-consumption circuit when the power transformer operates in a light load state. However, the additional switching circuit and the additional low-power-consumption circuit will increase the cost and the circuit area. SUMMARY

[0003] Some embodiments of the disclosure relate to a power transformer. The power transformer includes a power stage circuit, a ramp generator circuit, a calculation circuit, and a control circuit. The power stage circuit is configured to generate an output signal according to an input signal and a control signal. The ramp generator circuit is configured to generate a ramp signal according to the control signal, the input signal, and the output signal. The calculation circuit is configured to generate a calculation signal according to the output signal and a reference signal. The calculation circuit operates in a first mode when the power transformer operates in a light load state. The calculation circuit operates in a second mode when the power transformer operates in a normal state. The control circuit is configured to generate the control signal according to the calculation signal and the ramp signal. The control circuit includes a comparison circuit and a control signal generator. The comparison circuit is configured to generate a comparison signal according to the calculation signal and the ramp signal. The control signal generator is configured to generate the control signal according to the comparison signal.

[0004] In some embodiments, the calculation circuit includes an error amplifier, a second resistor, a capacitor, and a first switch. The error amplifier includes a first input terminal and a second output terminal. The first input terminal is configured to receive the reference signal, and the second input terminal is configured to receive the output signal through a first resistor. The second resistor is coupled to the second input terminal. The capacitor is coupled between the second resistor and an output terminal of the error amplifier. The first switch is configured to short circuit both ends of the capacitor. The first switch is turned on by a trigger signal when the power transformer operates in the light load state.

[0005] In some embodiments, the comparison circuit includes a comparator, a first current source, a second current source, and a second switch. The comparator is configured to receive the ramp signal and the calculation signal. The first current source is coupled to the comparator. The second current source is coupled to a ground terminal. The second switch is coupled between the comparator and the second current source. The second switch is turned off by the trigger signal when the power transformer operates in the light load state.

[0006] In some embodiments, the power transformer further includes a detector. The detector is configured to detect a current in the power stage circuit to generate the trigger signal.

[0007] In some embodiments, the detector is a zero-crossing detector.

[0008] In some embodiments, the first switch is turned on by the trigger signal to short circuit two ends of a resistor-capacitor circuit, and the resistor-capacitor circuit is formed by a capacitor and a second resistor connected in series.

[0009] In some embodiments, the calculation circuit further comprises a comparator. The comparator is used to compare the calculation signal and the reference signal to generate the trigger signal.

[0010] In some embodiments, the first switch is turned on by the trigger signal to short circuit two ends of a resistor-capacitor circuit, and the resistor-capacitor circuit is formed by a capacitor and a second resistor connected in series.

[0011] In some embodiments, the calculation circuit comprises an error amplifier, a second resistor, a capacitor, a third resistor, a fourth resistor, and a first switch. The error amplifier comprises a first input end and a second input end, wherein the first input end is used to receive the reference signal. The second resistor is coupled to a ground end. The capacitor is coupled between the second resistor and an output end of the error amplifier. The third resistor is coupled to the second input end and is used to receive the output signal. The fourth resistor is coupled between the second input end and the ground end. The first switch is used to short circuit two ends of the capacitor, wherein the first switch is turned on by a trigger signal when the power transformer operates in a light load state.

[0012] In some embodiments, the comparison circuit comprises a comparator, a first current source, a second current source, and a second switch. The comparator is used to receive the ramp signal and the calculation signal. The first current source is coupled to the comparator. The second current source is coupled to a ground end. The second switch is coupled between the comparator and the second current source. The second switch is turned off by the trigger signal when the power transformer operates in a light load state.

[0013] In some embodiments, the power transformer further comprises a detector. The detector is used to detect a current in the power stage circuit to generate the trigger signal.

[0014] In some embodiments, the first switch is turned on by the trigger signal to short circuit two ends of a resistor-capacitor circuit, and the resistor-capacitor circuit is formed by a capacitor and a second resistor connected in series.

[0015] In some embodiments, the calculation circuit further comprises a comparator. The comparator is used to compare the calculation signal and the reference signal to generate the trigger signal.

[0016] In some embodiments, the first switch is turned on by the trigger signal to short circuit two ends of a resistor-capacitor circuit, and the resistor-capacitor circuit is formed by a capacitor and a second resistor connected in series.

[0017] Some embodiments of the disclosure relate to a power transformer. The power transformer includes a power stage circuit configured to generate an output signal based on an input signal and a control signal; a ramp generation circuit configured to generate a ramp signal based on the control signal, the input signal, and the output signal; a calculation circuit configured to generate a calculation signal based on the output signal and a reference signal, wherein the calculation circuit operates in a first mode when the power transformer operates in a light load state and the calculation circuit operates in a second mode when the power transformer operates in a normal state; and a control circuit configured to generate the control signal based on the calculation signal and the ramp signal. The control circuit includes a comparison circuit configured to generate a comparison signal based on the calculation signal and the ramp signal, and a control signal generator configured to generate the control signal based on the comparison signal. BRIEF DESCRIPTION OF DRAWINGS

[0018] So that the manner in which the above recited and other features and advantages of the present disclosure can be understood in detail, a brief description of the drawings is

[0019] Figure 1 is a schematic diagram of a power transformer in accordance with some embodiments of the disclosure;

[0020] Figure 2 is a schematic diagram of a ramp generation circuit, a calculation circuit, and a control circuit in accordance with some embodiments of the disclosure;

[0021] Figure 3 is a schematic diagram of a ramp generation circuit, a calculation circuit, and a control circuit in accordance with some embodiments of the disclosure;

[0022] Figure 4 is a schematic diagram of a ramp generation circuit, a calculation circuit, and a control circuit in accordance with some embodiments of the disclosure;

[0023] Figure 5 is a schematic diagram of a ramp generation circuit, a calculation circuit, and a control circuit in accordance with some embodiments of the disclosure;

[0024] Figure 6 is a schematic diagram of a ramp generation circuit, a calculation circuit, and a control circuit in accordance with some embodiments of the disclosure;

[0025] Figure 7 is a schematic diagram of a ramp generation circuit, a calculation circuit, and a control circuit in accordance with some embodiments of the disclosure;

[0026] Figure 8This is a schematic diagram illustrating a ramp wave generating circuit, a computing circuit, and a control circuit according to some embodiments of this disclosure;

[0027] Figure 9 This is a schematic diagram illustrating a ramp wave generating circuit, a computing circuit, and a control circuit according to some embodiments of this disclosure; and

[0028] Figure 10 This is a flowchart illustrating a method of coupling to a transformer according to some embodiments of this disclosure.

[0029] [Symbol Explanation]

[0030] 100: Power Transformer

[0031] 110: Power stage circuit

[0032] 111: Filtering circuit

[0033] 112: Detector

[0034] 120, 120A, 120B, 120C, 120D, 120E, 120F, 120G, 120H: Slope wave generation circuit

[0035] 130, 130A, 130B, 130C, 130D, 130E, 130F, 130G, 130H: Calculation circuits

[0036] 131A: Error Amplifier

[0037] 132C: Comparator

[0038] 140, 140A, 140B, 140C, 140D, 140E, 140F, 140G, 140H: Control circuit

[0039] 141, 141A, 141C: Comparator circuits

[0040] 1411A, 1411C: Comparators

[0041] 142, 142A: Control signal generator

[0042] 1000: Transformation Method

[0043] V IN Input signal

[0044] M P :switch

[0045] M N M RMP ,S 1A ,S 1B ,S 1C ,S1D S2: Switch

[0046] L X N RMP :node

[0047] V X :Voltage

[0048] D P :Driver

[0049] D N :Driver

[0050] i L Current

[0051] L S Inductor

[0052] R CO ,R RMP1 ,R RMP2 ,R SUM ,R1,R2,R fb1 ,R fb2 :resistance

[0053] C O C RMP C C :capacitance

[0054] V OUT Output signal

[0055] V COM Comparison signal

[0056] V RMP :Ramp signal

[0057] V C : Calculate signal

[0058] V REF Reference signal

[0059] OUT: Output terminal

[0060] GND: ground terminal

[0061] TRIG1, TRIG2: Trigger signals

[0062] CS: Control signal

[0063] L: Load

[0064] IS1, IS2: Current source

[0065] S1010, S1020, S1030, S1040: Operation Detailed Implementation

[0066] The term "coupled" as used in this article can also refer to "electrical coupling," and the term "connection" can also refer to "electrical connection." "Coupled" and "connection" can also refer to two or more components cooperating or interacting with each other.

[0067] refer to Figure 1 . Figure 1 This is a schematic diagram of a power transformer 100 illustrated in accordance with some embodiments of this disclosure.

[0068] by Figure 1 For example, power transformer 100 includes power stage circuit 110, ramp generation circuit 120, calculation circuit 130, and control circuit 140. Power stage circuit 110 is coupled to ramp generation circuit 120 and calculation circuit 130. Ramp generation circuit 120 and calculation circuit 130 are coupled to control circuit 140. Control circuit 140 is coupled to power stage circuit 110.

[0069] Power stage circuit 110 is used to determine the input signal V IN And the control signal CS from the control circuit 140 generates the output signal V OUT The control signal CS can be a pulse width modulation (PWM) signal. The output signal V... OUT Essentially equal to the input signal V IN The product of the control signal CS's duty cycle (e.g., various percentages). For example, when the control signal CS's duty cycle is 30%, the output signal V... OUT Essentially equal to the input signal V IN The product of 30%.

[0070] by Figure 1 For example, power stage circuit 110 includes switch M P Switch M N Driver D P Driver D N And a filter circuit 111. In some embodiments, the power stage circuit 110 further includes a detector 112.

[0071] Switch M P Receive input signal V IN And the coupled node L X Switch M N Coupled to node L X Between and ground (GND). Driver D P Receives control signal CS and is used to turn switch M on or off according to control signal CS. P Driver D NReceives control signal CS and is used to turn switch M on or off according to control signal CS. N When switch M P On and switch M N At the deadline, at node L X voltage V X In response to input signal V IN Generate. When switch M P Cut off and switch M N When conducting, at node L X voltage V X In response to the generation of ground voltage at the ground terminal GND.

[0072] Filter circuit 111 includes inductor L S Resistance R CO and capacitor C O Current i L Response to node L X voltage V X Flow through inductor L S And the output signal V OUT It originates at the output terminal OUT. The load L is coupled to the output terminal OUT.

[0073] Detector 112 is used to detect nodes located at node L X voltage V X The relevant current generates a trigger signal TRIG1. Detector 112 can be implemented using a zero-crossing detector (ZCD).

[0074] The ramp generation circuit 120 is used to generate ramps based on the control signal CS and the input signal V. IN and output signal V OUT Generate ramp signal V RMP Specifically, the ramp generation circuit 120 generates a ramp based on the control signal CS and the input signal V. IN Generate a triangular wave, and sum the triangular wave and the output signal V. OUT To generate ramp signal V RMP Slope signal V RMP It is transmitted to the control circuit 140.

[0075] The calculation circuit 130 is used to calculate based on the output signal V OUT and reference signal V REF Generate calculation signal V C Calculate signal V CThe signal is transmitted to control circuit 140. When power transformer 100 operates in normal condition, calculation circuit 130 operates in Inductor Current Continuous-Time Conduction Mode (CCM). When power transformer 100 operates under light load, calculation circuit 130 operates in Inductor Current Discontinuous-Time Conduction Mode (DCM). The inductor current discontinuous-time conduction mode is a power-saving mode compared to the continuous-time conduction mode. In other words, calculation circuit 130 can switch between a non-power-saving mode and a power-saving mode. In some embodiments, the mode of calculation circuit 130 is changed based on trigger signal TRIG1 from detector 112. In some embodiments, the mode of calculation circuit 130 is changed based on trigger signal TRIG2 (e.g., ...). Figure 4 The trigger signal TRIG2 in the middle changes.

[0076] The implementation of the ramp generation circuit 120 and the calculation circuit 130 will be described in the following paragraphs.

[0077] Control circuit 140 is used to adjust the ramp signal V from ramp generation circuit 120. RMP And the calculation signal V from the calculation circuit 130 C Generate a control signal CS. Figure 1 For example, control circuit 140 includes comparator circuit 141 and control signal generator 142. The first input of comparator circuit 141 receives a ramp signal V. RMP The second input terminal of the comparator circuit 141 receives the calculation signal V. C Comparator circuit 141 operates based on the ramp signal V. RMP And calculate signal V C Generate comparison signal V COM Specifically, the comparator circuit 141 compares and calculates the signal V. C and ramp signal V RMP When calculating signal V C Greater than the ramp signal V RMP At that time, the comparator circuit 141 outputs a comparator signal V. COM (For example, having a logic value of 1) to drive the control signal generator 142. The control signal generator 142 is based on the comparison signal V. COM A control signal CS is generated and transmitted to the power stage circuit 110. In some embodiments, the control signal generator 142 includes an on-time controller and an AND gate. The on-time controller is based on a comparison signal V. COMGenerates a conduction time control signal, and the AND gate compares the signal V. COM The on-time control signal is used to output the control signal CS.

[0078] refer to Figure 2 . Figure 2 This is a schematic diagram illustrating a ramp wave generating circuit 120A, a calculation circuit 130A, and a control circuit 140A according to some embodiments of this disclosure.

[0079] In some embodiments, Figure 1 The ramp wave generating circuit 120 in the text is implemented using ramp wave generating circuit 120A. Figure 1 The computing circuit 130 in the text is implemented using computing circuit 130A, and Figure 1 The control circuit 140 is implemented using control circuit 140A.

[0080] by Figure 2 For example, the ramp generation circuit 120A includes a switch M. RMP Resistance R RMP1 Resistance R SUM Capacitor C RMP and resistance R RMP2 Switch M RMP Receive input signal V IN It is also controlled by the control signal CS. Resistor R RMP1 Coupling switch M RMP and the oblique wave node N RMP Resistance R SUM Coupled ramp node N RMP And receive output signal V OUT Resistance R RMP2 With capacitor C RMP Series coupled and receiving output signal V OUT Capacitor C RMP Coupled ramp node N RMP Slope signal V RMP Originating at the slope node N RMP .

[0081] The computing circuit 130A includes an error amplifier 131A, resistor R1, resistor R2, and capacitor C. C and switch S 1A The first input terminal of the error amplifier 131A receives the reference signal V. REF Furthermore, the second input terminal of the error amplifier 131A receives the output signal V through resistor R1. OUT Resistor R2 is coupled to the second input terminal of error amplifier 131A. Capacitor C C It is connected in series with resistor R2, and capacitor C CIt is coupled between resistor R2 and the output terminal of error amplifier 131A. Switch S 1A It is coupled in parallel with the capacitor. Switch S 1A Received from Figure 1 The trigger signal TRIG1 of the detector 112 is controlled. For example, when the power transformer 100 is operating under light load, the detector 112 detects the relevant node L. X voltage V X Upon a zero-current event, detector 112 outputs a trigger signal TRIG1 (e.g., with a logic value of 1) to turn on switch S. 1A The conducting switch S 1A Capacitor C can be made C The two ends of the circuit are short-circuited, and the calculation circuit 130A enters a power-saving mode (e.g., inductor current discontinuous time conduction mode). When the power transformer 100 is operating in normal mode, the detector 112 will not detect the zero-current event, and then the detector 112 will output a trigger signal TRIG1 (e.g., with a logic value of 0) to turn off the switch S. 1A Furthermore, the 130A calculation circuit enters a non-power-saving mode (e.g., inductor current continuous-time conduction mode).

[0082] The comparator circuit 141 in the control circuit 140A includes a comparator 1411A, a current source IS1, a current source IS2, and a switch S2. The comparator 1411A receives the ramp signal V from the ramp generation circuit 120A. RMP And the calculation signal V from the computing circuit 130A C Current source IS1 is coupled between comparator 1411A and ground GND. Switch S2 is coupled between comparator 1411A and current source IS2. Current source IS2 is coupled to ground GND. Switch S2 receives current from... Figure 1 The trigger signal TRIG1 of the detector 112 is controlled. For example, when the power transformer is operating under light load, the detector 112 detects the relevant node L. X voltage V X Upon detecting a zero-current event, detector 112 outputs a trigger signal TRIG1 (e.g., with a logic value of 1) to turn off switch S2. Since switch S2 is off, current source IS2 does not supply energy to comparator 1411A, thus saving energy. When power transformer 100 is operating normally, detector 112 does not detect a zero-current event, and then outputs a trigger signal TRIG1 (e.g., with a logic value of 0) to turn on switch S2. Comparator circuit 141A generates a comparison signal V. COM Furthermore, the control signal generator 142A of the control circuit 140A is based on the comparison signal V. COM Generates control signal CS.

[0083] In some related technologies, power transformers include additional switching circuitry. This switching circuitry is designed to switch the circuitry to additional low-power circuitry when the power transformer is operating under light load conditions. However, the additional switching circuitry, along with the additional low-power circuitry, increases cost and circuit area.

[0084] Compared to other related technologies, in this disclosure, the computing circuit 130A can operate in two different modes without additional switching circuitry. The power transformer 100 can utilize the computing circuit 130A to achieve seamless switching between a power-saving mode (e.g., discontinuous-time inductor current conduction mode) and a non-power-saving mode (e.g., continuous-time inductor current conduction mode). For example, due to switch S... 1A Capacitor C can be short-circuited in power-saving mode. C Calculate the signal V at both ends. C The voltage value will not drop excessively. In this case, when the load L changes and the power transformer 100 intends to enter non-power-saving mode, the calculated signal V... C It can be quickly charged to the ramp signal V. RMP The voltage value. Thus, this disclosure enables rapid, seamless switching without additional switching circuitry, reducing circuit cost and size.

[0085] refer to Figure 3 . Figure 3 This is a schematic diagram illustrating a ramp generation circuit 120B, a calculation circuit 130B, and a control circuit 140B according to some embodiments of this disclosure.

[0086] In some embodiments, Figure 1 The ramp wave generating circuit 120 is implemented using ramp wave generating circuit 120B. Figure 1 The computing circuit 130 in the middle is implemented using computing circuit 130B, and Figure 1 The control circuit 140 is implemented using control circuit 140B.

[0087] The ramp generation circuit 120B is similar to Figure 2 The ramp generation circuit 120A and the control circuit 140B are similar to the one in the example. Figure 2 The control circuit is 140A.

[0088] Figure 3 and Figure 2 One of the main differences lies in the capacitance C. C Connected in series with resistor R2 to form a resistive-capacitive (RC) circuit, and the switch S in calculation circuit 130B is... 1B It is coupled in parallel with the resistor-capacitor circuit. When the power transformer 100 operates under light load, the detector 112 detects the relevant node L. X voltage VX Upon a zero-current event, detector 112 outputs a trigger signal TRIG1 (e.g., with a logic value of 1) to turn on switch S. 1B The conducting switch S 1B A resistor-capacitor circuit (i.e., a capacitor C connected in series) can be used. C When the resistor R2 is short-circuited across its terminals, the calculation circuit 130B enters a power-saving mode (e.g., inductor current discontinuous time conduction mode). When the power transformer 100 is operating normally, the detector 112 will not detect zero-current events. The detector 112 then outputs a trigger signal TRIG1 (e.g., with a logic value of 0) to turn off switch S. 1B The computing circuit 130B enters a non-power-saving mode (e.g., inductor current continuous-time conduction mode).

[0089] Switch S 1B Similar to Figure 2 S switch 1A The functions of [the system] are not elaborated here.

[0090] refer to Figure 4 . Figure 4 This is a schematic diagram illustrating a ramp generation circuit 120C, a calculation circuit 130C, and a control circuit 140C according to some embodiments of this disclosure.

[0091] In some embodiments, Figure 1 The ramp wave generating circuit 120 in the text is implemented using ramp wave generating circuit 120C. Figure 1 The computing circuit 130 in the text is implemented using computing circuit 130C, and Figure 1 The control circuit 140 is implemented using control circuit 140C.

[0092] The ramp generation circuit 120C is similar to Figure 2 The ramp wave generation circuit is 120A.

[0093] Figure 4 and Figure 2 One of the main differences is that the computing circuit 130C also includes a comparator 132C. The comparator 132C compares and calculates the signal V. C With reference signal V REF To generate the trigger signal TRIG2. Switch S 1C With capacitor C C It is connected in parallel and controlled by the trigger signal TRIG2. For example, when the power transformer 100 operates under light load, the calculated signal V... C Below the reference signal V REF Furthermore, comparator 132C outputs a trigger signal TRIG2 (e.g., with a logic value of 1) to turn on switch S. 1C The conducting switch S1C Capacitor C can be made C The two ends of the circuit are short-circuited, and the calculation circuit 130C enters a power-saving mode (e.g., inductor current discontinuous time conduction mode). When the power transformer 100 is operating in normal mode, the calculation signal V... C Equal to or greater than the reference signal V REF Furthermore, the comparator 132C outputs a trigger signal TRIG2 (e.g., with a logic value of 0) to turn off switch S. 1C The computing circuit 130C enters a non-power-saving mode (e.g., inductor current continuous-time conduction mode).

[0094] Switch S 1C Similar to Figure 2 S switch 1A The functions of [the system] are not elaborated here.

[0095] in addition, Figure 4 and Figure 2 Another key difference is that the comparator circuit 141C contains only the comparator 1411C. The comparator circuit 141C is not connected to... Figure 2 The current source IS1, current source IS2, and switch S2 work together to output a comparison signal V. COM .

[0096] refer to Figure 5 . Figure 5 This is a schematic diagram illustrating a ramp generation circuit 120D, a calculation circuit 130D, and a control circuit 140D according to some embodiments of this disclosure.

[0097] In some embodiments, Figure 1 The ramp wave generating circuit 120 in the text is implemented using ramp wave generating circuit 120D. Figure 1 The computing circuit 130 in the text is implemented using computing circuit 130D, and Figure 1 The control circuit 140 is implemented using the control circuit 140D.

[0098] The ramp generation circuit 120D is similar to Figure 4 The ramp generation circuit 120C and the control circuit 140D are similar to the one in the example. Figure 4 The control circuit 140C is used in this system.

[0099] Figure 5 and Figure 4 One of the main differences is the capacitance C. C Connected in series with resistor R2 to form a resistive-capacitive (RC) circuit, and the switch S in circuit 130D is calculated. 1D It is connected in parallel with a resistor-capacitor circuit. When calculating signal V... C Below the reference signal V REFAt this time, comparator 132C outputs a trigger signal TRIG2 (e.g., with a logic value of 1) to turn on switch S. 1D The conducting switch S 1D A resistor-capacitor circuit (i.e., a capacitor C connected in series) can be used. C When the resistor R2 is short-circuited across its terminals, the calculation circuit 130D enters a power-saving mode (e.g., discontinuous inductor current conduction mode). When the power transformer 100 is operating normally, the calculation signal V... C Equal to or greater than the reference signal V REF Furthermore, the comparator 132C outputs a trigger signal TRIG2 (e.g., with a logic value of 0) to turn off switch S. 1D The computing circuit 130D enters a non-power-saving mode (e.g., inductor current continuous-time conduction mode).

[0100] Switch S 1D Similar to Figure 3 Switch S 1B Therefore, I will not elaborate further here.

[0101] refer to Figure 6 . Figure 6 This is a schematic diagram illustrating a ramp generation circuit 120E, a calculation circuit 130E, and a control circuit 140E according to some embodiments of this disclosure.

[0102] In some embodiments, Figure 1 The ramp wave generating circuit 120 in the text is implemented using ramp wave generating circuit 120E. Figure 1 The computing circuit 130 in the text is implemented using computing circuit 130E, and Figure 1 The control circuit 140 is implemented using the control circuit 140E.

[0103] The ramp generation circuit 120E is similar to Figure 2 The ramp generation circuit 120A and the control circuit 140E are similar to the one in the example. Figure 2 The control circuit is 140A.

[0104] The computing circuit 130E is similar to Figure 2 The computing circuit in the 130A is used. Figure 6 and Figure 2 One of the main differences is that the computing circuit 130E also includes a resistor R. fb1 and resistance R fb2 Resistance R fb1 replace Figure 2 The resistor R1 in the circuit. In other words, the resistor R... fb1 The second input terminal of the error amplifier 131A is coupled, and the error amplifier 131A passes through the resistor R. fb1 Receive output signal V OUTResistance R fb2 It is coupled between the second input terminal of the error amplifier 131A and ground GND. Resistor R fb1 With resistance R fb2 A voltage divider circuit is formed. This is achieved by designing resistor R. fb1 With resistance R fb2 The resistance value can be adjusted, and the voltage input to the second input terminal of the error amplifier 131A can be changed. For example, the voltage input to the second input terminal of the error amplifier 131A can be adjusted to be lower than the output signal V. OUT This allows the error amplifier 131A to receive a lower voltage.

[0105] in addition, Figure 6 and Figure 2 Another major difference between them is that, Figure 6 The resistor R2 is coupled to ground GND and capacitor C. C between.

[0106] refer to Figure 7 . Figure 7 This is a schematic diagram illustrating a ramp generation circuit 120F, a calculation circuit 130F, and a control circuit 140F according to some embodiments of this disclosure.

[0107] In some embodiments, Figure 1 The ramp wave generating circuit 120 is implemented using ramp wave generating circuit 120F. Figure 1 The computing circuit 130 in the text is implemented using computing circuit 130F, and Figure 1 The control circuit 140 is implemented using the control circuit 140F.

[0108] The 120F ramp generation circuit is similar to Figure 3 The ramp generation circuit 120B and the control circuit 140F are similar to the one in the example. Figure 3 The control circuit 140B is included.

[0109] The computing circuit 130F is similar to Figure 3 The computing circuit 130B in the middle. Figure 7 and Figure 3 One of the main differences is that the computing circuit 130F also includes a resistor R. fb1 and resistance R fb2 Resistance R fb1 replace Figure 3 The resistor R1 in the circuit. In other words, the resistor R... fb1 The second input terminal of the error amplifier 131A is coupled, and the error amplifier 131A passes through the resistor R. fb1 Receive output signal V OUT Resistance R fb2It is coupled between the second input terminal of the error amplifier 131A and the ground terminal GND. Additionally, Figure 7 and Figure 3 Another major difference is that, Figure 7 The resistor R2 is coupled to ground GND and capacitor C. C between.

[0110] refer to Figure 8 . Figure 8 This is a schematic diagram illustrating a ramp generation circuit 120G, a calculation circuit 130G, and a control circuit 140G according to some embodiments of this disclosure.

[0111] In some embodiments, Figure 1 The ramp wave generating circuit 120 in the text is implemented using ramp wave generating circuit 120G. Figure 1 The computing circuit 130 in the text is implemented using computing circuit 130G, and Figure 1 The control circuit 140 is implemented using control circuit 140G.

[0112] The ramp generation circuit 120G is similar to Figure 7 The ramp generation circuit 120F and the control circuit 140G are similar to the one in the example. Figure 7 The control circuit 140F is located within this circuit. Furthermore, Figure 8 The control circuit 140G and Figure 7 One of the main differences between the control circuits 140F and 140G is that the switch S2 in the control circuit 140G is controlled by the trigger signal TRIG2 from the comparator 132C.

[0113] The computing circuit 130G is similar to Figure 4 The computing circuit 130C is used in this system. Figure 8 The computing circuit 130G and Figure 4 One difference between the computing circuits 130C and 130G is that the computing circuit 130G includes a resistor R. fb1 and resistance R fb2 Resistance R fb1 replace Figure 4 The resistor R1 in the circuit. In other words, the resistor R... fb1 The second input terminal of the error amplifier 131A is coupled, and the error amplifier 131A passes through the resistor R. fb1 Receive output signal V OUT Resistance R fb2 It is coupled between the second input terminal of the error amplifier 131A and the ground terminal GND. Additionally, Figure 8 The computing circuit 130G and Figure 4 Another difference between the computing circuits 130C and those in the latter is that, Figure 8 The resistor R2 is coupled to ground GND and capacitor C.C between.

[0114] refer to Figure 9 . Figure 9 This is a schematic diagram illustrating the ramp generation circuit 120H, the calculation circuit 130H, and the control circuit 140H according to some embodiments of this disclosure.

[0115] In some embodiments, Figure 1 The ramp wave generating circuit 120 is implemented using ramp wave generating circuit 120H. Figure 1 The computing circuit 130 in the middle is implemented using computing circuit 130H, and Figure 1 The control circuit 140 is implemented using the control circuit 140H.

[0116] The ramp generation circuit 120H is similar to Figure 8 The ramp generation circuit 120G and the control circuit 140H are similar to the one in the example. Figure 8 The control circuit in the middle is 140G.

[0117] The calculation circuit 130H is similar to Figure 5 The computing circuit 130D in the middle. Figure 9 The computing circuit 130H and Figure 5 One of the main differences between the computing circuits 130D and 130H is that the computing circuit 130H also includes a resistor R. fb1 and resistance R fb2 Resistance R fb1 replace Figure 5 The resistor R1 in the circuit. In other words, the resistor R... fb1 The second input terminal of the error amplifier 131A is coupled, and the error amplifier 131A passes through the resistor R. fb1 Receive output signal V OUT Resistance R fb2 It is coupled between the second input terminal of the error amplifier 131A and the ground terminal GND. Additionally, Figure 9 The computing circuit 130H and Figure 5 Another major difference between the computing circuits of the 130D and those of the 130D is that, Figure 9 The resistor R2 is coupled to ground GND and capacitor C. C between.

[0118] refer to Figure 10 . Figure 10 This is a flowchart illustrating a transformer method 1000 coupled to some embodiments of this disclosure. Figure 10 For example, transformer method 1000 includes operation S1010, operation S1020, operation S1030 and operation S1040.

[0119] In some embodiments, the transformer method 1000 is applied to Figure 1 The power transformer 100 is described herein, but this disclosure is not limited thereto. For ease of understanding, the transformer method 1000 will be paired with... Figure 1 The power transformer 100 in the text is described.

[0120] During operation S1010, the power stage circuit 110 operates according to the input signal V. IN And the control signal CS generates the output signal V OUT As mentioned earlier, the output signal V OUT Essentially equal to the input signal V IN The product of the duty cycle of the control signal CS.

[0121] During operation S1020, the ramp generation circuit 120 operates based on the control signal CS and the input signal V. IN and output signal V OUT Generate ramp signal V RMP The ramp wave generating circuit 120 can utilize... Figure 2 The slope wave generation circuit 120A is used to implement this, but this disclosure is not limited to it.

[0122] During operation S1030, the calculation circuit 130 calculates based on the output signal V. OUT and reference signal V REF Generate calculation signal V C When the power transformer 100 operates under light load, the calculation circuit 130 can operate in the discontinuous inductor current conduction mode, and when the power transformer 100 operates under normal conditions, the calculation circuit 130 can operate in the continuous inductor current conduction mode.

[0123] In operation S1040, control circuit 140 calculates the signal V. C and ramp signal V RMP A control signal CS is generated. In some embodiments, the comparator circuit 141 calculates the signal V. C and ramp signal V RMP Generate comparison signal V COM And the control signal generator 142 is based on the comparison signal V COM Generates control signal CS.

[0124] In summary, this disclosure enables fast, seamless switching without the aforementioned additional switching circuitry, thereby reducing circuit cost and size.

[0125] Although this disclosure has been described above with reference to embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the scope defined in the appended claims.

Claims

1. A power transformer, characterized in that, Include: A power stage circuit for generating an output signal based on an input signal and a control signal; A ramp generation circuit is used to generate a ramp signal based on the control signal, the input signal and the output signal; A computing circuit for generating a computing signal based on the output signal and a reference signal, wherein the computing circuit operates in a first mode when the power transformer operates in a light-load state, and in a second mode when the power transformer operates in a normal state; and A control circuit for generating the control signal based on the calculated signal and the ramp signal, wherein the control circuit includes: A comparator circuit for generating a comparison signal based on the calculated signal and the ramp signal; and A control signal generator is used to generate the control signal based on the comparison signal. The comparator circuit includes: A comparator is used to receive the ramp signal and the calculated signal; A first current source is coupled to the comparator; A second current source is coupled to a ground terminal; as well as A first switch is coupled between the comparator and the second current source, wherein when the power transformer operates in the light-load state, the first switch is turned off by a trigger signal generated by a detector or a comparator.

2. The power transformer as described in claim 1, characterized in that, The computing circuit includes: An error amplifier includes a first input terminal and a second input terminal, wherein the first input terminal is used to receive the reference signal, and the second input terminal is used to receive the output signal through a first resistor; A second resistor is connected to the second input terminal; A capacitor is coupled between the second resistor and an output terminal of the error amplifier; and A second switch is used to short-circuit the two ends of the capacitor, wherein the second switch is turned on by the trigger signal when the power transformer is operating in the light load state.

3. The power transformer as described in claim 2, characterized in that, Also includes: The detector is used to detect a current in the power stage circuit to generate the trigger signal.

4. The power transformer as described in claim 3, characterized in that, The detector is a zero-crossing detector.

5. The power transformer as described in claim 3, characterized in that, The second switch is turned on by the trigger signal to short-circuit the two ends of a resistor-capacitor circuit, and the resistor-capacitor circuit is formed by the capacitor and the second resistor connected in series.

6. The power transformer as described in claim 1, characterized in that, The computing circuit includes: An error amplifier includes a first input terminal and a second input terminal, wherein the first input terminal is used to receive the reference signal; A first resistor is coupled to a ground terminal; A capacitor is coupled between the first resistor and an output terminal of the error amplifier; A second resistor is coupled to the second input terminal and used to receive the output signal; A third resistor is coupled between the second input terminal and the ground terminal; as well as A second switch is used to short-circuit the two ends of the capacitor, wherein the second switch is turned on by the trigger signal when the power transformer is operating in the light load state.

7. The power transformer as described in claim 6, characterized in that, Also includes: The detector is used to detect a current in the power stage circuit to generate the trigger signal.

8. The power transformer as described in claim 7, characterized in that, The second switch is turned on by the trigger signal to short-circuit the two ends of a resistor-capacitor circuit, and the resistor-capacitor circuit is formed by the capacitor and the first resistor connected in series.

9. The power transformer as described in claim 6, characterized in that, The computing circuit also includes the comparator. The comparator is used to compare the calculated signal and the reference signal to generate the trigger signal.

10. The power transformer as described in claim 9, characterized in that, The second switch is turned on by the trigger signal to short-circuit the two ends of a resistor-capacitor circuit, and the resistor-capacitor circuit is formed by the capacitor and the second resistor connected in series.

11. A transformer method, characterized in that, Include: An output signal is generated by a power stage circuit based on an input signal and a control signal. A ramp signal is generated by a ramp generation circuit based on the control signal, the input signal, and the output signal. A calculation circuit generates a calculation signal based on the output signal and a reference signal, wherein the calculation circuit operates in a first mode when the power transformer operates in a light-load state, and in a second mode when the power transformer operates in a normal state; and The control signal is generated by a control circuit based on the calculated signal and the ramp signal, and includes: A comparison signal is generated by a comparison circuit in the control circuit based on the calculated signal and the ramp signal; and The control signal is generated by a control signal generator in the control circuit based on the comparison signal. The comparator circuit includes: A comparator is used to receive the ramp signal and the calculated signal; A first current source is coupled to the comparator; A second current source is coupled to a ground terminal; as well as A first switch is coupled between the comparator and the second current source, wherein when the power transformer operates in the light-load state, the first switch is turned off by a trigger signal generated by a detector or a comparator.

12. A power transformer, characterized in that, Include: A power stage circuit for generating an output signal based on an input signal and a control signal; A ramp generation circuit is used to generate a ramp signal based on the control signal, the input signal and the output signal; A computing circuit for generating a computing signal based on the output signal and a reference signal, wherein the computing circuit operates in a first mode when the power transformer operates in a light-load state, and operates in a second mode when the power transformer operates in a normal state, wherein the computing circuit includes: An error amplifier includes a first input terminal and a second input terminal, wherein the first input terminal is used to receive the reference signal, and the second input terminal is used to receive the output signal through a first resistor; A second resistor; A capacitor, coupled in series with the second resistor, is connected between the second input terminal and an output terminal of the error amplifier; and A first switch for short-circuiting the capacitor, wherein when the power transformer operates under light load conditions, the first switch is activated by a trigger signal generated by a detector or a comparator; and A control circuit for generating the control signal based on the calculated signal and the ramp signal, wherein the control circuit includes: A comparator circuit for generating a comparison signal based on the calculated signal and the ramp signal; and A control signal generator is used to generate the control signal based on the comparison signal.

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