Radio frequency silicon on insulator structures with superior performance, stability and manufacturability

Abstract

The present application relates to radio frequency silicon on insulator structures with superior performance, stability and manufacturability. A semiconductor-on-insulator (e.g., silicon-on-insulator) structure with superior radio frequency device performance and a method of making such a structure are provided by utilizing single crystal silicon handle wafers sliced from float zone grown single crystal silicon ingots.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of Chinese Patent Application No. 201980044762.2, filed on July 11, 2019, entitled "Radio Frequency Silicon on an Insulator Structure with Superior Performance, Stability and Manufacturability".

[0003] Cross-reference of related applications

[0004] This application claims priority to U.S. Provisional Application No. 62 / 697,474, filed July 13, 2018, the disclosures of which are incorporated herein by reference as if fully expressed. Technical Field

[0005] This invention generally relates to the field of semiconductor wafer manufacturing. More specifically, this invention relates to a structure for fabricating a semiconductor-on-insulator (e.g., silicon-on-insulator) and a method for fabricating a semiconductor-on-insulator structure having superior radio frequency device performance. Background Technology

[0006] Semiconductor wafers are typically fabricated from single-crystal ingots (e.g., silicon ingots) that are trimmed and polished to have one or more flat edges or indentations for proper wafer orientation in subsequent processes. The ingot is then sliced ​​into individual wafers. While reference is made herein to semiconductor wafers constructed from silicon, other materials can be used to fabricate semiconductor wafers, such as germanium, silicon carbide, silicon-germanium, gallium arsenide, and other alloys of group III and V elements (e.g., gallium nitride or indium phosphide), or alloys of group II and VI elements (e.g., cadmium sulfide or zinc oxide).

[0007] Semiconductor wafers (e.g., silicon wafers) can be used in the fabrication of composite layer structures. Composite layer structures (e.g., semiconductor-on-insulator, and more specifically, silicon-on-insulator (SOI) structures) typically include a disposal wafer or layer, a device layer, and an insulating (i.e., dielectric) film (typically an oxide layer) between the disposal layer and the device layer. Typically, the thickness of the device layer is between 0.01 and 20 micrometers, for example, between 0.05 and 20 micrometers. Thick-film device layers may have a device layer thickness between about 1.5 micrometers and about 20 micrometers. Thin-film device layers may have a thickness between about 0.01 micrometers and about 0.20 micrometers. Generally, composite layer structures, such as silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and silicon-on-quartz, are created by placing two wafers in close contact, thereby initiating bonding through van der Waals forces, hydrogen bonding, or both, followed by heat treatment to strengthen the bonding. Annealing can convert terminal silanol groups into siloxane bonds between the two interfaces, thereby strengthening the bonding.

[0008] Following thermal annealing, the bonded structure undergoes further processing to remove most of the donor wafer to achieve layer transfer. For example, wafer thinning techniques (such as etching or polishing), commonly referred to as bonded and etched SOI (i.e., BESOI) or bonded and polished SOI (i.e., BGSOI), can be used, in which the silicon wafer is bound to a treatment wafer and then slowly etched away until only a thin silicon layer remains on the treatment wafer. See, for example, U.S. Patent No. 5,189,500, the disclosure of which is incorporated herein by reference as if fully described. This method is time-consuming and expensive, wastes one portion of the substrate, and typically does not produce suitable thickness uniformity for layers thinner than a few micrometers.

[0009] Another common method for achieving layer transfer utilizes hydrogen implantation followed by thermally induced layer splitting. Microparticles (atoms or ionized atoms, such as hydrogen atoms or a combination of hydrogen and helium atoms) are implanted at a specified depth below the front surface of the donor wafer. The implanted microparticles form a cleavage surface in the donor wafer at the specified depth at which they are implanted. The surface of the donor wafer is cleaned to remove organic compounds or other contaminants, such as boron compounds and any other particulate matter, deposited on the wafer during the implantation process.

[0010] Next, the front surface of the donor wafer is bonded to the treatment wafer via a hydrophilic bonding process to form a bonded wafer. Prior to bonding, the donor wafer and / or treatment wafer are activated by exposing the wafer surfaces to a plasma containing (for example) oxygen or nitrogen. Exposure to plasma modifies the surface structure in a process commonly referred to as surface activation, which makes the surfaces of one or both of the donor wafer and treatment wafer hydrophilic. The wafer surface can be additionally chemically activated by a wet treatment (e.g., SC1 cleaning). Wet treatment and plasma activation can occur in either order, or the wafer may undergo only one treatment. The wafers are then pressed together, forming a bond therebetween. Due to van der Waals forces, this bond is relatively weak and must be strengthened before further processing can occur.

[0011] In some processes, the hydrophilic bonding between the donor wafer and the treatment wafer (i.e., the bonding wafers) is strengthened by heating or annealing the bonding wafer pair. In some processes, wafer bonding can occur at low temperatures, for example, between approximately 300°C and 500°C. Lower bonding temperatures reduce the bridging layer of adsorbed water vapor on the surfaces and increase the density of hydrogen bonds between silanol groups on the surface of each wafer. In some processes, wafer bonding can occur at high temperatures, for example, between approximately 800°C and 1100°C. Higher temperatures lead to the formation of covalent bonds between the adjacent surfaces of the donor wafer and the treatment wafer (e.g., converting silanol hydrogen bonds into covalent siloxane bonds), thus strengthening the bonding between the donor wafer and the treatment wafer. During the heating or annealing of the bonding wafers, the microparticles previously implanted in the donor wafer weaken the cleavage surface.

[0012] Next, a portion of the donor wafer is separated from the bonded wafer along the cleaving surface (i.e., cleaved) to form an SOI wafer. Cleaving can be performed by placing the bonded wafer in a holder, wherein a mechanical force is applied perpendicular to the opposite side of the bonded wafer to pull the portion of the donor wafer away from the bonded wafer. According to some methods, a suction cup is used to apply the mechanical force. Separation of the portion of the donor wafer is initiated by applying a mechanical force at the edge of the bonded wafer at the cleaving surface to initiate the propagation of a crack along the cleaving surface. Then, the mechanical force applied by the suction cup pulls the portion of the donor wafer from the bonded wafer, thus forming the SOI wafer.

[0013] According to other methods, the bonding pair can alternatively be subjected to high temperatures for a short period of time to separate a portion of the donor wafer from the bonding wafer. Exposure to high temperatures causes cracks to initiate and propagate along the cleavage plane, thus separating a portion of the donor wafer. Cracks are attributed to the formation of voids from implanted ions grown via Oswald curing. The voids are filled with hydrogen and helium. The voids become a thin plate. Pressurized gas in the thin plate propagates microcavities and microcracks, which weaken the silicon on the implanted surface. If annealing is stopped at the appropriate time, the weakened bonding wafer can be cleaved by a mechanical process. However, if heat treatment is continued for a longer duration and / or at higher temperatures, the microcracks propagate to the point where all the cracks merge along the cleavage plane, thus separating a portion of the donor wafer. This method allows for better uniformity of the transfer layer and allows for the recycling of the donor wafer, but typically requires heating the implanted and bonding pairs to temperatures close to 500°C.

[0014] Using high-resistivity semiconductor-on-insulator (STI) wafers in RF-related devices (such as antenna switches) offers advantages over conventional substrates in terms of cost and integration. While the use of substrate wafers with high resistivity is necessary but not sufficient to reduce parasitic power losses and minimize inherent harmonic distortion when using conductive substrates in high-frequency applications, it is not always sufficient. Accordingly, the resistivity of wafers used in RF devices is typically greater than about 500 ohm-cm. (See now for reference...) Figure 1 The silicon structure 2 on the insulating layer includes a silicon wafer 4 with extremely high resistivity, a buried oxide (BOX) layer 6, and a silicon device layer 10. This substrate tends to form a highly conductive charge reversal or accumulation layer 12 at the BOX / disposal interface, leading to the generation of free carriers (electrons or holes). When the device operates at RF frequencies, this reduces the effective resistivity of the substrate and causes parasitic power losses and device nonlinearity. These reversal / accumulation layers can be attributed to the fixed charge of the BOX, the charge trapped by the oxide, the charge trapped at the interface, and even the DC bias applied to the device itself.

[0015] Therefore, a method is needed to suppress the formation of any induced inversion or accumulation layers, thereby maintaining the high resistivity of the substrate even in very close surface regions. It is known that a high-resistivity treatment layer between the substrate and the buried oxide (BOX) can improve the performance of RF devices fabricated using SOI wafers. Several methods have been proposed to form such high interface trapping layers. For example, see below. Figure 2 One method for generating a semiconductor-on-insulator multilayer structure 20 (e.g., silicon-on-insulator, or SOI) with a well-rich layer for RF device applications is based on a stack of undoped polysilicon film 28 deposited on a silicon substrate 22 having high resistivity, followed by the formation of an oxide layer (e.g., a buried oxide layer 24) and a top silicon layer 26 thereon. The polysilicon layer 28 acts as a high defect rate layer between the silicon substrate 22 and the buried oxide layer 24. See also Figure 2 This is depicted as a polycrystalline silicon film serving as a well-rich layer 28 between a high-resistivity substrate 22 and a buried oxide layer 24 in a silicon multilayer structure 20 on an insulating layer. An alternative approach is to implant heavy ions to create a near-surface damage layer. For example, the device of a radio frequency device is integrated into the top silicon layer 26.

[0016] Academic research has demonstrated that the polysilicon layer between the oxide and the substrate improves device isolation, reduces transmission line loss, and decreases harmonic distortion. For example, see: HS Gamble et al., “Low-loss CPW lines on surface stabilized high resistivity silicon,” Microwave Guided Wave Lett., 9(10), pp. 395–397, 1999; D. Lederer, R. Lobet, and J.-P. Raskin, “Enhanced high resistivity SOI wafers for RF applications,” IEEE Intl. SOI Conf., pp. 46–47, 2004; D. Lederer and J.-P. Raskin, “New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increased substrate.” "Resistivity", IEEE Electron Device Letters, Vol. 26, Chapter 11, pp. 805-807, 2005; D. Lederer, B. Aspar, C. Laghaé and J.-P. Raskin, "Performance of RF passive structures and SOI MOSFETs transferred on a passivated HR SOI substrate", IEEE International SOI Conference, pp. 29-30, 2006; and Daniel C. Krett.Kerret et al., “Identification of RF harmonic distortion on Si substrates and its reduction using a trap-rich layer,” Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008 (EEE Topical Meeting), pp. 151-154, 2008. Summary of the Invention

[0017] In simple terms, the present invention relates to a multilayer structure comprising: a monocrystalline silicon wafer processing substrate including two main, generally parallel surfaces (one of which is a front surface of the monocrystalline silicon wafer processing substrate and the other is a rear surface of the monocrystalline silicon wafer processing substrate), a circumferential edge connecting the front and rear surfaces of the monocrystalline silicon wafer processing substrate, and a central plane of the monocrystalline silicon wafer processing substrate between the front and rear surfaces of the monocrystalline silicon wafer processing substrate, wherein the monocrystalline silicon wafer processing substrate has a bulk resistivity of at least about 5000 ohms-cm and less than about 1×10⁻⁶ ohms-cm. 16 atoms / cm 3 interstitial oxygen concentration, and at least about 1×10 13 atoms / cm 3 The nitrogen concentration; a well-rich layer that is in contact with the front surface interface of the single-crystal silicon wafer processing substrate; a dielectric layer that is in contact with the well-rich layer; and a single-crystal semiconductor device layer that is in contact with the dielectric layer. Attached Figure Description

[0018] Figure 1 It is a depiction of a silicon wafer on an insulating layer including a high resistivity substrate and a buried oxide layer.

[0019] Figure 2 This is a description of a silicon-on-insulator wafer based on existing technology. The SOI wafer includes a polycrystalline silicon well-rich layer between a high-resistivity substrate and a buried oxide layer.

[0020] Figure 3 It is a graph depicting the harmonic distortion as a function of the substrate resistivity in an HR-SOI structure employing a well-rich layer.

[0021] Figure 4 It is a graph depicting the resistivity depth distribution of wafers after SOI processing with a rich well layer and wafers after Chuklaski growth.

[0022] Figure 5 This is a graph depicting the average resistivity of the first 90 micrometers below the BOX / processing interface of a floating region grown wafer after SOI processing with a rich well layer.

[0023] Figure 6 It is a graph depicting and comparing the sliding windows of SOI multilayer structures fabricated using either the floating zone method or the Chuklaski method on the treated substrate.

[0024] Figure 7 It is a graph depicting the resistivity of SOI multilayer structures fabricated using the floating zone method under different annealing conditions.

[0025] Figure 8 This is a graph depicting the harmonic distortion (HD2) of an SOI multilayer structure using the floating zone method relative to a pin-manufactured substrate compared to the harmonic distortion (HD2) of an SOI multilayer structure using the Chuklaski method relative to a pin-manufactured substrate. Detailed Implementation

[0026] According to the present invention, a method and a structure are provided for generating a semiconductor-on-insulator (e.g., silicon-on-insulator) structure that achieves superior performance, stability, and manufacturability of a radio frequency (RF) device. The present invention integrates a high resistivity (e.g., extremely high resistivity or ultra-high resistivity) floating zone (FZ) silicon-based wafer (processing wafer) and a well-rich layer into a semiconductor-on-insulator (e.g., silicon-on-insulator) structure.

[0027] Radio frequency (RF) chip design significantly benefits from higher substrate resistivity levels. Utilizing higher resistivity silicon substrates enables improvements in the quality factor of passive components (e.g., inductors and capacitors), reduced transmission line attenuation, and substrate electrical isolation between integrated digital, RF, and analog components. The industry standard is a substrate resistivity exceeding 1,000 ohms-cm, with even higher resistivity preferred. Integrating high-resistivity substrates into semiconductor-on-insulator (HRSOI) structures further improves RF capabilities by providing preferred device isolation, reduced conductive coupling to the substrate wafer, and lower junction capacitance.

[0028] Growing ultra-high resistivity Chuklaski (CZ) crystals to resistivity values ​​greater than 7,500 ohm-cm presents significant challenges. Due to the significantly reduced concentration of added electroactive dopants, extra emphasis must be placed on controlling dopants (e.g., boron and phosphorus) introduced from all raw materials and components used in the CZ crystal pulling machine. These materials and components include the polycrystalline silicon source material and the quartz crucible. Furthermore, the extremely low dopant level in the melt makes controlling the mass transfer of dopants to the boundary layer at the melt-solid interface and subsequently through the boundary layer crucial for achieving acceptable radial resistivity variations. Another key challenge in growing high-resistivity Chuklaski silicon ingots is controlling the behavior of interstitial oxygen incorporated during crystal growth. The interstitial oxygen concentration in Chuklaski-grown silicon is typically greater than 5 × 10⁻⁶. 17 atoms / cm 3 (10PPMA new - ASTM), for example, up to about 1×10 18 atoms / cm 3 (20 PPMA new - ASTM). The source of this interstitial oxygen is the dissolution of SiO2 from the crucible during crystal growth. In high resistivity CZ silicon, oxygen can be controlled to approximately 5 PPMA (2.5 × 10⁻⁶). 17 atoms / cm 3 ) range and lower, for example, about 2 PPMA (1×10 17 atoms / cm 3 Approximately 3 PPMA (1.5 × 10⁻⁶) 17 atoms / cm 3 ), and approximately 4 PPMA (2 × 10⁻⁶) 17 atoms / cm 3However, even at low concentrations, interstitial oxygen can aggregate into electrically active thermal donors that are strongly dependent on both the interstitial oxygen concentration and the annealing time / temperature in the range of 350°C to 500°C. At aggregation levels greater than four oxygen atoms, the thermal donors become electrically active, thus acting as dual donors. The formation of such donors is maximized at approximately 450°C and subsequently decays, and they can dissociate upon annealing at temperatures above approximately 550°C, returning to an electrically inactive state. However, at longer annealing times and higher annealing temperatures (e.g., in the range of 550°C to 850°C), so-called new thermal donors can form. Peak new thermal donor formation occurs at temperatures from 750°C to 800°C. We have recently discovered another class of excess donors in high-resistivity silicon subjected to high-temperature heat treatment. Fast-diffusion species introduced into the silicon wafer during extremely high-T annealing and quenched during wafer cooling have not yet been identified. Upon subsequent heating to the range of 450°C to 650°C, these species rapidly recombine with interstitial oxygen in the wafer to form electroactive "excess donors." These excess donors will dissociate upon heating to above approximately 1050°C to 1100°C. Oxythermal dual donors, new donors, and excess thermal donors enable electron conduction, which can alter the resistivity and type of the wafer depending on the number of donors generated relative to the background carrier concentration of the wafer. In p-type silicon, thermal donors increase the resistivity of the wafer until the thermal donor concentration exceeds the p-type carrier concentration, at which point the wafer transforms into n-type. Subsequently, further thermal donor generation will result in increasingly lower resistivity in the n-type wafer. Changes in resistivity during or at the end of the device process can disrupt resistivity-sensitive processes and lead to device performance degradation. Thermal donors can theoretically be annihilated by high-T annealing (greater than about 550°C for thermal double donors, and between about 1050°C and about 1100°C for new and excess donors). However, in practice, most of these donors form during low-temperature annealing steps (which can occur at about 450°C) that occur later in the integrated circuit manufacturing process after metallization (in the "back-end process, BEOL"). Once the metal is deposited, the wafer cannot be heated to T values ​​above about 500°C, therefore the thermal donor species formed in BEOL cannot be annihilated. While thermal donors formed in the 350°C to 500°C range can be eliminated by short-duration, high-temperature annealing, the presence of excess thermal donors becomes particularly noteworthy for high-resistivity silicon with resistivity greater than 4000 ohms-cm, and is significant for materials with resistivity greater than 7500 ohms-cm. In such materials, the dopant concentration can be 1.8 × 10⁻⁶. 12 / cm 3 (p-type) or N d <5×10 11 / cm 3 (n-type). For comparison, the excess heat donor concentration can be approximately 1 × 10⁻⁶ for materials annealed at temperatures between approximately 1100°C and 1125°C. 12 / cm 3 Excessive application of the additive reduces the amount to as low as 1×10⁻⁶ for materials annealed at approximately 1000°C. 11 / cm 3 Given the comparable concentrations of doped materials (e.g., boron, arsenic, phosphorus) and the concentration of excess thermal donors, materials designated as high resistivity may suffer from resistivity variability and even a significant switch from p-type to n-type.

[0029] Floating zone (FZ) silicon is an ultra-high purity alternative to CZ silicon. FZ can be fabricated at resistivity levels greater than 5,000 ohms-cm, greater than 7,500 ohms-cm, even greater than 10,000 ohms-cm, or even greater than 20,000 ohms-cm. The floating zone process minimizes the introduction of oxygen into the grown single crystal and advantageously minimizes the formation of oxygen-thermal double donors, new thermal donors, and excess thermal donors. The accompanying reduction in axial and radial resistivity variability in the ingot and the wafers sliced ​​from it, associated with thermal donor formation, is minimized. This improves both device performance and resistivity stability.

[0030] HRSOI wafers also experience parasitic conduction at the interface between the buried oxide (BOX) layer and the high-resistivity substrate, which can extend more than 10 micrometers into the underlying high-resistivity substrate. This is caused by the combination of normal oxide charges in the BOX and the extremely low doping concentration of the substrate. Figure 1 The parasitic surface conduction effect (referred to as PSC in the literature) shown in the figure results in a low effective substrate resistivity and increases RF loss, substrate nonlinearity, and crosstalk. A polycrystalline silicon layer 28 (reference 28) including a well-rich layer is used. Figure 2 The parasitic conductive layer 12 is placed between the BOX layer 24 and the high resistivity substrate 22 (reference). Figure 1 This is achieved by trapping free carriers attracted to the BOX / substrate interface, thereby suppressing the formation of accumulation or inversion layers. When the well-rich layer is combined with a stable floating-region silicon-processed wafer having a resistivity greater than 5,000 ohms-cm, greater than 7,500 ohms-cm, greater than 10,000 ohms-cm, greater than 20,000 ohms-cm, or greater than 30,000 ohms-cm, superior RF performance can be achieved, such as second harmonic distortion or HD2 values ​​better than -80 dBm, better than -90 dBm, better than -100 dBm, or better than -110 dBm. See also Figure 3 This describes the harmonic distortion as a function of the substrate resistivity in an HR-SOI structure employing a well-rich layer. As shown, higher resistivity wafers exhibit a preferred HD2 value. More specifically, SOI structures with floating-area treated substrates having resistivity values ​​greater than 20,000 ohms-cm or greater than 30,000 ohms-cm can achieve second harmonic distortion or HD2 values ​​better than -100 dBm, or even better than -110 dBm.

[0031] The use of floating zone (FZ) wafers aims to address several issues: 1) providing a manufacturable crystal growth path for resistivity target levels greater than 5,000 ohms-cm, greater than 7,500 ohms-cm, greater than 10,000 ohms-cm, greater than 20,000 ohms-cm, or greater than 30,000 ohms-cm, achieving improved RF performance when coupled with a well-rich layer; and 2) having an oxygen content below the detection limit, which reduces and eliminates the formation of electroactive thermal donors and excess thermal donors, thus preventing resistivity shifts that could degrade RF electrical performance and interfere with wafer processing in the device manufacturing line. Floating zone silicon is grown via vertical zone melting / refining of a high-purity polycrystalline bar. A single crystal is placed at one end of the bar to initiate single-crystal growth. The process avoids the use of a containment container, which significantly reduces the introduction of oxygen-containing impurities. Eliminating oxygen effects, such as those resulting from thermal donor formation, is necessary in ultra-high resistivity silicon. Nitrogen is typically intentionally added during FZ growth to control point defect formation and improve mechanical strength. The doping level and dopant type of ultra-high resistivity FZ depend on the purity of the polycrystalline source rod.

[0032] I. Floating Area Processing Chip

[0033] According to the present invention, wafers from single-crystal silicon ingot slices grown by the floating zone method are integrated as high resistivity treatment structures into structures having Figure 2 The structure shown is a semiconductor-on-insulator (e.g., silicon-on-insulator) multilayer structure 20. That is, the semiconductor-on-insulator (e.g., silicon-on-insulator) multilayer structure 20 includes a floating region high resistivity treatment substrate (e.g., semiconductor treatment substrate 22) (e.g., a wafer), a polysilicon layer 28 including a well-rich layer, a dielectric layer 24, and a device layer 26.

[0034] The substrate used in this invention comprises a semiconductor processing substrate (e.g., a single-crystal semiconductor processing wafer) and a semiconductor donor substrate (e.g., a single-crystal semiconductor donor wafer). The semiconductor device layer 26 in the semiconductor-on-insulator multilayer structure 20 is derived from the single-crystal semiconductor donor wafer. The semiconductor device layer 26 can be transferred onto the semiconductor processing substrate 22 by wafer thinning techniques (e.g., etching the semiconductor donor substrate) or by cleaving the semiconductor donor substrate, including a damaged plane.

[0035] Generally, single-crystal semiconductor processing wafers and single-crystal semiconductor donor wafers comprise two main, generally parallel surfaces. One of the parallel surfaces is the front surface of the substrate, and the other is the rear surface of the substrate. The substrate includes a circumferential edge connecting the front and rear surfaces, a main body region between the front and rear surfaces, and a central plane between the front and rear surfaces. The substrate additionally includes a virtual central axis perpendicular to the central plane and a radial length extending from the central axis to the circumferential edge. Furthermore, because semiconductor substrates (e.g., silicon wafers) typically have some total thickness variation (TTV), warpage, and bowing, the midpoint between every point on the front surface and every point on the rear surface may not fall precisely in the plane. However, as a practical matter, TTV, warpage, and bowing are usually so small that the approximate midpoint can be said to fall within an approximately equidistant virtual central plane between the front and rear surfaces.

[0036] Prior to any operation as described herein, the front and rear surfaces of the substrate may be substantially identical. The terms "front surface" or "rear surface" are used only for convenience and are generally used to distinguish the surfaces on which the operations of the methods of the present invention are performed. In the context of the invention, the "front surface" of a single-crystal semiconductor treatment substrate (e.g., a single-crystal silicon treatment wafer) refers to the principal surface of the substrate, which becomes the inner surface of the bonding structure. A well-rich layer is formed on this front surface. Correspondingly, the "rear surface" of a single-crystal semiconductor treatment substrate (e.g., a treatment wafer) refers to the principal surface that becomes the outer surface of the bonding structure. Similarly, the "front surface" of a single-crystal semiconductor donor substrate (e.g., a single-crystal silicon donor wafer) refers to the principal surface of the single-crystal semiconductor donor substrate, which becomes the inner surface of the bonding structure. The front surface of a single-crystal semiconductor donor substrate typically includes a dielectric layer, such as a silicon dioxide layer, which forms part or all of the buried oxide (BOX) layer in the final structure. The "rear surface" of a single-crystal semiconductor donor substrate (e.g., a single-crystal silicon donor wafer) refers to the principal surface that becomes the outer surface of the bonding structure. After completing the conventional bonding and wafer thinning steps, a semiconductor device layer of a semiconductor-on-insulator (e.g., silicon-on-insulator) composite structure is formed on the single-crystal semiconductor donor substrate.

[0037] The processed wafer comprises material (e.g., silicon) derived from an ingot grown by a floating zone method. Single-crystal silicon processed wafers sliced ​​from ingots grown by a floating zone method typically have a nominal diameter of at least about 20 mm, at least about 50 mm, at least about 100 mm, at least about 150 mm, at least about 200 mm, for example about 150 mm, or about 200 mm. Surface tension constraints during the growth process typically result in a diameter no greater than 250 mm or about 200 mm. The processed wafer thickness can vary between about 100 micrometers and about 5000 micrometers, for example between about 100 micrometers and about 1500 micrometers, for example between about 250 micrometers and about 1500 micrometers, for example between about 300 micrometers and about 1000 micrometers, suitably in the range of about 500 micrometers to about 1000 micrometers. In some specific embodiments, the wafer thickness may be about 725 micrometers. In some embodiments, the wafer thickness may be about 775 micrometers.

[0038] In some embodiments, the floating zone crystal ingot and the single-crystal semiconductor processing substrate sliced ​​from it have a bulk resistivity of at least about 5,000 ohms-cm, at least about 7,500 ohms-cm, for example at least about 10,000 ohms-cm, at least about 15,000 ohms-cm, or at least about 20,000 ohms-cm, at least about 25,000 ohms-cm, or even at least about 30,000 ohms-cm. In some embodiments, the single-crystal semiconductor processing substrate has a bulk resistivity of less than about 100,000 ohms-cm. High resistivity wafers may include typically very low concentrations (e.g., less than 1 × 10⁻⁶). 12 atoms / cm 3 or even less than 1×10 11 atoms / cm 3 Electroactive dopants, such as boron (p-type), gallium (p-type), aluminum (p-type), indium (p-type), phosphorus (n-type), antimony (n-type), and arsenic (n-type), are used. Methods for preparing high resistivity wafers from floating-zone single-crystal silicon ingots are known in the art, and such high resistivity wafers are available from commercial suppliers.

[0039] Silicon-processed wafers derived from floating-area growth ingots can be more reliably characterized to have ultra-high resistivity values ​​with a minimum-to-maximum variation of approximately 2X. For example, unlike UHRCz wafers where the specifications are typically single-sided (e.g., >= 7500 ohm-cm), acceptable wafer resistivity is a two-sided minimum-to-maximum specification, such as 10,000-20,000 ohm-cm or tighter. A tolerance of + / - 30% to 50% near the target value may be acceptable. This will enable end users to not only have improved RF electrical performance levels (such as...) Figure 3(As shown in the image), and is more predictable and less variable when compared to Chuklaski-grown silicon. The fundamental reason for this solution is that the floating-area silicon treatment wafer has an oxygen concentration below the detectable limit, thereby avoiding thermal donor formation and excessive thermal donor formation, which leads to the variability of ultra-high resistivity Chuklaski-grown silicon. In some embodiments, the floating-area silicon treatment wafer has an oxygen level below the detection limit of the metrology method (e.g., less than about 2.5 × 10⁻⁶). 16 atoms / cm 3 (0.5 PPMA, new ASTM standard), less than approximately 2 × 10 16 atoms / cm 3 (0.4 PPMA, new ASTM standard), less than approximately 1 × 10⁻⁶ 16 atoms / cm 3 (0.2 PPMA, new ASTM standard), or even less than about 1 × 10⁻⁶ 15 atoms / cm 3 (0.02 PPMA, new ASTM standard) and eliminates the presence of oxygen thermal donors and excess donors formed in the Chuklaski-grown silicon wafer, including detectable oxygen concentration. In some embodiments, the silicon-treated wafer has a concentration of less than 1 × 10⁻⁶. 11 Individual donors / cm 3 or even less than 5×10 10 Individual donors / cm 3 The excess thermal donor concentration. In some embodiments, the oxygen concentration is so low that the concentrations of dual-donor thermal donors, new thermal donors, and / or excess thermal donors are below a detectable limit, and a first approximation would be that the concentration of such donors is at least an order of magnitude smaller than the concentration of p-type acceptors or n-type donors. In other words, the concentration of any one of the dual-donor thermal donor concentrations, new thermal donor concentrations, and / or excess thermal donor concentrations, or the sum of the dual-donor thermal donor concentrations, new thermal donor concentrations, and / or excess thermal donor concentrations, is at least an order of magnitude smaller than the concentration of p-type acceptors or n-type donors, i.e., 1 / 10 smaller than the concentration of p-type or n-type dopants. In CZ, the thermal donor and excess concentrations can be below, equal to, or above the background doping concentration, depending on the oxygen concentration and thermal cycling details. The thermal dual donor concentration in CZ Si will remain at approximately 450°C, increasing to a considerable value with annealing time. The concentration will eventually saturate at a value dependent on the Oi. For a large Oi of approximately 15 nppma, the saturation concentration can be approximately 1 × 10⁻¹⁰. 16 / cm 3Or even higher. The saturated (maximum) TDD concentration will decrease as Oi decreases. It will be much greater than the actual dopant concentration involved in HR Si. The low donor concentration in FZ wafers reduces the variability of RF performance, reduces the impact of resistivity variability on device processes sensitive to wafer resistivity (electrostatic adsorption), and eliminates sensitivity to the formation of new thermal donors, another source of variability for ultra-high resistivity / low oxygen Chuklaski grown silicon wafers.

[0040] Furthermore, for example, after annealing at 450°C, the spread resistivity (SRP) of Chuklaski-grown silicon wafers is rarely flat in the first few tens of micrometers below the BOX / treatment interface. The SRP of Chuklaski-grown silicon wafers is typically affected by TD and the formation of excess donors, leading to significant changes in the distribution, such as... Figure 4 The above is shown in the image. However, the SRP of the floating region grown silicon wafer is very flat and exhibits a complete lack of thermal donors and excess donors in tests at 450°C and 600°C. See also Figure 4 .exist Figure 4 In the graphs, the lines marked with diamonds (◆) represent the resistivity of the wafer at each depth in the floating zone treatment before donor generation annealing (DGA) at 450°C, and the lines marked with X represent the resistivity of the wafer at each depth in the floating zone treatment after DGA annealing at 450°C. Furthermore, the lines marked with squares (■) represent the resistivity of the p-type wafer in the Chuklaski growth treatment after DGA annealing at 450°C. Finally, the lines marked with triangles (▲) represent the resistivity of the n-type wafer in the Chuklaski growth treatment after DGA annealing at 450°C. See also... Figure 5 The figure depicts the average resistivity 90 micrometers below the BOX / processing interface of the wafer after SOI processing with a well-rich layer, where the wafer has resistivity greater than 5000 ohm-cm and greater than 10,000 ohm-cm. The distribution is very flat and exhibits complete absence of thermal applicators in tests at 450°C and 600°C.

[0041] Because floating-zone grown silicon wafers have oxygen levels below detectable limits, they may be more prone to slippage during thermal processes. However, nitrogen can be added during the growth of the floating-zone crystal to control point defect formation and increase anti-slip strength. Specialized doping techniques (such as nucleus doping, pellet doping, and gas doping using nitrogen or ammonia) can be used to incorporate a uniform concentration of impurities. In some embodiments, the nitrogen concentration in the floating-zone grown silicon wafer may be at least about 1 × 10⁻⁶. 13 atoms / cm 3 For example, at least about 0.5 × 10 14 atoms / cm 3 At least about 1×10 14 atoms / cm 3In some embodiments, the nitrogen concentration in the floating region grown silicon wafer may be less than about 3 × 10⁻⁶. 15 atoms / cm 3 or less than about 1×10 15 atoms / cm 3 or less than approximately 7 × 10 14 atoms / cm 3 or less than approximately 3 × 10 14 atoms / cm 3 In some embodiments, the nitrogen concentration in the floating-area grown silicon wafer may be at least about 0.5 × 10⁻⁶. 14 atoms / cm 3 And less than approximately 3 × 10 14 atoms / cm 3 Demonstrating the growth of nitrogen-doped floating region silicon wafers in an SOI fabrication line exhibits acceptable sliding properties almost equivalent to those of Cukraski-grown silicon wafers.

[0042] In this regard, both floating-area silicon-treated wafers and Chuklaski-grown silicon-treated wafers were oxidized at 800°C, followed by a 2-hour annealing cycle at 1100°C, and then subjected to a slip test. No slip was observed in either wafer type. Correspondingly, nitrogen-doped floating-area wafers could continue to undergo the thermal cycles associated with well-rich layer deposition and subsequent SOI wafer fabrication without slip. In another furnace push test, the furnace was heated to 1000°C, and both floating-area and Chuklaski-grown silicon-treated wafers were rapidly pushed through the furnace. Both wafer types exhibited similar slip performance in this test.

[0043] In some embodiments, the front surface, back surface, or both the front and back surfaces of a single-crystal semiconductor processing substrate may undergo a process (e.g., an oxidation process) to grow a dielectric layer, such as a semiconductor oxide layer, a semiconductor nitride layer, or a semiconductor oxide nitride layer. In some embodiments, the dielectric layer comprises silicon dioxide, which can be formed by oxidizing the front surface of the silicon processing substrate. This can be achieved by thermal oxidation (in which some portion of the deposited semiconductor material film is consumed) and / or CVD oxide deposition and / or atomic layer deposition. In some embodiments, the semiconductor processing substrate can be thermally oxidized in a furnace such as an ASM A400. In the oxidation environment, the temperature range can be from 750°C to 1100°C. The oxidation environment atmosphere can be a mixture of an inert gas (e.g., Ar or N2) and O2. The oxygen content can vary from 1% to 10% or higher. In some embodiments, the oxidation environment atmosphere can be up to 100% oxygen (“dry oxidation”). In some embodiments, the oxidation environment atmosphere can be oxygen and ammonia, which is suitable for depositing silicon oxynitride. In some embodiments, the ambient atmosphere may include a mixture of an inert gas (e.g., Ar or N2) and an oxidizing gas (e.g., O2 and water vapor) (“wet oxidation”). In some embodiments, the ambient atmosphere may include a mixture of an inert gas (e.g., Ar or N2) and an oxidizing gas (e.g., O2 and water vapor) (“wet oxidation”) and a nitriding gas (e.g., ammonia). In some embodiments, the ambient atmosphere may include a mixture of an inert gas (e.g., Ar or N2) and a nitriding gas (e.g., ammonia) suitable for depositing silicon nitride. In an exemplary embodiment, a semiconductor wafer may be loaded into a vertical furnace (e.g., A400). The temperature is ramped up to an oxidation temperature using a mixture of N2 and O2. At the desired temperature, water vapor is introduced into the gas flow. After the desired oxide thickness has been obtained, the water vapor and O2 are shut off, the furnace temperature is reduced, and the wafer is removed from the furnace. The oxide layer on the front surface, the back surface, or both may be between about 100 angstroms and about 100,000 angstroms, between about 100 angstroms and about 10,000 angstroms, between about 100 angstroms and about 1,000 angstroms, for example between about 100 angstroms and about 700 angstroms, or between about 100 angstroms and about 500 angstroms, or between about 100 angstroms and about 250 angstroms.

[0044] In some embodiments, the oxide layer is relatively thin, for example, between about 5 angstroms and about 25 angstroms, such as between about 10 angstroms and about 15 angstroms. The thin oxide layer can be obtained on both sides of a semiconductor wafer by exposure to a standard cleaning solution (e.g., SC1 / SC2 cleaning solution). In some embodiments, the SC1 solution comprises 5 parts by weight of deionized water, 1 part by weight of aqueous NH4OH (ammonium hydroxide, 29 wt% NH3), and 1 part by weight of aqueous H2O2 (hydrogen peroxide, 30%). In some embodiments, the substrate can be oxidized by exposure to an aqueous solution comprising an oxidant (e.g., SC2 solution). In some embodiments, the SC2 solution comprises 5 parts by weight of deionized water, 1 part by weight of aqueous HCl (hydrochloric acid, 39 wt%), and 1 part by weight of aqueous H2O2 (hydrogen peroxide, 30%).

[0045] II. Well-rich layer

[0046] According to the method of the present invention, a well-rich layer comprising a polycrystalline or amorphous semiconductor material is deposited onto the pre-exposed surface of a single-crystal semiconductor wafer. Semiconductor materials suitable for forming well-rich layers in semiconductor devices on an insulating layer are suitably capable of forming highly defective layers in the manufacturing apparatus. Such materials include both polycrystalline and amorphous semiconductor materials. Materials that can be polycrystalline or amorphous include silicon (Si), silicon-germanium (SiGe), carbon-doped silicon (SiC), and germanium (Ge). Polycrystalline silicon refers to a material comprising small silicon crystals with random crystal orientation. The size of a polycrystalline silicon wafer can be as small as about 20 nanometers. According to the method of the present invention, the smaller the size of the deposited polycrystalline silicon wafer, the higher the defect rate in the well-rich layer. Amorphous silicon includes amorphous allotropic silicon, which lacks both short-range and long-range processes. Silicon wafers having a crystallinity of no more than about 10 nanometers can also be considered substantially amorphous. Silicon-germanium includes alloys of silicon and germanium in any molar ratio of silicon and germanium. Carbon-doped silicon includes compounds of silicon and carbon, which can vary the molar ratio of silicon and carbon. The resistivity of the polycrystalline silicon well-rich layer can be at least 100 ohm-cm, at least about 500 ohm-cm, at least about 1000 ohm-cm, or even at least about 3000 ohm-cm, for example, between about 100 ohm-cm and about 100,000 ohm-cm, or between about 500 ohm-cm and about 100,000 ohm-cm, or between about 1000 ohm-cm and about 100,000 ohm-cm, or between about 500 ohm-cm and about 3000 ohm-cm. Between ohms-cm and about 10,000 ohms-cm, or between about 750 ohms-cm and about 10,000 ohms-cm, between about 1,000 ohms-cm and about 10,000 ohms-cm, between about 2,000 ohms-cm and about 10,000 ohms-cm, between about 3,000 ohms-cm and about 10,000 ohms-cm, or between about 3,000 ohms-cm and about 8,000 ohms-cm.

[0047] Materials used for deposition onto optional pre-oxidation surfaces of single-crystal semiconductor wafers can be deposited using methods known in the art. For example, semiconductor materials can be deposited using metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or molecular beam epitaxy (MBE). Silicon precursors used for LPCVD or PECVD include methylsilane, silicon tetrahydrodeionide (silane), propane, disilane, pentasilane, neopentylsilane, tetrasilane, dichlorosilane (SiH2Cl2), silicon tetrachloride (SiCl4), and other silicon precursors. For example, polycrystalline silicon can be deposited onto a surface oxide layer by pyrolyzing silane (SiH4) in a temperature range between about 550°C and about 690°C (e.g., between about 580°C and about 650°C). The chamber pressure can range from about 70 mTorr to about 400 mTorr. Amorphous silicon can be deposited by plasma-enhanced chemical vapor deposition (PECVD) at temperatures typically ranging from about 75°C to about 300°C. Silicon germanium (especially amorphous silicon germanium) can be deposited at temperatures up to about 300°C by chemical vapor deposition containing organogermanium compounds (e.g., isobutylgermanane, alkylgermanium trichloride, and dimethylaminogermanium trichloride). Carbon-doped silicon can be deposited by thermal plasma-enhanced chemical vapor deposition in an epitaxial reactor using precursors such as silicon tetrachloride and methane. Suitable carbon precursors for CVD or PECVD include methylsilane, methane, ethane, ethylene, and other carbon precursors. For LPCVD deposition, methylsilane is a particularly preferred precursor because it provides both carbon and silicon. For PECVD deposition, the preferred precursor contains silane and methane. In some embodiments, the silicon layer may include a carbon concentration of at least about 1% on an atomic basis, for example, between about 1% and about 10% on an atomic basis.

[0048] In some embodiments, the deposition of the semiconductor material for the well-rich layer may be temporarily interrupted at least once, and preferably more than once, to prepare multiple layers of the well-rich material. The intermediate surface of the semiconductor material film may be exposed to an inert, oxidizing, nitriding, or passivating atmosphere to thereby damage or passivate the deposited semiconductor material. In other words, the method of the present invention may include depositing multiple layers of well-rich semiconductor material through a cyclic process in which semiconductor material is deposited, deposition is interrupted, semiconductor material layers are damaged or passivated, and the next layer of semiconductor material is deposited. In some embodiments, a multilayer comprising a passivated semiconductor layer may be formed, and an additional semiconductor layer may be deposited to form the well-rich layer. In some embodiments, the multilayer comprises more than one passivated semiconductor layer and one additional semiconductor layer among the well-rich layers. By depositing a well-rich layer in this manner, a multilayer comprising (for example) one or more passivation layers of semiconductor material, or two or more passivation layers (e.g., three or more passivation layers, such as at least four passivation layers, or between four and about 100 passivation layers, or between four and about 60 passivation layers, or between four and about 50 passivation layers, or between four and about 25 passivation layers, or between six and about 20 passivation layers) is deposited onto a treatment substrate. The depositable portion is limited by yield requirements and by a large number of semiconductor layers, which are currently depositable by a minimum practical layer thickness (currently about 20 nanometers). Damage or passivation of each of these layers of semiconductor material causes die growth in each layer of the multilayer to be limited by the thickness of the passivated multilayer during the high-temperature process of semiconductor fabrication on an insulating layer, rather than by the thickness of the entire well-rich layer as in prior art processes. In some embodiments, the semiconductor layer can be passivated by exposing the first semiconductor layer to an atmosphere including a nitrogen-containing gas (e.g., nitrogen, nitrous oxide, ammonia (NH3), nitrogen plasma, and any combination thereof). In this regard, the atmosphere in which the semiconductor layer is deposited may include a nitrogen-containing gas (e.g., nitrogen), and termination of the deposition process followed by exposure to the gas may be sufficient to form a thin passivation layer over the semiconductor layer. In some embodiments, the chamber may be evacuated of the deposition gas and flushed with a nitrogen-containing gas to achieve passivation of the previously deposited semiconductor layer. Exposure to nitrogen can nitrid the deposited semiconductor layer, for example, resulting in the formation of a thin silicon nitride layer only a few angstroms thick. Alternative passivation methods can be used. For example, the semiconductor layer can be passivated by exposing the first semiconductor layer to an atmosphere including an oxygen-containing gas (e.g., oxygen, ozone, water vapor, and any combination thereof). According to such embodiments, a thin layer of semiconductor oxide may be formed on the semiconductor layer, sufficient to passivate the layer. For example, a thin layer of silicon oxide may be formed between each layer of a multilayer. The oxide layer may be only a few angstroms thick, for example, between about 1 angstrom and about 20 angstroms, or between about 1 angstrom and about 10 angstroms. In some embodiments, air comprising both nitrogen and oxygen may be used as the passivation gas.In some embodiments, the semiconductor layer can be passivated by exposing the first semiconductor layer to a liquid selected from the group consisting of water, peroxides (e.g., hydrogen peroxide solution) or SCl solution (NH3:H2O2:H2O).

[0049] The total thickness of the well-rich layer can be between about 0.3 micrometers and about 5 micrometers, for example, between about 0.3 micrometers and about 3 micrometers, for example, between about 0.3 micrometers and about 2 micrometers or between about 2 micrometers and about 3 micrometers.

[0050] In some embodiments, a dielectric layer is formed on the surface of the rich well layer after deposition. In some embodiments, a single semiconductor processing substrate (e.g., a monocrystalline silicon processing substrate) is oxidized to form a semiconductor oxide (e.g., silicon dioxide) film on the rich well layer. In some embodiments, the rich well layer (e.g., a polycrystalline film) may be thermally oxidized (where some portion of the deposited semiconductor material film is consumed) or the semiconductor oxide (e.g., silicon dioxide) film may be grown by CVD oxide deposition. The oxide layer (e.g., a silicon dioxide layer) in contact with the polycrystalline or amorphous rich well layer (e.g., a polycrystalline or amorphous silicon rich well layer) may have a thickness between about 0.1 micrometers and about 10 micrometers, for example, between about 0.1 micrometers and about 4 micrometers, for example, between about 0.1 micrometers and about 2 micrometers, or between about 0.1 micrometers and about 1 micrometer. The oxidation process additionally oxidizes the back surface of the monocrystalline semiconductor processing wafer, which advantageously reduces potential warpage and bowing caused by the different coefficients of thermal expansion of silicon and silicon dioxide.

[0051] III. Preparation of the Joining Structure

[0052] A single-crystal semiconductor processing wafer (e.g., a single-crystal silicon processing wafer) prepared according to a floating-zone method is then bonded to a single-crystal semiconductor donor wafer prepared according to a conventional layer transfer method. In a preferred embodiment, the single-crystal semiconductor donor wafer comprises a material selected from the group consisting of silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. The donor wafer can be sliced ​​from an ingot prepared by a floating-zone or Chuklaski method. The wafer thickness can vary between about 100 micrometers and about 5000 micrometers, for example, between about 100 micrometers and about 1500 micrometers, for example, between about 250 micrometers and about 1500 micrometers, for example, between about 300 micrometers and about 1000 micrometers, suitably in the range of about 500 micrometers to about 1000 micrometers. In some specific embodiments, the wafer thickness can be about 725 micrometers. In some embodiments, the wafer thickness can be about 775 micrometers. Depending on the desired properties of the final integrated circuit device, a single-crystal semiconductor (e.g., silicon) donor wafer may include electroactive dopants such as boron (p-type), gallium (p-type), aluminum (p-type), indium (p-type), phosphorus (n-type), antimony (n-type), and arsenic (n-type). The resistivity of the single-crystal semiconductor (e.g., silicon) donor wafer may range from 1 ohm-cm to 100 ohm-cm, 1 ohm-cm to 50 ohm-cm, or 5 ohm-cm to 25 ohm-cm. The single-crystal semiconductor donor wafer may undergo standard process steps including oxidation, implantation, and post-implantation cleaning. Accordingly, a single-crystal semiconductor donor wafer that has been etched and polished, and optionally oxidized, undergoes ion implantation to form a damage layer in the donor substrate.

[0053] In some embodiments, a single-crystal semiconductor donor wafer includes a dielectric layer. The dielectric layer may include one or more insulating layers formed on the front surface of the single-crystal semiconductor donor wafer. The insulating layers may include materials selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride. In some embodiments, the insulating layer may include materials selected from the group consisting of Al₂O₃, AlN, or combinations thereof. In some embodiments, the dielectric layer includes multiple layers of insulating material, but other configurations are within the scope of this invention. Each insulating layer may include materials selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride. In some embodiments, the dielectric layer includes three layers of insulating material in the order of silicon dioxide, silicon nitride, and silicon dioxide. Each insulating layer may have a thickness of at least about 10 nanometers, for example, between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers, between 50 nanometers and about 400 nanometers, or between about 100 nanometers and about 400 nanometers, for example, about 50 nanometers, 100 nanometers, or 200 nanometers.

[0054] Ion implantation can be performed in commercially available instruments such as Applied Materials Quantum II, Quantum H, Quantum LEAP, or Quantum X. Implanted ions include He, H, H2, or combinations thereof. Ion implantation is performed at a density and duration sufficient to form a damage layer in the semiconductor donor substrate. Implantation densities can range from approximately 10 12 ions / cm 2 To about 10 17 ions / cm 2 For example, from about 10 14 ions / cm 2 To about 10 17 ions / cm 2 For example, from about 10 15 ions / cm 2 To about 10 17 ions / cm 2 or from about 10 16 ions / cm 2 To about 10 17 ions / cm 2 The implantation energy can range from about 1 keV to about 3,000 keV, for example from about 10 keV to about 3,000 keV. The implantation energy can also range from about 1 keV to about 3,000 keV, for example from about 5 keV to about 1,000 keV, or from about 5 keV to about 200 keV, or from 5 keV to about 100 keV, or from 5 keV to about 80 keV. The implantation depth determines the thickness of the single-crystal semiconductor device layer transferred to the disposal during the SOI process. Ions can be implanted to depths between about 100 angstroms and about 30,000 angstroms, for example between about 200 angstroms and about 20,000 angstroms, for example between about 2,000 angstroms and about 15,000 angstroms, or between about 15,000 angstroms and about 30,000 angstroms. In some embodiments, it may be desirable to subject the single-crystal semiconductor donor wafer (e.g., a single-crystal silicon donor wafer) to cleaning after implantation. In some preferred embodiments, cleaning may include Piranha cleaning, followed by DI water rinsing and SC1 / SC2 cleaning.

[0055] In some embodiments of the present invention, wherein the product has been implemented via He + H + H2 +The single-crystal semiconductor donor wafer, formed by any combination of ion implantation and ion implantation, is annealed at a temperature sufficient to form a thermally activated cleavage surface in the single-crystal semiconductor donor substrate. Examples of suitable tools may be, for example, a simple box furnace of the Blue M model. In some preferred embodiments, the ion-implanted single-crystal semiconductor donor substrate is annealed at a temperature ranging from about 200°C to about 350°C, from about 225°C to about 325°C, and preferably about 300°C. Thermal annealing can occur for a duration ranging from about 2 hours to about 10 hours, for example from about 2 hours to about 8 hours. Thermal annealing within these temperature ranges is sufficient to form a thermally activated cleavage surface. After thermal annealing to activate the cleavage surface, the surface of the single-crystal semiconductor donor substrate is optionally cleaned.

[0056] In some embodiments, an ion-implanted and optionally cleaned and optionally annealed single-crystal semiconductor donor wafer undergoes oxygen plasma and / or nitrogen plasma surface activation. In some embodiments, the oxygen plasma surface activation tool is a commercially available tool, such as one available from EV Group. 810LT Low-Temperature Plasma Activation System. An ion-implanted, optionally cleaned, single-crystal semiconductor donor wafer is loaded into a chamber. The chamber is evacuated and backfilled with O2 to a pressure below atmospheric pressure to generate plasma. The single-crystal semiconductor donor wafer is exposed to this plasma for a desired time, ranging from about 1 second to about 120 seconds. Oxygen plasma surface oxidation is performed to make the front surface of the single-crystal semiconductor donor substrate hydrophilic and capable of bonding to a single-crystal semiconductor treatment substrate prepared according to the method described above.

[0057] The hydrophilic front surface of the single-crystal semiconductor donor wafer and the front surface of the single-crystal semiconductor treatment wafer are then brought into close contact to form a bonding structure. According to the method of the invention, each of the front surfaces of the single-crystal semiconductor donor wafer and the single-crystal semiconductor treatment wafer may include one or more insulating layers. The insulating layers form the dielectric layer of the bonding structure.

[0058] Since mechanical bonding can be relatively weak, the bonding structure can be further annealed to strengthen the bonding between the single-crystal semiconductor donor wafer and the single-crystal semiconductor disposal wafer. In some embodiments of the invention, the bonding structure is annealed at a temperature sufficient to form a thermally activated cleavage surface in the single-crystal semiconductor donor substrate. Examples of suitable tools may be, for example, a simple box furnace of the Blue M type. In some embodiments, the bonding structure is annealed at temperatures ranging from about 200°C to about 400°C, from about 300°C to about 400°C, for example, from about 350°C to about 400°C.

[0059] In some embodiments, annealing may occur at relatively high pressures, such as between about 0.5 MPa and about 200 MPa, for example between about 0.5 MPa and about 100 MPa, for example between about 0.5 MPa and about 50 MPa, or between about 0.5 MPa and about 10 MPa, or between about 0.5 MPa and about 5 MPa. In conventional bonding methods, the temperature may be limited by thermal splitting. This occurs when the pressure of the thin plate at the implantation surface exceeds the external equalization pressure. Accordingly, conventional annealing may be limited to a bonding temperature between about 350°C and about 400°C due to thermal splitting. After implantation and bonding, the wafers are weakly held together. However, the gap between the wafers is sufficient to prevent gas infiltration or escape. The weak bonding can be strengthened by heat treatment, but the cavity formed during implantation is filled with gas. Upon heating, the gas within the cavity is pressurized. The estimated pressure can range from 0.2 to 1 GPa depending on the dosage (Cherkashin et al., J. Appl. Phys. 118, 245301 (2015)). When the pressure exceeds a critical value, the layers delaminate. This is called thermal splitting. It prevents high temperatures or prolonged periods during annealing. According to some embodiments of the invention, bonding occurs under high pressure, for example, between about 0.5 MPa and about 200 MPa, for example, between about 0.5 MPa and about 100 MPa, for example, between about 0.5 MPa and about 50 MPa, or between about 0.5 MPa and about 10 MPa, or between about 0.5 MPa and about 5 MPa, thereby achieving bonding at high temperatures. In some embodiments, the bonded structure is annealed at temperatures ranging from about 300°C to about 700°C, from about 400°C to about 600°C, for example, between about 400°C and about 450°C, or even between about 450°C and about 600°C, or between about 350°C and about 450°C. Increasing the thermal budget will have a positive impact on the bond strength. Thermal annealing can occur for durations ranging from about 0.5 hours to about 10 hours, for example, between about 0.5 hours and about 3 hours, preferably about 2 hours. Thermal annealing within such temperature ranges is sufficient to form a thermally activated cleavage surface. In conventional bond annealing, due to edge drop, the edges of both the treatment wafer and the donor wafer may become quite far apart. In this region, there is no layer transfer. It is referred to as a step. It is desirable that pressure bonding reduce this step, allowing the SOI layer to extend further outward toward the edge. The mechanism is based on the compression and outward "zipper movement" of the trapping gasket. After thermal annealing to activate the cleavage surface, the bonded structure can be cleaved.

[0060] Following thermal annealing, the bonding between the single-crystal semiconductor donor wafer and the single-crystal semiconductor treatment wafer becomes strong enough to initiate layer transfer via cleaving the bonding structure at a cleaving facet. Cleaving can occur according to techniques known in the art. In some embodiments, the bonding structure can be placed on a conventional cleaving stage, one side of which is attached to a fixed suction cup and the other side to a hinged arm via an additional suction cup. A crack is initiated near the suction cup attachment point, and the movable arm pivots about a hinge, thereby cleaving the wafer. Cleaving removes a portion of the semiconductor donor wafer, thereby leaving a single-crystal semiconductor device layer 26 (preferably a silicon device layer) on the semiconductor multilayer structure 20 over an insulating layer. See also Figure 2 .

[0061] Following cleavage, the cleaved structure can undergo high-temperature annealing to further enhance the bonding between the transfer device layer 26 and the single-crystal semiconductor substrate 22. Examples of suitable tools include vertical furnaces, such as the ASM A400. In some preferred embodiments, the bonded structure is annealed at a temperature from about 1000°C to about 1200°C, preferably at about 1000°C. Thermal annealing can occur for a duration from about 0.5 hours to about 8 hours, preferably about 4 hours. Thermal annealing within these temperature ranges is sufficient to enhance the bonding between the transfer device layer and the single-crystal semiconductor substrate.

[0062] Following splitting and high-temperature annealing, the bonded structure can undergo a cleaning process designed to remove thin thermal oxides and clean surface particles. In some embodiments, the desired thickness and smoothness of the single-crystal semiconductor device layer can be achieved by undergoing a vapor-phase HCl etching process in a horizontal-flow single-wafer epitaxial reactor using H2 as the carrier gas. In some embodiments, the semiconductor device layer 26 may have a thickness between about 20 nanometers and about 3 micrometers, for example, between about 20 nanometers and about 2 micrometers, for example, between about 20 nanometers and about 1.5 micrometers, or between about 1.5 micrometers and about 3 micrometers.

[0063] In some embodiments, the epitaxial layer may be deposited on the transferred single-crystal semiconductor device layer 26. The deposited epitaxial layer may include substantially the same electrical characteristics as the underlying single-crystal semiconductor device layer 26. Alternatively, the epitaxial layer may include electrical characteristics different from the underlying single-crystal semiconductor device layer 26. The epitaxial layer may include materials selected from the group consisting of silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. Depending on the desired properties of the final integrated circuit device, the epitaxial layer may include electrically active dopants such as boron (p-type), gallium (p-type), aluminum (p-type), indium (p-type), phosphorus (n-type), antimony (n-type), and arsenic (n-type). The resistivity of the epitaxial layer may range from 1 ohm-cm to 1050 ohm-cm, from 1 ohm-cm to 50 ohm-cm, and typically from 5 ohm-cm to 25 ohm-cm. In some embodiments, the epitaxial layer may have a thickness between about 20 nanometers and about 3 micrometers, for example between about 20 nanometers and about 2 micrometers, for example between about 20 nanometers and about 1.5 micrometers or between about 1.5 micrometers and about 3 micrometers.

[0064] Next, the completed SOI multilayer structure, including a single-crystal semiconductor wafer 22, a polycrystalline silicon layer 28 including a well-rich layer, a dielectric layer 24, and a semiconductor device layer 26, can withstand end-of-line metrological testing and undergo a final cleaning using typical SC1-SC2 processes. Accordingly, the present invention relates to an SOI multilayer structure including a well-rich layer and a processing substrate fabricated using a nitrogen-doped high-resistivity (>20 kΩ-cm) floating region material. Compared to standard Chuklaski processing wafers, floating region wafers offer superior resistivity stability compared to typical BEOL annealing. The higher resistivity achievable using the FZ process enables a step improvement in substrate RF loss, crosstalk, and harmonic distortion that is not easily obtained using conventional CZ silicon materials. We report the first demonstration of an FZ CTLSOI with -110 dBm HD2 on our CPW structure.

[0065] The invention is further illustrated by the following non-limiting examples.

[0066] Example 1. Floating area chip

[0067] This study used wafers from commercially grown 200 mm high-resistivity, nitrogen-doped floating-region crystals. The wafer's resistivity was greater than 20 kΩ-cm. The oxygen concentration within the wafer was less than 1 × 10⁻⁶. 16 atoms / cm 3 The mechanical strength of wafers with different nitrogen levels was evaluated, ranging from 0.5 × 10⁻⁶. 14 / cm 3 Up to 3×10 14 / cm 3The nitrogen concentration is then adjusted. Next, a well-rich layer is deposited on the FZ wafer. The wafer is then processed into an SOI wafer using a high-volume manufacturing (HVM) process. At the end of the SOI wafer manufacturing process, the wafer undergoes standard quality inspections, including surface inspection using a KLA Tencor SP1, flatness and shape measurements using an ADE9700, and sliding inspection.

[0068] Example 2. Sliding stress test

[0069] SOI wafers with low and high nitrogen concentrations fabricated using treated substrates prepared via the floating zone method were subjected to enhanced thermal stress testing by inducing different radial thermal gradients on the wafers to simulate rapid thermal program (RTP) thermal cycling. The purpose of thermal stress was to intentionally induce slippage within the wafers and to test the robustness of the mechanical strength of SOI structures with FZ treated substrates relative to SOI wafers with treated substrates prepared via the Chuklaski (CZ) method. SOI structures fabricated on CZ wafers with interstitial oxygen Oi ~3.5 PPMA (new-ASTM) were mixed to form control wafers. It was found that while UHR SOI structures with FZ treated substrates exhibited a slip-free “window” of induced thermal gradients considered sufficient for safe handling in subsequent device process flows, the window was not as wide as that of the higher-oxygen CZ wafers. See also Figure 6 The comparison involved sliding windows used in fabricating SOI multilayer structures on treated substrates using either the floating zone method or the Chuklaski method. Within the range of nitrogen tested in these wafers, some minor improvements were observed with increasing N concentration.

[0070] Example 3. Resistivity stability

[0071] Extended resistivity distribution (SRP) measurements were performed at the end of the production line to verify the resistivity stability of the wafers. The resistivity of SOI wafers with treatment substrates prepared via the oxygen-containing Chuklaski (CZ) method formed thermal double donors at temperatures ranging from 350°C to 500°C, with the formation rate peaking sharply at approximately 450°C. This can lead to a decrease in resistivity in treated wafers during BEOL metal annealing processes, which typically fall within this temperature range. Since SOI structures with FZ treatment substrates are virtually oxygen-free, these SOI structures are unaffected by such resistivity variations. See also Figure 7 As expected, the resistivity of the SOI structure with the FZ-treated substrate remained the same before and after 1 hour of annealing at 450°C. Furthermore, since the FZ-treated substrate is nitrogen-doped, annealing at 600°C for 1 hour was performed to verify that, as expected in CZ silicon in the presence of both oxygen and nitrogen, no NO-related donors were formed.

[0072] Example 4. Harmonic Distortion

[0073] Radio frequency (RF) tests were performed on several SOI structures with FZ-treated substrates. The top silicon layer of the SOI wafer was removed (via wet chemical etching), and a coplanar waveguide structure was fabricated directly on the BOX layer. Second harmonic distortion (HD2) and third harmonic distortion (HD3) were measured relative to the input power at up to 35 dBm. A diameter measurement device across the wafer was used to determine the radial uniformity of the results. The results were then compared with similarly fabricated planar waveguide structures on SOI wafers with treated substrates prepared using the Chuklaski method.

[0074] Figure 8 This paper demonstrates the HD2 performance of our first and second generation SOI wafers with treatment substrates prepared via the Chuklaski method. The HD2 values ​​for these wafers at Pin = 15 dBm are -80 dBm and -90 dBm, respectively. In contrast, the SOI structure with an FZ treatment substrate exhibits a significant 20 dBm improvement in HD2, reaching -110 dBm at Pin = 15 dBm. The performance difference is driven by the resistivity difference between typical CZ and FZ wafers. HD2 was measured at multiple sites on the wafers, and no strong radial variation in HD2 was observed. The SOI structure with the FZ treatment substrate consistently outperforms the SOI wafer with the treatment substrate prepared via the Chuklaski method.

[0075] In describing elements of the present invention or embodiments thereof, the articles “a,” “an,” “the,” and “said” are intended to mean the presence of one or more elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that additional elements besides those listed may be present.

[0076] Since various changes can be made to the foregoing without departing from the scope of the invention, it is intended that all issues contained in the foregoing description and illustrated in the accompanying drawings should be interpreted as illustrative rather than limiting.

Claims

1. A multi-layer structure comprising: A single-crystal silicon wafer processing substrate comprising two principal, generally parallel surfaces, one of which is a front surface and the other is a rear surface; a circumferential edge connecting the front and rear surfaces; and a central plane of the single-crystal silicon wafer processing substrate between the front and rear surfaces, wherein the single-crystal silicon wafer processing substrate has a bulk resistivity of at least 5000 ohms-cm and less than 1 × 10⁻⁶ ohms-cm. 16 atoms / cm 3 The interstitial oxygen concentration, and at least 1×10 13 atoms / cm 3 nitrogen concentration; A well-rich layer that contacts the front surface interface of the single-crystal silicon wafer disposal substrate and includes one or more polycrystalline semiconductor layers or one or more amorphous semiconductor layers. A dielectric layer, which is in interface contact with the well-rich layer; and A single-crystal semiconductor device layer, which is in contact with the dielectric layer at the interface; The multilayer structure described above exhibits a second harmonic distortion (HD2) value better than -90 dBm at an RF input power of 15 dBm; and The single-crystal silicon wafer processing substrate includes a silicon wafer sliced ​​from a single-crystal silicon ingot grown by a floating zone method.

2. The multilayer structure according to claim 1, wherein the silicon wafer sliced ​​from a single-crystal silicon ingot grown by the floating zone method has a diameter of at least 150 mm.

3. The multilayer structure according to claim 1, wherein the silicon wafer sliced ​​from a single-crystal silicon ingot grown by the floating zone method has a diameter of at least 200 mm.

4. The multilayer structure according to claim 1, wherein the single-crystal silicon wafer disposal substrate has a bulk resistivity of at least 7,500 ohms-cm.

5. The multilayer structure according to claim 1, wherein the single-crystal silicon wafer disposal substrate has a bulk resistivity of at least 10,000 ohms-cm.

6. The multilayer structure according to claim 1, wherein the single-crystal silicon wafer disposal substrate has a bulk resistivity of at least 15,000 ohms-cm.

7. The multilayer structure according to claim 1, wherein the single-crystal silicon wafer disposal substrate has a bulk resistivity of at least 20,000 ohms-cm.

8. The multilayer structure according to claim 1, wherein the single-crystal silicon wafer processing substrate has a bulk resistivity of less than 100,000 ohms-cm.

9. The multilayer structure according to claim 1, wherein the single-crystal silicon wafer processing substrate has a density of less than 1 × 10⁻⁶. 11 Individual donors / cm 3 Excessive heat application concentration.

10. The multilayer structure according to claim 1, wherein the single-crystal silicon wafer processing substrate has a density of less than 5 × 10⁻⁶. 10 Individual donors / cm 3 Excessive heat application concentration.

11. The multilayer structure according to claim 1, wherein the single-crystal silicon wafer processing substrate comprises less than 1 × 10⁻⁶ 12 atoms / cm 3 The concentration of the p-type dopant is less than that of the p-type dopant, and further wherein the concentration of the oxygen-thermal dual donor, the new donor and the excess thermal donor or any combination thereof is at least one order of magnitude less than the concentration of the p-type dopant.

12. The multilayer structure according to claim 1, wherein the single-crystal silicon wafer processing substrate comprises less than 1 × 10⁻⁶ 11 atoms / cm 3 The concentration of the p-type dopant is less than that of the p-type dopant, and further wherein the concentration of the oxygen-thermal dual donor, the new donor and the excess thermal donor or any combination thereof is at least one order of magnitude less than the concentration of the p-type dopant.

13. The multilayer structure according to claim 1, wherein the single-crystal silicon wafer processing substrate comprises less than 1 × 10⁻⁶ 12 atoms / cm 3 The concentration of the n-type dopant is less than that of the concentration of the oxythermal dual donor, the new donor and the excess thermal donor or any combination thereof, and the concentration of the oxythermal dual donor is at least one order of magnitude less than that of the n-type dopant.

14. The multilayer structure according to claim 1, wherein the single-crystal silicon wafer processing substrate comprises less than 1 × 10⁻⁶ 11 atoms / cm 3 The concentration of the n-type dopant is less than that of the concentration of the n-type dopant, and further wherein the concentration of the oxygen-thermal dual donor, the new donor, and the excess thermal donor, or any combination thereof, is at least one order of magnitude less than the concentration of the n-type dopant.

15. The multilayer structure according to claim 1, wherein the single-crystal silicon wafer processing substrate has a density of less than 1 × 10⁻⁶. 15 atoms / cm 3 The interstitial oxygen concentration.

16. The multilayer structure according to claim 1, wherein the single-crystal silicon wafer disposal substrate has a density of at least 1 × 10⁻⁶. 14 atoms / cm 3 The nitrogen concentration.

17. The multilayer structure according to claim 1, wherein the single-crystal silicon wafer processing substrate has a density of less than 3 × 10⁻⁶. 15 atoms / cm 3 The nitrogen concentration.

18. The multilayer structure according to claim 1, wherein the single-crystal silicon wafer disposal substrate has a density of less than 1 × 10⁻⁶. 15 atoms / cm 3 The nitrogen concentration.

19. The multilayer structure according to claim 1, wherein the single-crystal silicon wafer processing substrate has a density of less than 7 × 10⁻⁶. 14 atoms / cm 3 The nitrogen concentration.

20. The multilayer structure according to claim 1, wherein the single-crystal silicon wafer processing substrate has a density between 5 × 10⁻⁶ and 10⁻⁶. 14 atoms / cm 3 Up to 2×10 15 atoms / cm 3 The nitrogen concentration between.

21. The multilayer structure of claim 1, wherein the well-rich layer comprises one or more polycrystalline semiconductor layers, each of the one or more polycrystalline semiconductor layers comprising a material selected from the group consisting of silicon, SiGe, SiC and Ge.

22. The multilayer structure of claim 1, wherein the well-rich layer comprises one or more amorphous semiconductor layers, each of the one or more amorphous semiconductor layers comprising a material selected from the group consisting of silicon, SiGe, SiC and Ge.

23. The multilayer structure according to claim 1, wherein the well-rich layer has a resistivity greater than 1000 ohm-cm.

24. The multilayer structure according to claim 1, wherein the well-rich layer has a resistivity greater than 3000 ohm-cm.

25. The multilayer structure according to claim 1, wherein the well-rich layer has a resistivity between 2,000 ohm-cm and 10,000 ohm-cm.

26. The multilayer structure of claim 1, wherein the well-rich layer has a resistivity between 3,000 ohm-cm and 10,000 ohm-cm.

27. The multilayer structure of claim 1, wherein the well-rich layer has a resistivity between 3,000 ohm-cm and 5,000 ohm-cm.

28. The multilayer structure according to claim 1, wherein the well-rich layer has a thickness between 0.1 micrometers and 50 micrometers.

29. The multilayer structure according to claim 1, wherein the well-rich layer has a thickness between 0.1 micrometers and 20 micrometers.

30. The multilayer structure according to claim 1, wherein the well-rich layer has a thickness between 0.1 micrometers and 10 micrometers.

31. The multilayer structure according to claim 1, wherein the well-rich layer has a thickness between 0.5 micrometers and 5 micrometers.

32. The multilayer structure according to claim 1, wherein the dielectric layer comprises a material selected from silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, aluminum oxide, aluminum nitride, and any combination thereof.

33. The multilayer structure according to claim 1, wherein the dielectric layer comprises a material selected from silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and any combination thereof.

34. The multilayer structure according to claim 1, wherein the multilayer structure exhibits a second harmonic distortion (HD2) value better than -100dBm at an RF input power of 15dBm.

35. The multilayer structure of claim 1, wherein the multilayer structure exhibits a second harmonic distortion (HD2) value better than -110 dBm at an RF input power of 15 dBm.

Images