A defect detection structure and method for wafer testing

Abstract

The present application discloses a defect detection structure and method for wafer testing, which belongs to the field of semiconductor devices and manufacturing. The structure includes: a plurality of detection groups; the two ends of the detection group include a first wafer connection, an M0 metal layer and a second wafer connection with adjacent preset spacings, and an M0 cutting structure for cutting the M0 metal layer, wherein the first wafer connection and the second wafer connection include fins Fin with preset spacings; the M0 metal layer is derived through a metal wiring layer, and the first wafer connection and the second wafer connection are derived through a first layer of metal wiring layer. Through the above structure, a defect detection structure for wafer testing is specially designed for WAT level, and by performing a conduction test at a specific position, it is determined whether a defective fin Fin exists, thereby solving the problem that there is no targeted detection means for Fin merge anomalies in related technologies.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices and manufacturing, and specifically to a defect detection structure and method for wafer testing. Background Art

[0002] With the development of the times, chips have become a "necessity" in global life. With the advancement of chip technology, people's lives are becoming more and more intelligent, travel is becoming more and more convenient, and the amount of information available every day is increasing. As the chip size continues to shrink, traditional planar MOS tubes can no longer meet the requirements. Both the width of the gate and the thickness of the gate oxide are close to the physical limit.

[0003] The FIN-FET fin transistor structure came into being as a new generation of M0S tube. The fin-shaped gate surrounds the active area on three sides, greatly improving the switching speed and efficiency, allowing the M0S tube to continue to develop along Moore's Law.

[0004] The development process of fin transistors is a new challenge for materials and processes. The FIN process involves self-aligned quadruple patterning technology, which obtains the required size of FiN AA through two pattern conductions. In the process, some of the Fin's Hard Mask parts need to be integrated in advance. If they cannot be integrated, Fin failure will occur, thus affecting the normal operation of the circuit. Summary of the invention

[0005] The present application provides a defect detection structure and method for wafer testing, which can solve the problem that there is no targeted detection means for Fin merge anomalies in the related art.

[0006] On the one hand, an embodiment of the present application provides a defect detection structure for wafer testing, the structure comprising: a plurality of detection groups;

[0007] The two ends of the detection group include a first wafer connection, an M0 metal layer and a second wafer connection with adjacent preset intervals, and an M0 cutting structure for cutting the M0 metal layer, wherein a fin Fin with a preset interval is included between the first wafer connection and the second wafer connection;

[0008] The M0 metal layer is derived through a metal wiring layer, and the first wafer connection and the second wafer connection are derived through a first layer of metal wiring layer.

[0009] Optionally, the preset spacing between the fins Fin is a side wall fusion spacing.

[0010] Optionally, adjacent preset spacings between the first wafer connection, the M0 metal layer and the second wafer connection are set according to a minimum line width requirement and a minimum spacing requirement between lines.

[0011] Optionally, the M0 metal layer straddles the fin to be tested Fin.

[0012] Optionally, the M0 metal layer is derived through a metal wiring layer at an upper metal contact hole.

[0013] Optionally, the first wafer connection and the second wafer connection are derived through a first metal wiring layer at a gate metal contact hole.

[0014] On the other hand, a defect detection method for wafer testing is provided, the method is applicable to the defect detection structure for wafer testing described above, the method comprising:

[0015] At the beginning of the test, all wafer connections are pressurized and opened;

[0016] Apply voltage at a first position and a second position to measure current, wherein the first position is parallel to the defective fin Fin, and the second position is located above and below the first position and is parallel to the first position;

[0017] In response to the existence of the defective fin Fin, a large current is conducted at the first position and / or the second position;

[0018] In response to the defective fin Fin not existing, a micro current exists at the first position and / or the second position.

[0019] Optionally, the pressurizing position at each wafer connection is located above the first position and the second position.

[0020] Optionally, the defect detection method for wafer testing is applicable to 14nm and below Fin-FET processes.

[0021] In summary, the present invention provides a defect detection structure and method for wafer testing, the structure includes a plurality of detection groups; the two ends of the detection group include a first wafer connection, an M0 metal layer and a second wafer connection with adjacent preset spacings, and an M0 cutting structure for cutting the M0 metal layer, wherein the first wafer connection and the second wafer connection include fins with preset spacings; the M0 metal layer is derived through a metal wiring layer, and the first wafer connection and the second wafer connection are derived through a first layer of metal wiring layer. A defect detection structure for wafer testing is specially designed for WAT level through the above structure, and a conduction test is performed at a specific position to determine whether a defective fin Fin exists, thereby solving the problem that there is no targeted detection means for Finmerge anomalies in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 is a schematic structural diagram of a defect detection structure for wafer testing provided by an embodiment of the invention;

[0024] Figure 2 It is a flow chart of a defect detection method for wafer testing provided in an embodiment of the invention. DETAILED DESCRIPTION

[0025] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0026] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0027] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0028] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0029] Please refer to Figure 1, which shows a schematic structural diagram of a defect detection structure for wafer testing provided by an illustrative embodiment of the present application, taking the first wafer connection PO1 and the second wafer connection PO2 as an example of a detection group, the structure includes several detection groups.

[0030] For each inspection group, at both ends of the inspection group there are a first wafer connection PO1, an M0 metal layer (shown as M0A in the figure) and a second wafer connection PO2 with adjacent preset spacings, and an M0 cutting structure (shown as M0C in the figure) for cutting the M0 metal layer, wherein a fin Fin with a preset spacing is included between the first wafer connection and the second wafer connection.

[0031] like Figure 1 As shown, the M0 metal layer is derived through the metal wiring layer M1, and the first wafer connection and the second wafer connection are derived through the first metal wiring layer M0P.

[0032] Optionally, the preset spacing between the fins Fin is a sidewall fusion spacing.

[0033] Optionally, adjacent preset spacings between the first wafer connection, the M0 metal layer and the second wafer connection are set according to minimum line width requirements and minimum line spacing requirements, wherein the minimum line width requirements and minimum line spacing requirements are specified by design rule documents.

[0034] Optionally, the M0 metal layer straddles the fin to be tested, such as Figure 1 As shown, a Defect Fin is also indicated for marking the detected defective fin Fin.

[0035] In one possible implementation, the M0 metal layer spans the position where the Defect Fin may appear, ensuring that if a defect occurs, the M0 metal layer will contact the Defect Fin, and the length of M0 must be controlled not to be too long to ensure that it cannot contact the opposite valid Fin. Once the M0 metal layer contacts the opposite valid Fin, the entire defect detection structure will be short-circuited, and the test result will be inaccurate. The defect detection structure of this design requires the Defect Fin as a short-circuit channel to determine whether a Defect Fin exists, so other short-circuit sources must be avoided.

[0036] Further, such as Figure 1 As shown, the M0 metal layer is derived through the metal wiring layer V0-M1 at the upper metal contact hole, and V0 is used to mark the contact hole.

[0037] Furthermore, the first wafer connection and the second wafer connection are derived through the first metal wiring layer M0P+V0 at the gate metal contact hole, wherein the gate metal contact hole is located at POn, and n refers to a number from 1 to n.

[0038] In summary, the present invention provides a defect detection structure and method for wafer testing, the structure includes a plurality of detection groups; the two ends of the detection group include a first wafer connection, an M0 metal layer and a second wafer connection with adjacent preset spacings, and an M0 cutting structure for cutting the M0 metal layer, wherein the first wafer connection and the second wafer connection include fins with preset spacings; the M0 metal layer is derived through a metal wiring layer, and the first wafer connection and the second wafer connection are derived through a first layer of metal wiring layer. A defect detection structure for wafer testing is specially designed for WAT level through the above structure, and a conduction test is performed at a specific position to determine whether a defective fin Fin exists, thereby solving the problem that there is no targeted detection means for Finmerge anomalies in the related art.

[0039] Please refer to Figure 2 , which shows a schematic flow chart of a defect detection method for wafer testing provided by an exemplary embodiment of the present application. The method comprises:

[0040] Step 201, when the test starts, all wafer connections are pressurized and opened.

[0041] like Figure 2 As shown, during the test, the PO part (denoted as Figure 2 All PAD1 in the circuit are pressurized and turned on.

[0042] Step 202 , applying voltage at a first position and a second position to measure current, the first position is parallel to the defective fin Fin, and the second position is located above and below the first position and is parallel to the first position.

[0043] As shown in Figure 2, the first position is recorded as PAD2 and the second position is recorded as PAD3.

[0044] Step 203 : In response to the existence of the defective fin Fin, a large current is conducted at the first position and / or the second position.

[0045] Step 204 : in response to the defective fin Fin not existing, a micro current exists at the first position and / or the second position.

[0046] In a possible implementation, the existence of defectfin is determined based on the current condition after voltage application, thereby determining whether the Fin merge process is normal. This graph can be used for 14nm and below Fin-FET processes to detect Fin merge conditions.

[0047] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A defect detection structure for wafer testing, characterized in that: The structure includes: a number of detection groups; The two ends of the detection group include a first wafer connection, an M0 metal layer and a second wafer connection with adjacent preset intervals, and an M0 cutting structure for cutting the M0 metal layer, wherein a fin Fin with a preset interval is included between the first wafer connection and the second wafer connection; The M0 metal layer is derived through a metal wiring layer, and the first wafer connection and the second wafer connection are derived through a first metal wiring layer; The M0 metal layer straddles the fin to be tested.

2. The defect detection structure for wafer testing according to claim 1, characterized in that: The preset distance between the fins is the sidewall fusion distance.

3. The defect detection structure for wafer testing according to claim 1, characterized in that: The adjacent preset spacings between the first wafer connection, the M0 metal layer and the second wafer connection are set according to the minimum line width requirement and the minimum spacing requirement between lines.

4. The defect detection structure for wafer testing according to claim 1, characterized in that: The M0 metal layer is led out through the metal wiring layer at the upper metal contact hole.

5. The defect detection structure for wafer testing according to claim 1, characterized in that: The first wafer connection and the second wafer connection are led out through a first metal wiring layer at a gate metal contact hole.

6. A defect detection method for wafer testing, characterized in that: The method is applicable to the defect detection structure for wafer testing according to claim 1, and the method comprises: At the beginning of the test, all wafer connections are pressurized and opened; Apply voltage at a first position and a second position to measure current, wherein the first position is parallel to the defective fin Fin, and the second position is located above and below the first position and is parallel to the first position; In response to the existence of the defective fin Fin, a large current is conducted at the first position and / or the second position; In response to the defective fin Fin not existing, a micro current exists at the first position and / or the second position.

7. The method according to claim 6, characterized in that The pressurizing positions at the wafer connections are located above the first position and the second position.

8. The method according to claim 6, characterized in that The defect detection method for wafer testing is applicable to 14nm and below Fin-FET processes.

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