Multi-section high-flatness wafer cutting method

Abstract

The invention belongs to the technical field of wafer processing, and discloses a multi-section high-flatness wafer cutting method which comprises the following steps: S1, wafer pretreatment and stress buffer layer preparation; s2, performing layered rough cutting by using a diamond blade; s3, plasma fine cutting and interface repairing; s4, performing multi-layer cooling and surface polishing; and S5, surface quality closed-loop detection is carried out. According to the method, copper layer residues and resin carbonization defects are synchronously eliminated. Cryogenic treatment induces lattice reconstruction through ultrafast phase change and blocks a chain reaction of dislocation defects, so that the intrinsic mechanical strength of the material is recovered, and a chemical mechanical polishing system activates the self-repairing characteristic of the material while removing a sub-surface damaged layer through the synergistic effect of abrasive chemical activity and mechanical shearing force, so that an atomic-scale smooth interface is formed, and the self-repairing performance of the material is improved. A closed-loop detection system depends on multi-dimensional data fusion and ion beam fixed-point repair, accurate positioning and performance recovery of cross-scale defects are achieved, and the electrical integrity of a chip functional area is ensured.

Description

Technical Field

[0001] The present invention belongs to the technical field of wafer processing, and in particular relates to a multi-stage high-flatness wafer cutting method. Background Art

[0002] Wafer dicing is a key process in semiconductor manufacturing, primarily used to cut large wafers into individual chips (dies). This process typically utilizes high-precision diamond cutting tools or laser cutting equipment. First, a thin film is coated on the wafer surface, serving as a reference for dicing. Precision mechanical equipment or a laser beam then cuts the wafer along predetermined paths. The wafer dicing process requires a high degree of precision and stability to ensure that the size, position, and performance of each chip meet design requirements. With advances in semiconductor technology, the wafer dicing process is gradually evolving toward higher precision and smaller sizes. Modern dicing technology not only improves production efficiency but also significantly enhances chip performance, power consumption, and integration. It is widely used in smartphones, computers, automotive electronics, and other fields.

[0003] Traditional wafer dicing methods are limited by their single-stage cutting process and low flatness. This single-stage process utilizes a single energy input mode, making it difficult to adapt to the heterogeneous properties of wafer multilayer materials. Mechanical blade dicing, a typical single-stage process, generates mechanical stress at the interface between hard and brittle materials due to high-speed rotation, which can easily lead to stress concentration. This can cause microcracks to propagate at the junction of the silicon substrate and dielectric layer, leading to chip edge chipping. Especially when processing copper-resin composite structures, the disparity between the high ductility of the copper layer and the brittleness of the resin leads to an imbalance in material removal rates. A single energy input cannot simultaneously and precisely separate the conductive and dielectric layers, resulting in copper foil residue or excessive resin ablation. For wafers thicker than 100μm, single-stage laser dicing requires multiple repeated scans due to energy penetration depth limitations. This exacerbates heat accumulation, leading to the risk of cross-section carbonization and dielectric delamination. This one-size-fits-all approach fails to dynamically adapt to material properties, resulting in a trade-off between cutting efficiency and quality.

[0004] Uneven energy distribution during the cutting process directly leads to the degradation of wafer surface flatness. When cutting with a mechanical blade, the random distribution of diamond abrasives causes fluctuations in cutting force, forming periodic lines on the surface of the silicon wafer, with depth deviations up to micron level. The energy gradient distribution of the Gaussian beam in laser cutting causes excessive vaporization of the material in the center of the cutting path, while the heat-affected zone at the edge melts and recondenses, forming a wavy cross-sectional morphology. Especially when processing new ABF carriers, the differential absorption characteristics of copper-polyimide by a single-wavelength laser lead to step-like uneven defects at the interface, affecting the subsequent solder ball implantation accuracy. Although plasma cutting can achieve atomic-level etching, when the ion beam uniformity is insufficient, nano-scale burrs are easily generated on the edge of thin wafers, reducing the mechanical strength of the chip. These methods lack a real-time energy compensation mechanism, making it difficult to eliminate the surface undulations caused by material anisotropy. Summary of the Invention

[0005] The object of the present invention is to provide a multi-stage high-flatness wafer cutting method to solve the problems raised in the above background technology.

[0006] In order to achieve the above object, the present invention provides the following technical solution: a multi-stage high-flatness wafer cutting method, comprising the following steps:

[0007] S1: Wafer pretreatment and stress buffer layer preparation;

[0008] S2: diamond blade layered rough cutting;

[0009] S3: plasma fine cutting and interface repair;

[0010] S4: multi-layer cooling and surface polishing;

[0011] S5: closed-loop detection of surface quality;

[0012] The wafer pretreatment and stress buffer layer preparation include wafer cleaning and stress buffer layer coating, the diamond blade layered rough cutting includes blade parameter configuration and cutting path planning, the plasma fine cutting and interface repair include plasma parameter configuration and interface trimming, the multi-layer cooling and surface polishing include liquid nitrogen cryogenic treatment and chemical mechanical polishing, and the surface quality closed-loop detection includes three-dimensional morphology detection and micro-defect repair.

[0013] As a further technical solution of the present invention, the wafer cleaning includes using a cleaning solution mixed with anhydrous ethanol and deionized water in a volume ratio of 3:1, cleaning at a 40kHz ultrasonic frequency for 15 minutes, and strictly controlling the temperature within the range of 24±0.5℃. After cleaning, the wafer is dried by a 0.2MPa nitrogen air knife at a 45° spray angle to ensure that the surface residual particle density is ≤3 pieces / cm 2 .

[0014] As a further technical solution of the present invention, the stress buffer layer coating includes selecting a polyimide-silicon carbide composite coating material with a thickness of 8 μm and an elastic modulus of 5 GPa, and uniformly covering the wafer surface at a rotation speed of 3000 rpm through a spin coating process. The curing conditions are set to a constant temperature of 150°C for 30 minutes to form a mechanical impact resistance layer.

[0015] As a further technical solution of the present invention, the blade parameter configuration includes using a DAD3650 special diamond blade with a diameter of 55 mm, a thickness of 25 μm, a diamond particle size of 3 μm, a metal bond type, and the cutting parameters are set to a spindle speed of 30,000 rpm, a feed speed of 15 mm / s, and a cutting depth of 80% of the wafer thickness. Real-time feedback adjustment is performed by a laser thickness gauge, and the coolant is deionized water containing 0.5% nano-alumina particles, with a flow rate of 18 L / min and a spray pressure of 0.3 MPa.

[0016] As a further technical solution of the present invention, the cutting path planning includes executing a spiral progressive cutting trajectory with a step size of 4 μm per circle, controlling the cutting path width to 30±1.5 μm, and calibrating the cutting line position deviation in real time to ≤±0.8 μm through a CCD vision system.

[0017] As a further technical solution of the present invention, the plasma parameter configuration includes using an ICP high-density plasma etcher, introducing a gas mixed with CF4 and O2 in a volume ratio of 4:1, a flow rate of 150sccm, the RF power is set to 800W, the bias power is 200W, the etching rate is controlled at 0.8μm / min, and the fine cutting of the remaining 20% ​​of the wafer thickness is completed. The temperature is controlled using a -20°C low-temperature stage, and the wafer surface temperature fluctuation is ≤±3°C.

[0018] As a further technical solution of the present invention, the interface finishing includes helium-assisted plasma post-treatment under the conditions of 0.5 Torr pressure and 50 W power, removing microcracks on the cut surface by ion bombardment, and the surface roughness improvement rate is ≥60%.

[0019] As a further technical solution of the present invention, the liquid nitrogen cryogenic treatment includes using a liquid nitrogen spray pressure of 0.8 MPa, cooling the wafer from room temperature to -196°C at a cooling rate of 10°C / s, and keeping the temperature for 15 minutes to eliminate residual stress.

[0020] As a further technical solution of the present invention, the chemical mechanical polishing includes using SiO2 and CeO2 composite abrasives with a particle size of 50nm, a concentration of 25wt%, a polishing disk speed of 80rpm, a down pressure of 3psi, a polishing time of 8 minutes, and a removal amount of 0.5μm to achieve atomic-level surface flatness.

[0021] As a further technical solution of the present invention, the three-dimensional morphology detection includes detection using a Zygo NewView9000 white light interferometer, requiring a flatness error of ≤1.2μm RMS value, a line width consistency error of ±1.0μm, and use of a focused ion beam FIB for fixed-point repair, with an ion beam energy of 30keV, a repair depth of 0.1-0.3μm, a positioning accuracy of ±50nm, and elimination of nanoscale surface defects.

[0022] The beneficial effects of the present invention are as follows:

[0023] (1) The present invention systematically solves the problems of stress concentration and interface damage in traditional cutting by optimizing gradient energy input and material adaptability. The elastic modulus gradient design of the stress buffer layer effectively absorbs mechanical impact energy, inhibits the extension path of microcracks along the grain boundary, and significantly reduces the risk of collapse at the interface of hard and brittle materials. The layered cutting strategy combines the microscopic self-sharpening effect of diamond tools with the atomic-level etching ability of plasma to achieve differential removal rate matching of heterogeneous materials and simultaneously eliminate copper layer residues and resin carbonization defects. Deep cryogenic treatment induces lattice reconstruction through ultrafast phase transition, blocks the chain reaction of dislocation defects, and restores the intrinsic mechanical strength of the material. The chemical mechanical polishing system activates the self-repairing properties of the material while removing the subsurface damage layer through the synergistic effect of abrasive chemical activity and mechanical shear force, forming an atomic-level smooth interface. The closed-loop detection system relies on multi-dimensional data fusion and ion beam fixed-point repair to achieve precise positioning and performance recovery of cross-scale defects, ensuring the electrical integrity of the chip functional area.

[0024] (2) The present invention achieves a simultaneous leap in cutting quality and device performance through thermal-mechanical-electric multi-field coupling control, and the synergistic effect of plasma etching and helium post-treatment completes interface chemical bond reorganization and micro-region lattice repair in a low-temperature environment, eliminating dielectric loss and crosstalk in high-frequency signal transmission. Spiral progressive cutting path planning is combined with real-time visual feedback, and tool wear and vibration errors are offset by a dynamic compensation mechanism to ensure the consistency of cutting path geometric accuracy. The nanoparticle enhanced cooling system forms a turbulent boundary layer at the tool interface, and suppresses thermally induced phase change and material softening through micro-region heat transfer enhancement to maintain edge cutting stability. White light interferometry detection technology constructs a defect evolution database through global morphology modeling and local feature extraction, providing a data-driven basis for self-optimization of process parameters. Focused ion beam repair technology reconstructs conductive channels and insulating barriers at the nanoscale through precise energy control of sputtering-deposition, and restores the carrier migration characteristics of defective areas. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the overall process of the present invention;

[0026] Figure 2 A schematic diagram of the process of wafer pretreatment and stress buffer layer preparation according to the present invention;

[0027] Figure 3 This is a schematic diagram of the process of rough cutting by a diamond blade in layers according to the present invention;

[0028] Figure 4 Schematic diagram of the process of plasma fine cutting and interface repair of the present invention;

[0029] Figure 5 Schematic diagram of the process of multi-layer cooling and surface polishing of the present invention;

[0030] Figure 6 Schematic diagram of the process of closed-loop detection of surface quality of the present invention. DETAILED DESCRIPTION

[0031] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0032] like Figures 1 to 6 As shown, in an embodiment of the present invention, a multi-stage high-flatness wafer cutting method includes the following steps:

[0033] S1: Wafer pretreatment and stress buffer layer preparation;

[0034] S2: diamond blade layered rough cutting;

[0035] S3: plasma fine cutting and interface repair;

[0036] S4: multi-layer cooling and surface polishing;

[0037] S5: closed-loop detection of surface quality;

[0038] Wafer pretreatment and stress buffer layer preparation include wafer cleaning and stress buffer layer coating, diamond blade layered rough cutting includes blade parameter configuration and cutting path planning, plasma fine cutting and interface repair include plasma parameter configuration and interface trimming, multi-layer cooling and surface polishing include liquid nitrogen cryogenic treatment and chemical mechanical polishing, surface quality closed-loop detection includes three-dimensional morphology detection and micro-defect repair.

[0039] By matching the stress buffer layer design with gradient materials, the impact energy generated by mechanical cutting is effectively absorbed, significantly reducing the risk of wafer delamination and microcrack propagation. Layered rough cutting, combined with spiral progressive trajectory control, efficiently removes material while maintaining edge geometric accuracy. Combined with plasma anisotropic etching, nanoscale interface finishing is achieved, eliminating burrs and heat-affected zones left behind by traditional processes. Cryogenic treatment suppresses dislocation defects through ultra-fast lattice reconstruction, and combined with a chemical-mechanical synergistic polishing mechanism, the surface is atomically smooth, simultaneously improving the chip's electrical signal transmission performance and packaging reliability. The closed-loop quality inspection system integrates multi-dimensional morphology analysis and fixed-point repair technology to ensure the consistency of the physical properties and electrical parameters of the cut surface.

[0040] like Figure 2 As shown, wafer cleaning includes using a cleaning solution mixed with anhydrous ethanol and deionized water in a volume ratio of 3:1, cleaning at a 40kHz ultrasonic frequency for 15 minutes, and strictly controlling the temperature within the range of 24±0.5℃. After cleaning, it is dried with a 0.2MPa nitrogen air knife at a 45° spray angle to ensure that the surface residual particle density is ≤3 pieces / cm 2 The stress buffer layer coating includes selecting a polyimide-silicon carbide composite coating material with a thickness of 8μm and an elastic modulus of 5GPa. The spin coating process is used to evenly cover the wafer surface at a speed of 3000rpm. The curing conditions are set to a constant temperature of 150℃ for 30 minutes to form a mechanical impact resistance layer.

[0041] The synergistic effect of organic solvents and deionized water deeply removes contaminants from the wafer surface. The cavitation effect of high-frequency ultrasound is combined to peel off micro-nano particles, while chemical attack of sensitive materials by cleaning fluids is simultaneously suppressed, laying an atomic-level clean foundation for subsequent processing. Directed airflow control technology is used in the drying stage to eliminate surface oxidation and stress distortion caused by traditional thermal drying, ensuring uniform energy distribution on the wafer surface. The anti-mechanical impact layer constructs a gradient modulus interface on the wafer surface through a molecular-level interpenetrating network of organic-inorganic composite materials. This can not only efficiently absorb the dynamic impact load during the cutting process, but also bridge the substrate micro-defects through the three-dimensional network structure formed by cross-linking and curing, achieving multi-level dissipation of stress waves. The continuous and dense film formed by the spin coating process forms an adaptive interface through thermal curing, dynamically adjusting the stress distribution path during mechanical processing to prevent crack initiation and propagation.

[0042] like Figure 3As shown, the blade parameter configuration includes the use of a DAD3650 special diamond blade with a diameter of 55 mm, a thickness of 25 μm, a diamond particle size of 3 μm, a metal bond type, and the cutting parameters are set to a spindle speed of 30,000 rpm, a feed speed of 15 mm / s, and a cutting depth of 80% of the wafer thickness. Real-time feedback adjustment is performed by a laser thickness gauge. The coolant is deionized water containing 0.5% nano-alumina particles, with a flow rate of 18 L / min and a spray pressure of 0.3 MPa. The cutting path planning includes executing a spiral progressive cutting trajectory with a step size of 4 μm per circle and a cutting lane width control of 30 ± 1.5 μm. The cutting line position deviation is calibrated in real time by a CCD vision system to be ≤ ± 0.8 μm.

[0043] Through the synergistic effect of composite diamond particles and metal binders, stable micro-cutting units are formed at ultra-high speeds, enabling the cutting edge to achieve a balance between self-sharpening and wear resistance during dynamic processing, thereby breaking through the fracture threshold of traditional tools in the processing of hard and brittle materials. Spiral progressive trajectory planning combined with multi-dimensional motion control allows the cutting force to be evenly released along the lattice cleavage plane, while simultaneously suppressing lateral vibration and thermal stress accumulation. The trajectory superposition effect forms a continuous and smooth cutting surface under submicron regulation, greatly reducing the risk of wafer delamination. The cooling system uses the turbulent heat transfer enhancement and boundary lubrication effects of nanoparticles to construct a dynamic thermal resistance barrier at the tool-material interface, blocking phase change damage caused by localized high temperatures. The visual feedback system, based on optical distortion compensation algorithms and sub-pixel feature capture, solves the geometric deviation of the tool posture and cutting path in real time.

[0044] like Figure 4 As shown, the plasma parameter configuration includes using an ICP high-density plasma etcher, introducing a gas mixed with CF4 and O2 in a volume ratio of 4:1, with a flow rate of 150 sccm, the RF power is set to 800 W, the bias power is 200 W, and the etching rate is controlled at 0.8 μm / min to complete the fine cutting of the remaining 20% ​​wafer thickness. The temperature is controlled using a -20°C low-temperature stage, and the wafer surface temperature fluctuation is ≤±3°C. The interface finishing includes helium-assisted plasma post-treatment under 0.5 Torr pressure and 50 W power conditions, and microcracks on the cut surface are removed by ion bombardment, with a surface roughness improvement rate of ≥60%.

[0045] Through the directional energy regulation of high-density plasma, precise dissociation of molecular bonds in wafer materials and efficient discharge of volatile products are achieved, while the degradation of sidewall roughness caused by lateral etching is simultaneously suppressed, providing atomic-level profile control for micro-nanostructures. The low-temperature environment combined with the synergistic effect of multi-band radio frequency reduces lattice thermal vibrations while enhancing the mobility of active particles, allowing chemical etching and physical sputtering to achieve a dynamic balance, effectively blocking the chain expansion of thermally induced defects. Helium-based post-treatment selectively eliminates subsurface lattice distortion layers and microcrack networks through micro-area energy transfer mediated by inert gases, promoting in-situ crystal reconstruction on the material surface and forming a single-crystalline transition interface with low defect density. The photochemical effect generated during the interaction between plasma and material further induces the self-assembly arrangement of surface hydroxyl groups and fluorinated groups, constructing a chemically inert protective layer to improve the environmental stability of the device.

[0046] like Figure 5 As shown, the liquid nitrogen cryogenic treatment includes using a liquid nitrogen spray pressure of 0.8 MPa to cool the wafer from room temperature to -196°C at a cooling rate of 10°C / s, and keeping it warm for 15 minutes to eliminate residual stress. The chemical mechanical polishing includes using SiO2 and CeO2 composite abrasives with a particle size of 50 nm and a concentration of 25 wt%, a polishing disk speed of 80 rpm, a down pressure of 3 psi, a polishing time of 8 minutes, and a removal amount of 0.5 μm to achieve atomic-level surface flatness.

[0047] Through the rapid phase change of liquid nitrogen and the ultra-low temperature energy conduction mechanism, a directional lattice reconstruction effect is induced inside the wafer, and the dislocation defects and residual stress fields accumulated during the material processing are simultaneously eliminated, so that the crystal structure can be restored to its intrinsic orderly arrangement. A densified subsurface layer is formed on the surface of the wafer after cryogenic treatment, which significantly improves the resistance to crack propagation and mechanical strength, creating stable substrate conditions for subsequent processing. The chemical mechanical polishing stage utilizes the interfacial catalytic effect of nano-abrasives. Through the synergistic effect of chemically active substances and mechanical shear force, the surface amorphous damage layer is peeled off layer by layer at the atomic scale, while activating the self-healing properties of the material surface. During the polishing process, the charge interaction between the abrasive and the substrate induces the formation of a dynamic hydration film layer, which not only reduces the friction coefficient but also achieves precise control of the material removal rate.

[0048] like Figure 6 As shown, the three-dimensional morphology detection includes detection using the Zygo NewView 9000 white light interferometer, requiring a flatness error of ≤1.2μm RMS value, a line width consistency error of ±1.0μm, and the use of focused ion beam FIB fixed-point repair with an ion beam energy of 30keV, a repair depth of 0.1-0.3μm, and a positioning accuracy of ±50nm to eliminate nanoscale surface defects.

[0049] A full-surface digital topography model is established through non-contact optical interferometry technology, achieving sub-micron-level full-domain mapping of the wafer surface undulations and linewidth features, providing a precise spatial coordinate reference for subsequent repairs. High-density ion beam fixed-point repair technology constructs an energy gradient distribution based on topography data, selectively eliminating subsurface lattice distortion through a dual mechanism of ion sputtering and surface reconstruction, while simultaneously maintaining the electrical integrity of the substrate material. The spectral confocal characteristics of the white light interferometer can penetrate the surface of the repair area and monitor the evolution of the interface morphology in real time, forming a dynamic closed-loop control of detection-repair-verification. The nano-level positioning system, combined with a multimodal data fusion algorithm, eliminates microscopic defects while accurately avoiding the functional circuit area, ensuring the structural integrity of the effective area of ​​the device.

[0050] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A multi-stage high-flatness wafer cutting method, characterized by: The following steps are involved: S1: Wafer pretreatment and stress buffer layer preparation; S2: diamond blade layered rough cutting; S3: plasma fine cutting and interface repair; S4: multi-layer cooling and surface polishing; S5: closed-loop detection of surface quality; The wafer pretreatment and stress buffer layer preparation include wafer cleaning and stress buffer layer coating, the diamond blade layered rough cutting includes blade parameter configuration and cutting path planning, the plasma fine cutting and interface repair include plasma parameter configuration and interface trimming, the multi-layer cooling and surface polishing include liquid nitrogen cryogenic treatment and chemical mechanical polishing, and the surface quality closed-loop detection includes three-dimensional morphology detection and micro-defect repair.

2. The multi-stage high-flatness wafer cutting method according to claim 1, characterized in that: The wafer cleaning process involves using a mixture of anhydrous ethanol and deionized water in a volume ratio of 3:1, cleaning at a 40kHz ultrasonic frequency for 15 minutes, and strictly controlling the temperature within the range of 24±0.5°C. After cleaning, the wafer is dried using a 0.2MPa nitrogen air knife at a 45° spray angle to ensure that the surface residual particle density is ≤3 particles / cm 2 .

3. The multi-stage high-flatness wafer cutting method according to claim 1, characterized in that: The stress buffer layer coating includes selecting a polyimide-silicon carbide composite coating material with a thickness of 8 μm and an elastic modulus of 5 GPa, uniformly covering the wafer surface at a rotation speed of 3000 rpm through a spin coating process, and setting the curing conditions to a constant temperature of 150° C. for 30 minutes to form an anti-mechanical impact layer.

4. The multi-stage high-flatness wafer cutting method according to claim 1, characterized in that: The blade parameter configuration includes using a DAD3650 special diamond blade with a diameter of 55 mm, a thickness of 25 μm, a diamond particle size of 3 μm, a metal bond type, and the cutting parameters are set to a spindle speed of 30,000 rpm, a feed speed of 15 mm / s, a cutting depth of 80% of the wafer thickness, and real-time feedback adjustment through a laser thickness gauge. The coolant is deionized water containing 0.5% nano-alumina particles, with a flow rate of 18 L / min and a spray pressure of 0.3 MPa.

5. The multi-stage high-flatness wafer cutting method according to claim 1, characterized in that: The cutting path planning includes executing a spiral progressive cutting trajectory with a step size of 4 μm per circle, controlling the cutting path width to 30±1.5 μm, and calibrating the cutting line position deviation in real time to ≤±0.8 μm through a CCD vision system.

6. The multi-stage high-flatness wafer cutting method according to claim 1, characterized in that: The plasma parameter configuration includes using an ICP high-density plasma etcher, introducing a gas mixture of CF4 and O2 in a volume ratio of 4:1, a flow rate of 150 sccm, setting the RF power to 800 W, the bias power to 200 W, and controlling the etching rate at 0.8 μm / min to complete the fine cutting of the remaining 20% ​​of the wafer thickness. The temperature is controlled using a -20°C low-temperature stage, and the wafer surface temperature fluctuation is ≤±3°C.

7. The multi-stage high-flatness wafer cutting method according to claim 1, characterized in that: The interface finishing includes helium-assisted plasma post-treatment under the conditions of 0.5 Torr pressure and 50W power, removing microcracks on the cut surface by ion bombardment, and improving the surface roughness by ≥60%.

8. The multi-stage high-flatness wafer cutting method according to claim 1, characterized in that: The liquid nitrogen cryogenic treatment includes using a liquid nitrogen spray pressure of 0.8 MPa, cooling the wafer from room temperature to -196° C. at a cooling rate of 10° C. / s, and keeping the temperature for 15 minutes to eliminate residual stress.

9. The multi-stage high-flatness wafer cutting method according to claim 1, characterized in that: The chemical mechanical polishing includes using SiO2 and CeO2 composite abrasives with a particle size of 50nm and a concentration of 25wt%, a polishing disk speed of 80rpm, a down pressure of 3psi, a polishing time of 8 minutes, and a removal amount of 0.5μm to achieve atomic-level surface flatness.

10. The multi-stage high-flatness wafer cutting method according to claim 1, characterized in that: The three-dimensional morphology detection includes detection using a Zygo NewView 9000 white light interferometer, requiring a flatness error of ≤1.2μm RMS value and a line width consistency error of ±1.0μm. Focused ion beam FIB fixed-point repair is used with an ion beam energy of 30keV, a repair depth of 0.1-0.3μm, and a positioning accuracy of ±50nm to eliminate nanoscale surface defects.

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