Ultrathin multi-layer memory chip stacking and packaging method and system

Abstract

The invention relates to the technical field of chip packaging, and discloses an ultrathin multi-layer storage chip stacking packaging method, which comprises the following steps of: obtaining a storage chip to be packaged, performing chip quality division on the storage chip to be packaged to obtain a target chip, and performing fine classification on the target chip to obtain a plurality of groups of chips; performing thickness optimization on the multiple groups of divided chips to obtain thickness-optimized chips, and performing chip selection on the thickness-optimized chips to obtain selected chips; performing material coating on the selected chip to obtain a coated chip, performing chip curing on the coated chip to obtain a cured chip, and performing chip stacking on the cured chip to obtain a stacked chip; carrying out three-dimensional modeling on the stacked chips so as to carry out dispensing path planning on the stacked chips to obtain a dispensing path, and carrying out chip reinforcement on the stacked chips to obtain reinforced chips; and performing internal interconnection, preliminary packaging and shell injection molding on the reinforced chip to obtain a packaged chip. According to the invention, the packaging quality of the ultrathin multi-layer memory chip can be improved.

Description

Technical Field

[0001] The invention relates to an ultra-thin multi-layer storage chip stacking packaging method, belonging to the technical field of chip packaging. Background Art

[0002] As modern electronic devices are rapidly developing towards miniaturization and high performance, ultra-thin multi-layer memory chip stacking packaging technology has become the key to improving the capacity and performance of memory chips. It can greatly expand storage capacity in a limited space by precisely stacking multiple memory chips and packaging them reasonably, meeting the needs of many smart terminals and other devices.

[0003] At present, when implementing ultra-thin multi-layer memory chip stacking packaging, the initial chip is first prepared, and pre-processing work such as cutting, cleaning, and thinning is performed; then the intermediate layer is prepared, the chip is aligned and stacked and temporarily fixed, and then the stacking operation is repeated until the designed number of layers is reached; then the vias are drilled to achieve internal interconnection, connect the chip and the packaging substrate, and after welding, the bottom filling and external protection molding are performed, and finally the finished product is inspected to ensure quality. However, the existing methods have certain defects. In the chip pretreatment link, the precision control of thinning and other operations is difficult, and uneven thickness is prone to affect subsequent stacking. In the chip stacking process, it is difficult to ensure high-precision alignment of each layer of chips by relying solely on conventional positioning methods. When the number of layers increases, the accumulated deviation will interfere with the electrical connection. In the internal interconnection stage, the process of via drilling and metal layer deposition is complicated, and the problem of poor conductivity will occur if there is a slight mistake. In addition, welding defects such as cold solder joints and voids are prone to occur during welding, and the bottom filling may also cause stress hazards due to uneven filling, resulting in low chip packaging quality. Summary of the invention

[0004] In order to solve the above problems, the present invention provides an ultra-thin multi-layer memory chip stacking packaging method, which can improve the packaging quality of the ultra-thin multi-layer memory chip.

[0005] To achieve the above object, the present invention provides an ultra-thin multi-layer memory chip stacking packaging method, comprising:

[0006] Acquire a memory chip to be packaged, perform an optical scan on the memory chip to be packaged to obtain a scanned image, use the scanned image to analyze the surface defect degree and circuit integrity of the memory chip to be packaged, perform chip quality classification on the memory chip to be packaged based on the surface defect degree and the circuit integrity, extract chips that meet the preset quality after chip quality classification to obtain target chips, use the scanned image to identify the chip thickness and pad distribution state of the target chip, and sub-classify the target chip based on the chip thickness and the pad distribution state to obtain multiple groups of chips;

[0007] Using a preconfigured thickness sensor, measure the chip thickness of each group of chips in the multiple groups of chips to obtain thickness measurement data, use the thickness measurement data to construct a preferred thickness range for the multiple groups of chips, optimize the thickness of the multiple groups of chips based on the preferred thickness range to obtain thickness-optimized chips, perform quality inspection on the thickness-optimized chips, and select the thickness-optimized chips according to the inspection results of the quality inspection to obtain selected chips;

[0008] Querying material parameters of the selected chip, and configuring the middle layer material of the selected chip based on the material parameters, coating the selected chip with material using the middle layer material to obtain a coated chip, curing the coated chip with a preconfigured curing characteristic curve to obtain a cured chip, identifying the identification attribute and the middle layer position of the cured chip, planning a stacking path for the cured chip based on the identification attribute and the middle layer position to obtain a planned path, and stacking the cured chips based on the planned path to obtain a stacked chip;

[0009] Querying the stacking structure of the stacked chip, and based on the stacking structure, performing three-dimensional modeling on the stacked chip to obtain a stacked chip model, using the stacked chip model to perform glue dispensing path planning on the stacked chip to obtain a glue dispensing path, and based on the glue dispensing path, performing chip reinforcement on the stacked chip to obtain a reinforced chip;

[0010] Query the three-dimensional model and circuit layout information of the reinforced chip to interconnect the reinforced chip internally to obtain a link chip, query the stacking parameters and filling requirements of the link chip to preliminarily package the link chip to obtain a preliminarily packaged chip, identify the process parameters of the preliminarily packaged chip, and based on the process parameters, perform shell injection molding on the preliminarily packaged chip to obtain a packaged chip.

[0011] Optionally, analyzing the surface defect degree and circuit integrity of the memory chip to be packaged by using the scanned image includes:

[0012] Gray-scale the scanned image to obtain a gray-scale image;

[0013] Performing image surface detection on the grayscale image to determine the surface defect profile of the memory chip to be packaged;

[0014] Performing defect morphology processing on the surface defect profile to obtain a refined defect state;

[0015] Quantifying the refined defect state to determine the surface defect degree of the memory chip to be packaged;

[0016] Using the scanned image to identify circuit wiring features of the memory chip to be packaged;

[0017] The circuit wiring characteristics are used to identify the circuit integrity of the memory chip to be packaged.

[0018] Optionally, the identifying the chip thickness and pad distribution state of the target chip by using the scanned image includes:

[0019] Extracting a vertical boundary contour area of ​​the scanned image;

[0020] Calculate the vertical pixel value of the vertical boundary contour area;

[0021] Performing size conversion on the vertical pixel value to obtain the chip thickness of the target chip;

[0022] Performing target detection on the scanned image to obtain a detected target;

[0023] Identifying feature points of the detection target;

[0024] The shape, size and distance characteristics of the pads corresponding to the target chip are analyzed based on the characteristic points, and the number and arrangement of the pads are counted to determine the pad distribution state.

[0025] Optionally, identifying feature points of the detection target includes:

[0026] Constructing a scale space of the detection target;

[0027] Marking key points of the detection target in the scale space to obtain marked key points;

[0028] After the directions of the marked key points are assigned, the marked key points are characterized by using the following formula to obtain the feature points:

[0029]

[0030] Among them, M represents the feature point, H represents the image gradient value of the scanned image corresponding to the detected target, θ represents the direction of the marked key point, L represents the scanned image, L(A+1, B), L(A-1, B), L(A, B+1), and L(A, B-1) represent the neighboring points of the origin L(A, B) of the scanned image in the scale space.

[0031] Optionally, the performing quality inspection on the thickness optimization chip includes:

[0032] collecting a microscopic image of the thickness optimized chip;

[0033] identifying detailed features of the microscopic image;

[0034] Performing appearance inspection on the thickness optimized chip using the refined features;

[0035] Constructing multiple test patterns and test vectors of the thickness optimized chip;

[0036] After inputting a preset electrical signal into the thickness optimization chip, a circuit performance test is performed on the thickness optimization chip according to the multiple test modes and test vectors;

[0037] Configuring a high temperature aging test environment and a temperature and humidity cycle test environment for the thickness optimization chip, so as to perform a reliability test on the thickness optimization chip by using the high temperature aging test environment and the temperature and humidity cycle test environment;

[0038] After the appearance inspection, circuit performance inspection and reliability test are completed, the quality inspection of the thickness optimized chip is completed.

[0039] Optionally, the method of using the intermediate layer material to coat the selected chip with a material to obtain a coated chip includes:

[0040] Inquiring the material properties of the intermediate layer material and the chip size of the selected chip to configure a corresponding coating device;

[0041] Obtaining coating accuracy requirements for the selected chip;

[0042] Based on the coating accuracy requirement, parameters of the coating device are set to obtain a debugging device;

[0043] The debugging device is used to coat the selected chip with material to obtain a coated chip.

[0044] Optionally, performing stacking path planning for the cured chip based on the identification attribute and the position of the intermediate layer to obtain a planned path includes:

[0045] Determining a stacking order of the cured chips according to the identification attributes;

[0046] Determining a chip alignment method of the solidified chips when stacking according to the position of the intermediate layer;

[0047] Querying the device motion characteristics of the stacking device corresponding to the solidified chip;

[0048] Based on the stacking sequence, the chip alignment method and the device motion characteristics, constructing stacking constraints of the solidified chip;

[0049] constructing an initial stacking path of the cured chips;

[0050] Based on the stacking constraint, preliminarily screening the initial stacking path to obtain a screening path;

[0051] Using a preconfigured ant colony algorithm, a global search is performed on the screening path to obtain a search pheromone;

[0052] The search pheromone is updated using the following formula to obtain the updated pheromone:

[0053] γ ij (T+1)=(1-θ)·γ ij (T)+Δγ ij

[0054] Among them, γ ij (t+1) represents the update pheromone, θ represents the decay coefficient of the search pheromone, γ ij (t) represents the search pheromone concentration from path i to path j at time t, Δγ ij represents the newly added pheromone concentration, T represents the time when the search for pheromones begins,

[0055] Based on the updated pheromone, calculating the probability value of each path in the screening path being selected;

[0056] A stacking path of the solidified chips is selected based on the probability value to obtain a planned path.

[0057] Optionally, the calculating, based on the update pheromone, a probability value of each path in the screening path being selected includes:

[0058] The probability value of each path being selected in the screening path is calculated using the following formula:

[0059]

[0060] Among them, P represents the probability value, τ ij (t) represents the updated pheromone concentration, η ij represents heuristic information, α represents the pheromone importance factor, β represents the heuristic information importance factor, k∈allowed k It represents the set of next paths that can be selected at the current node k, that is, the set of all candidate paths that meet the constraints.

[0061] Optionally, the using the stacked chip model to plan a dispensing path for the stacked chip to obtain a dispensing path includes:

[0062] constructing an initial dispensing path for the stacked chips;

[0063] Creating a dispensing simulation scene of the stacked chip according to the stacked chip model;

[0064] Using the initial dispensing path as a simulation animation trajectory of the stacked chips;

[0065] Performing glue dispensing simulation on the stacked chips according to the glue dispensing simulation scene and the simulation animation trajectory;

[0066] The stacked chip dispensing path is determined based on the simulation result of the dispensing simulation.

[0067] In a second aspect, the present invention provides an ultra-thin multi-layer memory chip stacking packaging system, the system comprising:

[0068] A chip classification module is used to obtain a memory chip to be packaged, optically scan the memory chip to be packaged to obtain a scanned image, analyze the surface defect degree and circuit integrity of the memory chip to be packaged by using the scanned image, perform chip quality classification on the memory chip to be packaged based on the surface defect degree and the circuit integrity, extract chips that meet the preset quality after chip quality classification to obtain target chips, identify the chip thickness and pad distribution state of the target chip by using the scanned image, and perform sub-classification on the target chip based on the chip thickness and the pad distribution state to obtain multiple groups of chips;

[0069] A chip selection module is used to measure the chip thickness of each group of chips in the multiple groups of chips by using a preconfigured thickness sensor to obtain thickness measurement data, construct a preferred thickness range for the multiple groups of chips by using the thickness measurement data, optimize the thickness of the multiple groups of chips based on the preferred thickness range to obtain thickness-optimized chips, perform quality inspection on the thickness-optimized chips, and select the thickness-optimized chips according to the inspection results of the quality inspection to obtain selected chips;

[0070] a chip stacking module, for querying the material parameters of the selected chip, and configuring the middle layer material of the selected chip based on the material parameters, coating the selected chip with the middle layer material to obtain a coated chip, curing the coated chip with a preconfigured curing characteristic curve to obtain a cured chip, identifying the identification attribute and the middle layer position of the cured chip, planning a stacking path for the cured chip based on the identification attribute and the middle layer position to obtain a planned path, and stacking the cured chips based on the planned path to obtain a stacked chip;

[0071] A chip reinforcement module, used for querying the stacking structure of the stacked chips, and based on the stacking structure, performing three-dimensional modeling on the stacked chips to obtain a stacked chip model, using the stacked chip model to perform glue dispensing path planning on the stacked chips to obtain a glue dispensing path, and based on the glue dispensing path, performing chip reinforcement on the stacked chips to obtain a reinforced chip;

[0072] The chip packaging module is used to query the three-dimensional model and circuit layout information of the reinforced chip to interconnect the reinforced chip internally to obtain a link chip, query the stacking parameters and filling requirements of the link chip to perform preliminary packaging of the link chip to obtain a preliminary packaged chip, identify the process parameters of the preliminary packaged chip, and based on the process parameters, perform shell injection molding on the preliminary packaged chip to obtain a packaged chip.

[0073] Compared with the problems described in the background technology, the present invention first divides the chip quality of the storage chip to be packaged based on the surface defect degree and the circuit integrity, which can facilitate the subsequent targeted processing of chips of different qualities. For example, high-quality chips can be used in packaging products with higher quality requirements, and medium-quality chips can be used in some scenarios with slightly lower performance requirements or used after additional processing according to actual conditions, which is helpful to reasonably allocate resources, improve overall packaging efficiency and ensure that the quality of the final packaged product adapts to different needs; further, the embodiment of the present invention uses a pre-configured thickness sensor to measure the chip thickness of each group of chips in the multiple groups of chips, and the thickness measurement data obtained can be used to determine whether the chip meets the expected process requirements. At the same time, it also provides an accurate reference basis for further optimizing the chip thickness, which is an important basic link to ensure the accuracy and quality of the entire packaging process. By using the thickness measurement data, the preferred thickness interval of the multiple groups of chips is constructed to determine an ideal thickness range, that is, the preferred thickness interval. This interval is set after comprehensively considering multiple factors such as the bonding accuracy between the layers of the chips when stacked, the size requirements after the overall packaging, etc., which can maximize the guarantee of the smooth progress of subsequent packaging and the stability of product performance; further, the present invention queries the material parameters of the selected chip, and configures the intermediate layer material of the selected chip based on the material parameters, so as to fully and deeply understand the various material characteristics of the selected chip, including the chemical composition The key elements such as composition, physical properties (such as hardness, thermal expansion coefficient, dielectric constant, etc.) and surface state are determined to provide an accurate data basis for the reasonable selection and configuration of subsequent intermediate layer materials, ensuring that the intermediate layer and the chip can achieve good adaptation in many aspects such as physics and chemistry, and then use the intermediate layer material to fix the selected chip, and use the pre-configured curing characteristic curve to cure the coated chip to obtain a cured chip that can better fix the chip position, enhance the bonding force between chips, and prevent the chip from being displaced or loosened during subsequent use. The present invention queries the stacking structure of the stacked chips, and based on the stacking structure, three-dimensionally models the stacked chips to obtain a stacked chip model that can help The invention is used to analyze the overall performance characteristics of the stacked chips and the possible weak links. For example, by understanding the stacking method of the chips, its performance in terms of heat conduction, electrical connection, etc. can be estimated, providing a basis for optimizing chip performance. At the same time, the reliability risks that may be caused by unreasonable stacking structure can be discovered in advance. Based on the dispensing path, the stacked chips are reinforced to obtain reinforced chips. The structural integrity of the stacked chips can be maintained through effective chip reinforcement, and good electrical connection and thermal conductivity performance between chips can be guaranteed, ensuring that the chips can continuously and stably perform their functions during long-term use. It plays an important supporting role in the performance and life of the entire electronic product, and helps to improve the overall quality of the product and user satisfaction.Furthermore, the present invention performs shell injection molding on the preliminary packaged chip based on the process parameters to obtain the packaged chip. According to the identified process parameters, an appropriate injection mold and injection molding material (such as commonly used engineering plastics ABS, PP, etc.) are selected, and the preliminary packaged chip is placed at a specific position of the injection mold. The molten injection molding material is injected into the mold cavity by the injection molding machine according to the set mold temperature, injection molding pressure, injection speed and other process parameters, so that it is wrapped around the preliminary packaged chip, and a solid shell is formed after cooling and solidification, and finally a packaged chip is obtained. The shell injection molding operation is performed by the injection molding machine according to the parameter setting, and finally a packaged chip is obtained, thereby improving the packaging quality of the ultra-thin multi-layer memory chip. ; BRIEF DESCRIPTION OF THE DRAWINGS

[0074] Figure 1 A schematic diagram of a process for stacking and packaging ultra-thin multi-layer memory chips provided by an embodiment of the present invention;

[0075] Figure 2 A schematic diagram of a module of an ultra-thin multi-layer memory chip stacking packaging system provided by an embodiment of the present invention.

[0076] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments. DETAILED DESCRIPTION

[0077] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0078] The embodiment of the present application provides an ultra-thin multi-layer memory chip stacking packaging method. The execution subject of the ultra-thin multi-layer memory chip stacking packaging method includes but is not limited to at least one of the electronic devices such as a server and a terminal that can be configured to execute the method provided by the embodiment of the present application. In other words, the ultra-thin multi-layer memory chip stacking packaging method can be executed by software or hardware installed in a terminal device or a server device. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0079] Embodiment 1:

[0080] Reference Figure 1 FIG. 1 is a flow chart of an ultra-thin multi-layer memory chip stacking packaging method provided by an embodiment of the present invention. In this embodiment, the ultra-thin multi-layer memory chip stacking packaging method includes:

[0081] S1. Obtain a memory chip to be packaged, optically scan the memory chip to be packaged to obtain a scanned image, use the scanned image to analyze the surface defect degree and circuit integrity of the memory chip to be packaged, classify the memory chip to be packaged based on the surface defect degree and the circuit integrity, extract chips that meet the preset quality after chip quality classification, obtain target chips, use the scanned image to identify the chip thickness and pad distribution status of the target chip, and sub-classify the target chip based on the chip thickness and the pad distribution status to obtain multiple groups of chips.

[0082] The embodiment of the present invention can clarify the beginning of the work by obtaining the memory chip to be packaged, ensuring that the corresponding chips are available for processing in the subsequent packaging process, which is a prerequisite for the orderly development of the entire packaging process. Among them, the memory chip to be packaged refers to an ultra-thin memory chip that has completed the main basic processes such as circuit manufacturing and wafer processing in the chip manufacturing process, but has not yet been packaged.

[0083] Optionally, the memory chips to be packaged can be obtained by selecting a suitable chip batch from memory chips in stock according to packaging project requirements.

[0084] The embodiment of the present invention optically scans the memory chip to be packaged to obtain a scanned image, which can obtain intuitive image information of the appearance and part of the internal structure of the memory chip, and present the actual physical state of the chip in a visual form. These images can reflect many detailed features of the chip and provide a data basis for subsequent analysis work.

[0085] Optionally, the scanned image may be scanned by a professional chip surface detection scanner, such as a laser chip scanner.

[0086] Furthermore, the embodiments of the present invention can accurately grasp the key quality indicators of the chip by utilizing the scanned image to analyze the surface defects and circuit integrity of the storage chip to be packaged. The surface defects are related to the stability and reliability of the chip after packaging, and the circuit integrity directly determines whether the chip can work normally. Through this analysis, chips with quality risks can be discovered in advance, avoiding subsequent packaging of chips with problems, thereby ensuring the quality of the final packaged product.

[0087] As an embodiment of the present invention, the use of the scanned image to analyze the surface defect degree and circuit integrity of the memory chip to be packaged includes: graying the scanned image to obtain a grayscale image, performing image surface detection on the grayscale image to determine the surface defect contour of the memory chip to be packaged, performing defect morphology processing on the surface defect contour to obtain a refined defect state, quantifying the refined defect state to determine the surface defect degree of the memory chip to be packaged, using the scanned image to identify the circuit wiring features of the memory chip to be packaged, and using the circuit wiring features to identify the circuit integrity of the memory chip to be packaged.

[0088] Among them, the grayscale image refers to an image representation that only contains brightness information but no color information. The surface defect contour refers to the boundary shape of the defective part of the object surface in the image (usually an image that has been processed to a certain extent, such as a binary image, etc.). It outlines the boundary between the defective area and the normal area. Through this contour, we can intuitively understand the shape, size and specific location of the defect on the surface of the object. The circuit wiring feature refers to the layout, direction, width, spacing and interconnection relationship of the circuit in the electronic circuit on the substrate (such as PCB board) or the inside of the chip.

[0089] Optionally, the grayscale image can be obtained by binarizing the scanned image, the surface defect contour of the memory chip to be packaged can be obtained by using the Canny edge detection algorithm to perform edge detection on the grayscale image to identify defects such as scratches and cracks on the chip surface, the refined defect state can be obtained by corroding and dilating the image area corresponding to the surface defect contour, the quantification of the refined defect state to determine the surface defect degree of the memory chip to be packaged can be achieved by using a threshold segmentation algorithm to separate the defect area from the background according to the difference in grayscale value between the chip surface material and the defective part, and counting indicators such as the area and number of the defective area to quantify the surface defect degree, the circuit wiring feature can be obtained by extracting the width and continuity of the circuit line using a winding machine model, and the identification of the circuit integrity of the memory chip to be packaged using the circuit wiring feature can be achieved by comparing the circuit wiring feature with a standard, defect-free circuit wiring template using a pattern recognition algorithm to check whether there is a line interruption, short circuit, etc.

[0090] The embodiment of the present invention can facilitate the subsequent targeted processing of chips of different qualities by classifying the chip quality of the storage chip to be packaged based on the surface defect degree and the circuit integrity. For example, high-quality chips can be used in packaging products with higher quality requirements, and medium-quality chips can be used in some scenarios with slightly lower performance requirements or used after additional processing according to actual conditions, which helps to reasonably allocate resources, improve overall packaging efficiency, and ensure that the quality of the final packaged product adapts to different needs.

[0091] Optionally, the chip quality classification of the memory chip to be packaged is performed based on the surface defect degree and the circuit integrity. According to the specific requirements of the packaging project and the general specifications for the quality of memory chips in the industry, detailed chip quality classification standards are formulated. For example, a threshold value of the ratio of the total area of ​​surface defects to the total area of ​​the chip is set (such as less than 0.1% for high quality, 0.1%-0.5% for medium quality, etc.), and at the same time, different levels of evaluation criteria for circuit integrity are stipulated, such as if there is no open circuit or short circuit and the circuit connections of each functional module are normal, it is high quality, and if there are a small number of repairable line problems, it is medium quality, etc., the data obtained through surface defect degree and circuit integrity analysis are compared with the formulated quality classification standards, and by writing corresponding program codes or using professional data analysis software, a quality grade label is automatically added to each chip, and the chips are classified into corresponding different quality sets such as high quality, medium quality, and low quality, to achieve chip quality classification.

[0092] Furthermore, the embodiment of the present invention obtains the target chip by extracting the chips that meet the preset quality after chip quality classification, which can further ensure that the chips involved in packaging are of expected quality, reduce the possibility of packaging failure or poor performance of the packaged product due to initial chip quality problems, and lay the foundation for creating high-quality packaged storage chip products.

[0093] Optionally, the target chip can be determined based on the goal of this packaging task. For example, if the goal is to produce high-quality memory chip packaging products for high-end electronic products, then the preset quality is clearly set as a high-quality chip. If it is only for packaging some ordinary electronic products with slightly lower performance requirements, the requirements can be appropriately relaxed, and chips of medium quality and above can be selected. The specific preset quality grade range is determined and extracted from the corresponding memory chips to be packaged after chip quality classification.

[0094] Furthermore, the embodiment of the present invention ensures that the subsequent packaging process can be accurately adapted and optimized according to the actual situation of the chip by using the scanned image to identify the chip thickness and pad distribution status of the target chip, thereby improving the accuracy and reliability of packaging.

[0095] As an embodiment of the present invention, the use of the scanned image to identify the chip thickness and pad distribution status of the target chip includes: extracting the vertical boundary contour area of ​​the scanned image, calculating the vertical pixel value of the vertical boundary contour area, converting the vertical pixel value to size to obtain the chip thickness of the target chip, performing target detection on the scanned image to obtain a detection target, identifying feature points of the detection target, analyzing the shape, size and distance characteristics of the pads corresponding to the target chip based on the feature points, and counting the number and arrangement of the pads to determine the pad distribution status.

[0096] Optionally, the extraction of the vertical boundary contour area of ​​the scanned image can be achieved by using image processing software (such as ImageJ, OpenCV, etc.), identifying the vertical boundary in the image through an edge detection algorithm (such as Canny edge detection), and then using a contour extraction function to extract the vertical boundary contour area. The vertical pixel value of the vertical boundary contour area can be selected by OpenCV to extract the vertical boundary contour area, and a pixel value statistical tool is used to perform statistical analysis on the pixel values ​​in the vertical direction in the area to obtain the corresponding value. The chip thickness can be based on a known ratio between image pixels and actual sizes (determined in advance by calibration), and the vertical pixel value is converted into an actual physical size according to the ratio, thereby obtaining the chip thickness. For example, 1 pixel corresponds to an actual 0.1 mm. Based on this conversion, the detection target can be detected with the help of a deep learning target detection framework (such as YOLO, Faster R-CNN, etc.), input the scanned image data with the relevant categories of the target chip labeled for training, and then use the trained model to detect the new scanned image. The pad distribution state can be obtained by analyzing the coordinates and distribution of the feature points, combining with the geometric calculation method, calculating the approximate shape, size and distance between the pads, and at the same time counting the number and arrangement order of the pads corresponding to the feature points, and then determining its distribution state.

[0097] Further, as an optional embodiment of the present invention, the identifying feature points of the detection target includes: constructing a scale space of the detection target, marking key points of the detection target in the scale space to obtain marked key points, assigning directions to the marked key points, and determining feature points of the marked key points using the following formula to obtain feature points:

[0098]

[0099] Among them, M represents the feature point, H represents the image gradient value of the scanned image corresponding to the detected target, θ represents the direction of the marked key point, L represents the scanned image, L(A+1, B), L(A-1, B), L(A, B+1), and L(A, B-1) represent the neighboring points of the origin L(A, B) of the scanned image in the scale space.

[0100] Furthermore, the embodiment of the present invention subclassifies the target chip based on the chip thickness and the pad distribution state to obtain multiple groups of chips, thereby improving the accuracy and efficiency of the chip in the packaging process, and can facilitate more accurate and efficient operations in the packaging process. For example, chips in the same group can more easily ensure the alignment accuracy between layers when stacked, and can be better matched when making electrical connections, which helps to improve the orderliness of the entire packaging process and the quality consistency of the final packaged products.

[0101] Optionally, the target chip is subclassified based on the chip thickness and the pad distribution state to obtain multiple groups of chips. The classification intervals and grouping rules of chip thickness and pad distribution state can be determined according to the actual needs and experience of the chip packaging process. For example, the chip thickness is divided into a group every certain micron value range (such as 0-50 microns as a group, 50-100 microns as a group, etc.), and the pad distribution state is classified according to the arrangement of the pads, the spacing range and other characteristics (such as grouping those with the same array arrangement and similar spacing into one group, etc.).

[0102] S2. Using a preconfigured thickness sensor, measure the chip thickness of each group of chips in the multiple groups of chips to obtain thickness measurement data; using the thickness measurement data, construct a preferred thickness range for the multiple groups of chips; based on the preferred thickness range, perform thickness optimization on the multiple groups of chips to obtain thickness optimized chips; perform quality inspection on the thickness optimized chips; and based on the inspection results of the quality inspection, perform chip selection on the thickness optimized chips to obtain selected chips.

[0103] The embodiment of the present invention uses the preconfigured thickness sensor to measure the chip thickness of each group of chips in the multiple groups of chips. The thickness measurement data obtained can be used to determine whether the chip meets the expected process requirements. It also provides an accurate reference basis for further optimizing the chip thickness, which is an important basic link to ensure the accuracy and quality of the entire packaging process.

[0104] Among them, the thickness sensor refers to a sensor used to measure the thickness of an object. It can convert the physical quantity of the thickness of the object into an electrical signal or other form of signal that can be measured and analyzed, and then obtain the specific value of the thickness. The appropriate thickness sensor can be selected according to factors such as the chip size, accuracy requirements and measurement environment. For example, for high-precision requirements and small chip sizes, a laser thickness sensor can be selected. It measures the distance by emitting a laser beam and receiving reflected light, and then obtains the chip thickness. For larger chips and moderate accuracy requirements, capacitive or inductive thickness sensors can also be selected, which detect thickness based on the influence of different media on electric or magnetic fields.

[0105] The embodiment of the present invention utilizes the thickness measurement data to construct the preferred thickness intervals of the multiple groups of chips, and can determine an ideal thickness range, i.e., the preferred thickness interval. This interval is set after comprehensively considering multiple factors such as the fitting accuracy between the layers of the chips when stacked, the dimensional requirements after the overall packaging, etc., and can maximize the smooth progress of subsequent packaging and the stability of product performance.

[0106] Optionally, the preferred thickness range can be determined by comprehensively considering the requirements of the subsequent stacking packaging process for chip thickness and relevant standards and specifications in the industry, combined with actual production experience. On the one hand, the maximum and minimum thickness ranges allowed are analyzed to ensure good bonding between layers when the chips are stacked and to avoid problems such as structural instability caused by cumulative thickness errors; on the other hand, the chip thickness range used by successful packaged products of the same type is used as a reference. For example, after analysis and empirical judgment, for a certain type of memory chip, its preferred thickness range is determined to be [50μm, 80μm], that is, chips with thickness within this range can better meet the process requirements in the subsequent packaging process, and the specific needs need to be set in combination with actual applications.

[0107] The embodiment of the present invention optimizes the thickness of the multiple groups of chips based on the preferred thickness range to obtain thickness-optimized chips, which can reduce problems such as alignment deviation and poor connection caused by thickness differences, improve the electrical performance and overall stability of the packaged product, and ensure that the packaging quality reaches a high level.

[0108] Optionally, the thickness optimization of the multiple groups of chips is performed to obtain thickness optimized chips. The thickness measurement data of each group of chips can be compared with the determined preferred thickness range. By writing a program script or using a database query statement, the chips are divided into three categories according to their thickness: chips with a thickness greater than the upper limit of the range (need to be thinned), chips with a thickness within the range (no need to be processed, directly used as part of the thickness optimization) and chips with a thickness less than the lower limit of the range (need to be thickened or other compensatory measures), and classified according to the thickness range, such as thinning (for chips with thickness exceeding the upper limit): For chips that need to be thinned, place them on a high-precision chip grinding device, which has precise speed, pressure and grinding time control functions. According to the specific value of the chip exceeding the preferred thickness range, combined with factors such as chip material and size, set appropriate grinding parameters. For example, if the chip thickness exceeds the upper limit by 10μm, the speed of the grinding equipment can be set to 5000 rpm and the grinding pressure to 0.5N / cm 2 The grinding operation is performed with parameters such as grinding time of 2 minutes. During the grinding process, the online thickness monitoring system is used to monitor the change of chip thickness in real time. When the chip thickness reaches the optimal range, the grinding operation is stopped.

[0109] Thickening or compensatory measures (for chips with thickness below the lower limit): For chips with thickness slightly below the lower limit, if the chip structure allows, the chip can be appropriately thickened by adding a thin layer of polymer material with good chip compatibility as an intermediate layer on the chip surface. Use high-precision coating equipment to accurately control the flow rate, coating speed and other parameters of the coating material according to the calculated thickness value required for thickening, and evenly coat the intermediate layer material on the chip surface so that the chip thickness reaches the preferred range; or in the subsequent stacking process, by adjusting the thickness of other matching chips or intermediate layers, the total thickness of the stacking structure can meet the requirements as a whole, and finally complete the thickness optimization of all chips to obtain thickness-optimized chips.

[0110] The embodiment of the present invention can comprehensively check the various performance indicators and quality conditions of the thickness optimized chip by performing quality inspection on the thickness optimized chip. It is not limited to the parameter of thickness, but also includes chip surface quality (whether there are scratches, cracks and other defects), circuit performance (whether there are problems such as short circuit and open circuit), electrical parameters (such as whether resistance, capacitance, etc. meet the standards) and other aspects.

[0111] As an embodiment of the present invention, the quality inspection of the thickness optimization chip includes: collecting a microscopic image of the thickness optimization chip, identifying refined features of the microscopic image, using the refined features to perform an appearance inspection on the thickness optimization chip, constructing multiple test modes and test vectors for the thickness optimization chip, inputting a preset electrical signal into the thickness optimization chip, and then performing a circuit performance inspection on the thickness optimization chip according to the multiple test modes and test vectors, configuring a high-temperature aging test environment and a temperature and humidity cycle test environment for the thickness optimization chip, so as to perform a reliability test on the thickness optimization chip using the high-temperature aging test environment and the temperature and humidity cycle test environment, and completing the quality inspection of the thickness optimization chip after the appearance inspection, circuit performance inspection and reliability test are completed.

[0112] Among them, the preset electrical signal refers to a series of electrical signals with specific parameters that are set in advance and input to the chip pins when the chip is tested for circuit performance. These parameters usually include voltage amplitude, frequency, phase, and current size, etc., which are intended to simulate various excitation signals that the chip may receive in actual working scenarios, so as to comprehensively detect the response of the internal circuit of the chip, determine whether the chip can work normally and whether various performance indicators meet the design requirements. The multiple test modes refer to a collection of specific test methods or strategies used for different functional characteristics, working states or detection focuses of the chip. Each test mode focuses on evaluating the performance and functional integrity of the chip from a specific perspective, and often covers a series of related test operations and corresponding processes such as electrical signal input and output monitoring. The test vector refers to a set of electrical signal input values ​​arranged in a specific order and having a clear logical relationship and the corresponding expected output values ​​under a specific test mode. It can be figuratively understood as a "signal instruction set" that guides the chip to complete a specific test process and is used to verify the specific functions or performance of the chip.

[0113] Optionally, the microscopic image can be collected by a high-resolution optical microscope, and the refined features can be extracted and identified by the volume and network in the deep learning model. The appearance inspection of the thickness optimized chip using the refined features can be achieved by using the ImageJ / Fiji tool in combination with the refined features to identify and mark the areas where the thickness optimized chip has appearance defects, and judging whether the chip appearance is qualified according to a preset appearance quality standard (such as the ratio of the total area of ​​surface defects to the total area of ​​the chip is less than a certain value, etc.), the preset electrical signal can be input through an integrated circuit tester, the multiple test modes can be set through the chip design document including detailed design data such as the circuit architecture inside the chip, the composition of the logic modules, and the connection relationship between the modules, the test vector can be set using binary code through the chip logic function truth table, the high temperature aging test environment can be obtained by placing the chip in a high temperature environment box and setting a specific high temperature value (such as 125°C) and duration (such as 168 hours), and the temperature and humidity cycle test environment can be obtained by placing the chip in a temperature and humidity test box and cyclically switching the temperature and humidity of the temperature and humidity test box.

[0114] In the embodiment of the present invention, the thickness optimized chip is selected according to the test result of the quality test, and the selected chip can further ensure that the chips involved in the final packaging are of high quality, thereby avoiding the packaging failure caused by the chip's own quality problems or the performance defects of the packaged finished product from the source.

[0115] Optionally, the thickness optimized chip is selected according to the test results of the quality test, and the selected chip can be obtained by summarizing the results of various quality tests such as appearance test, circuit performance test and reliability test based on the test results of the quality test, and integrating all the test data into a quality assessment report. Each chip corresponds to a detailed test result record, and these results are comprehensively analyzed using data analysis methods. According to the preset high-quality chip screening standards, it is determined which chips have met or exceeded the standard requirements in various indicators.

[0116] S3. Query the material parameters of the selected chip, and configure the middle layer material of the selected chip based on the material parameters, use the middle layer material to coat the selected chip to obtain a coated chip, use a preconfigured curing characteristic curve to cure the coated chip to obtain a cured chip, identify the identification attributes and the middle layer position of the cured chip, plan a stacking path for the cured chip based on the identification attributes and the middle layer position to obtain a planned path, and stack the cured chips based on the planned path to obtain a stacked chip.

[0117] The embodiment of the present invention can query the material parameters of the selected chip and configure the intermediate layer material of the selected chip based on the material parameters to fully and deeply understand the various material characteristics of the selected chip, including key factors such as chemical composition, physical properties (such as hardness, thermal expansion coefficient, dielectric constant, etc.) and surface state, so as to provide an accurate data basis for the subsequent reasonable selection and configuration of the intermediate layer material, ensure that the intermediate layer and the chip can achieve good adaptation in many aspects such as physics and chemistry, and then use the intermediate layer material to fix the selected chip.

[0118] The intermediate layer material refers to a functional material that is coated on the surface of the chip and is located between two or more chips to be stacked. Its existence is to fill the tiny gaps between the chips, so that the chips can be better connected and work together, and at the same time play a variety of roles such as electrical insulation, stress buffering, and enhanced bonding, thereby improving the stability, reliability and electrical performance of the entire chip stacking packaging structure. It includes organic polymer materials such as epoxy resin and polyimide, as well as some inorganic materials such as ceramics and metal oxides.

[0119] Optionally, the material parameters can be obtained by searching for chip specifications, technical documents and other materials provided by chip manufacturers, and the intermediate layer material can be selected by comprehensively considering the functional requirements of the intermediate layer in the entire packaging structure (such as providing electrical insulation, buffering stress, and enhancing the bonding force between chips, etc.) based on the selected chip material parameters found. For example, if the chip generates a lot of heat during operation, it is necessary to select an intermediate layer material with a higher thermal conductivity to help dissipate heat; if the chip has strict requirements on electrical insulation performance, a material with a low dielectric constant and good insulation performance should be selected.

[0120] It should be noted that after the middle layer material is configured, corresponding pretreatment operations need to be performed according to its characteristics. For example, for some materials that need to be stored under specific temperature and humidity conditions to ensure stable performance, the environmental conditions must be adjusted in advance to achieve the best state; for powdered or granular materials, grinding, screening and other operations may be required to ensure that the particle size is uniform so that subsequent coating operations can be carried out evenly.

[0121] The embodiment of the present invention utilizes the intermediate layer material to coat the selected chip with material, and obtains a coated chip, so that the chip is covered with the intermediate layer material to form an intermediate layer film with a specific thickness and uniformity, thereby ensuring that the intermediate layer material can fully play its function in the packaging structure, such as providing an electrical insulation barrier, serving as a stress buffer layer, etc.

[0122] As an embodiment of the present invention, the method of using the intermediate layer material to coat the selected chip with material to obtain a coated chip includes: querying the material properties of the intermediate layer material and the chip size of the selected chip, configuring a corresponding coating device, obtaining the coating accuracy requirements of the selected chip, setting parameters for the coating device based on the coating accuracy requirements to obtain a debugging device, and using the debugging device to coat the selected chip with material to obtain a coated chip.

[0123] Among them, the material properties refer to the viscosity and fluidity of the coating material corresponding to the selected chip. The coating accuracy requirements, such as low coating viscosity, or the need for patterned coating in specific areas of the chip, can be obtained by querying the material parameter table of the coating material corresponding to the selected chip.

[0124] Optionally, the coating device can be configured with a spin coater, a screen printer or a spray coating device. The debugging device can install and debug the selected coating device in place, and set key coating parameters according to the specific conditions of the selected intermediate layer material and chip. Taking the spin coater as an example, it is necessary to adjust the rotation speed, acceleration time, coating time and other parameters. Generally, a small amount of trial coating is carried out first to observe the coating effect, such as the uniformity and thickness of the film layer, and gradually optimize the parameters to achieve the ideal coating quality requirements.

[0125] Furthermore, the embodiment of the present invention cures the coated chip by using the preconfigured curing characteristic curve to obtain a cured chip that can better fix the chip position, enhance the bonding force between chips, and prevent the chip from shifting or loosening during subsequent use.

[0126] Among them, the preconfigured curing characteristic curve refers to the curing time curve of the chip coating material at different temperatures. The curing characteristic curve can be obtained by conducting experiments in advance, preparing multiple groups of identical intermediate layer material samples, and placing them under different combinations of curing conditions such as temperature and time for curing treatment. For example, different constant temperatures (such as 80°C, 100°C, 120°C, etc.) and corresponding constant temperature times (such as 1 hour, 2 hours, 3 hours, etc.) are set, and at the same time, changes in key performance indicators of the material during the curing process are monitored, such as the increase in hardness, the stability of the dielectric constant, etc., and the curing characteristic curve of the material is drawn out through these data.

[0127] Optionally, the coated chip is cured by using the pre-configured curing characteristic curve, and the cured chip can be selected according to the curing requirements of the intermediate layer material (such as heating method, temperature range, whether light is required, etc.), and suitable curing equipment is commonly selected, such as a thermal oven, a UV curing box, an infrared curing furnace, etc., and the relevant parameters of the equipment are set according to the optimal curing conditions determined by the curing characteristic curve, such as the heating rate, constant temperature, constant temperature time, etc. of the thermal oven; for the UV curing box, the intensity of ultraviolet rays, irradiation time and other parameters should be set, and then the coated chip is placed on the carrying platform of the curing equipment, ensuring that the chips are neatly placed and have appropriate spacing between each other to avoid mutual influence during the curing process. Start the curing equipment, perform the curing operation according to the set parameters, so that the intermediate layer material undergoes a chemical reaction under the corresponding temperature, light and other conditions, and changes from a liquid or flowable state to a solid state to achieve curing.

[0128] The embodiment of the present invention helps to accurately distinguish chips of different types and functions during the stacking process by identifying the identification attributes and the intermediate layer position of the solidified chip, and orderly combine them according to design requirements, avoiding packaging errors caused by chip confusion, and ensuring the rationality and correctness of the chip layout in the packaging structure, thereby achieving the expected functions and performance requirements.

[0129] The identification attributes refer to the chip number, model mark, pin layout characteristics and arrangement.

[0130] Optionally, the identification attributes can be obtained by selecting a high-resolution optical microscope, an electron microscope (select a suitable microscope type according to the accuracy requirements and size of the chip) or an industrial camera and other image acquisition equipment, placing the cured chip on the stage of the equipment, adjusting the equipment's focal length, lighting conditions, magnification and other parameters to ensure that the image information of the chip surface and the middle layer can be clearly obtained, while ensuring that the image contrast, brightness, etc. meet subsequent analysis requirements, and then using image analysis software (such as ImageJ, Image-Pro Plus, etc.) to process and analyze the collected images to identify the identification attributes of the cured chip. The position of the middle layer can also be obtained by analysis with the help of image analysis software, so it is not elaborated here.

[0131] The embodiment of the present invention performs stacking path planning for the solidified chip based on the identification attribute and the position of the intermediate layer. The planned path can optimize the entire stacking process in advance, clarify the operation trajectory of each chip at different stages, enable the stacking equipment to perform tasks in an orderly manner, reduce unnecessary repeated operations, avoid collisions between chips, and improve the accuracy and speed of stacking.

[0132] As an embodiment of the present invention, the stacking path planning of the cured chip based on the identification attribute and the intermediate layer position to obtain the planned path includes: determining the stacking order of the cured chips according to the identification attribute, determining the chip alignment method of the cured chips during stacking according to the intermediate layer position, querying the device motion characteristics of the stacking device corresponding to the cured chip, constructing the stacking constraints of the cured chip based on the stacking order, the chip alignment method and the device motion characteristics, constructing the initial stacking path of the cured chip, preliminarily screening the initial stacking path based on the stacking constraints to obtain a screening path, using a preconfigured ant colony algorithm to perform a global search on the screening path to obtain a search pheromone, and updating the search pheromone using the following formula to obtain an updated pheromone:

[0133] γ ij (T+1)=(1-θ)·γ ij (T)+Δγ ij

[0134] Among them, γ ij (t+1) represents the update pheromone, θ represents the decay coefficient of the search pheromone, γ aij (t) represents the search pheromone concentration from path i to path j at time t, Δγ ij represents the newly added pheromone concentration, T represents the time when the search for pheromones begins,

[0135] Based on the update pheromone, the probability value of each path in the screening path being selected is calculated, and based on the probability value, a stacking path of the solidified chip is selected to obtain a planned path.

[0136] The motion characteristics refer to the limiting properties of different chip stacking devices (such as a robotic arm system) such as their own motion range, motion speed, and operable angle.

[0137] It should be explained that the solidified chips are dispersedly placed on a larger plane and are to be stacked into a tight multi-layer structure. Therefore, it is necessary to analyze how to pick up each chip in turn with the shortest moving distance and place it in the target stacking position. At this time, the chip number, model and other identification attributes determine its order in the stacking structure. The position of the middle layer on the chip determines the alignment method of adjacent chips when they are stacked. In order to achieve the shortest path, it is necessary to consider how to plan the optimal movement trajectory of the chip from the initial position to the stacking position while satisfying the condition of precise fitting of the middle layer. For example, the middle layers of adjacent chips need to be completely overlapped and aligned. Therefore, when planning the path, it is necessary to avoid circuitous and redundant adjustment actions so that the chip can be moved to a position that can be accurately aligned in the most direct way to reduce unnecessary distance consumption.

[0138] Optionally, the stacking constraints of the solidified chip based on the stacking sequence, the chip alignment method and the device motion characteristics can be constructed by constructing constraints based on the device motion characteristics, such as analyzing the motion range limitation: fully understanding the motion range parameters of each moving part of the stacking device (such as a robotic arm, an automated stacker, etc.). For example, the extension length of the robotic arm has maximum and minimum value limits, and the rotation angle range of each joint is also determined. Based on this information, define the range constraints of the chip's operable area in space. It is stipulated that the chip's pick-up and placement positions must be within the space that the device can effectively reach, to prevent the planning of paths that exceed the device's motion capabilities, and to avoid the situation where the device cannot reach the specified position for operation; consider speed and acceleration limitations: according to the device's motion speed and acceleration capabilities in different directions, set the speed and acceleration constraints during the chip movement process. For example, the maximum movement speed of the device in the X-axis direction is v1, and the maximum acceleration is a1. Then, when planning the path for the chip to move from the initial position to the target position along the X-axis direction, its speed change and maximum speed cannot exceed the corresponding limits, thereby ensuring that the device can operate the chip smoothly and safely, while also avoiding damage to the device due to unreasonable speed planning. Damage or affect the stacking accuracy; determine the constraints of grabbing and placing operations: formulate corresponding constraints for the specific methods and related parameters of the equipment to grab and place chips. For example, if the equipment grabs the chip through a vacuum suction cup, the minimum and maximum suction force range of the suction cup to adsorb the chip must be specified to ensure that the chip can be stably grabbed without causing damage to the chip; for the placement operation, determine the requirements such as the pressing depth and placement angle when the chip is placed at the target position to ensure that the chip can be accurately and firmly placed in the stacking position to achieve a good stacking effect. Finally, integrate and summarize the various constraints constructed based on the stacking order, chip alignment method and equipment motion characteristics to form a complete set of solidified chip stacking constraints. This set covers many requirements, from time sequence, spatial alignment to equipment operation. These constraints need to be strictly followed in the subsequent initial stacking path construction, screening and optimization processes to ensure that the planned chip stacking path is feasible and meets actual production requirements. For example, the final stacking constraint set may include content like this: "The chips must be stacked in the order of model ABC. The angular deviation of the chip around each axis during movement shall not exceed the specified value. The extension length of the robot arm must be within the range of [L1, L2]. The pressing depth when placing the chip is h cm..." and other detailed and specific constraints provide clear specifications and restrictions for the entire chip stacking path planning.

[0139] The initial stacking path can be automatically planned by computer-aided design (CAD) software. Based on the stacking constraints, the initial stacking path is preliminarily screened to obtain a screening path. The initial stacking path can be checked against the stacking constraints one by one by a reinforcement learning algorithm, and the paths that do not meet the constraints such as chip stacking order, alignment method, and device motion characteristics are removed. The remaining ones are the screening paths. Based on the update pheromone, the probability value of each path in the screening path being selected is calculated, and the stacking path of the solidified chip is selected based on the probability value to obtain a planned path.

[0140] Further, as an optional embodiment of the present invention, the calculating the probability value of each path in the screening path being selected based on the update pheromone includes: calculating the probability value of each path in the screening path being selected using the following formula:

[0141]

[0142] Among them, P represents the probability value, τ ij (t) represents the updated pheromone concentration, η ij represents heuristic information, α represents the pheromone importance factor, β represents the heuristic information importance factor, k∈allowed k It represents the set of next paths that can be selected at the current node k, that is, the set of all candidate paths that meet the constraints.

[0143] Optionally, the stacking path of the solidified chips is selected based on the probability value to obtain the planned path, which can be obtained by selecting a path with a higher probability value, such as a path corresponding to a probability greater than 80%, and the specific selection needs to be combined with actual application.

[0144] The embodiment of the present invention stacks the solidified chips based on the planned path to obtain stacked chips, which can ensure the accuracy and quality of stacking, reduce chip alignment errors and poor connections caused by human operating errors or insufficient equipment accuracy, improve the stability and reliability of the packaging structure, and lay the foundation for the final packaged product to have good electrical properties, mechanical properties and long-term stability.

[0145] S4. Query the stacking structure of the stacked chip, and based on the stacking structure, perform three-dimensional modeling of the stacked chip to obtain a stacked chip model, use the stacked chip model to plan a glue dispensing path for the stacked chip to obtain a glue dispensing path, and based on the glue dispensing path, reinforce the stacked chip to obtain a reinforced chip.

[0146] The embodiment of the present invention queries the stacking structure of the stacked chip and performs three-dimensional modeling of the stacked chip based on the stacking structure. The stacked chip model obtained can help analyze the overall performance characteristics of the stacked chip and possible weak links. For example, by understanding the stacking method of the chip, its performance in heat conduction, electrical connection, etc. can be predicted, providing a basis for optimizing chip performance, and also can discover in advance the reliability risks that may be caused by unreasonable stacking structure.

[0147] Optionally, the stacked structure can be identified by querying the design drawings corresponding to the stacked chip. For example, for a multi-layer memory chip, the design drawings will detail the length and width of each layer of memory chips, the distribution of storage units, and the locations of connection pins with other functional chips (such as control chips, etc.); the manufacturing process instructions will mention what kind of insulating material is used in the middle layer and what kind of coating and curing processes are used to achieve electrical isolation and physical connection between chips; the assembly process records will indicate which layer of chips to place first, whether there are specific alignment marks and other information. The stacked chip model can be constructed through SolidWorks tools.

[0148] Furthermore, the embodiment of the present invention utilizes the stacked chip model to plan the glue dispensing path for the stacked chip, and the obtained glue dispensing path can effectively control the amount of glue used, avoid waste, and reduce production costs. At the same time, it can reduce electrical or thermal performance problems such as short circuits and poor heat dissipation caused by uneven distribution of glue or excessive use, thereby ensuring the normal operation of the stacked chip and the stability of the overall performance, which is of great significance for improving product quality and market competitiveness.

[0149] As an embodiment of the invention, the stacked chip model is used to plan the glue dispensing path of the stacked chip to obtain the glue dispensing path, including: constructing an initial glue dispensing path of the stacked chip, creating a glue dispensing simulation scene of the stacked chip according to the stacked chip model, using the initial glue dispensing path as a simulation animation trajectory of the stacked chip, performing glue dispensing simulation on the stacked chip according to the glue dispensing simulation scene and the simulation animation trajectory, and determining the glue dispensing path of the stacked chip based on the simulation result of the glue dispensing simulation.

[0150] Optionally, the operating principle of the initial glue dispensing path is the same as the step for planning the stacking path of the cured chip, and the principle of obtaining the planned path is the same, so it is not repeated here. The creation of the glue dispensing simulation scene of the stacked chip based on the stacked chip model can import the built stacked chip 3D model into the glue dispensing simulation software (such as RoboDK, etc.), set the glue dispensing equipment model, glue properties and other related parameters in the software, and build a virtual scene simulating the real glue dispensing operation. The initial glue dispensing path can be used as the simulation animation trajectory of the stacked chip in the glue dispensing simulation software. The previously constructed initial glue dispensing path can be imported into the glue dispensing simulation software to associate it with the stacked chip model in the scene, and the path operation is set. The animation parameters such as motion speed are set to become the trajectory of the animation display. The glue dispensing simulation of the stacked chip according to the glue dispensing simulation scene and the simulation animation trajectory can be performed by starting the simulation function of the glue dispensing simulation software. Based on the set scene, trajectory and corresponding physical simulation algorithm, the dynamic process of the glue dispensing equipment dispensing the chip along the trajectory is simulated to observe the distribution of glue on the chip. The glue dispensing path of the stacked chip is determined based on the simulation result of the glue dispensing simulation. Problems such as uneven glue coverage and unreasonable path (such as intersection, excessive length, etc.) that appear in the simulation can be analyzed. The initial path is adjusted and optimized in the software, and the simulation verification is repeated until the final glue dispensing path that meets the requirements is obtained.

[0151] Furthermore, the embodiment of the present invention reinforces the stacked chip based on the glue dispensing path, and the reinforced chip can maintain the structural integrity of the stacked chip through effective chip reinforcement, ensure good electrical connection and thermal conductivity between chips, and ensure that the chip can continue to and stably perform its function during long-term use. It plays an important supporting role in the performance and life of the entire electronic product, and helps to improve the overall quality of the product and user satisfaction.

[0152] S5. Query the three-dimensional model and circuit layout information of the reinforced chip to interconnect the reinforced chip internally to obtain a link chip, query the stacking parameters and filling requirements of the link chip to preliminarily package the link chip to obtain a preliminarily packaged chip, identify the process parameters of the preliminarily packaged chip, and based on the process parameters, perform shell injection molding on the preliminarily packaged chip to obtain a packaged chip.

[0153] The embodiment of the present invention queries the three-dimensional model and circuit layout information of the reinforced chip to internally interconnect the reinforced chip, and obtains the link chip, which can help to analyze and estimate the electrical performance, signal transmission characteristics, etc. after interconnection in advance, so as to optimize the interconnection scheme according to actual needs, improve the overall function and performance of the chip, and enable it to better meet the requirements of the application scenarios for chip computing speed, signal integrity, etc.

[0154] Optionally, the link chip can be constructed by micro-nano processing technology (such as photolithography, electron beam exposure combined with metal deposition process) according to the layout inside the chip to achieve internal interconnection and obtain a link chip.

[0155] Furthermore, the embodiment of the present invention performs preliminary packaging of the link chip by querying the stacking parameters and filling requirements of the link chip. The preliminary packaged chip can optimize the heat dissipation performance of the chip, enhance the bonding strength between the chip and the packaging shell, and at the same time protect the chip to a certain extent, prevent external environmental factors (such as moisture, dust, etc.) from damaging the chip, and extend the service life of the chip.

[0156] Among them, the stacking parameters refer to a series of key dimensions and layout-related data information related to the physical structure of the chip during the multi-layer stacking process of the chip; the filling requirements refer to the specific provisions on the materials and their related characteristics, amounts, filling positions, etc. that need to be filled between the chip and the substrate, in the gaps inside the chip, etc. in order to meet the requirements of the chip in terms of performance, protection and structural stability during the chip packaging process.

[0157] The optional preliminary packaged chip can be obtained by searching the chip design document for the stacking parameters and filling requirements of the linked chip, and then using flip chip packaging and other processes (with bottom filling equipment for filling and welding equipment to connect the chip to the substrate), and operating according to the parameters and requirements to complete the preliminary packaging.

[0158] It should be further explained that the process parameters of the preliminary packaged chip can be obtained by testing the preliminary packaged chip using professional testing equipment (such as calipers to measure dimensions, thermal analysis instruments to measure thermal performance, etc.).

[0159] Based on the process parameters, the shell of the preliminary packaged chip is injection-molded to obtain the packaged chip. According to the identified process parameters, an appropriate injection mold and injection molding material (such as commonly used engineering plastics ABS, PP, etc.) are selected, and the preliminary packaged chip is placed at a specific position of the injection mold. The molten injection molding material is injected into the mold cavity by the injection molding machine according to the set mold temperature, injection pressure, injection speed and other process parameters, so that it is wrapped around the preliminary packaged chip. After cooling and solidification, a solid shell is formed to finally obtain the packaged chip. The shell can be injection-molded by the injection molding machine according to the parameter settings to finally obtain the packaged chip.

[0160] Embodiment 2:

[0161] like Figure 2 , is a system functional module diagram of a method for implementing ultra-thin multi-layer memory chip stacking packaging provided by an embodiment of the present invention.

[0162] The ultra-thin multi-layer memory chip stacking packaging system 200 of the present invention can be installed in an electronic device. According to the functions to be implemented, the ultra-thin multi-layer memory chip stacking packaging system can include a data fusion module 201, a commodity demand trend analysis module 202, a logistics supply strategy construction module 203, and a management report generation module 204. The module of the present invention can also be called a unit, which refers to a series of computer program segments that can be executed by an electronic device processor and can complete fixed functions, which are stored in the memory of the electronic device.

[0163] In the embodiment of the present invention, the functions of each module / unit are as follows:

[0164] The chip classification module 201 is used to obtain the memory chip to be packaged, optically scan the memory chip to be packaged to obtain a scanned image, analyze the surface defect degree and circuit integrity of the memory chip to be packaged by using the scanned image, perform chip quality classification on the memory chip to be packaged based on the surface defect degree and the circuit integrity, extract the chips that meet the preset quality after chip quality classification, obtain the target chip, identify the chip thickness and pad distribution state of the target chip by using the scanned image, and sub-classify the target chip based on the chip thickness and the pad distribution state to obtain multiple groups of chips;

[0165] The chip selection module 202 is used to measure the chip thickness of each group of chips in the multiple groups of chips by using a preconfigured thickness sensor to obtain thickness measurement data, construct a preferred thickness range of the multiple groups of chips by using the thickness measurement data, optimize the thickness of the multiple groups of chips based on the preferred thickness range to obtain thickness-optimized chips, perform quality inspection on the thickness-optimized chips, and select the thickness-optimized chips according to the inspection results of the quality inspection to obtain selected chips;

[0166] The chip stacking module 203 is used to query the material parameters of the selected chip, and configure the middle layer material of the selected chip based on the material parameters, use the middle layer material to coat the selected chip with material to obtain a coated chip, use a preconfigured curing characteristic curve to cure the coated chip to obtain a cured chip, identify the identification attribute and the middle layer position of the cured chip, plan a stacking path for the cured chip based on the identification attribute and the middle layer position to obtain a planned path, and stack the cured chips based on the planned path to obtain a stacked chip;

[0167] The chip reinforcement module 204 is used to query the stacking structure of the stacked chips, and based on the stacking structure, perform three-dimensional modeling on the stacked chips to obtain a stacked chip model, use the stacked chip model to perform glue dispensing path planning on the stacked chips to obtain a glue dispensing path, and based on the glue dispensing path, perform chip reinforcement on the stacked chips to obtain a reinforced chip;

[0168] The chip packaging module 205 is used to query the three-dimensional model and circuit layout information of the reinforced chip to internally interconnect the reinforced chip to obtain a link chip, query the stacking parameters and filling requirements of the link chip to preliminarily package the link chip to obtain a preliminarily packaged chip, identify the process parameters of the preliminarily packaged chip, and based on the process parameters, perform shell injection molding on the preliminarily packaged chip to obtain a packaged chip.

[0169] In detail, each module in the ultra-thin multi-layer memory chip stacking packaging system 200 described in the embodiment of the present invention is used in the same manner as described above. Figure 1 The same technical means as the ultra-thin multi-layer memory chip stacking packaging method described in the invention can produce the same technical effects, which will not be repeated here.

[0170] In the several embodiments provided by the present invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are only illustrative, for example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation.

[0171] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0172] In addition, each functional module in each embodiment of the present invention may be integrated into one processing unit, each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0173] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0174] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0175] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features invented herein.

Claims

1. A method for stacking and packaging ultra-thin multi-layer memory chips, characterized in that: The method comprises: Acquire a memory chip to be packaged, perform an optical scan on the memory chip to be packaged to obtain a scanned image, use the scanned image to analyze the surface defect degree and circuit integrity of the memory chip to be packaged, perform chip quality classification on the memory chip to be packaged based on the surface defect degree and the circuit integrity, extract chips that meet the preset quality after chip quality classification to obtain target chips, use the scanned image to identify the chip thickness and pad distribution state of the target chip, and sub-classify the target chip based on the chip thickness and the pad distribution state to obtain multiple groups of chips; Using a preconfigured thickness sensor, measure the chip thickness of each group of chips in the multiple groups of chips to obtain thickness measurement data, use the thickness measurement data to construct a preferred thickness range for the multiple groups of chips, optimize the thickness of the multiple groups of chips based on the preferred thickness range to obtain thickness-optimized chips, perform quality inspection on the thickness-optimized chips, and select the thickness-optimized chips according to the inspection results of the quality inspection to obtain selected chips; Querying material parameters of the selected chip, and configuring the middle layer material of the selected chip based on the material parameters, coating the selected chip with material using the middle layer material to obtain a coated chip, curing the coated chip with a preconfigured curing characteristic curve to obtain a cured chip, identifying the identification attribute and the middle layer position of the cured chip, planning a stacking path for the cured chip based on the identification attribute and the middle layer position to obtain a planned path, and stacking the cured chips based on the planned path to obtain a stacked chip; Querying the stacking structure of the stacked chip, and based on the stacking structure, performing three-dimensional modeling on the stacked chip to obtain a stacked chip model, using the stacked chip model to perform glue dispensing path planning on the stacked chip to obtain a glue dispensing path, and based on the glue dispensing path, performing chip reinforcement on the stacked chip to obtain a reinforced chip; Query the three-dimensional model and circuit layout information of the reinforced chip to interconnect the reinforced chip internally to obtain a link chip, query the stacking parameters and filling requirements of the link chip to preliminarily package the link chip to obtain a preliminarily packaged chip, identify the process parameters of the preliminarily packaged chip, and based on the process parameters, perform shell injection molding on the preliminarily packaged chip to obtain a packaged chip.

2. The ultra-thin multi-layer memory chip stacking packaging method according to claim 1, characterized in that: The step of analyzing the surface defect degree and circuit integrity of the memory chip to be packaged by using the scanned image comprises: Gray-scale the scanned image to obtain a gray-scale image; Performing image surface detection on the grayscale image to determine the surface defect profile of the memory chip to be packaged; Performing defect morphology processing on the surface defect profile to obtain a refined defect state; Quantifying the refined defect state to determine the surface defect degree of the memory chip to be packaged; Using the scanned image to identify circuit wiring features of the memory chip to be packaged; The circuit wiring characteristics are used to identify the circuit integrity of the memory chip to be packaged.

3. The ultra-thin multi-layer memory chip stacking packaging method according to claim 1, characterized in that: The step of using the scanned image to identify the chip thickness and pad distribution state of the target chip includes: Extracting a vertical boundary contour area of ​​the scanned image; Calculate the vertical pixel value of the vertical boundary contour area; Performing size conversion on the vertical pixel value to obtain the chip thickness of the target chip; Performing target detection on the scanned image to obtain a detected target; Identifying feature points of the detection target; The shape, size and distance characteristics of the pads corresponding to the target chip are analyzed based on the characteristic points, and the number and arrangement of the pads are counted to determine the pad distribution state.

4. The ultra-thin multi-layer memory chip stacking packaging method according to claim 3, characterized in that: The identifying feature points of the detection target includes: Constructing a scale space of the detection target; Marking key points of the detection target in the scale space to obtain marked key points; After the directions of the marked key points are assigned, the marked key points are characterized by using the following formula to obtain the feature points: Among them, M represents the feature point, H represents the image gradient value of the scanned image corresponding to the detected target, θ represents the direction of the marked key point, L represents the scanned image, L(A+1, B), L(A-1, B), L(A, B+1), and L(A, B-1) represent the neighboring points of the origin L(A, B) of the scanned image in the scale space.

5. The ultra-thin multi-layer memory chip stacking packaging method according to claim 1, characterized in that: The quality inspection of the thickness optimized chip includes: collecting a microscopic image of the thickness optimized chip; identifying detailed features of the microscopic image; Performing appearance inspection on the thickness optimized chip using the refined features; Constructing multiple test patterns and test vectors of the thickness optimized chip; After inputting a preset electrical signal into the thickness optimization chip, a circuit performance test is performed on the thickness optimization chip according to the multiple test modes and test vectors; Configuring a high temperature aging test environment and a temperature and humidity cycle test environment for the thickness optimization chip, so as to perform a reliability test on the thickness optimization chip by using the high temperature aging test environment and the temperature and humidity cycle test environment; After the appearance inspection, circuit performance inspection and reliability test are completed, the quality inspection of the thickness optimized chip is completed.

6. The ultra-thin multi-layer memory chip stacking packaging method according to claim 1, characterized in that: The method of using the intermediate layer material to coat the selected chip with a material to obtain a coated chip comprises: Inquiring the material properties of the intermediate layer material and the chip size of the selected chip to configure a corresponding coating device; Obtaining coating accuracy requirements for the selected chip; Based on the coating accuracy requirement, parameters of the coating device are set to obtain a debugging device; The debugging device is used to coat the selected chip with material to obtain a coated chip.

7. The ultra-thin multi-layer memory chip stacking packaging method according to claim 1, characterized in that: The stacking path planning of the solidified chip based on the identification attribute and the position of the intermediate layer to obtain the planned path includes: Determining a stacking order of the cured chips according to the identification attributes; Determining a chip alignment method of the solidified chips when stacking according to the position of the intermediate layer; Querying the device motion characteristics of the stacking device corresponding to the solidified chip; Based on the stacking sequence, the chip alignment method and the device motion characteristics, constructing stacking constraints of the solidified chip; constructing an initial stacking path of the cured chips; Based on the stacking constraint, preliminarily screening the initial stacking path to obtain a screening path; Using a preconfigured ant colony algorithm, a global search is performed on the screening path to obtain a search pheromone; The search pheromone is updated using the following formula to obtain the updated pheromone: c ij (T+1)=(1-θ)·γ ij (T)+Δγ ij Among them, γ ij (t+1) represents the update pheromone, θ represents the decay coefficient of the search pheromone, γ ij (t) represents the search pheromone concentration from path i to path j at time t, Δγ ij represents the newly added pheromone concentration, and T represents the time when the search for pheromones begins; Based on the updated pheromone, calculating the probability value of each path in the screening path being selected; A stacking path of the solidified chips is selected based on the probability value to obtain a planned path.

8. The ultra-thin multi-layer memory chip stacking packaging method according to claim 7, characterized in that: The step of calculating the probability value of each path in the screening path being selected based on the updated pheromone comprises: The probability value of each path being selected in the screening path is calculated using the following formula: Among them, P represents the probability value, τ ij (t) represents the updated pheromone concentration, η ij represents heuristic information, α represents the pheromone importance factor, β represents the heuristic information importance factor, k∈allowed i It represents the set of next paths that can be selected at the current node k, that is, the set of all candidate paths that meet the constraints.

9. The ultra-thin multi-layer memory chip stacking packaging method according to claim 1, characterized in that: The method of planning a dispensing path for the stacked chip by using the stacked chip model to obtain a dispensing path includes: constructing an initial dispensing path for the stacked chips; Creating a dispensing simulation scene of the stacked chip according to the stacked chip model; Using the initial dispensing path as a simulation animation trajectory of the stacked chips; Performing glue dispensing simulation on the stacked chips according to the glue dispensing simulation scene and the simulation animation trajectory; The stacked chip dispensing path is determined based on the simulation result of the dispensing simulation.

10. The ultra-thin multi-layer memory chip stacking packaging method according to claim 1, characterized in that: The system comprises: A chip classification module is used to obtain a memory chip to be packaged, optically scan the memory chip to be packaged to obtain a scanned image, analyze the surface defect degree and circuit integrity of the memory chip to be packaged by using the scanned image, perform chip quality classification on the memory chip to be packaged based on the surface defect degree and the circuit integrity, extract chips that meet the preset quality after chip quality classification to obtain target chips, identify the chip thickness and pad distribution state of the target chip by using the scanned image, and perform sub-classification on the target chip based on the chip thickness and the pad distribution state to obtain multiple groups of chips; A chip selection module is used to measure the chip thickness of each group of chips in the multiple groups of chips by using a preconfigured thickness sensor to obtain thickness measurement data, construct a preferred thickness range for the multiple groups of chips by using the thickness measurement data, optimize the thickness of the multiple groups of chips based on the preferred thickness range to obtain thickness-optimized chips, perform quality inspection on the thickness-optimized chips, and select the thickness-optimized chips according to the inspection results of the quality inspection to obtain selected chips; a chip stacking module, for querying the material parameters of the selected chip, and configuring the middle layer material of the selected chip based on the material parameters, coating the selected chip with the middle layer material to obtain a coated chip, curing the coated chip with a preconfigured curing characteristic curve to obtain a cured chip, identifying the identification attribute and the middle layer position of the cured chip, planning a stacking path for the cured chip based on the identification attribute and the middle layer position to obtain a planned path, and stacking the cured chips based on the planned path to obtain a stacked chip; A chip reinforcement module, used for querying the stacking structure of the stacked chips, and based on the stacking structure, performing three-dimensional modeling on the stacked chips to obtain a stacked chip model, using the stacked chip model to perform glue dispensing path planning on the stacked chips to obtain a glue dispensing path, and based on the glue dispensing path, performing chip reinforcement on the stacked chips to obtain a reinforced chip; The chip packaging module is used to query the three-dimensional model and circuit layout information of the reinforced chip to interconnect the reinforced chip internally to obtain a link chip, query the stacking parameters and filling requirements of the link chip to perform preliminary packaging of the link chip to obtain a preliminary packaged chip, identify the process parameters of the preliminary packaged chip, and based on the process parameters, perform shell injection molding on the preliminary packaged chip to obtain a packaged chip.

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