Semiconductor structure and method of forming a contact structure

Abstract

A method according to the present disclosure includes receiving a workpiece including a first gate structure including a first cap layer thereon, a first source / drain contact abutting the first gate structure, a second gate structure including a second cap layer thereon, a second source / drain contact, an ESL over the first and second source / drain contacts, and a first dielectric layer over the ESL. The method also includes forming a pair of contact openings to expose the first cap layer and the first source / drain contact, forming a pair of contacts in the pair of contact openings, depositing a second dielectric layer after forming the pair of contacts, forming a source / drain contact via opening through the second dielectric layer, the ESL layer, and the first dielectric layer to expose the second source / drain contact, and forming a source / drain contact via in the source / drain contact via opening. Embodiments of the present application provide semiconductor structures and methods of forming contact structures.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods for forming contact structures. Background Technology

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in several generations of ICs, each with smaller and more complex circuitry than the previous one. In the course of IC development, functional density (i.e., the number of interconnect devices per chip area) has typically increased, while geometry (i.e., the smallest component (or wire) that can be produced using manufacturing processes) has decreased. This scaling down process usually yields benefits through increased production efficiency and reduced associated costs.

[0003] As IC devices continue to shrink in scale, the size of contact vias, such as gate contact vias and source / drain contact vias, is becoming increasingly smaller. While advanced photolithography techniques allow for the formation of high aspect ratio via openings, filling these openings with conductive material has proven challenging. Furthermore, the deposition of metal filler layers on different metal surfaces can experience varying deposition rates, resulting in unsatisfactory metal filling or voids. While existing methods for forming contacts to transistors are adequate for their intended purpose, they are not entirely satisfactory. Summary of the Invention

[0004] In one embodiment, a method is provided. The method includes: receiving a workpiece including: a first gate structure including a first capping layer on the first gate structure; a first source / drain contact adjacent to the first gate structure; a second gate structure including a second capping layer on the second gate structure; a second source / drain contact; an etch stop layer (ESL) located over the first source / drain contact and the second source / drain contact; and a first dielectric layer located over the ESL. The method further includes: forming a pair of contact openings to expose the first capping layer and the first source / drain contact; forming a pair of contacts in the pair of contact openings; depositing a second dielectric layer after forming the pair of contacts; forming a source / drain contact via opening through the second dielectric layer, the ESL layer, and the first dielectric layer to expose the second source / drain contact; and forming a source / drain contact via in the source / drain contact via opening.

[0005] In another embodiment, a method is provided. The method includes: receiving a workpiece including: a first gate structure; a first source / drain contact adjacent to the first gate structure; a second gate structure; a second source / drain contact; an etch stop layer (ESL) above the first source / drain contact and the second source / drain contact; and a first dielectric layer above the ESL. The method may further include: forming a pair of contacts to connect to the first gate structure and the first source / drain contact; depositing a second dielectric layer over the first dielectric layer and the pair of contacts; forming a source / drain contact via through the second dielectric layer, the first dielectric layer, and the ESL layer to connect the second source / drain contact; depositing a third dielectric layer over the source / drain contact via and the second dielectric layer; and forming a gate contact through the third dielectric layer, the second dielectric layer, the first dielectric layer, and the ESL layer to connect to the second gate structure.

[0006] In another embodiment, a semiconductor structure is provided. The semiconductor structure includes: a first gate structure including a first capping layer; a first source / drain contact adjacent to the first gate structure; a second gate structure including a second capping layer; a second source / drain contact; an etch stop layer (ESL) located above the first source / drain contact and the second source / drain contact; a first dielectric layer located above the ESL; a second dielectric layer located above the first dielectric layer; a pair of contacts spanning over the first gate structure and the first source / drain contact, and contacting the first source / drain contact and the first capping layer; a source / drain contact via disposed above the second source / drain contact; and a gate contact disposed above the second capping layer. The second dielectric layer is disposed directly above the top surface of the pair of contacts. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1 This is a flowchart of a method for manufacturing common rail contacts according to various aspects of the present invention;

[0009] Figures 2-14 It is in accordance with various aspects of the present invention Figure 1 Partial cross-sectional views of the workpiece at various stages of manufacturing using the methods described in the document;

[0010] Figure 15 This is a partial top view of a semiconductor device including gate contacts, source / drain contact vias, and contact points according to various aspects of the present invention. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to readily describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0013] Furthermore, when using terms such as "approximately" or "about," to describe numbers or ranges of numbers, the term is intended to cover numbers within a reasonable range that takes into account the inherent variations that occur during manufacturing, as understood by those skilled in the art. For example, the number or range of numbers covers a reasonable range including the described number, such as within + / - 10% of the described number based on known manufacturing tolerances associated with manufacturing a part (which has characteristics associated with the number). For example, a material layer with a thickness of "about 5 nm" can cover a size range from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%. Furthermore, reference numbers and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] As semiconductor device dimensions continue to shrink proportionally, the use of local interconnect structures to connect gate structures and adjacent source / drain contacts has become commonplace. In some examples, the gate structure is covered by a capping layer with a different composition than the source / drain contacts. During the formation of the local interconnect structure, the fill layer is deposited using chemical vapor deposition (CVD) or selective deposition methods. It can be observed that the fill layer is deposited at a faster rate on the source / drain contacts than over the capping layer. Furthermore, the surfaces of the source / drain contacts and the capping layer can be exposed to various oxidizing or reducing atmospheres prior to the metal-filling process used to form the local interconnect structure. Differences in the reducing properties of different materials can also lead to different deposition rates. These different deposition rates on different surfaces can result in poor contact between the local interconnect structure and the gate structure.

[0015] This invention provides a method for forming pair contacts before forming source / drain contact vias and gate contacts to connect a gate structure to adjacent source / drain contacts. The pair contact openings have a low aspect ratio, and metal filling into the pair contact openings is performed using a combination of physical vapor deposition (PVD) and chemical vapor deposition (CVD). As a result, the top surfaces of the source / drain contact vias and gate contacts are higher than the top surfaces of the pair contacts. Embodiments of this invention can reduce or eliminate problems associated with different deposition rates on different surfaces. The method of this invention reduces the likelihood of void formation.

[0016] Various aspects of the invention will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating a method 100 for forming a contact structure according to an embodiment of the present invention. Method 100 is merely an example and is not intended to limit the invention to what is explicitly shown in method 100. Other steps may be provided before, during, and after method 100, and some described steps may be replaced, eliminated, or moved for other embodiments of the method. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 2-14 To describe method 100, Figures 2-14 It is based on Figure 1 Partial cross-sectional views of workpiece 200 at different manufacturing stages of an embodiment of method 100. To avoid any doubt, Figures 2-14 The X, Y, and Z directions are perpendicular to each other, and throughout the entire Figures 2-14 The term "semiconductor device" is used throughout the invention. Since workpiece 200 will be manufactured into a semiconductor device or semiconductor structure, it may be referred to herein as semiconductor device 200 or semiconductor structure 200, depending on the context. Throughout the invention, similar reference numerals denote similar features unless otherwise stated.

[0017] refer to Figure 1 and Figure 2 Method 100 includes block 102, wherein a workpiece 200 is received. Workpiece 200 includes a substrate 202. In the depicted embodiment, substrate 202 includes silicon (Si). Alternatively or additionally, substrate 202 may include: another basic semiconductor, such as germanium (Ge); compound semiconductors, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); alloy semiconductors, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium arsenide phosphide (GaInAsP); or combinations thereof. In some embodiments, substrate 202 includes one or more group III-V materials, one or more group II-VI materials, or combinations thereof. In some embodiments, substrate 202 is a semiconductor-on-insulator (SOI) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GeOI) substrate. The SOI substrate can be fabricated using oxygen implantation (SIMOX), wafer bonding, and / or other suitable methods. Substrate 202 may include various doped regions (not shown) configured according to the design requirements of semiconductor device 200, such as p-type doped regions, n-type doped regions, or combinations thereof. P-type doped regions (e.g., p-type wells) include p-type dopants, such as boron (B), boron difluoride (BF2), other p-type dopants, or combinations thereof. N-type doped regions (e.g., n-type wells) include n-type dopants, such as phosphorus (P), arsenic (As), other n-type dopants, or combinations thereof. Ion implantation processes, diffusion processes, and / or other suitable doping processes can be implemented to form the various doped regions. Substrate 202 in Figure 2 It is shown in dashed lines, and for simplicity, in Figures 3-14 omitted.

[0018] like Figure 2As shown, workpiece 200 includes an active region 204 of a multi-gate device, such as a fin field-effect transistor (FinFET) or a multi-bridge channel (MBC) transistor. When the active region 204 is used for a FinFET, it can be a fin element (or fin structure) extending along the X-direction. When the active region 204 is used for an MBC transistor, it can be a vertically stacked array of channel members, each of which extends along the X-direction. Because the gate structure of the MBC transistor surrounds each of the channel regions, the MBC transistor can also be referred to as a gate-all-around transistor (SGT) or a gate-all-around (GAA) transistor. The channel members take the form of nanostructures, such as nanosheets, nanowires, or nanorods. The active region 204 can be formed by patterning a substrate 202 or by depositing one or more epitaxial layers over the substrate 202. In the depicted embodiment, the active region 204 is formed by patterning a portion of the substrate 202 and includes silicon (Si). Although not explicitly shown in the accompanying drawings, an isolation component may be formed between the active region 204 and an adjacent active region (not explicitly shown). In some embodiments, the isolation component may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, a combination thereof, and / or other suitable materials.

[0019] like Figure 2As shown, workpiece 200 also includes a first gate structure 206-1, a second gate structure 206-2, and a third gate structure 206-3 disposed above the channel region 10 of the active region 204. For ease of reference, the first gate structure 206-1, the second gate structure 206-2, and the third gate structure 206-3 may be collectively referred to as gate structure 206. The channel region 10 of the active region 204 is interspersed by source / drain regions 20. Each of the channel regions 10 intersects between two source / drain regions 20. Gate structure 206 surrounds the channel region 10 of the active region 204. When the active region 204 comprises a vertical stack of channel members, gate structure 206 surrounds each of the channel members. Although not explicitly shown in the figures, each of the gate structures 206 includes a gate dielectric layer and a gate electrode located above the gate dielectric. The gate dielectric layer may include an interface layer and a high-k dielectric layer. In some cases, the interface layer may include silicon oxide. High-k dielectric layers are formed using dielectric materials with high dielectric constants (e.g., greater than the dielectric constant of silicon oxide (k≈3.9)). Exemplary high-k dielectric materials for high-k dielectric layers include hafnium oxide (HfO), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. In one embodiment, the high-k dielectric layer is formed of hafnium oxide (HfO). The gate electrode may include multiple layers, such as a work function layer, a binder / barrier layer, and / or a metal filler (or bulk) layer. The work function layer includes a conductive material tuned to have a desired work function (e.g., an n-type work function or a p-type work function), such as an n-type work function material and / or a p-type work function material. P-type work function materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other p-type work function materials, or combinations thereof. N-type work function materials include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-type work function materials, or combinations thereof. The binder / barrier layer may include a material that promotes adhesion between adjacent layers (e.g., the work function layer and the metal filler layer), and / or a material that blocks and / or reduces diffusion between gate layers (e.g., the work function layer and the metal filler layer).For example, the adhesive / barrier layer includes metals (e.g., W, Al, Ta, Ti, Ni, Cu, Co, other suitable metals, or combinations thereof), metal oxides, metal nitrides (e.g., TiN), or combinations thereof. The metal filler layer may include suitable conductive materials such as aluminum (Al), copper (Cu), tungsten (W), ruthenium (Ru), titanium (Ti), suitable metals, or combinations thereof. The metal filler layer may be omitted when the work function material occupies all gate openings.

[0020] Each of the gate structures 206 has its sidewalls padded by gate spacers 210. Gate spacers 210 can be single-layer or multi-layer. In some embodiments, gate spacers 210 may include silicon carbonitride, silicon oxycarbonide, silicon oxycarbonitride, or silicon nitride. In some embodiments, gate structures 206 may be formed using gate replacement or a post-gate process. In an example of a post-gate process, a dummy gate stack is formed over the channel region 10 of the active region 204. Gate spacers 210 are then deposited over workpiece 200, including over the sidewalls of the dummy gate stack. An anisotropic etching process is then performed to recess the source / drain regions 20 to form source / drain trenches, leaving the subsequent gate spacers 210 extending along the sidewalls of the dummy gate stacks. After forming the source / drain trenches, first source / drain components 205-1 and second source / drain components 205-2 are deposited into the source / drain trenches in the source / drain regions 20. The first source / drain component 205-1 and the second source / drain component 205-2 may be formed by vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low-pressure CVD (LPCVD), and / or plasma-enhanced CVD (PECVD), molecular beam epitaxy (MBE), or other suitable epitaxial processes, or combinations thereof. The source / drain component may also be referred to as an epitaxial component. Depending on the design of the semiconductor device 200, the first source / drain component 205-1 and the second source / drain component 205-2 may be n-type or p-type. When they are n-type, they may comprise silicon (Si) doped with an n-type dopant (e.g., phosphorus (P) or arsenic (As)). When they are p-type, they may comprise silicon germanium (SiGe) doped with a p-type dopant (e.g., boron (B) or boron difluoride (BF2)). In some embodiments, an annealing process may be performed to activate the dopants in the first source / drain component 205-1 and the second source / drain component 205-2. In the depicted embodiments, the first source / drain component 205-1 and the second source / drain component 205-2 may comprise phosphorus-doped silicon (Si:P) or boron-doped silicon germanium (SiGe:B).

[0021] After the source / drain components (e.g., first source / drain component 205-1 and second source / drain component 205-2) are formed, a contact etch stop layer (CESL) 212 and a first interlayer dielectric (ILD) layer 214 are deposited over the workpiece 200. In some embodiments, CESL 212 may comprise silicon nitride, silicon oxynitride, and / or other materials known in the art. CESL 212 may be deposited using atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), plasma-enhanced chemical vapor deposition (PECVD), and / or other suitable deposition processes. The first ILD layer 214 may comprise materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or silicon-doped oxides such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The first ILD layer 214 can be deposited on top of CESL 212 using CVD, flowable CVD (FCVD), spin coating, or other suitable deposition techniques. The workpiece 200 is then planarized using a chemical mechanical polishing (CMP) process to expose the dummy gate stack. The dummy gate stack is then removed and replaced with a gate structure 206, the composition of which is described above.

[0022] The gate structure 206 is covered by a capping layer 208. In some embodiments, the capping layer 208 may include fluorine-free tungsten (FFW) deposited using chemical vapor deposition (CVD) or metal-organic chemical vapor deposition (MOCVD). Figure 2 As shown, the workpiece 200 may further include a self-aligned cover (SAC) layer 216 located above the cover layer 208. In some embodiments, the SAC layer 216 may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium alumina, hafnium oxide, or a suitable dielectric material. The SAC layer 216 may be deposited using CVD, ALD, PEALD, or a suitable method.

[0023] Now for reference Figure 1 and Figure 3Method 100 includes block 104, wherein a first source / drain contact 224-1 is formed to connect to a first source / drain component 205-1, and a second source / drain contact 224-2 is formed to connect to a second source / drain component 205-2. Block 104 includes forming a source / drain contact opening over the source / drain region 20 through the first ILD layer 214 and CESL 212, and forming the first source / drain contact 224-1 and the second source / drain contact 224-2 in the source / drain contact opening. The formation of the source / drain contact opening may include using photolithography and / or etching processes. In some embodiments, the photolithography process includes: forming a resist layer over the workpiece 200, exposing the resist layer to pattern radiation, and developing the exposed resist layer to form a patterned resist layer. Then, using a patterned resist layer as a mask element, a dry etching process is performed on workpiece 200 to expose a portion of the first source / drain component 205-1 and a portion of the second source / drain component 205-2. The dry etching process at frame 104 may include the use of fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), hydrocarbons (e.g., CH4), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. After forming the source / drain contact openings, a silicide layer 218 is formed in the source / drain contact openings. In some cases, the silicide layer 218 may include titanium silicide, cobalt silicide, nickel silicide, tantalum silicide, or tungsten silicide. Subsequently, a metal filler layer 222 is deposited over the silicide layer 218 using bottom-up selective CVD to form a first source / drain contact 224-1 over the first source / drain component 205-1 and a second source / drain contact 224-2 over the second source / drain component 205-2. It is noteworthy that, due to the use of bottom-up selective CVD, no barrier layer is deposited prior to the deposition of the metal filler layer 222. Bottom-up selective CVD provides selective deposition of metal on metal, which has a slower conventional CVD deposition rate. The metal filler layer 222 may include ruthenium (Ru), cobalt (Co), nickel (Ni), or copper (Co). In the depicted embodiment, the metal filler layer 222 includes cobalt (Co). After depositing the metal filler layer 222, a chemical mechanical polishing (CMP) process may be performed to remove excess material and define the final shape of the first source / drain contact 224-1 and the second source / drain contact 224-2. After the CMP process, the top surface of workpiece 200 is basically flat.

[0024] Now for reference Figure 1 and Figure 4Method 100 includes block 106, wherein an intermediate etch stop layer (MESL) 226 and a second interlayer dielectric (ILD) layer 228 are deposited over a workpiece 200. In block 106, MESL 226 and the second interlayer dielectric (ILD) layer 228 are sequentially deposited over the workpiece 200. In some embodiments, the composition and formation process of MESL 226 may be similar to that of CESL 212, while the composition and formation process of the second ILD layer 228 may be similar to that of the first ILD layer 214.

[0025] refer to Figure 1 and Figure 5 Method 100 includes a block 108 in which a contact opening 230 is formed to expose a capping layer 208 above a first gate structure 206-1 and a first source / drain contact 224-1. In an exemplary process, a patterned photoresist layer may be formed over the workpiece 200 to expose the region located directly above the first gate structure 206-1 and the first source / drain contact 224-1. The workpiece 200 is then anisotropically etched using the patterned photoresist layer as an etch mask. Because the anisotropic etching at block 108 is selective for the second ILD layer 228, MESL 226, and SAC layer 216, the endpoints of the contact opening 230 may fall on the top surface of the first source / drain contact 224-1 and the top surface of the capping layer 208 above the first gate structure 206-1. As a result, a... Figure 5 The contact opening 230 is shown. The contact opening 230 exposes not only the first source / drain contact 224-1 but also the capping layer 208 above the first gate structure 206-1. The anisotropic etching process at block 108 can be dry etching, using oxygen (O2), nitrogen (N2), fluorine-containing gases (e.g., CF4, SF6, NF3, BF3, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), hydrocarbons (e.g., CH4), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. In some embodiments, a pre-cleaning process can be performed after forming the contact opening 230 to remove oxides from the first source / drain contact 224-1 and the capping layer 208.

[0026] refer to Figure 1 and Figure 6Method 100 includes block 110, wherein a contact point 232 is formed in a contact point opening 230. Operations at block 110 include depositing a barrier layer 231 and a metal filler layer into the contact point opening 230, and planarizing the workpiece 200 to remove excess metal material. At block 110, the barrier layer 231 may be deposited using physical vapor deposition (PVD), and the metal filler layer may be deposited over the barrier layer 231 using chemical vapor deposition (CVD). In some embodiments, the barrier layer 231 may comprise a metal nitride such as titanium nitride (TiN), and the metal filler layer over the barrier layer 231 may comprise tungsten (W). Notably, the deposition process for the contact point 232 differs from that for the source / drain contacts. As described above, the source / drain contacts (e.g., the first source / drain contact 224-1) are deposited using bottom-up selective CVD without a barrier, while the contact point 232 is deposited using CVD and includes the barrier layer 231. After the deposition of the metal material, the workpiece 200 is planarized using, for example, a CMP process until all the metal material above the second ILD layer 228 is removed. After planarization, a pair of contacts 232 is formed in the pair of contact openings 230. The pair of contacts 232 (or, more precisely, the barrier layer 231 of the pair of contacts 232) are in direct contact with the second ILD layer 228, MESL 226, the metal fill layer 222 of the first source / drain contact 224-1, the gate spacer 210, the SAC layer 216, and the capping layer 208 above the first gate structure 206-1. Since the capping layer 208 is conductive, the pair of contacts 232 falling on the first source / drain contact 224-1 and the capping layer 208 are electrically connected to the first source / drain contact 224-1 and the first gate structure 206-1.

[0027] refer to Figure 1 and Figure 7 Method 100 includes frame 112, wherein a third ILD layer 234 is deposited over workpiece 200. Like the first ILD layer 214 and the second ILD layer 228, the third ILD layer 234 may comprise materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxides such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The third ILD layer 234 may be deposited over the second ILD layer 228 and the contact point 232 by CVD, flowable CVD (FCVD), spin coating, or other suitable deposition techniques.

[0028] refer to Figure 1 and Figure 8Method 100 includes a frame 114 in which a source / drain contact via opening 236 is formed to expose a second source / drain contact 224-2. The formation of the source / drain contact via opening 236 may include a photolithography process and an etching process. The photolithography process forms an etching mask including an opening located directly above the second source / drain contact 224-2. (Reference) Figure 8 A dry etching process is then performed to completely etch through the third ILD layer 234, the second ILD layer 228, and MESL 226 to expose the top surface of the metal filler layer 222 of the second source / drain contact 224-2. An exemplary dry etching process at block 114 may include using oxygen (O2), nitrogen (N2), hydrogen (H2), fluorine-containing gases (e.g., CF4, SF6, NF3, BF3, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. In one embodiment, the source / drain contact via opening 236 is etched using nitrogen plasma, hydrogen plasma, or both.

[0029] refer to Figure 1 and Figure 9 Method 100 includes a frame 116 in which the second source / drain contact 224-2 is recessed. A selective wet etching process can be performed to selectively recess the metal filler layer 222 of the second source / drain contact 224-2 so that the source / drain contact via opening 236 extends into the second source / drain contact 224-2. In some embodiments, the selective wet etching process includes using deionized (DI) water, nitric acid (HNO3), hydrogen peroxide (H2O2), hydrochloric acid (HCl), or isopropanol (IPA). In one embodiment, the metal filler layer 222 is formed of cobalt (Co), and the recess at frame 116 is implemented using hydrogen peroxide (H2O2). Figure 9 As shown, due to the isotropic nature of the wet etching process, the top surface of the metal filling layer 222 of the second source / drain contact 224-2 becomes concave or pit-shaped. Figure 9 In some of the represented embodiments, after the recess, a portion of the source / drain contact via opening 236 may undercut MESL 226 around the second source / drain contact 224-2. The recess at frame 116 can improve adhesion and increase the interfacial surface area with the source / drain contact via 240 (described below) to be formed.

[0030] refer to Figure 1 and Figure 10Method 100 includes block 118, wherein a source / drain contact via 240 is formed in a source / drain contact via opening 236. Operations at block 118 may include metal deposition and surface planarization. In an exemplary process, a metal filler layer is deposited over workpiece 200, including in the source / drain contact via opening 236. In some embodiments, the metal filler layer may include tungsten (W) or ruthenium (Ru). In the depicted embodiment, the metal filler layer includes tungsten (W). In some embodiments, the metal filler layer may be deposited using bottom-up selective CVD or a suitable deposition technique. After depositing the metal filler layer, a CMP process is performed to planarize workpiece 200 to remove excess material and form the source / drain contact via 240. Figure 10 As shown, the source / drain contact via 240 extends through the third ILD layer 234, the second ILD layer 228, and MESL 226. Due to the recessed process at frame 116, the source / drain contact via 240 partially extends into the metal fill layer 222 of the second source / drain contact 224-2, and can be undercut around the edge of the second source / drain contact 224-2. Figure 10 In some of the represented embodiments, the difference in height between the top surface of the source / drain contact via 240 and the top surface of the contact point 232 is substantially equal to the thickness of the third ILD layer 234.

[0031] refer to Figure 1 and Figure 11 Method 100 includes frame 120, wherein a fourth dielectric layer 242 is deposited over workpiece 200. Like the first ILD layer 214 and the second ILD layer 228, the fourth ILD layer 242 may comprise materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxides such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The fourth ILD layer 242 may be deposited over the third ILD layer 234 and the top surface of the source / drain contact via 240 by CVD, flowable CVD (FCVD), spin coating, or other suitable deposition techniques.

[0032] refer to Figure 1 and Figure 12Method 100 includes block 122, wherein a gate contact opening 244 is formed to expose a capping layer 208 over a second gate structure 206-2. The gate contact opening 244 is formed over the second gate structure 206-2 or the third gate structure 206-3, through a fourth ILD layer 242, a third ILD layer 234, a second ILD layer 228, a MESL 226, and a SAC layer 216, and may include the use of photolithography and / or etching processes. The photolithography process includes forming a resist layer over the fourth ILD layer 242, exposing the resist layer to patterned radiation, and developing the exposed resist layer to form a patterned resist layer. The patterned resist layer is then used as an etching mask to etch the workpiece 200 in a dry etching process. Exemplary dry etching processes for frame 122 may include the use of oxygen (O2), nitrogen (N2), hydrogen (H2), fluorine-containing gases (e.g., CF4, SF6, NF3, BF3, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. Following the dry etching process, the patterned resist layer may be removed by ashing. A wet cleaning process may be implemented to remove debris from the capping layer 208 above the second gate structure 206-2 and the third gate structure 206-3. In some embodiments, the wet cleaning process may include the use of deionized (DI) water or isopropanol (IPA).

[0033] refer to Figure 1 , Figure 13 ,and Figure 14 Method 100 includes block 124, wherein a gate contact 250 is formed in a gate contact opening 244. The gate contact 250 may include a metal filler layer 248. The metal filler layer 248 for the gate contact 250 may include tungsten (W) or ruthenium (Ru) and may be deposited using bottom-up selective CVD. Figure 13 After the metal filler layer 248 shown is deposited on top of the workpiece 200, the workpiece 200 is planarized using a CMP process to form a shape as shown. Figure 14 The gate contact 250 is shown. Planarization is implemented at frame 124 until the top surfaces of the gate contact 250, the source / drain contact via 240, and the third ILD layer 234 are coplanar. The top surfaces of the gate contact 250, the source / drain contact via 240, and the third ILD layer 234 are all higher than the top surface of the contact point 232 by the thickness T of the third ILD layer 234. In some cases, Figure 14The thickness T of the third ILD layer 234 can be between approximately 5 nm and approximately 45 nm. When the thickness of the third ILD layer 234 is greater than 45 nm, the aspect ratio of the gate contact opening 244 or the source / drain contact via opening 236 may be too large, resulting in unsatisfactory metal filling. When the thickness of the third ILD layer 234 is less than 5 nm, the contact point 232 may not be sufficiently insulated from the overlying metal lines or contact structure.

[0034] Still referencing Figure 14 According to the present invention, contact point 232 includes a lower portion extending into the SAC layer 216 above the first gate structure 206-1, and an upper portion disposed above the first source / drain contact 224-1 and the lower portion. The lower portion of contact point 232 is disposed between two adjacent gate spacers 210 and contacts the capping layer 208 on the first gate structure 206-1. The upper portion of contact point 232 is disposed in the MESL 226 and the second ILD layer 228. Figure 14 As shown, along the perpendicular to substrate 202 ( Figure 2In the Z direction (as shown), the lower portion has a first height H1, and the upper portion has a second height H2. In the depicted embodiment, the first height H1 substantially corresponds to the thickness of the SAC layer 216 and falls within the range of approximately 10 nm to approximately 25 nm. When the thickness of the SAC layer 216 is greater than 25 nm, the additional etching required to damage the SAC layer 216 when forming the contact opening 230 may penetrate the first source / drain contact 224-1. When the thickness of the SAC layer 216 is less than 10 nm, the contact opening 230 may laterally extend, resulting in undesirable connections to adjacent gate contacts. The upper second height H2 substantially corresponds to the total thickness of the MESL 226 and the second ILD layer 228 and can be between approximately 30 nm and approximately 40 nm. When the second height H2 is less than 30 nm, the formation of the contact opening 230 may damage the first gate structure 206-1 and the capping layer 208. When the second height H2 is greater than 40 nm, the contact opening 230 may not satisfactorily expose the capping layer 208 above the first gate structure 206-1. The contact 232 has a third height H3, which is the sum of the lower first height H1 and the upper second height H2. In some cases, the third height H3 can be between approximately 40 nm and 60 nm. The lower portion has a first top opening width W1 along the X direction, while the upper portion has a second opening width W2 along the X direction. In some cases, the first top opening width W1 can be between approximately 10 nm and approximately 25 nm, while the second top opening width W2 can be between approximately 14 nm and approximately 40 nm. When the second top opening width W2 is less than 14 nm, the contact 232 may have poor landing on the first source / drain contact 224-1. When the second top opening width W2 is greater than 40 nm, the contact 232 may contact adjacent gate contacts, resulting in undesirable electrical connections. In general, the contact point 232 of the present invention has a nominal aspect ratio between about 0.9 and about 2 (i.e., the third height H3 divided by the second top opening width W2, or H3 / W2). It can be seen that if the hypothetical contact point also extends through the third ILD layer 234 having a thickness T, its aspect ratio would be calculated as the sum of the third height H3 and the thickness T divided by the second opening width W2. This hypothetical contact point has a nominal aspect ratio between about 1.5 and 3, which would hinder satisfactory metal filling in its underside and could lead to voids and defects. These voids and defects could increase contact resistance.

[0035] Figure 14The contact point 232, source / drain contact via 240, and gate contact 250 are depicted along the same cross section. In some embodiments, although the shape, depth, and relative vertical position may remain the same, the contact point 232, source / drain contact via 240, and gate contact 250 may not be on the same cross section. Figure 15 An example is provided in which the pair contact 232, source / drain contact via 240, and gate contact 250 of semiconductor device 200 do not necessarily appear on the same cross section. Figure 15 The semiconductor device 200 includes a plurality of gate structures 206 extending along the Y direction, a plurality of active regions 204 extending along the X direction, and a plurality of source / drain contacts 224 extending along the Y direction. The semiconductor device 200 includes a plurality of pair contacts 232, a plurality of source / drain contact vias 240, and a plurality of gate contacts 250. Each of the pair contacts 232 spans and is electrically connected to the gate structure 206 and the adjacent source / drain contact 224. Each of the source / drain contact vias 240 is disposed directly above the source / drain contact 224. Each of the gate contacts 250 is disposed directly above the gate structure 206 and is electrically connected to the gate structure 206. Figure 15 As shown, cutting the cross section of contact point 232 along the X direction does not cut through any source / drain contact via 240 or any gate contact 250.

[0036] The contact points and method of this invention offer several advantages. For example, the contact point openings that expose the gate structure and adjacent source / drain contacts are not deeper than the source / drain contact via openings or the gate contact openings. This results in a smaller aspect ratio for the contact point openings, which facilitates satisfactory metal filling. The contact points can be formed of tungsten (W) and can be deposited using a combination of PVD and CVD. The smaller aspect ratio and two-stage metal filling improve the integrity of the contact points and reduce the contact resistance to the gate structure.

[0037] This invention provides numerous different embodiments. In one embodiment, a method is provided. The method includes: receiving a workpiece including: a first gate structure including a first capping layer on the first gate structure; a first source / drain contact adjacent to the first gate structure; a second gate structure including a second capping layer on the second gate structure; a second source / drain contact; an etch stop layer (ESL) located over the first source / drain contact and the second source / drain contact; and a first dielectric layer located over the ESL. The method further includes: forming a pair of contact openings to expose the first capping layer and the first source / drain contact; forming a pair of contacts in the pair of contact openings; depositing a second dielectric layer after forming the pair of contacts; forming a source / drain contact via opening through the second dielectric layer, the ESL layer, and the first dielectric layer to expose the second source / drain contact; and forming a source / drain contact via in the source / drain contact via opening.

[0038] In some embodiments, the method may further include: depositing a third dielectric layer over the source / drain contact via after forming the source / drain contact via; forming a gate contact via opening to expose a second capping layer; and forming a gate contact via in the gate contact via opening. In some embodiments, the method may further include: recessing a second source / drain contact before forming the source / drain contact via. In some embodiments, recessing the second source / drain contact includes using hydrogen peroxide. In some cases, the first and second capping layers comprise fluorine-free tungsten. In some embodiments, the first and second source / drain contacts comprise cobalt. In some embodiments, forming a pair of contacts includes: depositing a barrier layer over the pair of contact opening using physical vapor deposition (PVD); depositing a metal fill layer over the barrier layer using chemical vapor deposition (CVD); and planarizing the deposited metal fill layer. In some embodiments, after planarization, the top surface of the pair of contacts is coplanar with the top surface of the first dielectric layer. In some embodiments, the metal fill layer comprises tungsten.

[0039] In another embodiment, a method is provided. The method includes: receiving a workpiece including: a first gate structure; a first source / drain contact adjacent to the first gate structure; a second gate structure; a second source / drain contact; an etch stop layer (ESL) above the first source / drain contact and the second source / drain contact; and a first dielectric layer above the ESL. The method may further include: forming a pair of contacts to connect to the first gate structure and the first source / drain contact; depositing a second dielectric layer over the first dielectric layer and the pair of contacts; forming a source / drain contact via through the second dielectric layer, the first dielectric layer, and the ESL layer to connect the second source / drain contact; depositing a third dielectric layer over the source / drain contact via and the second dielectric layer; and forming a gate contact through the third dielectric layer, the second dielectric layer, the first dielectric layer, and the ESL layer to connect to the second gate structure.

[0040] In some embodiments, the method may further include: planarizing the workpiece after forming the gate contact until the top surface of the gate contact is coplanar with the top surface of the source / drain contact via. In some embodiments, the workpiece may further include: a first capping layer over the first gate structure; a second capping layer over the second gate structure; a first self-aligned capping (SAC) layer over the first capping layer; and a second SAC layer over the second capping layer. In some embodiments, a portion of the pair of contacts extends through the first SAC layer to land on the first capping layer. In some embodiments, the gate contact extends through the second SAC layer to land on the second capping layer. In some embodiments, forming the pair of contacts includes: forming a pair of contact opening to expose the top surfaces of the first source / drain contact and the first capping layer; depositing a barrier layer over the pair of contact opening using physical vapor deposition (PVD); depositing a metal fill layer over the barrier layer using chemical vapor deposition (CVD); and planarizing the deposited metal fill layer. In some embodiments, the metal fill layer includes tungsten.

[0041] In another embodiment, a semiconductor structure is provided. The semiconductor structure includes: a first gate structure including a first capping layer; a first source / drain contact adjacent to the first gate structure; a second gate structure including a second capping layer; a second source / drain contact; an etch stop layer (ESL) located above the first source / drain contact and the second source / drain contact; a first dielectric layer located above the ESL; a second dielectric layer located above the first dielectric layer; a pair of contacts spanning over the first gate structure and the first source / drain contact, and contacting the first source / drain contact and the first capping layer; a source / drain contact via disposed above the second source / drain contact; and a gate contact disposed above the second capping layer. The second dielectric layer is disposed directly above the top surface of the pair of contacts.

[0042] In some embodiments, the first source / drain contact and the second source / drain contact comprise cobalt. In some cases, the first and second capping layers comprise fluorine-free tungsten. In some embodiments, the contact points comprise tungsten.

[0043] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a contact structure, comprising: Receiving workpieces, including: A first gate structure includes a first cover layer on the first gate structure, and a first self-aligned cover layer is further included above the first cover layer; The first source / drain contact is adjacent to the first gate structure; The second gate structure includes a second cover layer. Second source / drain contact; An etch stop layer is located above the first source / drain contact and the second source / drain contact; and A first dielectric layer is located above the etch stop layer; An opening is formed at the contact point to expose the first cover layer and the first source / drain contact; A pair of contact points is formed in the opening of the pair of contact points, and a portion of the pair of contact points extends through the first self-aligning cover layer to contact the first cover layer; After the formation of the contact points, a second dielectric layer is deposited; Forming a via opening through the second dielectric layer, the etch stop layer, and the first dielectric layer to expose the second source / drain contacts; and A source / drain contact via is formed in the opening of the source / drain contact via.

2. The method for forming a contact structure according to claim 1, further comprising: After forming the source / drain contact via, a third dielectric layer is deposited above the source / drain contact via; A gate contact via opening is formed to expose the second cover layer; as well as A gate contact via is formed in the gate contact via opening.

3. The method for forming a contact structure according to claim 1 further includes: Before forming the source / drain contact via, the second source / drain contact is recessed.

4. The method for forming a contact structure according to claim 3, wherein, The recessed second source / drain contact includes the use of hydrogen peroxide.

5. The method for forming a contact structure according to claim 1, wherein, The first and second cover layers comprise fluorine-free tungsten.

6. The method for forming a contact structure according to claim 1, wherein, The first source / drain contact and the second source / drain contact comprise cobalt and have no barrier layer.

7. The method for forming a contact structure according to claim 1, wherein, The formation of the contact points includes: A barrier layer was deposited over the opening at the contact point using physical vapor deposition (PVD); A metal filler layer is deposited over the barrier layer using chemical vapor deposition (CVD); and Planarize the deposited metal filler layer.

8. The method for forming a contact structure according to claim 7, wherein, After planarization, the top surface of the contact point is coplanar with the top surface of the first dielectric layer.

9. The method for forming a contact structure according to claim 7, wherein, The metal filler layer includes tungsten.

10. A method for forming a contact structure, comprising: Receiving workpieces, including: First gate structure; A first cover layer is located above the first gate structure; A first self-aligned overlay is located above the first overlay; The first source / drain contact is adjacent to the first gate structure; Second gate structure; Second source / drain contact; An etch stop layer is located above the first source / drain contact and the second source / drain contact; and A first dielectric layer is located above the etch stop layer; A pair of contact points are formed to connect to the first gate structure and the first source / drain contact, wherein a portion of the pair of contact points extends through the first self-aligned capping layer to contact the first capping layer; A second dielectric layer is deposited above the first dielectric layer and the contact points; A via is formed through the second dielectric layer, the first dielectric layer, and the etch stop layer to connect the second source / drain contact; A third dielectric layer is deposited over the source / drain contact via and the second dielectric layer; and A gate contact is formed through the third dielectric layer, the second dielectric layer, the first dielectric layer, and the etch stop layer to connect the second gate structure.

11. The method for forming a contact structure according to claim 10, further comprising: After the gate contact is formed, the workpiece is planarized until the top surface of the gate contact is coplanar with the top surface of the source / drain contact via.

12. The method for forming a contact structure according to claim 10, wherein, The workpiece also includes: A second cover layer is located above the second gate structure; and A second self-aligned overlay is located above the second overlay.

13. The method for forming a contact structure according to claim 12, wherein, A portion of the contact point extends through the first self-aligned cover layer to land on the first cover layer.

14. The method for forming a contact structure according to claim 12, wherein, The gate contact extends through the second self-aligned cover layer to land on the second cover layer.

15. The method for forming a contact structure according to claim 12, wherein, The formation of the contact points includes: An opening is formed at the contact point to expose the first source / drain contact and the top surface of the first capping layer; A barrier layer was deposited over the opening at the contact point using physical vapor deposition (PVD); A metal filler layer is deposited over the barrier layer using chemical vapor deposition (CVD); and Planarize the deposited metal filler layer.

16. The method for forming a contact structure according to claim 15, wherein, The metal filler layer includes tungsten.

17. A semiconductor structure comprising: A first gate structure includes a first cover layer on the first gate structure, and a first self-aligned cover layer is further included above the first cover layer; The first source / drain contact is adjacent to the first gate structure; The second gate structure includes a second cover layer. Second source / drain contact; An etch stop layer is located above the first source / drain contact and the second source / drain contact; A first dielectric layer is located above the etch stop layer; The second dielectric layer is located above the first dielectric layer; The pair of contacts spans over the first gate structure and the first source / drain contact, the pair of contacts contacts the first source / drain contact, and a portion of the pair of contacts extends through the first self-aligned capping layer to contact the first capping layer. A source / drain contact via is disposed above the second source / drain contact; as well as Gate contacts are disposed above the second cover layer. The second dielectric layer is disposed directly above the top surface of the contact point.

18. The semiconductor structure according to claim 17, wherein, The first source / drain contact and the second source / drain contact comprise cobalt and have no barrier layer.

19. The semiconductor structure according to claim 17, wherein, The first and second cover layers comprise fluorine-free tungsten.

20. The semiconductor structure according to claim 17, wherein, The contact points comprise tungsten.

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