Semiconductor structure and manufacturing method

Abstract

This disclosure provides a semiconductor structure and a method for manufacturing the same. By exposing a portion of the first active component in the first bottom dielectric layer, the thickness of the first bottom dielectric layer is reduced. This allows other electronic components to be stacked on the first bottom dielectric layer in this manner, thereby reducing the overall thickness of the semiconductor structure and achieving miniaturization and thinning of semiconductor packaged products.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to semiconductor structures and their manufacturing methods. Background Technology

[0002] With the increasing demand for miniaturization, multifunctionality, and high efficiency in electronic product systems, high-density packaging structures such as stacked packaging structures and double-side modules (DSMs) are receiving more and more attention in System-in-Package (SiP) applications.

[0003] However, in order to achieve more functions, the number of integrated semiconductor components (such as memory chips) is increasing. Semiconductor components stacked on the substrate surface require more space, and existing high-density packaging structures are difficult to reduce thickness, which hinders the miniaturization and thinning of semiconductor packaging products. Summary of the Invention

[0004] This disclosure provides semiconductor structures and methods for manufacturing them.

[0005] In a first aspect, this disclosure provides a semiconductor structure comprising: a first redistribution layer including a first bottom wiring layer and a first bottom dielectric layer, wherein the first bottom wiring layer is embedded in the first bottom dielectric layer; a first passive component electrically connected to the first bottom wiring layer; a first active component electrically connected to the first bottom wiring layer, the first active component having a first side surface; a first molding layer covering the first redistribution layer, the first passive component, and the first active component; wherein a portion of the first bottom dielectric layer exposes the first active component so that the first side surface contacts the first bottom dielectric layer and the first molding layer.

[0006] In some alternative implementations, the first bottom dielectric layer exposes a portion of the first passive component.

[0007] In some alternative embodiments, the first redistribution layer further includes a first intermediate circuit layer, a first top circuit layer, and a first top dielectric layer. The first top dielectric layer is disposed on the first bottom dielectric layer. The first intermediate circuit layer is electrically connected to the first bottom circuit layer and the first top circuit layer, respectively. The first top circuit layer is embedded in the first top dielectric layer and exposed from the first top dielectric layer.

[0008] In some alternative implementations, the first top dielectric layer covers a portion of the first passive component and exposes a portion of the first active component so that the first side surface contacts the first top dielectric layer.

[0009] In some alternative implementations, the semiconductor structure further includes a first electronic component electrically connected to the first top line layer.

[0010] In some alternative implementations, the width of the first top dielectric layer is smaller than the width of the first bottom dielectric layer.

[0011] In some alternative implementations, the thickness of the first active component is greater than the thickness of the first passive component.

[0012] In some alternative embodiments, the semiconductor structure further includes: a substrate having a first surface and a second surface opposite to the first surface, wherein a first bottom circuit layer is disposed on the first surface.

[0013] In some alternative embodiments, the semiconductor structure further includes: a second redistribution layer including a second bottom wiring layer and a second bottom dielectric layer, the second bottom dielectric layer being disposed on a second surface and the second bottom wiring layer being embedded within the second bottom dielectric layer; a second passive component electrically connected to the second bottom wiring layer; a second active component electrically connected to the second bottom wiring layer, the second active component having a second side surface; a second molding layer covering the second redistribution layer, the second passive component, and the second active component; the second bottom dielectric layer exposing a portion of the second active component so that the second side surface contacts the second bottom dielectric layer and the second molding layer.

[0014] In some alternative implementations, the second bottom dielectric layer exposes a portion of the second passive component.

[0015] In some alternative embodiments, the second rewiring layer further includes a second intermediate wiring layer, a second top wiring layer, and a second top dielectric layer, wherein the second intermediate wiring layer is electrically connected to the second bottom wiring layer and the second top wiring layer, respectively, and the second top wiring layer is embedded in the second top dielectric layer and exposed from the second top dielectric layer.

[0016] In some alternative implementations, the second top dielectric layer covers a portion of the second passive component and exposes a portion of the second active component so that the second side surface contacts the second top dielectric layer.

[0017] In some alternative implementations, the semiconductor structure further includes a second electronic component electrically connected to the second top line layer.

[0018] In some alternative implementations, the width of the second top dielectric layer is smaller than the width of the second bottom dielectric layer.

[0019] In some alternative implementations, the thickness of the second active component is greater than the thickness of the second passive component.

[0020] In some optional embodiments, the linewidth and line spacing L / S of the first bottom line layer and / or the second bottom line layer are greater than 50 μm, and the thickness of the first bottom line layer and / or the second bottom line layer is between 20 μm and 50 μm; the L / S of the first intermediate line layer and / or the second intermediate line layer is less than 20 μm, and the thickness of the first intermediate line layer and / or the second intermediate line layer is between 5 μm and 30 μm; the L / S of the first top line layer and / or the second top line layer is less than 50 μm, and the thickness of the first top line layer and / or the second top line layer is between 10 μm and 30 μm.

[0021] In a second aspect, this disclosure provides a method for manufacturing a semiconductor structure, the method comprising: disposing a first passive component and a first active component on a first bottom circuit layer, the first passive component and the first active component being electrically connected to the first bottom circuit layer respectively, the first active component having a first side surface; disposing a first bottom dielectric layer on the first bottom circuit layer such that the first bottom circuit layer is embedded in the first bottom dielectric layer; filling in a first molding compound, the first molding compound covering a first redistribution layer, the first passive component and the first active component to form a first molding layer, wherein a portion of the first bottom dielectric layer exposes the first active component such that the first side surface contacts the first bottom dielectric layer and the first molding layer.

[0022] In some alternative implementations, the first bottom dielectric layer exposes a portion of the first passive component.

[0023] In some alternative embodiments, before the first passive component and the first active component are disposed on the first bottom circuit layer, the method further includes: providing a substrate having a first surface and a second surface opposite to the first surface; and disposing the first bottom circuit layer on the first surface of the substrate.

[0024] In some alternative embodiments, before filling the first molding compound, the method further includes: disposing a first intermediate circuit layer on a first bottom dielectric layer; disposing a first top dielectric layer on the first intermediate circuit layer; disposing a first top circuit layer on the first top dielectric layer, wherein the first intermediate circuit layer is electrically connected to the first bottom circuit layer and the first top circuit layer respectively, the first top dielectric layer covers a portion of the first passive component and exposes a portion of the first active component so that a first side surface contacts the first top dielectric layer; and disposing a first electronic component on the first top circuit layer, wherein the first electronic component is electrically connected to the first top circuit layer.

[0025] In some optional embodiments, the method further includes: forming a second bottom circuit layer on a second surface of a substrate; forming a second passive component and a second active component on the second bottom circuit layer, the second passive component and the second active component being electrically connected to the second bottom circuit layer respectively, the second active component having a second side surface; forming a second bottom dielectric layer on the second bottom circuit layer such that the second bottom circuit layer is embedded within the second bottom dielectric layer; filling in a second molding compound, the second molding compound covering the second redistribution layer, the second passive component and the second active component to form a second molding layer, the second bottom dielectric layer exposing a portion of the second active component such that the second side surface contacts the second bottom dielectric layer and the second molding layer.

[0026] In some alternative implementations, the second bottom dielectric layer exposes a portion of the second passive component.

[0027] In some alternative embodiments, before filling the second molding compound, the method further includes: disposing a second intermediate circuit layer on the second bottom dielectric layer; disposing a second top dielectric layer on the second intermediate circuit layer; disposing a second top circuit layer on the second top dielectric layer, wherein the second intermediate circuit layer is electrically connected to the second bottom circuit layer and the second top circuit layer respectively, the second top dielectric layer covers a portion of the second passive component and exposes a portion of the second active component so that the second side surface contacts the second top dielectric layer; and disposing a second electronic component on the second top circuit layer, wherein the second electronic component is electrically connected to the second top circuit layer.

[0028] To address the issue of limited thickness reduction in existing high-density packaging structures, the semiconductor structure and manufacturing method disclosed herein reduce the thickness of the first bottom dielectric layer by exposing a portion of the first active component. This allows for the stacking of other electronic components on the first bottom dielectric layer in this manner, thereby reducing the overall thickness of the semiconductor structure and achieving miniaturization and thinning of the semiconductor packaged product. Attached Figure Description

[0029] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0030] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0031] Figure 2A This is a schematic diagram of a semiconductor structure according to yet another embodiment of the present disclosure;

[0032] Figure 2B This is a schematic diagram of a semiconductor structure according to yet another embodiment of the present disclosure;

[0033] Figure 3 This is a schematic diagram of a semiconductor structure according to yet another embodiment of the present disclosure;

[0034] Figure 4 This is a schematic diagram of a semiconductor structure according to yet another embodiment of the present disclosure;

[0035] Figures 5A to 5E A structural schematic diagram of the semiconductor structure manufacturing process according to this disclosure;

[0036] Figure 6A This is a schematic diagram of a semiconductor structure according to yet another embodiment of the present disclosure;

[0037] Figure 6B This is a schematic diagram of a semiconductor structure according to yet another embodiment of the present disclosure;

[0038] Figure 7 This is a schematic diagram of a semiconductor structure according to yet another embodiment of the present disclosure;

[0039] Figure 8 This is a schematic diagram of a semiconductor structure according to yet another embodiment of the present disclosure.

[0040] Symbol explanation:

[0041] 1-First redistribution layer, 101-First bottom circuit layer, 102-First bottom dielectric layer, 103-First intermediate circuit layer, 104-First top dielectric layer, 105-First top circuit layer, 2-First passive component, 3-First active component, 4-First electronic component, 5-First molding layer, 6-Substrate, 7-Second redistribution layer, 701-Second bottom circuit layer, 702-Second bottom dielectric layer, 703-Second intermediate circuit layer, 704-Second top dielectric layer, 705-Second top circuit layer, 8-Second passive component, 9-Second active component, 10-Second electronic component, 11-Second molding layer, 12-Third electronic component, 13-External electrical connector. Detailed Implementation

[0042] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0043] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0044] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0045] Please refer to Figure 1 , Figure 1 A schematic diagram of a semiconductor structure according to an embodiment of the present disclosure is shown. The semiconductor structure may include: a first redistribution layer 1, a first passive component 2, a first active component 3, and a first molding layer 5. The first redistribution layer 1 may include a first bottom wiring layer 101 and a first bottom dielectric layer 102. The first bottom wiring layer 101 may be embedded within the first bottom dielectric layer 102. The first passive component 2 may be electrically connected to the first bottom wiring layer 101. The first active component 3 may have a first side surface. The first molding layer 5 may cover the first redistribution layer 1, the first passive component 2, and the first active component 3. The first bottom dielectric layer 102 may expose a portion of the first active component 3 so that the first side surface contacts the first bottom dielectric layer 102 and the first molding layer 5.

[0046] The first redistribution layer 1 can be, for example, a hybrid redistribution layer, which can include conductive traces of different sizes, and conductive traces of different sizes can correspond to different numbers of I / O (Input / Output).

[0047] The first rewiring layer 1 can be a single layer or multiple layers. In practice, depending on the number of I / Os and design requirements, single-layer or multi-layer rewiring can be implemented. For multi-layer rewiring, please refer to... Figure 4 , Figure 4 A schematic diagram of another embodiment of the semiconductor structure according to the present disclosure is shown.

[0048] The first bottom dielectric layer 102 can be made of, for example, silicon oxide, polyimide (PI), or other suitable dielectric materials. The first bottom dielectric layer 102 can cover the electrical contacts of the first passive component 2 and the gap between the electrical contacts of the first passive component 2 and the substrate 6, thus serving to fix the first active component 3 and the first passive component 2.

[0049] The first bottom circuit layer 101 can be made of metals such as gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu) or their alloys.

[0050] The first passive component 2 can be, for example, a capacitor, an inductor, a resistor, etc.

[0051] The first active component 3 can be, for example, a chip of various sizes and functions.

[0052] The first molding layer 5 can be formed from various molding compounds. For example, molding compounds may include epoxy resin, BT (Bismaleimide Triazine Resin) resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0053] In existing semiconductor structures, the bottom dielectric layer can cover the active component, so the side surface of the active component only contacts the bottom dielectric layer. However, in the semiconductor structure disclosed herein, because the first bottom dielectric layer 102 exposes part of the first active component 3, the first side surface of the first active component 3 can contact the first bottom dielectric layer 102 and the first molding layer 5.

[0054] Compared to existing semiconductor structures, the first bottom dielectric layer 102 of the semiconductor structure disclosed herein has a smaller thickness, which can effectively reduce the thickness of the semiconductor structure. Furthermore, the first active component 3 is partially embedded within the first bottom dielectric layer 102, which can improve its stress resistance.

[0055] In some alternative implementations, the first bottom dielectric layer 102 may expose a portion of the first passive component 2.

[0056] In some optional embodiments, the first redistribution layer 1 may further include a first intermediate wiring layer 103, a first top wiring layer 105 and a first top dielectric layer 104. The first top dielectric layer 104 is disposed on the first bottom dielectric layer 102. The first intermediate wiring layer 103 is electrically connected to the first bottom wiring layer 101 and the first top wiring layer 105 respectively. The first top wiring layer 105 is embedded in the first top dielectric layer 104 and exposed from the first top dielectric layer 104.

[0057] In some alternative implementations, the first top dielectric layer 104 may cover a portion of the first passive component 2 and expose a portion of the first active component 3 such that the first side surface contacts the first top dielectric layer 104.

[0058] Since the first bottom dielectric layer 102 can expose a portion of the first passive component 2, the first top dielectric layer 104 disposed on the first bottom dielectric layer 102 can cover a portion of the first passive component 2. Since the first bottom dielectric layer 102 can expose a portion of the first active component 3, the first side surface of the first active component 3 can contact the first bottom dielectric layer 102, the first top dielectric layer 104, and the first molding layer 5.

[0059] Please refer to Figure 6A , Figure 6A A schematic diagram of another embodiment of the semiconductor structure according to the present disclosure is shown.

[0060] In some alternative implementations, such as Figure 6A As shown, the first mold sealing layer 5 can expose a portion of the first bottom dielectric layer 102.

[0061] Please refer to Figure 6B , Figure 6B A schematic diagram of another embodiment of the semiconductor structure according to the present disclosure is shown.

[0062] In some alternative implementations, such as Figure 6B As shown, the first mold sealing layer 5 can further expose a portion of the first top dielectric layer 104.

[0063] In some alternative implementations, the semiconductor structure may further include: a first electronic component 4 electrically connected to the first top line layer 105.

[0064] The first electronic component 4 can be an active component (such as a chip) or a passive component (such as a capacitor, inductor, or resistor).

[0065] Please refer to Figure 3 , Figure 3 A schematic diagram of another embodiment of the semiconductor structure according to the present disclosure is shown.

[0066] In some alternative implementations, the semiconductor structure may further include a third electronic component 12 electrically connected to the second intermediate circuit layer 703.

[0067] The third electronic component 12 can be an active component, such as a chip, or a passive component, such as a capacitor, inductor, or resistor.

[0068] In practice, the placement and arrangement of electronic components can be adjusted according to actual design requirements. For example, a first active component 3 and a first passive component 2 can be sequentially placed on the first bottom circuit layer 101, a third electronic component 12 can be placed on the first middle circuit layer 103, and a first electronic component 4 can be placed on the first top circuit layer 105. Alternatively, the first active component 3 and the first passive component 2 can be placed on the first bottom circuit layer 101, and the first electronic component 4 can be placed on the first top circuit layer 105.

[0069] The electronic components offer high flexibility in placement, are suitable for multi-size chip packaging, have high packaging density and compact size, and make high utilization of conductive vias between circuit layers, which helps reduce costs.

[0070] Please refer to Figure 2A , Figure 2A A schematic diagram of another embodiment of the semiconductor structure according to the present disclosure is shown.

[0071] In some alternative implementations, such as Figure 2A As shown, the width of the first top dielectric layer 104 can be smaller than the width of the first bottom dielectric layer 102.

[0072] Please refer to Figure 2B , Figure 2B A schematic diagram of another embodiment of the semiconductor structure according to the present disclosure is shown.

[0073] In some alternative implementations, such as Figure 2B As shown, the width of the first top dielectric layer 104 can be greater than the width of the first bottom dielectric layer 102, so that the first top dielectric layer 104 covers the side of the first bottom dielectric layer 102.

[0074] In existing semiconductor structures, the width of the bottom dielectric layer can be smaller than the width of the top dielectric layer, and the top dielectric layer can cover the bottom dielectric layer. A molding layer can also cover the top dielectric layer, and the side surface of the molding layer can be perpendicular to the horizontal plane. However, in the semiconductor structure disclosed herein, the width of the first top dielectric layer 104 can be smaller than the width of the first bottom dielectric layer 102, and the molding layer can cover both the first top dielectric layer 104 and the first bottom dielectric layer 102. The side surface of the molding layer can form an angle of less than 90 degrees with the horizontal plane, i.e., the side surface of the molding layer is an inclined surface.

[0075] Compared to existing semiconductor structures, the semiconductor structure disclosed herein has more circuit layers and more I / Os per unit package volume. Furthermore, since the width of the first top dielectric layer 104 is smaller than the width of the first bottom dielectric layer 102, forming a gradually inward-sloping side step, the side surface of the molding layer can be a sloping surface, which can effectively reduce the package size of the semiconductor structure and makes it less likely for stress to be generated and accumulated on the sides.

[0076] In practice, to increase the number of I / Os and meet product size requirements, the width or area of ​​the first bottom dielectric layer 102 can be maximized, making it easier to control the overall size of the semiconductor structure. However, in existing semiconductor products, the top dielectric layer has the largest width, but in the manufacturing process, because the bottom dielectric layer is set first and then the top dielectric layer is set on top of the bottom dielectric layer, it is difficult to control the overall size of the semiconductor structure.

[0077] In some alternative implementations, the thickness of the first active component 3 may be greater than the thickness of the first passive component 2.

[0078] In some alternative embodiments, the semiconductor structure further includes: a substrate 6 having a first surface and a second surface opposite to the first surface, wherein a first bottom circuit layer 101 is disposed on the first surface.

[0079] The substrate 6 can be a coreless substrate or a cored substrate. The substrate 6 can be made of rigid or flexible substrate materials. Rigid substrate materials can be, for example, copper-clad laminate materials, and flexible substrate materials can be, for example, PI (Polyimide) materials. The substrate 6 can be, for example, a PCB (Printed Circuit Board). The substrate 6 can be, for example, a BGA (Ball Grid Array) substrate, and can be provided with multiple external electrical connectors 13. The external electrical connectors 13 can be, for example, metal bumps and multiple solder balls.

[0080] In some alternative implementations, the portion of the first bottom dielectric layer 102 near the first active component 3 and the first passive component 2 may be curved.

[0081] When the first active component 3 and the first passive component 2 are placed on the substrate 6 in a vertical direction, capillary action occurs during the formation of the first bottom dielectric layer 102. The portion of the first bottom dielectric layer 102 near the first active component 3 and the first passive component 2 can be curved, which further fixes the first active component 3 and the first passive component 2, and enhances the adhesion and structural strength.

[0082] In some alternative embodiments, the semiconductor structure may further include: a second redistribution layer 7, including a second bottom circuit layer 701 and a second bottom dielectric layer 702, the second bottom dielectric layer 702 being disposed on a second surface, and the second bottom circuit layer 701 being embedded within the second bottom dielectric layer 702; a second passive component 8, electrically connected to the second bottom circuit layer 701; a second active component 9, electrically connected to the second bottom circuit layer 701, the second active component 9 having a second side surface; a second molding layer 11, covering the second redistribution layer 7, the second passive component 8, and the second active component 9; the second bottom dielectric layer 702 exposing a portion of the second active component 9 such that the second side surface contacts the second bottom dielectric layer 702 and the second molding layer 11.

[0083] The second redistribution layer 7 can be, for example, a hybrid redistribution layer, which can include conductive traces of different sizes, and conductive traces of different sizes can correspond to different numbers of I / O (Input / Output).

[0084] The second routing layer 7 can be a single layer or multiple layers. In practice, single-layer or multi-layer rerouting can be performed depending on the number of I / Os and design requirements.

[0085] The second bottom dielectric layer 702 can be made of, for example, silicon oxide, PI, or other suitable dielectric materials.

[0086] The second bottom circuit layer 701 can be, for example, made of metals such as gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), and copper (Cu) or their alloys. The second bottom dielectric layer 702 can cover the electrical contacts of the second passive component 8 and / or the gap between the electrical contacts of the second passive component 8 and the substrate 6, thus serving to fix the second active component 9 and / or the second passive component 8.

[0087] The second passive component 8 can be, for example, a capacitor, an inductor, a resistor, etc.

[0088] The second active component 9 can be, for example, a chip of various sizes and functions.

[0089] The second molding layer 11 can be formed from various molding compounds. For example, molding compounds may include epoxy resin, BT (Bismaleimide Triazine Resin) resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0090] The semiconductor structure disclosed herein can be applied to a DSM structure, with substrate 6 as the center, and the overall balance of the DSM structure is good.

[0091] In some alternative implementations, the second bottom dielectric layer 702 may expose a portion of the second passive component 8.

[0092] In some alternative embodiments, the second redistribution layer 7 may further include a second intermediate wiring layer 703, a second top wiring layer 705, and a second top dielectric layer 704. The second intermediate wiring layer 703 is electrically connected to the second bottom wiring layer 701 and the second top wiring layer 705, respectively. The second top wiring layer 705 is embedded in the second top dielectric layer 704 and exposed from the second top dielectric layer 704.

[0093] In some alternative implementations, the second top dielectric layer 704 may cover a portion of the second passive component 8 and expose a portion of the second active component 9 such that the second side surface contacts the second top dielectric layer 704.

[0094] In some alternative implementations, the semiconductor structure may further include a second electronic component 10 electrically connected to the second top line layer 705.

[0095] The second electronic component 10 can be an active component, such as a chip, or a passive component, such as a capacitor, inductor, or resistor.

[0096] In some alternative implementations, the width of the second top dielectric layer 704 may be smaller than the width of the second bottom dielectric layer 702.

[0097] In some alternative implementations, the thickness of the second active component 9 may be greater than the thickness of the second passive component 8.

[0098] In some optional embodiments, the line width and line spacing L / S of the first bottom line layer 101 and / or the second bottom line layer 701 can be greater than 50 μm, and the thickness of the first bottom line layer 101 and / or the second bottom line layer 701 can be between 20 μm and 50 μm; the L / S of the first intermediate line layer 103 and / or the second intermediate line layer 703 can be less than 20 μm, and the thickness of the first intermediate line layer 103 and / or the second intermediate line layer 703 can be between 5 μm and 30 μm; the L / S of the first top line layer 105 and / or the second top line layer 705 can be less than 50 μm, and the thickness of the first top line layer 105 and / or the second top line layer 705 can be between 10 μm and 30 μm.

[0099] The first bottom circuit layer 101, the first intermediate circuit layer 103, and the first top circuit layer 105 may include conductive traces of different sizes. The second bottom circuit layer 701, the second intermediate circuit layer 703, and the second top circuit layer 705 may also include conductive traces of different sizes. Different sizes of conductive traces can correspond to different numbers of I / O (Input / Output) operations.

[0100] Please refer to Figures 5A to 5E , Figures 5A to 5E A schematic diagram of the manufacturing process of the semiconductor structure according to the present disclosure is shown. The figures have been simplified for better understanding of the aspects of the present disclosure.

[0101] Please refer to Figure 5A A first passive component 2 and a first active component 3 can be set on the first bottom line layer 101.

[0102] The first passive component 2 and the first active component 3 can be electrically connected to the first bottom circuit layer 101, and the first active component 3 has a first side surface.

[0103] In some alternative implementations, the first bottom dielectric layer 102 may expose a portion of the first passive component 2.

[0104] In some alternative embodiments, before the first passive component 2 and the first active component 3 are disposed on the first bottom circuit layer 101, the method may further include: providing a substrate 6 having a first surface and a second surface opposite to the first surface; and disposing the first bottom circuit layer 101 on the first surface of the substrate 6.

[0105] In some alternative embodiments, a second bottom circuit layer 701 may be provided on the second surface of the substrate 6; a second passive component 8 and a second active component 9 are provided on the second bottom circuit layer 701, the second passive component 8 and the second active component 9 are electrically connected to the second bottom circuit layer 701 respectively, and the second active component 9 has a second side surface.

[0106] In some alternative implementations, the second bottom dielectric layer 702 exposes a portion of the second passive component 8.

[0107] Please refer to Figure 5B A first bottom dielectric layer 102 is provided on the first bottom circuit layer 101 so that the first bottom circuit layer 101 is embedded in the first bottom dielectric layer 102.

[0108] In some alternative embodiments, a second bottom dielectric layer 702 is provided on the second bottom circuit layer 701 so that the second bottom circuit layer 701 is embedded in the second bottom dielectric layer 702.

[0109] Please refer to Figure 5C In some optional embodiments, before filling the first molding compound, the method may further include: disposing a first intermediate circuit layer 103 on a first bottom dielectric layer 102; disposing a first top dielectric layer 104 on the first intermediate circuit layer 103; disposing a first top circuit layer 105 on the first top dielectric layer 104, wherein the first intermediate circuit layer 103 is electrically connected to the first bottom circuit layer 101 and the first top circuit layer 105 respectively, the first top dielectric layer 104 covers a portion of the first passive component 2 and exposes a portion of the first active component 3 so that the first side surface contacts the first top dielectric layer 104; and disposing a first electronic component 4 on the first top circuit layer 105, wherein the first electronic component 4 is electrically connected to the first top circuit layer 105.

[0110] In some alternative embodiments, before filling the second molding compound, the method may further include: disposing a second intermediate circuit layer 703 on the second bottom dielectric layer 702; disposing a second top dielectric layer 704 on the second intermediate circuit layer 703; disposing a second top circuit layer 705 on the second top dielectric layer 704, wherein the second intermediate circuit layer 703 is electrically connected to the second bottom circuit layer 701 and the second top circuit layer 705 respectively, the second top dielectric layer 704 covers a portion of the second passive component 8 and exposes a portion of the second active component 9 so that the second side surface contacts the second top dielectric layer 704; and disposing a second electronic component 10 on the second top circuit layer 705, wherein the second electronic component 10 is electrically connected to the second top circuit layer 705.

[0111] Please refer to Figure 5D The first molding compound is filled in, and the first molding compound covers the first redistribution layer 1, the first passive component 2 and the first active component 3 to form the first molding layer 5. The first bottom dielectric layer 102 exposes a portion of the first active component 3 so that the first side surface contacts the first bottom dielectric layer 102 and the first molding layer 5.

[0112] In some alternative embodiments, the method may further include: filling a second molding compound that covers the second redistribution layer 7, the second passive component 8, and the second active component 9 to form a second molding compound 11, wherein a portion of the second bottom dielectric layer 702 exposes the second active component 9 so that a second side surface contacts the second bottom dielectric layer 702 and the second molding compound 11.

[0113] Please refer to Figure 5D In some alternative embodiments, the method may further include: providing an external electrical connector 13 on a second surface of the substrate 6.

[0114] Please refer to Figure 7 , Figure 7 A schematic diagram of another embodiment of the semiconductor structure according to the present disclosure is shown.

[0115] In some alternative implementations, such as Figure 7 As shown, the first surface of the substrate 6 may be provided with a plurality of separate first bottom dielectric layers 102 and a first top dielectric layer 104 stacked on the first bottom dielectric layers 102, and each is covered by a separate first molding layer 5. The second surface of the substrate 6 may be provided with a second bottom dielectric layer 702 and the second top dielectric layer 704 stacked on the second bottom dielectric layer 702 may be continuous (i.e. not separated (left and right)), but each is covered by a separate second molding layer 11.

[0116] Please refer to Figure 8 , Figure 8 A schematic diagram of another embodiment of the semiconductor structure according to the present disclosure is shown.

[0117] In some alternative implementations, such as Figure 8 As shown, the first bottom wiring layer 101 and the first top wiring layer 105 can be electrically connected via a bond wire. The first intermediate wiring layer 103 and the first top wiring layer 105 can also be electrically connected via a bond wire. That is, they can be electrically connected using wire bonding.

[0118] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent components can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor structure, comprising: The first wiring layer includes a first bottom wiring layer and a first bottom dielectric layer, wherein the first bottom wiring layer is embedded in the first bottom dielectric layer. The first passive component is electrically connected to the first bottom circuit layer; A first active component is electrically connected to the first bottom wiring layer, and the first active component has a first side surface; The first module cover layer encapsulates the first wiring layer, the first passive component, and the first active component; The first bottom dielectric layer exposes a portion of the first active component so that the first side surface contacts the first bottom dielectric layer and the first molding layer.

2. The semiconductor structure according to claim 1, wherein, The first bottom dielectric layer exposes a portion of the first passive component.

3. The semiconductor structure according to claim 2, wherein, The first redistribution layer further includes a first intermediate circuit layer, a first top circuit layer, and a first top dielectric layer. The first top dielectric layer is disposed on the first bottom dielectric layer. The first intermediate circuit layer is electrically connected to the first bottom circuit layer and the first top circuit layer, respectively. The first top circuit layer is embedded in the first top dielectric layer and exposed from the first top dielectric layer.

4. The semiconductor structure according to claim 3, wherein, The first top dielectric layer covers a portion of the first passive component and exposes a portion of the first active component so that the first side surface contacts the first top dielectric layer.

5. The semiconductor structure according to claim 3 or 4, wherein, The semiconductor structure also includes: The first electronic component is electrically connected to the first top line layer.

6. The semiconductor structure according to claim 3, wherein, The width of the first top dielectric layer is smaller than the width of the first bottom dielectric layer.

7. The semiconductor structure according to claim 1, wherein, The thickness of the first active component is greater than the thickness of the first passive component.

8. The semiconductor structure according to claim 5, wherein, The semiconductor structure also includes: The substrate has a first surface and a second surface opposite to the first surface, and the first bottom circuit layer is disposed on the first surface.

9. The semiconductor structure according to claim 8, wherein, The semiconductor structure also includes: The second wiring layer includes a second bottom wiring layer and a second bottom dielectric layer, wherein the second bottom dielectric layer is disposed on the second surface and the second bottom wiring layer is embedded in the second bottom dielectric layer. The second passive component is electrically connected to the second bottom circuit layer; A second active component is electrically connected to the second bottom circuit layer, and the second active component has a second side surface; The second encapsulation layer covers the second rewiring layer, the second passive component, and the second active component; The second bottom dielectric layer exposes a portion of the second active component so that the second side surface contacts the second bottom dielectric layer and the second molding layer.

10. The semiconductor structure according to claim 9, wherein, The second bottom dielectric layer exposes a portion of the second passive component.

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