Package structure, package and method of forming the same

Abstract

Embodiments of the present invention provide a package structure, a package, and a method of forming the same. The package structure includes a first die, a second die over the first die and electrically connected to the first die, an insulating material around the second die, a first antenna extending through the insulating material and electrically connected to the second die, the first antenna adjacent to a first sidewall of the second die, wherein the first antenna includes a first conductive plate extending through the insulating material and a plurality of first conductive pillars extending through the insulating material, and wherein the first conductive plate is between the plurality of first conductive pillars and the first sidewall of the second die.

Description

Technical Field

[0001] The embodiments of the present invention provide a package structure, a package, and a method for forming the same. Background Technology

[0002] In modern semiconductor devices and systems, the integration and miniaturization of components are progressing at an increasingly rapid pace. In wireless applications, a growing challenge in the integration process is the placement of radio frequency devices or antennas. Conventional antenna designs associated with integrated circuits often come with limited performance and capabilities due to the competitive goal of size reduction. Therefore, improved integrated antenna structures are needed. Summary of the Invention

[0003] According to one aspect of the present invention, a package structure is provided comprising: a first die; a second die, above the first die and electrically connected to the first die; an insulating material surrounding the second die; and a first antenna extending through the insulating material and electrically connected to the second die, the first antenna being adjacent to a first sidewall of the second die. The first antenna includes: a first conductive plate extending through the insulating material; and a plurality of first conductive posts extending through the insulating material, wherein the first conductive plate is located between the plurality of first conductive posts and the first sidewall of the second die.

[0004] According to another aspect of the present invention, a package is provided comprising: a first package structure located above and electrically connected to a first redistribution structure. The first package structure includes: a first die located above and electrically connected to a second die; an insulating material sealing the first die; a first antenna including a first portion extending through the insulating material to a feed line between the first die and the second die; and a third die located above and electrically connected to the first redistribution structure. The package further includes a first sealant surrounding the first package structure and the third die.

[0005] According to another aspect of the present invention, a method of forming a package is provided, comprising: bonding a first die to a second die, wherein bonding the first die to the second die includes bonding a feed line and a first conductive pad of the second die to a second conductive pad of the first die; depositing an insulating material to surround the first die; etching a first opening in the insulating material to expose the first conductive pad of the second die, and etching a second opening in the insulating material to expose the feed line; and depositing conductive material in the first opening and the second opening to form a plurality of first conductive pillars in the first opening and a first conductive plate in the second opening. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figures 1 to 10 Cross-sectional and top views are shown of intermediate steps during the process of forming package 1000 according to some embodiments.

[0008] Figure 11A and Figure 11B A top view and a cross-sectional view of a package 2000 according to an alternative embodiment are shown.

[0009] Figure 12A and Figure 12B A top view and a cross-sectional view of the package 3000 according to an alternative embodiment are shown.

[0010] Figure 13A and Figure 13B A top view and a cross-sectional view of a package 4000 according to an alternative embodiment are shown.

[0011] Figure 14A and Figure 14B A top view and a cross-sectional view of a package 5000 according to an alternative embodiment are shown.

[0012] Figure 15A and Figure 15B A top view and a cross-sectional view of a package 6000 according to an alternative embodiment are shown.

[0013] Figure 16A and Figure 16B A top view and a cross-sectional view of a package 7000 according to an alternative embodiment are shown.

[0014] Figure 17A and Figure 17B A top view and a cross-sectional view of a package 8000 according to an alternative embodiment are shown.

[0015] Figure 18A and Figure 18B A top view and a cross-sectional view of a package 9000 according to an alternative embodiment are shown.

[0016] Figure 19A and Figure 19B A top view and a cross-sectional view of the package 10000 according to an alternative embodiment are shown.

[0017] Figure 20 A cross-sectional view of the package 11000 according to an alternative embodiment is shown.

[0018] Figure 21A cross-sectional view of the package 12000 according to an alternative embodiment is shown.

[0019] Figure 22 A cross-sectional view of the package 13000 according to an alternative embodiment is shown.

[0020] Figure 23 A schematic diagram showing simulation results for different insulating materials according to some embodiments is presented. Detailed Implementation

[0021] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] Furthermore, for ease of description, this document may use spacing relation terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing relation terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing relation descriptors used herein may be interpreted accordingly.

[0023] The methods provided in various embodiments are applied to, but not limited to, the formation of integrated system-on-a-chip (SoIC) packages, which include vertical through-dielectric via (TDV) walls and TDV gratings to form an antenna resonator cavity. TDV walls and TDV gratings with varying heights and widths can be formed. Additionally, the spacing between two adjacent vertical TDV walls and the spacing between two adjacent vertical TDV gratings can be varied. The advantageous features of one or more embodiments disclosed herein can allow high-frequency lateral RF transmission suitable for 5G and 6G high-frequency (e.g., 29, 38, 77, and 120 GHz) radio frequency (RF) transceivers, as well as portable, wearable, IoT (Internet of Things) and smartphone products. Furthermore, thinly plated TDV walls and TDV gratings can be used as embedded SoIC high-frequency RF transmit and receive antenna structures. Moreover, because the formation process of the TDV walls and TDV gratings is compatible with current processes, manufacturing costs are reduced and efficiency is increased.

[0024] Figures 1 to 10 References are shown according to some example embodiments. Figure 10 The cross-sectional view and top view of the package 1000 with section AA shown are taken during an intermediate stage of manufacturing. Figures 11A to 22 A cross-sectional view and a top view of the package according to an alternative embodiment are shown. Figure 23 A schematic diagram showing simulation results for different insulating materials according to some embodiments is presented.

[0025] refer to Figure 1 The image shows die 100. For clarity, Figure 1 A detailed cross-sectional view of embodiment die 100 is shown and can be referenced herein. Die 100 may be a bare-chip semiconductor die (e.g., an unpackaged semiconductor die). For example, die 100 may be a logic die (e.g., an application processor (AP), a central processing unit, a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a hybrid memory cube (HBC), a static random access memory (SRAM) die, a wide input / output (wide I / O) memory die, a magnetoresistive random access memory (mRAM) die, a resistive random access memory (rRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a baseband transceiver die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), a biomedical die, or combinations thereof.

[0026] Die 100 can be processed according to applicable manufacturing processes to form integrated circuits in die 100. For example, die 100 may include a substrate 102, such as silicon (doped or undoped), or an active layer of a semiconductor-on-insulator (SOI) substrate. Substrate 102 may include other semiconductor materials, such as: germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonate; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Devices such as transistors, diodes, capacitors, resistors, etc., may be formed in and / or on substrate 102 and may be interconnected via interconnect structure 108, which includes, for example, metallization patterns in one or more dielectric layers. The interconnect structure 108 and the devices on substrate 102 are electrically connected to form one or more integrated circuits.

[0027] Die 100 may also include a through-substrate via (TSV) 106, which may be electrically connected to a metallization pattern in interconnect structure 108. TSV 106 may include a conductive material (e.g., copper) and may extend from interconnect structure 108 into substrate 102. An insulating barrier layer (not explicitly shown) may be formed around at least a portion of TSV 106 in substrate 102. The insulating barrier layer may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc., and may be used to physically and electrically isolate TSV 106 from substrate 102. In a subsequent process step, substrate 102 may be thinned to expose TSV 106. After thinning, TSV 106 provides electrical connectivity from the back side of substrate 102 to the front side of substrate 102.

[0028] Die 100 may also include contact pads 110, which enable external connections to interconnect structures 108 and devices. Contact pads 110 may comprise copper, aluminum (e.g., 28K aluminum), or other conductive materials. Figure 1 As shown, contact pads 110 are disposed on the active side or front side, which may be referred to as die 100. The active side / front side of die 100 may refer to one side of the substrate 102 on which active devices are formed. The back side of die 100 may refer to the side of the substrate 102 opposite to the active side / front side.

[0029] A passivation film 112 is disposed on the interconnect structure 108, and contact pads 110 are exposed at the top surface of the passivation film 112. The passivation film 112 may include silicon oxide (e.g., SiO2), silicon oxynitride, silicon nitride, etc. In some embodiments, the contact pads 110 may extend above the top surface of the passivation film 112.

[0030] Die 100 can be formed as a portion of a larger wafer (e.g., interconnected and connected to other dies). Subsequently, the dies can be diced from each other and from other components of the wafer. Dividing processes can include mechanical sawing, laser cutting, plasma cutting, combinations thereof, etc.

[0031] After the dicing process, chip probe (CP) testing can be applied to each die (e.g., using contact pad 110). The CP test checks the electrical function of each die, and dies that pass the CP test are referred to as known good dies (KGD). Dies that fail the CP test are discarded or repaired.

[0032] A bonding layer 120 is formed above the contact pads 110 and the interconnect structure 108 of each KGD. The bonding layer 120 may include any material capable of forming dielectric-to-dielectric bonding. For example, the bonding layer 120 may include silicon oxide (e.g., SiO2), silicon oxynitride, silicon nitride, etc. Contact pads 118 may be disposed in the bonding layer 120 and exposed at the front surface of the die 100. Contact pads 118 may be electrically connected to conductive vias 114 that extend through the dielectric layer 116. The dielectric layer 116 may include tetraethylsilicate (TEOS), etc., and may surround and cover the contact pads 110 to provide a planar surface on which the bonding layer 120 is formed.

[0033] Figure 2 Bottom die 200 is shown. Unless otherwise stated, bottom die 200 may have a structure similar to that described for die 100, and details will not be repeated herein. The materials of the components in bottom die 200 can be found by referring to similar components in die 100, which begin with the number "1" and correspond to the components in bottom die 200, having reference numbers beginning with the number "2".

[0034] Still referencing Figure 2The bottom die 200 may include one or more devices 58 / 60 designed for a specific purpose, such as a logic die, a central processing unit (CPU) die, a system-on-a-chip (SoC), a field-programmable gate array (FPGA), a graphics processing unit (GPU), a neural processing unit (NPU), or combinations thereof, for use in applications related to 5G, artificial intelligence (AI), the Internet of Things (IoT), automotive radar, and high-performance computing (HPC). In embodiments, the bottom die 200 includes integrated circuit devices such as transistors, capacitors, inductors, resistors, metallization layers, conductive connectors, etc., as desired for a particular function. In some embodiments, the bottom die 200 may include more than one type of device of the same type, or may include different devices. For example, the bottom die 200 may include one or more devices 58 providing one or more baseband blocks (e.g., for processing digital data into radio frequency signals) and one or more additional devices 60. Each device 60 may be designed for a specific purpose, such as SoC, HPC, NPU, or AI.

[0035] The metallization pattern in the interconnect structure 208 of the bottom chip 200 may include, for example, one or more ground lines 256 and signal lines 257. In an embodiment, the ground line 256 may be electrically connected to the TDV grating 296 (in... Figure 6 (as shown below), it is connected via conductive connector 320 ( Figure 9 (As shown below) Electrically grounded. The bottom die 200 can be formed as a portion of a larger wafer (e.g., interconnected with each other and connected to other bottom dies 200). After the various components are formed in the bottom die 200, a thinning process can be applied to thin the bottom die 200.

[0036] A bonding layer 220 is formed over the contact pads 210 and the interconnect structure 208 of each KGD. The bonding layer 220 may be similar to bonding layer 120. Conductive components (e.g., contact pads 218 and feed lines 271) may be disposed in the bonding layer 220 and exposed at the front surface of the bottom die 200. The conductive components in the bonding layer 220 may be electrically connected to the ground line 256 and signal line 257 of the interconnect structure 208, for example, through conductive vias 214 extending through the dielectric layer 216. The dielectric layer 216 may include TEOS, etc., and the dielectric layer 216 may be formed around and over the contact pads 210 to provide a planar surface on which the bonding layer 220 is formed.

[0037] exist Figure 3 In the middle, the bottom die 200 is bonded to the die 100, for example, using a hybrid bonding process. Figure 3As shown, the hybrid bonding process directly bonds the bonding layer 220 of the bottom die 200 to the bonding layer 120 of the die 100 via a fusion bonding process. In this embodiment, the bonding between the bonding layer 220 and the bonding layer 120 can be an oxide-to-oxide bonding process. The hybrid bonding process also directly bonds the contact pads 218 of the bottom die 200 and the feed line 271 to the contact pads 118 of the die 100 via direct metal-to-metal bonding. Therefore, the die 100 and the bottom die 200 are electrically connected.

[0038] As an example, the hybrid bonding process begins by aligning the die 100 with the bottom die 200, for instance, by aligning contact pads 218 and feed lines 271 with contact pads 118. When the die 100 is aligned with the bottom die 200, contact pads 218 and feed lines 271 can overlap with their respective contact pads 118. Next, the hybrid bonding process includes a pre-bonding step during which the die 100 is brought into contact with the bottom die 200. The hybrid bonding process continues with annealing, for example, at a temperature between about 100°C and about 450°C and for a duration between about 0.5 hours and about 3 hours, to allow copper in contact pads 118, contact pads 218, and feed lines 271 to diffuse to each other, thus forming a direct metal-to-metal bond.

[0039] exist Figure 4 In this embodiment, an insulating material 294 is formed above die 100 and bottom die 200. The insulating material 294 may comprise a dielectric material (such as silicon oxide) formed by any oxidation process (such as CVD or PECVD technology using tetraethyl orthosilicate (TEOS) and oxygen as precursors). A planarization step, such as CMP, may be performed to make the top surface of the insulating material 294 flush with the top surface of die 100. The planarization step may further expose the TSV 106 of die 100. In an embodiment, after the planarization step, the height H1 of die 100 may be in the range of 20 μm to 775 μm. In an embodiment, the dielectric constant of the insulating material 294 may be in the range of 3.9 to 4.2.

[0040] exist Figure 5In the process, for example, photolithography and one or more etching processes are used to form a first opening 293 through insulating material 294 to expose contact pads 218, and a second opening 295 through insulating material 294 to expose feed lines 271 of the bottom chip 200. The etching process can be dry etching and can include inductively coupled plasma (ICP) etching, reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching process can be anisotropic. In some embodiments, the etching process may include the use of a first gas, including carbide (CF4), methane (CH4), hexafluoroethane (C2F6), octafluoropropane (C3F8), etc., or combinations thereof. The plasma may further use a second gas, including nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), helium (He), etc. An inert gas may optionally be provided in the etching process.

[0041] exist Figure 6 In this process, a seed layer (not shown) is deposited into the first opening 293 and the second opening 295. The seed layer may be deposited as a blanket over the top surface of the insulating material 294, the top surface of the die 100, the sidewalls of the first opening 293 and the second opening 295, and the bottom surface of the first opening 293 and the second opening 295. The seed layer may include a conductive material, such as copper or titanium, and may be deposited using processes such as sputtering, evaporation, CVD, plasma-enhanced chemical vapor deposition (PECVD), electroplating, or electroless plating. A conductive material may then be deposited over the seed layer using electroplating, electroless plating, CVD, PECVD, etc., to fill the first opening 293 and the second opening 295. The conductive material may be a metal such as copper, silver, platinum, gold, nickel, tin, titanium, cobalt, zinc, lead, aluminum, tungsten, tantalum, hafnium, or chromium. A planarization step, such as CMP, can be performed to make the top surface of the conductive material and seed layer flush with the top surface of the insulating material 294 and the top surface of the die 100.

[0042] The remaining conductive material and seed layer in the first opening 293 form a TDV grating 296, and the remaining conductive material and seed layer in the second opening 295 form a TDV wall 297. In an embodiment, each TDV wall 297 may have a first width W1 in the range of 10 μm to 1000 μm. In an embodiment, each TDV grating 296 may have a second width W2 in the range of 10 μm to 1000 μm. Each TDV wall 297 and its adjacent corresponding TDV grating 296 may be referred to as an antenna 40.

[0043] A patch antenna is a microstrip antenna comprising a flat rectangular patch or metal "patch" typically mounted on a larger metal plate called a ground plane. In the embodiments described herein, each of the TDV walls 297 serves as a "patch antenna," and adjacent TDV gratings 296 serve as the respective ground plane of the TDV wall 297. The TDV walls 297 and their respective TDV gratings 296 form antenna 40. Insulating material 294 fills the space between each TDV wall 297 and its corresponding TDV grating 296, forming an antenna cavity structure between the TDV wall 297 and the corresponding TDV grating 296, such as between a first sidewall of the TDV grating 296 and a second sidewall of the corresponding TDV wall 297 facing the first sidewall. When the package 1000 is mounted to its intended application environment, the TDV grating 296 is electrically grounded. For example, in some embodiments, the TDV grating 296 is electrically connected to a conductive connector 320 (which is subsequently...) Figure 9 (As shown in the figure). The TDV grating 296 may include a conductive mesh, or a group of electrically connected vertical rods or columns parallel to each other. In an embodiment, the TDV grating 296 may be formed as a solid metal planar structure or any other suitable structure. In one embodiment, the TDV wall 297 may include a conductive plate. Each TDV wall 297 may be electrically connected to the die 100 via a corresponding feed line 271, and each TDV grating 296 may be electrically connected to the die 100 via a corresponding ground line 256. In an embodiment, each TDV grating and its corresponding TDV wall 297 may be electrically coupled to each other.

[0044] Advantages achievable as a result of forming the System-on-a-Chip (SOIC) package 1000 include vertical TDV walls 297 and corresponding vertical TDV gratings 296 to form an antenna resonant cavity between each vertical TDV wall 297 and its corresponding vertical TDV grating 296. The TDV walls 297 and TDV gratings 296 can be formed with varying heights and widths. Additionally, the spacing between two adjacent vertical TDV walls 297 and the spacing between two adjacent vertical TDV gratings 296 can also be varied. These advantages may include allowing high-frequency lateral RF transmission suitable for 5G and 6G high-frequency (e.g., 29, 38, 77, and 120 GHz) radio frequency (RF) transceivers, as well as portable, wearable, IoT (Internet of Things) and smartphone products, according to one or more embodiments disclosed herein. Furthermore, the thinly plated TDV walls 297 and TDV gratings 296 can serve as embedded SOIC high-frequency RF transmit and receive antenna structures. Furthermore, the insulating material 294 surrounding the die 100 has a dielectric constant of 3.9 to 4.2, which helps reduce coupling effects caused by inductors, capacitors, and balancers in the die 100. Additionally, since the forming processes of the TDV wall 297 and TDV grating 296 are compatible with current processes, manufacturing costs are reduced and efficiency is increased.

[0045] exist Figure 7 In the middle, dielectric layer 310 is deposited in Figure 6 The structure shown is as follows. The dielectric layer 310 may include oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), and other dielectric materials formed by CVD, ALD, PVD, etc. The dielectric layer 310 is then patterned using acceptable photolithography and etching techniques (e.g., wet etching or dry etching) to form openings in the RDL 312. The openings may expose the top surfaces of the TDV grating 296 and TSV 106. For example, the etching process that can be performed may include dry etching, which includes inductively coupled plasma (ICP) etching, reactive ion etching (RIE), and combinations thereof. Next, a seed layer (not shown) is deposited over the openings and the dielectric layer 310. The seed layer may include conductive materials such as copper, titanium, etc., and may be deposited using processes such as sputtering, evaporation, CVD, plasma-enhanced chemical vapor deposition (PECVD), electroplating, electroless plating, etc. The conductive material may then be deposited over the seed layer to fill the openings by electroplating, electroless plating, CVD, PECVD, etc. The conductive material can be a metal such as copper. A planarization step such as CMP can be performed to make the top surface of the conductive material flush with the top surface of the dielectric layer 310.

[0046] exist Figure 8 In this configuration, dielectric layer 316 is deposited above dielectric layer 310 and RDL 312. Dielectric layer 316 may include oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), or other dielectric materials formed by PECVD, CVD, ALD, etc. In an embodiment, dielectric layer 316 may include silicon nitride having a thickness T1, where the thickness T1 can be [missing information]. to Within the range. Next, a polymer layer 318 is formed over the dielectric layer 316. In embodiments, the polymer layer 318 may include polyamide, polyphenylthiazole (PbO), polymer derivatives, etc. The polymer layer 318 may be formed using a spin coating process or the like and may have a thickness T2 in the range of 1 μm to 20 μm.

[0047] exist Figure 9In this process, an opening of the conductive connector 320 is formed through a dielectric layer 316 and a polymer layer 318. The opening can be formed using acceptable photolithography and etching techniques. Next, the conductive connector 320 is formed to fill the opening. The conductive connector 320 may include microbumps, bumps formed using electroless nickel-palladium immersion gold (Enepig) technology, etc. To form the conductive connector 320, a conductive material 322 can be formed in the opening using deposition processes such as sputtering, evaporation, CVD, plasma-enhanced chemical vapor deposition (PECVD), electroplating, electroless plating, etc. The conductive material 322 may include aluminum, copper, silver, gold, nickel, tungsten, alloys thereof, and / or multiple layers thereof. Next, a mask is formed and patterned on the polymer layer 318 and the conductive material 322 to form an opening overlapping the conductive material 322. Subsequently, a conductive material 324 is formed in the opening and over the conductive material 322 using electroplating, electroless plating, etc. The mask is then removed. The conductive material 324 may include pure copper or a copper alloy.

[0048] Still referencing Figure 9 Conductive material 326 may be formed on conductive material 324. Conductive material 326 may include nickel and can be formed by electroless nickel-palladium immersion gold (Enepig) plating, comprising a nickel layer, a palladium layer on the nickel layer, and a gold layer on the palladium layer. In an alternative embodiment, conductive material 326 may be formed by an electroplating process. In some embodiments, some conductive connectors 320 may be electrically connected to the bottom die 200 via die 100, and some conductive connectors 320 may be electrically connected to the bottom die 200 via antenna 40 (e.g., TDV grating 296 or TDV wall 297).

[0049] Figure 10A top view of package 1000 is shown. Package 1000 may include a single die 100 having one or more antennas 40 adjacent to each sidewall of die 100. In one embodiment, the number of antennas 40 adjacent to each sidewall of die 100 is equal to each other. In another embodiment, the number of antennas 40 adjacent to each sidewall of die 100 is different from each other. In yet another embodiment, the number of antennas 40 adjacent to at least one sidewall of die 100 may differ from the number of antennas 40 adjacent to at least one other sidewall of die 100. A TDV wall 297 (e.g., patch antenna) of each antenna 40 is electrically connected to die 100 via an antenna feed 271 disposed between die 100 and 200. An antenna oscillation cavity is formed between each TDV wall 297 of antenna 40 and a TDV grating 296. The TDV grating 296 serves as a ground plane for antenna 40. In an embodiment, the distance D1 between the sidewall of the die 100 and the sidewall of the TDV wall 297 facing the sidewall of the die 100 can be in the range of 10 μm to 9990 μm. In an embodiment, the distance D2 between the sidewall of the TDV grating 296 and the sidewall of the corresponding TDV wall 297 facing the sidewall of the TDV grating 296 can be in the range of 10 μm to 9990 μm. In an embodiment, the distance D3 between the first sidewall of the TDV grating 296 and the first edge of the insulating material 294 of the package 1000 can be in the range of 10 μm to 9990 μm, and the distance D4 between the second sidewall of the TDV grating 296 and the second edge of the insulating material 294 of the package 1000 can be in the range of 10 μm to 9990 μm, wherein the first edge and the second edge are perpendicular to each other, and the first sidewall and the second sidewall of the TDV grating 296 are perpendicular to each other. In embodiments where each TDV grating 296 comprises a group of vertical rods or posts that are electrically connected to each other in parallel, the spacing S1 between two adjacent vertical rods or posts of the TDV grating 296 can be in the range of 10 μm to 9900 μm.

[0050] Each antenna 40 of the package 1000 includes a vertical TDV wall 297 and a corresponding vertical TDV grating 296 to form an antenna resonant cavity between the vertical TDV wall 297 and its corresponding vertical TDV grating 296. In this way, the main surface of the vertical TDV wall 297 (e.g., a conductive plate) is disposed in a plane perpendicular to the main surface of the substrate 202. Additionally, the main surface of the TDV grating 296 (e.g., the main surface of each conductive post) is disposed in a plane perpendicular to the main surface of the substrate 202. The antenna 40 is a directional antenna, which allows it to transmit or receive power in a specific direction. Due to the vertical orientation of the TDV wall 297 and TDV grating 296 of each antenna 40, each antenna 40 is capable of transmitting or receiving 5G+ and 6G high-frequency radiation in a lateral direction parallel to the main surface of the substrate 202.

[0051] Figure 11A A cross-sectional view of the package 2000 according to an alternative embodiment is shown and Figure 11B A top view is shown. Unless otherwise stated, the same reference numerals are used in this embodiment (and the embodiments discussed below) to indicate... Figures 1 to 10 Similar components are shown in the embodiments illustrated. Therefore, the process steps and applicable materials will not be repeated herein.

[0052] exist Figure 11A The image shows a package 2000 comprising a single die 100 having one or more antennas 40 adjacent to each of the first, second, and third sidewalls. In one embodiment, the fourth sidewall of the die 100 has no adjacent antennas 40. In one embodiment, the number of antennas 40 adjacent to each of the first, second, and third sidewalls of the die 100 is equal to each other. In another embodiment, the number of antennas 40 adjacent to each of the first, second, and third sidewalls of the die 100 is different from each other. In yet another embodiment, the number of antennas 40 adjacent to at least one of the first, second, and third sidewalls of the die 100 may differ from the number of antennas 40 adjacent to at least one of the first, second, and third sidewalls. Figure 11B References are shown based on some example embodiments. Figure 11A The cross-sectional view of the package 2000 of section BB is shown.

[0053] Figure 12A A cross-sectional view of the package 3000 according to an alternative embodiment is shown and Figure 12B A top view is shown. Figure 12A The image illustrates a package 3000 comprising a single die 100, the single die 100 having one or more antennas 40 adjacent to each of a first sidewall and a second sidewall of the die 100. In one embodiment, the third and fourth sidewalls of the die 100 have no antennas 40 adjacent to them. In another embodiment, the first and second sidewalls of the die 100 are parallel to each other, and the third and fourth sidewalls of the die 100 are also parallel to each other. In another embodiment, the number of antennas 40 adjacent to the first sidewall of the die 100 is equal to the number of antennas 40 adjacent to the second sidewall of the die 100. In yet another embodiment, the number of antennas 40 adjacent to the first sidewall of the die 100 differs from the number of antennas 40 adjacent to the second sidewall of the die 100. Figure 12B References are shown based on some example embodiments. Figure 12A The cross-sectional view of the package 3000 of section CC shown is shown.

[0054] Figure 13A A cross-sectional view of the package 4000 according to an alternative embodiment is shown and Figure 13B A top view is shown. Figure 13A The image shows a package 4000 comprising a single die 100, each die 100 having one or more antennas 40 adjacent to a first sidewall of each die 100. In one embodiment, the third and fourth sidewalls of the die 100 do not have antennas 40 adjacent to them. In another embodiment, the first and second sidewalls of the die 100 are perpendicular to each other, and the third and fourth sidewalls of the die 100 are also perpendicular to each other. In another embodiment, the number of antennas 40 adjacent to the first sidewall of the die 100 is equal to the number of antennas 40 adjacent to the second sidewall of the die 100. In yet another embodiment, the number of antennas 40 adjacent to the first sidewall of the die 100 and the number of antennas 40 adjacent to the second sidewall of the die 100 are different. Figure 13B References are shown based on some example embodiments. Figure 13A The cross-sectional view of the package 4000 of section DD is shown.

[0055] Figure 14A A cross-sectional view of the package 5000 according to an alternative embodiment is shown and Figure 14B A top view is shown. Figure 14A The image shows a package 5000 comprising a single die 100 having one or more antennas 40 adjacent to a first sidewall of the die 100. In an embodiment, the second, third, and fourth sidewalls of the die 100 do not have antennas 40 adjacent to them. Figure 14B References are shown based on some example embodiments. Figure 14A The cross-sectional view of the EE package 4000 is shown.

[0056] Figure 15A A cross-sectional view of the package 6000 according to an alternative embodiment is shown and Figure 15B A top view is shown. Figure 15AThe image shows a package 6000 including a die region 42, which may include two or more dies 100 adjacent to each other. The package 6000 includes one or more antennas 40 adjacent to each of a first, second, third, and fourth side of the die region 42. A TDV wall 297 (e.g., a patch antenna) of each antenna 40 is electrically connected to one of the dies 100 in the die region 42 via an antenna feed line 271. In one embodiment, the number of antennas 40 adjacent to each of the first, second, third, and fourth sides of the die region 42 is the same. In another embodiment, the number of antennas 40 adjacent to each of the first, second, third, and fourth sides of the die region 42 is different. In yet another embodiment, the number of antennas 40 adjacent to at least one of the first, second, third, and fourth sides may be different from the number of antennas 40 adjacent to at least another of the first, second, third, and fourth sides. In an embodiment, the first number of antennas 40 adjacent to one of the first and third sides of the die region 42 and the second number of antennas 40 adjacent to one of the second and fourth sides of the die region 42 are different. In an embodiment, the distance D5 between the first sidewall of the first TDV wall 297 and the second sidewall of the second TDV wall 297 can be in the range of 10 μm to 99000 μm, wherein the first sidewall faces the second sidewall, wherein the first antenna 40 includes the first TDV wall 297 and the second antenna 40 includes the second TDV wall 297, wherein the first antenna 40 and the second antenna 40 are adjacent to each other. Figure 15B References are shown based on some example embodiments. Figure 15A The cross-sectional view of the package 6000 of section FF shown is shown.

[0057] Figure 16A A cross-sectional view of the package 7000 according to an alternative embodiment is shown and Figure 16B The top view is shown. Figure 16AThe image shows a package 7000 including a die region 42, which may include two or more dies 100 adjacent to each other. The package 7000 includes one or more antennas 40 adjacent to first, second, and third sides of the die region 42. In one embodiment, a fourth side of the die region 42 is not adjacent to an antenna 40. A TDV wall 297 (e.g., a patch antenna) of each antenna 40 is electrically connected to one of the dies 100 in the die region 42 via an antenna feed line 271. In one embodiment, the number of antennas 40 adjacent to each of the first, second, and third sides of the die region 42 is the same. In another embodiment, the number of antennas 40 adjacent to each of the first, second, and third sides of the die region 42 is different. In yet another embodiment, the number of antennas 40 adjacent to at least one of the first, second, and third sides of the die region 42 may be different from the number of antennas 40 adjacent to at least another of the first, second, and third sides of the die region 42. In one embodiment, the first number of antennas 40 adjacent to each of the first and third sides of the die region 42 is different from the second number of antennas 40 adjacent to the second side of the die region 42, wherein the second side is perpendicular to the first and third sides. Figure 16B References are shown based on some example embodiments. Figure 16A The cross-sectional view of the package 7000 of GG shown is shown.

[0058] Figure 17A A cross-sectional view of the package 8000 according to an alternative embodiment is shown and Figure 17B A top view is shown. Figure 17A The image shows a package 8000 including a die region 42, which may include two or more dies 100 adjacent to each other. The package 8000 includes one or more antennas 40 adjacent to each of the first and third sides of the die region 42. In one embodiment, the second and fourth sides of the die region 42 are not adjacent to any antenna 40. A TDV wall 297 (e.g., a patch antenna) of each antenna 40 is electrically connected to one of the dies 100 in the die region 42 via an antenna feed line 271. In one embodiment, the number of antennas 40 adjacent to each of the first and third sides of the die region 42 is the same. In another embodiment, the number of antennas 40 adjacent to each of the first and third sides of the die region 42 is different. In another embodiment, the first and third sides of the die region 42 are perpendicular to the second and fourth sides of the die region 42. Figure 17B The illustrations are based on some example embodiments. Figure 17A The cross-sectional view of the package 8000 with section HH shown is shown.

[0059] Figure 18A A cross-sectional view of an intermediate step in forming package 9000 according to an alternative embodiment is shown, and Figure 18BA top view is shown. Figure 18A The image shows a package 9000 including a die region 42, which may include two or more dies 100 adjacent to each other. The package 9000 includes one or more antennas 40 adjacent to each of the first and second sides of the die region 42. In one embodiment, the third and fourth sides of the die region 42 are not adjacent to any antenna 40. The TDV wall 297 (e.g., a patch antenna) of each antenna 40 is electrically connected to one of the dies 100 in the die region 42 via an antenna feed line 271. In one embodiment, the number of antennas 40 adjacent to the first and second sides of the die region 42 is the same. In another embodiment, the number of antennas 40 adjacent to the first and second sides of the die region 42 is different. In one embodiment, the first side of the die region 42 is perpendicular to the second side of the die region 42. Figure 18B References are shown based on some example embodiments. Figure 18A The cross-sectional view of the package 9000 in section II shown is shown.

[0060] Figure 19A A cross-sectional view of the package 10000 according to an alternative embodiment is shown and Figure 19B A top view is shown. Figure 19A The image shows a package 10000 including a die region 42, which may include two or more dies 100 adjacent to each other. The package 10000 includes one or more antennas 40 adjacent to a first side of the die region 42. In an embodiment, the second, third, and fourth sides of the die region 42 are not adjacent to the antennas 40. The TDV wall 297 of each antenna 40 (e.g., a patch antenna) is electrically connected to one of the dies 100 in the die region 42 via an antenna feed line 271. Figure 19B References are shown based on some example embodiments. Figure 19A The cross-sectional view of the package 10000 of section JJ shown is shown.

[0061] Figure 20 A cross-sectional view of package 11000 according to some embodiments is shown. Package 11000 includes one or more integrated circuit dies 500 and previously... Figures 1 to 19B One or more of any of the packages 10000 shown are used to form an integrated circuit package. The integrated circuit package may also be referred to as an integrated fan-out (InFO) package.

[0062] Package 11000 includes a first package component 400, which includes an integrated circuit die 500. The integrated circuit die 500 can be formed in a wafer, which may include different device regions that are segmented in subsequent steps to form multiple integrated circuit dies. The integrated circuit die 500 can be processed according to applicable manufacturing processes to form an integrated circuit. For example, the integrated circuit die 500 includes a semiconductor substrate 406, such as an active layer of silicon (doped or undoped) or a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 406 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonate; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 406 has an active surface (sometimes referred to as the front side) and a passive surface (sometimes referred to as the back side).

[0063] Devices can be formed on the front surface of the semiconductor substrate 406. These devices can be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. An interlayer dielectric (ILD) 408 is located above the front surface of the semiconductor substrate 406. The ILD 408 surrounds and may cover the device. The ILD 408 may comprise one or more dielectric layers formed of materials such as phosphate silicate glass (PSG), borosilicate glass (BSG), boron-doped phosphate silicate glass (BPSG), undoped silicate glass (USG), etc.

[0064] Conductive plugs extend through ILD 408 to be electrically and physically coupled to devices. For example, when the device is a transistor, the conductive plugs can couple the gate and source / drain regions of the transistor. The conductive plugs can be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, or combinations thereof. Interconnection structure 410 is located above ILD 408 and the conductive plugs. Interconnection structure 410 interconnects devices to form an integrated circuit. Interconnection structure 410 can be formed, for example, by metallization patterns in a dielectric layer on ILD 408. The metallization patterns include metal lines and vias formed in one or more low-k dielectric layers. The metallization patterns of interconnection structure 410 are electrically coupled to devices via the conductive plugs.

[0065] The integrated circuit die 500 also includes pads 412 for external connections, such as aluminum pads. Pads 412 are located on the active side of the integrated circuit die 500, such as in and / or on the interconnect structure 410. One or more passivation films 414 are located on the integrated circuit die 500, such as on portions of the interconnect structure 410 and the pads 412. Openings extend through the passivation films 414 to the pads 412. Die connectors 416, such as conductive pillars (e.g., formed of a metal such as copper), extend through the openings in the passivation films 414 and are physically and electrically coupled to the corresponding pads 412. Die connectors 416 may be formed, for example, by electroplating. Die connectors 416 are electrically coupled to the corresponding integrated circuit of the integrated circuit die 500.

[0066] Each integrated circuit die 500 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SOC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a stacked memory die, a high bandwidth memory (HBM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc.

[0067] One or more integrated circuit dies 500 and one or more packages 1000 can be encapsulated by a sealant 402 (e.g., molding compound, epoxy resin, etc.). The packages 400 and dies 500 can be electrically connected to each other via a front-side redistribution structure 418. In an embodiment, one or more packages 1000 can be encapsulated by a previously... Figures 11A to 19B One or more packages shown are replaced by 2000 to 10000. The front redistribution structure 418 includes any number of dielectric layers and any number of metallization patterns. The metallization patterns may also be referred to as redistribution layers or redistribution lines. The UBM 604 may be formed of the same material as the metallization patterns of the front redistribution structure 418. The conductive connector 602 may be a ball grid array (BGA) connector, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using electroless nickel-palladium immersion gold (Enepig) technology, etc. The conductive connector 602 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. A sealant 402 is formed on and around the various components.

[0068] The packaging substrate 600 may include a printed circuit board (PCB). In an embodiment, the packaging substrate 600 includes a substrate core 610 and bonding pads 606 on the substrate core 610. The substrate core 610 may be made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium, indium phosphide, silicon germanium, gallium arsenide, and combinations thereof may also be used. Additionally, the substrate core 610 may be an SOI substrate. Typically, an SOI substrate comprises layers of semiconductor materials such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the substrate core 610 is based on an insulating core such as a glass fiber reinforced resin core. An example core material is a glass fiber resin, such as FR4. Alternative core materials include bis(imide-triazine) BT resin, or alternatively, other PCB materials or films. Laminated films such as ABF or other laminates may be used for the substrate core 610.

[0069] The substrate core 610 may include active and passive devices (not shown). Various devices, such as transistors, capacitors, resistors, and combinations thereof, can be used to meet the structural and functional requirements of the device stack design. Any suitable method can be used to form the devices.

[0070] The substrate core 610 may also include a metallization layer and vias (not shown), with bonding pads 606 physically and / or electrically coupled to the metallization layer and vias. Metallization layers can be formed on active and passive devices and are designed to connect various devices to form functional circuitry. The metallization layers can be formed from alternating layers of dielectric material (e.g., a low-k dielectric) and conductive material (e.g., copper), with vias interconnecting the layers of conductive material, and can be achieved by any suitable method (such as deposition, damascene, dual damascene, etc.). In some embodiments, the substrate core 610 substantially contains no active or passive devices.

[0071] In some embodiments, the conductive connector 602 is reflowed to attach the first package component 400 to the bonding pad 606. The conductive connector 602 electrically and / or physically couples the package substrate 600 to the first package component 400, the package substrate 600 including a metallization layer in a substrate core 610. In some embodiments, a solder resist 608 is formed on the substrate core 610. The conductive connector 602 may be disposed in an opening in the solder resist 608 for electrical and mechanical coupling to the bonding pad 606. The solder resist 608 may be used to protect areas of the substrate core 610 from external damage.

[0072] The conductive connector 602 may have epoxy solder (not shown) formed thereon, and at least some epoxy resin portions of the remaining epoxy solder reflowed after the first package component 400 is attached to the package substrate 600. These remaining epoxy resin portions may act as underfill to reduce stress and protect the joint created by the reflow of the conductive connector 602. In some embodiments, an underfill 420 may be formed between the first package component 400 and the package substrate 600 and surrounding the conductive connector 602. The underfill 420 may be formed by a capillary process after attachment of the first package component 400, or it may be formed by a suitable deposition method before attachment of the first package component 400.

[0073] In some embodiments, the package substrate 600 may include bonding pads 612 above the substrate core 610. A conductive connector 614 may be connected to the bonding pads 612 to allow the package substrate 600 to be electrically coupled to external circuitry or devices. The conductive connector 614 may be a ball grid array (BGA) connector, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using electroless nickel-palladium immersion gold (Enepig) technology, etc. The conductive connector 614 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, solder resist 608 is formed on the substrate core 610, and the conductive connector 614 may be disposed in openings in the solder resist 608 for electrical and mechanical coupling to the bonding pads 612. The solder resist 608 may be used to protect areas of the substrate core 610 from external damage.

[0074] In some embodiments, passive devices (e.g., surface mount devices (SMDs, not shown) may also be attached to the first package assembly 400 (e.g., to UBM 604) or the package substrate 600 (e.g., to bonding pads 606). For example, a conductive connector 602 may be used to bond passive devices to the same surface of the first package assembly 400 or the package substrate 600. Passive devices may be attached to the package assembly before the first package assembly 400 is mounted onto the package substrate 600, or passive devices may be attached to the package substrate 600 before or after the first package assembly 400 is mounted onto the package substrate 600.

[0075] Figure 21 A cross-sectional view of package 12000 according to some embodiments is shown. Unless otherwise stated, the same reference numerals in this embodiment (and the embodiments discussed below) indicate those formed by the same process. Figures 1 to 20 The components in the embodiments shown are therefore not repeated herein. The process steps and applicable materials are also described previously. Figures 1 to 19BThe diagram shows one or more integrated circuit dies 500 and one or more packages 10000 to form an integrated circuit package including a device stack. The device stack can also be referred to as a package-on-package (POP) structure.

[0076] exist Figure 21 In this embodiment, the third encapsulation component 800 is coupled to the second encapsulation component 700. The second encapsulation component 700 may be similar to the first encapsulation component 400; unless otherwise specified, the same reference numerals are used in this embodiment. Figure 20 Similar components are shown in the illustrated embodiments. The second encapsulation component 700 may include a back-side redistribution structure 422 and a through-hole 424 extending through a sealant 402, the through-hole 424 electrically connecting the back-side redistribution structure 422 to the front-side redistribution structure 418. In the illustrated embodiment, the back-side redistribution structure 422 may include one or more dielectric layers and at least one metallization pattern (sometimes referred to as a redistribution layer or redistribution line).

[0077] The third package component 800 includes, for example, a substrate 812 and one or more stacked dies 802 (e.g., 802a and 802b) coupled to the substrate 812. While other embodiments show a set of stacked dies 802 (802a and 802b), multiple stacked dies 802 (each having one or more stacked dies) may be disposed side-by-side on the same surface of the substrate 812. The substrate 812 may be made of a semiconductor material such as silicon, germanium, diamond, etc. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium, indium phosphide, silicon germanium, gallium arsenide, gallium arsenide phosphide, gallium indium phosphide, and gallium indium phosphide may also be used. Alternatively, the substrate 812 may be a silicon-on-insulator (SOI) substrate. Typically, SOI substrates comprise layers of semiconductor materials such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium-on-insulator (SGOI), or combinations thereof. In an alternative embodiment, the substrate 812 is based on an insulating core such as a glass fiber reinforced resin core. An example core material is a glass fiber resin, such as FR4. Alternatives to the core material include bismuth imide-triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. Substrate 812 may be used for materials such as Ajinomoto multilayer film (ABF) or other laminates.

[0078] The substrate 812 may include active and passive devices (not shown). Various devices, such as transistors, capacitors, resistors, and combinations thereof, can be used to meet the structural and functional requirements of the design of the third package assembly 800. Any suitable method can be used to form the devices.

[0079] The substrate 812 may also include a metallization layer (not shown) and conductive vias 814. The metallization layer can be formed on active and passive devices and is designed to connect various devices to form a functional circuit. The metallization layer can be formed of alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper), having vias interconnecting the conductive material layers, and can be formed by any suitable method (e.g., deposition, damascene, dual damascene, etc.). In some embodiments, the substrate 812 substantially does not contain active or passive devices.

[0080] Substrate 812 may have bonding pads 810 on a first side of substrate 812 for coupling to stacked die 802, and bonding pads 816 on a second side of substrate 812 (opposite to the first side of substrate 812) for coupling to conductive connector 818. In some embodiments, bonding pads 810 and 816 are formed by forming grooves 810 and 816 on the first and second sides of substrate 812. Grooves can be formed to allow bonding pads 810 and 816 to be embedded in the dielectric layer. In other embodiments, grooves are omitted, and bonding pads 810 and 816 may be formed on the dielectric layer. In some embodiments, bonding pads 810 and 816 include a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, or combinations thereof. Conductive material of bonding pads 810 and 816 may be deposited over the thin seed layer. The conductive material may be formed by electroplating, electroless plating, CVD, atomic layer deposition (ALD), PVD, or combinations thereof. In one embodiment, the conductive material of the bonding pads 810 and 816 is copper, tungsten, aluminum, silver, gold, or a combination thereof.

[0081] In some embodiments, bonding pads 810 and 816 are UBMs comprising three layers of conductive material, such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers may be used to form bonding pads 810 and 816, such as a chromium / chromium-copper alloy / copper / gold arrangement, a titanium / tungsten / copper arrangement, or a copper / nickel / gold arrangement. Any suitable material or layer of material that may be used for bonding pads 810 and 816 is fully intended to be included within the scope of the present application. In some embodiments, a conductive via 814 extends through the substrate 812 and couples at least one of the pads 810 to at least one of the bonding pads 816.

[0082] In the illustrated embodiment, the stacked die 802 is coupled to the substrate 812 via a wire bond 806, but other connections, such as conductive bumps, may be used. In this embodiment, the stacked die 802 is a stacked memory die. For example, the stacked die 802 may be a memory die such as a low-power (LP) dual-data-rate (DDR) memory module, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, etc.

[0083] The stacked die 802 and wire bond 806 can be sealed by a molding material 808. The molding material 808 can be, for example, molded onto the stacked die 802 and wire bond 806 using compression molding. In some embodiments, the molding material 808 is a molding compound, polymer, epoxy resin, silica filler, etc., or a combination thereof. A curing process can be performed to cure the molding material 808; the curing process can be thermosetting, UV curing, etc., or a combination thereof. Subsequently, the coupled third package component 800 and second package component 700 use a conductive connector 602 to connect with the above-described... Figure 20 It is mounted to the package substrate 600 in a similar manner (as previously described). Figure 20 middle).

[0084] Figure 22 A cross-sectional view of a package 13000 according to some embodiments is shown. Unless otherwise stated, the same reference numerals in this embodiment (and the embodiments discussed below) indicate those formed by the same process. Figures 1 to 22 The components in the embodiments shown are therefore not repeated herein. The process steps and applicable materials are packaged in a manner that includes one or more integrated circuit dies 500 and previously used in… Figures 1 to 19B Any one or more of package 1000 to package 10000 shown are used to form an integrated circuit package. The integrated circuit package may also be referred to as a chip-on-wafer (CoWoS) package.

[0085] exist Figure 22 The diagram illustrates a fourth package assembly 900, which may include one or more devices designed for a specific purpose, such as memory dies (e.g., DRAM dies, stacked memory dies, high-bandwidth memory (HBM) dies, etc.), logic dies, central processing unit (CPU) dies, I / O dies, system-on-a-chip (SoC), assembly-on-wafer (CoW), integrated fan-out (InFO), packages, radio frequency (RF) dies, and combinations thereof. In embodiments, the fourth package assembly 900 includes integrated circuit devices, such as transistors, capacitors, inductors, resistors, metallization layers, conductive connectors, etc., for specific functions as required. In some embodiments, the fourth package assembly 900 may include more than one device of the same type, or may include different devices. Figure 22 A fourth packaging assembly 900 is shown, which includes a package 1000. Figures 1 to 10 (as previously described in) and two integrated circuit die 500 (such as Figure 20At least one of the previously described components (as described earlier) is sealed and connected to the redistribution structure and contact pads. In other embodiments, the fourth package assembly 900 may include more than one of the package 1000 and the integrated circuit 500. In embodiments, one or more packages 1000 may be derived from a previously described integrated circuit. Figures 11A to 19B One or more packages shown are replaced 2000 to 10000.

[0086] Package 1000 and integrated circuit die 500 are attached to interposer 916. Interposer 916 may include substrate 914 and interconnect structure 912. Fourth package assembly 900 may include underfill material 904 disposed between package 1000 and integrated circuit die 500 and interconnect structure 912. In some embodiments, fourth package assembly 900 may include sealant 906 surrounding package 1000 and integrated circuit die 500.

[0087] Still referencing Figure 22 The image shows a packaging substrate 1100. The packaging substrate 1100 includes a substrate core 610 and bonding pads 606 above the substrate core 610. The substrate core 610 can be made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium, indium phosphide, silicon germanium, gallium arsenide, and combinations thereof can also be used. Additionally, the substrate core 610 can be an SOI substrate. Typically, an SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the substrate core 610 is based on an insulating core such as a glass fiber reinforced resin core. An example core material is a glass fiber resin, such as FR4. Alternatives to the core material include bis(imide-triazine) resin, or alternatively, other PCB materials or films. Laminated films such as ABF or other laminates can be used for the substrate core 610.

[0088] The substrate core 610 may include active and passive devices (not shown). Various devices, such as transistors, capacitors, resistors, and combinations thereof, can be used to meet the structural and functional requirements of the device stack design. Any suitable method can be used to form the devices.

[0089] The substrate core 610 may also include a metallization layer and vias (not shown), with bonding pads 606 physically and / or electrically coupled to the metallization layer and vias. The metallization layer can be formed on active and passive devices and is designed to connect various devices to form a functional circuit. The metallization layer can be formed of alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper), having vias interconnecting the conductive material layers, and can be formed by any suitable method (e.g., deposition, damascene, dual damascene, etc.). In some embodiments, the substrate core 610 substantially does not contain active or passive devices.

[0090] In some embodiments, the package substrate 1100 may include a conductive connector 902. The conductive connector 902 may be coupled to a bonding pad 606. The conductive connector 902 may be a ball grid array (BGA) connector, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using electroless nickel-palladium immersion gold (Enepig) technology, etc. The conductive connector 902 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, a solder resist 608 is formed on the substrate core 610, and the conductive connector 902 may be disposed in openings in the solder resist 608 for electrical and mechanical coupling to the bonding pad 606. The solder resist 608 may be used to protect areas of the substrate core 610 from external damage.

[0091] A fourth package assembly 900 is placed on the conductive connector 902 of the package substrate 1100, forming an electrical connection between the fourth package assembly 900 and the package substrate 1100. The fourth package assembly 900 can be positioned such that the conductive bump 908 is aligned with the conductive connector 902 of the package substrate 1100. Once physical contact is made, the conductive connector 902 of the package substrate 1100 can be bonded to the fourth package assembly 900 using a reflow process. An underfill 918 can then be formed around the conductive connector 902 between the fourth package assembly 900 and the package substrate 1100.

[0092] In some embodiments, the package substrate 1100 may include bonding pads 612 above the substrate core 610. A conductive connector 614 may be connected to the bonding pads 612 to allow electrical coupling of the package substrate 1100 to external circuitry or devices. The conductive connector 614 may be a ball grid array (BGA) connector, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using electroless nickel-palladium immersion gold (Enepig) technology, etc. The conductive connector 614 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, solder resist 608 is formed on the substrate core 610, and the conductive connector 614 may be disposed in openings in the solder resist 608 for electrical and mechanical coupling to the bonding pads 612. The solder resist 608 may be used to protect areas of the substrate core 610 from external damage.

[0093] exist Figure 23 The diagram illustrates simulation results for different insulating materials, based on some embodiments. The simulated antenna configuration is similar to... Figure 9 The structure shown is configured with a resonant frequency set to approximately 77 GHz. Two different insulating film materials were simulated, and their S-parameter S11 (a general representation of signal return loss) performance was compared. Reference Figure 23 Lines 370 and 372 represent simulation results for materials with dielectric constants of approximately 3.0 and 83, respectively. Figure 23 As shown, the first dielectric material with a dielectric constant of 3.0 exhibits return loss in the range of -10 dB to 0 dB, with a local minimum around 75-88 GHz. Conversely, the second dielectric material with a dielectric constant of 83 exhibits signal loss in the range of -62 dB to -23 dB. Specifically, the second dielectric material provides a sharper frequency-selective gain at a valley around 76 GHz.

[0094] The embodiments disclosed herein have several advantageous features. The embodiments include forming an integrated system-on-a-chip (SOIC) package comprising vertically penetrating dielectric via (TDV) walls and TDV gratings to form an antenna resonant cavity. TDV walls and TDV gratings with varying heights and widths can be formed. Additionally, the spacing between two adjacent vertical TDV walls and the spacing between two adjacent vertical TDV gratings can be varied. The advantageous features of one or more embodiments disclosed herein can allow high-frequency lateral RF transmission suitable for 5G and 6G high-frequency (e.g., 29, 38, 77, and 120 GHz) radio frequency (RF) transceivers, as well as portable, wearable, IoT (Internet of Things) and smartphone products. Furthermore, the thinly plated TDV walls and TDV gratings can serve as embedded SOIC high-frequency RF transmit and receive antenna structures. Moreover, manufacturing costs are reduced and efficiency is increased because the fabrication process of the TDV walls and TDV gratings is compatible with current processes.

[0095] According to one embodiment, the package structure includes: a first die; a second die, above the first die and electrically connected to the first die; an insulating material surrounding the second die; and a first antenna extending through the insulating material and electrically connected to the second die, the first antenna being adjacent to a first sidewall of the second die. The first antenna includes: a first conductive plate extending through the insulating material; and a plurality of first conductive posts extending through the insulating material, wherein the first conductive plate is located between the plurality of first conductive posts and the first sidewall of the second die. In one embodiment, the dielectric constant of the insulating material is in the range of 3.9 to 4.2. In one embodiment, the insulating material separates adjacent first conductive posts among the plurality of first conductive posts. In one embodiment, the main surface of the first conductive plate and the main surface of each of the plurality of first conductive posts are disposed in a plane perpendicular to the main surface of the first die. In one embodiment, the package structure further includes: a redistribution structure located above the insulating material, the second die, and the first antenna; a first conductive connector located above the redistribution structure, the first conductive connector being electrically connected to the first antenna through the redistribution structure; and a second conductive connector located above the redistribution structure, the second conductive connector being electrically connected to the first die through the second die and the redistribution structure. In one embodiment, the package structure further includes: a second antenna extending through the insulating material and electrically connected to the second die, the second antenna being adjacent to a second sidewall of the second die. The second antenna includes: a second conductive plate extending through the insulating material; and a plurality of second conductive posts extending through the insulating material, wherein the second conductive plate is located between the plurality of second conductive posts and the second sidewall of the second die. In one embodiment, the package structure further includes: a third antenna extending through the insulating material and electrically connected to the second die, the third antenna being adjacent to a third sidewall of the second die; and a fourth antenna extending through the insulating material and electrically connected to the second die, the fourth antenna being adjacent to a fourth sidewall of the second die. In one embodiment, the first sidewall and the second sidewall are parallel to each other. In one embodiment, the first sidewall and the second sidewall are perpendicular to each other.

[0096] According to one embodiment, the package includes: a first package structure located above and electrically connected to a first redistribution structure, wherein the first package structure includes a first die located above and electrically connected to a second die; an insulating material sealing the first die; a first antenna including a first portion extending through the insulating material to a feed line between the first die and the second die; and a third die located above and electrically connected to the first redistribution structure; and a first sealant surrounding the first package structure and the third die. In one embodiment, the first portion of the first antenna includes a first conductive plate. In one embodiment, a second portion of the first antenna extends through the insulating material and includes a conductive mesh. In one embodiment, a third portion of the first antenna extends through the insulating material and includes a plurality of conductive posts. In one embodiment, the feed line electrically connects the first conductive plate to the first die and the second die. In one embodiment, the package includes: a second redistribution structure located above the first package structure; and a second package structure located above the second redistribution structure and coupled to the second redistribution structure via a first conductive connector, wherein the first package structure and the second package structure are electrically connected via the first conductive connector and the second redistribution structure. In one embodiment, the second package structure includes: a first substrate; a plurality of stacked dies located above the first substrate; and a second sealant surrounding the plurality of stacked dies.

[0097] According to one embodiment, a method includes: bonding a first die to a second die, wherein bonding the first die to the second die includes bonding a first conductive pad of a feed line and a first conductive pad of the second die to a second conductive pad of the first die; depositing an insulating material to surround the first die; etching a first opening in the insulating material to expose the first conductive pad of the second die, and etching a second opening in the insulating material to expose the feed line; and depositing conductive material in the first and second openings to form a plurality of first conductive posts in the first opening and a first conductive plate in the second opening. In one embodiment, the method further includes: forming a redistribution structure over the insulating material, the first die, the plurality of first conductive posts, and the first conductive plate; forming a first conductive connector over the redistribution structure, the first conductive connector being electrically connected to the plurality of first conductive posts through the redistribution structure; and forming a second conductive connector over the redistribution structure, the second conductive connector being electrically connected to the second die through the first die and the feed line. In one embodiment, the dielectric constant of the insulating material is in the range of 3.9 to 4.2. In one embodiment, the second opening is located between the first die and the first opening.

[0098] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A package structure, comprising: First die; The second die is located above the first die and is electrically connected to the first die; Insulating material is located around the second core. A first antenna extends through the insulating material and is electrically connected to the second die, the first antenna being adjacent to a first sidewall of the second die, wherein the first antenna comprises: A first conductive plate extends through the insulating material; and A plurality of first conductive posts extend through the insulating material, wherein a first conductive plate is located between the plurality of first conductive posts and the first sidewall of the second die, and wherein the first conductive plate and the plurality of first conductive posts overlap with the first die, and an antenna oscillation cavity is formed between the first conductive plate and the plurality of first conductive posts.

2. The packaging structure according to claim 1, wherein, The dielectric constant of the insulating material is in the range of 3.9 to 4.

2.

3. The packaging structure according to claim 1, wherein, The insulating material separates adjacent first conductive posts among the plurality of first conductive posts.

4. The packaging structure according to claim 1, wherein, The main surface of the first conductive plate and the main surface of each of the plurality of first conductive pillars are disposed in a plane perpendicular to the main surface of the first die.

5. The packaging structure according to claim 1, further comprising: A redistribution structure is located above the insulating material, the second die, and the first antenna; A first conductive connector is located above the redistribution structure, and the first conductive connector is electrically connected to the first antenna through the redistribution structure; and A second conductive connector is located above the redistribution structure, and the second conductive connector is electrically connected to the first die through the second die and the redistribution structure.

6. The packaging structure according to claim 1, further comprising: A second antenna extends through the insulating material and is electrically connected to the second die, the second antenna being adjacent to a second sidewall of the second die, wherein the second antenna comprises: A second conductive plate extends through the insulating material; and A plurality of second conductive posts extend through the insulating material, wherein the second conductive plate is located between the plurality of second conductive posts and the second sidewall of the second die.

7. The packaging structure according to claim 6, further comprising: A third antenna extends through the insulating material and is electrically connected to the second die, the third antenna being adjacent to the third sidewall of the second die; and A fourth antenna extends through the insulating material and is electrically connected to the second die, the fourth antenna being adjacent to a fourth sidewall of the second die.

8. The packaging structure according to claim 6, wherein, The first sidewall and the second sidewall are parallel to each other.

9. The packaging structure according to claim 6, wherein, The first sidewall and the second sidewall are perpendicular to each other.

10. A package comprising: A first package structure is located above and electrically connected to the first redistribution structure, wherein the first package structure includes: The first die is located above the second die and is electrically connected to the second die; Insulating material is used to seal the first core. A first antenna includes a first portion extending through the insulating material to a feed line between a first die and a second die, the first portion of the first antenna being in physical contact with the feed line exposed at the front surface of the second die; and A third die, located above and electrically connected to the first redistribution structure; and A first sealant surrounds the first encapsulation structure and the third die.

11. The package according to claim 10, wherein, The first portion of the first antenna includes a first conductive plate.

12. The package according to claim 11, wherein, A second portion of the first antenna extends through the insulating material, and the second portion of the first antenna includes a conductive mesh.

13. The package according to claim 11, wherein, A third portion of the first antenna extends through the insulating material, and the third portion of the first antenna includes a plurality of conductive posts.

14. The package according to claim 13, wherein, The feeder electrically connects the first conductive plate to the first die and the second die.

15. The package according to claim 13, further comprising: The second redistribution structure is located above the first encapsulation structure; A second package structure is located above the second redistribution structure and is connected to the second redistribution structure via a first conductive connector, wherein the first package structure and the second package structure are electrically connected to the second redistribution structure via the first conductive connector.

16. The package according to claim 15, wherein, The second package structure includes: First substrate; Multiple stacked dies are located above the first substrate; and A second sealant is applied around multiple stacked dies.

17. A method of forming a package, comprising: Joining the first die to the second die, wherein joining the first die to the second die includes joining the feed line and the first conductive pad of the second die to the second conductive pad of the first die; Deposit insulating material to surround the first core; A first opening is etched in the insulating material to expose the first conductive pad of the second die, and a second opening is etched in the insulating material to expose the feed line; and Conductive material is deposited in the first opening and the second opening to form a plurality of first conductive pillars in the first opening and a first conductive plate in the second opening, wherein an antenna oscillation cavity is formed between the first conductive plate and the plurality of first conductive pillars.

18. The method of claim 17, further comprising: A redistribution structure is formed above the insulating material, the first die, the plurality of first conductive pillars, and the first conductive plate; A first conductive connector is formed above the redistribution structure, and the first conductive connector is electrically connected to the plurality of first conductive posts through the redistribution structure; as well as A second conductive connector is formed above the redistribution structure, and the second conductive connector is electrically connected to the second die through the first die and the feed line.

19. The method of claim 17, wherein, The dielectric constant of the insulating material is in the range of 3.9 to 4.

2.

20. The method of claim 17, wherein, The second opening is located between the side wall of the first core and the first opening.

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