Bidirectional Silicon Controlled Rectifier

Abstract

The present invention provides a bidirectional thyristor rectifier comprising: a substrate of a first conductivity type, a well region of a second conductivity type, a shallow trench isolation structure, six heavily doped regions of the first conductivity type, six heavily doped regions of the second conductivity type, and four electrostatic discharge (ESD) injection layers of the first conductivity type. In the well region, there are four active regions arranged side by side, and the middle active region has forward and reverse thyristors and the ESD injection layer, and the active regions on both sides have forward and reverse diodes, and a heavily doped region of the first conductivity type in contact with the ESD injection layer of the first conductivity type is arranged between the thyristor rectifier and the diode, so that the heavily doped region of the second conductivity type of the diode is electrically connected to the aforementioned heavily doped region of the first conductivity type, so that the entire bidirectional thyristor rectifier can add two low-voltage auxiliary trigger paths composed of forward and reverse diodes, so as to greatly reduce the trigger voltage of the bidirectional thyristor rectifier in the forward and reverse working modes.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor electrostatic protection, and in particular to a compact silicon controlled rectifier (Low-voltage and Compact Dual-directional SCR, LVCDDSCR for short) for bidirectional low-voltage protection. Background Art

[0002] With the continuous development of integrated circuit technology, chip damage caused by electrostatic discharge (ESD) events has become more and more serious, seriously restricting the reliability of semiconductor products. Therefore, it is very necessary to provide effective on-chip ESD protection design for chips. In the specific chip ESD protection design, it is usually encountered that the working voltage of some I / O ports has both positive and negative voltages at the same time, and it is necessary to provide bidirectional ESD protection for them. Among the many ESD protection devices available, the bidirectional thyristor rectifier (DDSCR) has high protection capability, low on-resistance and parasitic capacitance, and is therefore a very suitable bidirectional ESD protection device.

[0003] However, in the traditional DDSCR structure, an isolation structure is usually required, that is, a deep N-well is used to isolate the two P-wells of the device from the P-type substrate to prevent the device from being short-circuited by the substrate diode when working in reverse. In advanced processes, the above-mentioned deep N-well will further evolve into a buried layer area. At this time, in order to achieve effective isolation, a lateral N-well isolation ring structure is also required for the DDSCR. The existence of the isolation structure in the DDSCR device will greatly increase the layout area of ​​the device, thereby equivalently reducing the area efficiency of the device.

[0004] In order to eliminate the dependence of traditional DDSCR devices on complex isolation structures, some studies have proposed a compact self-isolated DDSCR device, such as Figure 1A As shown, a shallow trench isolation structure (STI) is used in a P-type substrate 100 to divide two active regions in an N-type well region 102. One active region includes an N+ doping region 104a and a P+ doping region 106a, and the function of the P well in a traditional DDSCR is replaced by a P-ESD injection layer 108a in an advanced CMOS process; the other active region also includes an N+ doping region 104b, a P+ doping region 106ba and a P-ESD injection layer 108b. Therefore, a bidirectional ESD protection function can be realized in an N-type well region 102, thereby greatly reducing the device area and improving the area efficiency.

[0005] However, by Figure 1BFrom the equivalent circuit diagram, it can be seen that the compact self-isolated DDSCR device is not optimized for the trigger path. At this time, when the ESD pulse comes, the device can only pass the internal parasitic PNP transistor (i.e. Figure 1B The common emitter collector junction avalanche breakdown voltage (BV CEO ) to trigger conduction, which will generate a large trigger voltage. With the continuous miniaturization of integrated circuit process nodes, the ESD design window (i.e., the working area of ​​the ESD protection circuit) is constantly shrinking, which makes it very likely that the above-mentioned compact self-isolated DDSCR device will not be able to complete the ESD charge discharge work before the internal circuit of the chip fails due to the excessively high trigger voltage, which poses a great challenge to the reliability of the chip. Summary of the invention

[0006] The present invention is directed to a bidirectional silicon controlled rectifier, which is used for bidirectional low voltage protection and can significantly reduce the trigger voltage of the device in forward and reverse working modes.

[0007] According to an embodiment of the present invention, a bidirectional silicon controlled rectifier comprises: a substrate of a first conductivity type, a well region of a second conductivity type, a shallow trench isolation structure, six heavily doped regions of the first conductivity type, six heavily doped regions of the second conductivity type, and four ESD implantation layers (ESD implantation) of the first conductivity type. The shallow trench isolation structure is formed in the substrate, and separates a first active region, a second active region, a third active region, and a fourth active region arranged side by side in the well region.

[0008] The second active region includes a first heavily doped region of the first conductivity type, a first heavily doped region of the second conductivity type, a second heavily doped region of the first conductivity type, and a first ESD injection layer of the first conductivity type, wherein the first heavily doped region of the second conductivity type is located between the first heavily doped region of the first conductivity type and the second heavily doped region of the first conductivity type and is separated from both by a distance, the first ESD injection layer of the first conductivity type is arranged at the bottom of the first heavily doped region of the second conductivity type, the first heavily doped region of the first conductivity type, and the second heavily doped region of the first conductivity type, and the first heavily doped region of the first conductivity type is electrically connected to the first heavily doped region of the second conductivity type.

[0009] In the third active area adjacent to the second active area, there are a third heavily doped area of ​​the first conductivity type, a second heavily doped area of ​​the second conductivity type, a fourth heavily doped area of ​​the first conductivity type and a second ESD injection layer of the first conductivity type, wherein the third heavily doped area of ​​the first conductivity type is adjacent to the first heavily doped area of ​​the first conductivity type, the second heavily doped area of ​​the second conductivity type is located between the third heavily doped area of ​​the first conductivity type and the fourth heavily doped area of ​​the first conductivity type and is separated from the two by a distance, the second ESD injection layer of the first conductivity type is arranged at the bottom of the third heavily doped area of ​​the first conductivity type, the second heavily doped area of ​​the second conductivity type and the fourth heavily doped area of ​​the first conductivity type, and the third heavily doped area of ​​the first conductivity type is electrically connected to the second heavily doped area of ​​the second conductivity type.

[0010] In the first active area adjacent to the second active area, there are a fifth heavily doped region of the first conductivity type, a third heavily doped region of the second conductivity type, a fourth heavily doped region of the second conductivity type and a third ESD injection layer of the first conductivity type, wherein the fifth heavily doped region of the first conductivity type is in contact with the third heavily doped region of the second conductivity type and is separated from the fourth heavily doped region of the second conductivity type by a distance, and the third ESD injection layer of the first conductivity type is arranged at the bottom of the fifth heavily doped region of the first conductivity type and the fourth heavily doped region of the second conductivity type, and the fifth heavily doped region of the first conductivity type is electrically connected to the third heavily doped region of the second conductivity type, and the fourth heavily doped region of the second conductivity type is electrically connected to the second heavily doped region of the first conductivity type.

[0011] In the fourth active area adjacent to the third active area, there are a sixth heavily doped area of ​​the first conductivity type, a fifth heavily doped area of ​​the second conductivity type, a sixth heavily doped area of ​​the second conductivity type and a fourth ESD injection layer of the first conductivity type, wherein the sixth heavily doped area of ​​the first conductivity type is in contact with the fifth heavily doped area of ​​the second conductivity type and is separated from the sixth heavily doped area of ​​the second conductivity type by a distance, and the fourth ESD injection layer of the first conductivity type is arranged at the bottom of the sixth heavily doped area of ​​the first conductivity type and the sixth heavily doped area of ​​the second conductivity type, and the sixth heavily doped area of ​​the first conductivity type is electrically connected to the fifth heavily doped area of ​​the second conductivity type, and the sixth heavily doped area of ​​the second conductivity type is electrically connected to the fourth heavily doped area of ​​the first conductivity type.

[0012] In the bidirectional silicon controlled rectifier according to the embodiment of the present invention, at least one first external diode may be further included, connected in the circuit between the fourth heavily doped region of the second conductivity type and the second heavily doped region of the first conductivity type.

[0013] In the bidirectional silicon controlled rectifier according to the embodiment of the present invention, at least one second external diode may be further included, connected in the circuit between the sixth heavily doped region of the second conductivity type and the fourth heavily doped region of the first conductivity type.

[0014] In the bidirectional silicon controlled rectifier according to the embodiment of the present invention, the first conductivity type is P type, and the second conductivity type is N type.

[0015] In the bidirectional silicon controlled rectifier according to the embodiment of the present invention, the first conductivity type is N-type, and the second conductivity type is P-type.

[0016] In the bidirectional thyristor rectifier according to an embodiment of the present invention, a parasitic PNP transistor is formed by the first heavily doped region of the first conductivity type, the first ESD injection layer of the first conductivity type, the well region, the fifth heavily doped region of the second conductivity type and the sixth heavily doped region of the first conductivity type, and a forward diode is formed by the fourth ESD injection layer of the first conductivity type and the sixth heavily doped region of the second conductivity type. The parasitic PNP transistor and the forward diode form a first low-voltage auxiliary trigger path through the fourth heavily doped region of the first conductivity type, the second ESD injection layer of the first conductivity type and the third heavily doped region of the first conductivity type.

[0017] In the bidirectional thyristor rectifier according to an embodiment of the present invention, a parasitic PNP transistor is formed by the third heavily doped region of the first conductivity type, the second ESD injection layer of the first conductivity type, the well region, the third heavily doped region of the second conductivity type and the fifth heavily doped region of the first conductivity type, and a reverse diode is formed by the third ESD injection layer of the first conductivity type and the fourth heavily doped region of the second conductivity type. The parasitic PNP transistor and the reverse diode form a second low-voltage auxiliary trigger path through the second heavily doped region of the first conductivity type, the first ESD injection layer of the first conductivity type and the first heavily doped region of the first conductivity type.

[0018] In the bidirectional thyristor according to the embodiment of the present invention, a silicide block (SAB) layer may also be included, which is formed on the surface without heavily doped areas in the first active area, the second active area, the third active area and the fourth active area.

[0019] Based on the above, the bidirectional thyristor rectifier of the present invention can significantly reduce the trigger voltage of the device in the forward and reverse working modes by providing two low-voltage auxiliary trigger paths composed of diode strings. Moreover, for different ESD design windows, the bidirectional thyristor rectifier of the present invention can also flexibly adapt to various protection requirements by adjusting the number of diodes in the auxiliary trigger path. In addition, the bidirectional thyristor rectifier of the present invention can still realize the bidirectional ESD protection function in one N-well, so it still has the advantage of self-isolation and is expected to achieve very high area efficiency.

[0020] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1A The structure cross-section diagram of an existing compact self-isolated DDSCR device.

[0022] Figure 1B for Figure 1A Equivalent circuit diagram of a compact self-isolated DDSCR device.

[0023] Figure 2A The figure is a structural cross-sectional view of a bidirectional silicon-controlled rectifier in one embodiment of the present invention.

[0024] Figure 2B for Figure 2A The equivalent circuit diagram of a bidirectional thyristor rectifier.

[0025] Figure 3A It is a structural cross-sectional view of a bidirectional silicon-controlled rectifier in the embodiment of the present invention.

[0026] Figure 3B for Figure 3A The equivalent circuit diagram of a bidirectional thyristor rectifier.

[0027] Figure 4A It is a structural cross-sectional view of another bidirectional silicon-controlled rectifier in the embodiment of the present invention.

[0028] Figure 4B for Figure 4A The equivalent circuit diagram of a bidirectional thyristor rectifier.

[0029] Figure 5A It is a structural cross-sectional view of yet another bidirectional silicon-controlled rectifier in the embodiment of the present invention.

[0030] Figure 5B for Figure 5A The equivalent circuit diagram of a bidirectional thyristor rectifier.

[0031] Description of Reference Numerals

[0032] 100: P-type substrate

[0033] 102: N-type well region

[0034] 104a, 104b: N+ doped regions

[0035] 106a, 106b: P+ doped regions

[0036] 108a, 108b: P-ESD injection layer

[0037] 200: substrate of the first conductivity type

[0038] 202: Well region of the second conductivity type

[0039] 204. STI: Shallow Trench Isolation

[0040] 206a, 206b, 206c, 206d: active area

[0041] 208a, 208b, 212a, 212b, 216a, 216b: heavily doped regions of the first conductivity type

[0042] 210a, 210b, 218a, 218b, 220a, 220b: heavily doped regions of the second conductivity type

[0043] 214a, 214b, 214c, 214d: ESD injection layer of the first conductivity type

[0044] 222. SAB: Silicide Barrier

[0045] D1: First external diode

[0046] D2: Second external diode

[0047] P1: First low voltage auxiliary trigger path

[0048] P2: Second low voltage auxiliary trigger path

[0049] PAD1, PAD2: Interface end DETAILED DESCRIPTION

[0050] Hereinafter, embodiments of the present invention will be described in detail. However, these embodiments are illustrative, and the present invention is not limited thereto. In addition, the drawings are for illustrative purposes only and are not drawn to their original size. Whenever possible, the same reference numerals are used to represent the same or similar parts in the drawings and description.

[0051] Figure 2AThe figure is a cross-sectional view of the structure of a bidirectional silicon-controlled rectifier (DDSCR) according to an embodiment of the present invention.

[0052] Please refer to Figure 2A The DDSCR of this embodiment is a compact silicon controlled rectifier (Low-voltage and Compact DDSCR, LVCDDSCR for short) for bidirectional low voltage protection, comprising a substrate 200 of a first conductivity type, a well region 202 of a second conductivity type and a shallow trench isolation structure 204 formed in the substrate 200, a first heavily doped region 208a of the first conductivity type, a first heavily doped region 210a of the second conductivity type, a second heavily doped region 212a of the first conductivity type, a first ESD injection layer (ESD The shallow trench isolation structure 204 at least separates the first active area 206a, the second active area 206b, the third active area 206c and the fourth active area 206d in parallel in the well region 202. However, the present invention is not limited thereto, and other active regions may be separated in the substrate 200 according to device design requirements. The doping concentration of the "ESD injection layer of the first conductivity type" herein is usually between the doping concentration of the well region 202 of the second conductivity type and the doping concentration of the heavily doped region (such as the heavily doped region of the first conductivity type or the heavily doped region of the second conductivity type).

[0053] In the second active region 206b, the first heavily doped region 210a of the second conductivity type is located between the first heavily doped region 208a of the first conductivity type and the second heavily doped region 212a of the first conductivity type and is separated from both by a distance, the first ESD injection layer 214a of the first conductivity type is arranged at the bottom of the first heavily doped region 210a of the second conductivity type, the first heavily doped region 208a of the first conductivity type and the second heavily doped region 212a of the first conductivity type, and the first heavily doped region 208a of the first conductivity type is electrically connected to the first heavily doped region 210a of the second conductivity type.

[0054] In the third active region 206c, the third heavily doped region 208b of the first conductivity type is adjacent to the first heavily doped region 208a of the first conductivity type set in the second active region 206b, the second heavily doped region 210b of the second conductivity type is located between the third heavily doped region 208b of the first conductivity type and the fourth heavily doped region 212b of the first conductivity type and is separated from both by a distance, the second ESD injection layer 214b of the first conductivity type is set at the bottom of the third heavily doped region 208b of the first conductivity type, the second heavily doped region 210b of the second conductivity type and the fourth heavily doped region 212b of the first conductivity type, and the third heavily doped region 208b of the first conductivity type is electrically connected to the second heavily doped region 210b of the second conductivity type.

[0055] In the first active region 206a adjacent to the second active region 206b, the fifth heavily doped region 216a of the first conductivity type is in contact with the third heavily doped region 218a of the second conductivity type and is separated from the fourth heavily doped region 220a of the second conductivity type by a distance, and the third ESD injection layer 214c of the first conductivity type is disposed at the bottom of the fifth heavily doped region 216a of the first conductivity type and the fourth heavily doped region 220a of the second conductivity type. The fifth heavily doped region 216a of the first conductivity type is electrically connected to the third heavily doped region 218a of the second conductivity type. Figure 2A In the figure, the fourth heavily doped region 220a of the second conductivity type is electrically connected to the second heavily doped region 212a of the first conductivity type arranged in the second active region 206b, and there is a first external diode D1 in the circuit between the fourth heavily doped region 220a of the second conductivity type and the second heavily doped region 212a of the first conductivity type.

[0056] In the fourth active region 206d adjacent to the third active region 206c, the sixth heavily doped region 216b of the first conductivity type is in contact with the fifth heavily doped region 218b of the second conductivity type and is separated from the sixth heavily doped region 220b of the second conductivity type by a distance, and the fourth ESD injection layer 214d of the first conductivity type is disposed at the bottom of the sixth heavily doped region 216b of the first conductivity type and the sixth heavily doped region 220b of the second conductivity type. The sixth heavily doped region 216b of the first conductivity type is electrically connected to the fifth heavily doped region 218b of the second conductivity type. Figure 2A In the circuit, the sixth heavily doped region 220b of the second conductivity type is electrically connected to the fourth heavily doped region 212b of the first conductivity type arranged in the third active region 206c, and there is a second external diode D2 in the circuit between the sixth heavily doped region 220b of the second conductivity type and the fourth heavily doped region 212b of the first conductivity type.

[0057] In this embodiment, the first conductivity type is P type, and the second conductivity type is N type. However, the present invention is not limited thereto; in another embodiment, the first conductivity type is N type, and the second conductivity type is P type. In addition, the bidirectional thyristor rectifier of this embodiment further includes a silicide barrier layer 222, which is formed on the surface of the first active area 206a, the second active area 206b, the third active area 206c, and the fourth active area 206d without heavily doped areas, respectively, for shielding the metal silicide (not shown in the cross-sectional view) between the associated active areas with different doping types, thereby avoiding short circuits between the first active area 206a, the second active area 206b, the third active area 206c, and the fourth active area 206d.

[0058] Figure 2B for Figure 2A The equivalent circuit diagram of the bidirectional thyristor rectifier is shown in Figure 1, where P type is the first conductivity type and N type is the second conductivity type. Figure 2A and Figure 2B When a positive ESD pulse comes to the interface PAD1 and the interface PAD2 is grounded, the device first passes Figure 2A The "first low voltage auxiliary trigger path P1" shown in the figure conducts current, wherein the first heavily doped region 208a of the first conductivity type, the first ESD injection layer 214a of the first conductivity type, the well region 202, the fifth heavily doped region 218b of the second conductivity type and the sixth heavily doped region 216b of the first conductivity type constitute a parasitic PNP transistor ( Figure 2B The parasitic PNP transistor and the forward diode (together with the second external diode D2) form a first low-voltage auxiliary trigger path P1 through the fourth heavily doped region 212b of the first conductivity type, the second ESD injection layer 214b of the first conductivity type and the third heavily doped region 208b of the first conductivity type.

[0059] At this time, if Figure 2B As shown in the figure, PNP1 is turned on, while NPN1 is not turned on. After that, as the current continues to increase, when the resistor R PESD2 When the voltage drop on the NPN1 reaches 0.7V, NPN1 is also turned on and generates current positive feedback with PNP1, eventually forming a low-resistance current discharge path, that is, Figure 2A The “Forward SCR Path” in.

[0060] On the other hand, when the bidirectional thyristor works in the reverse mode, that is, a positive ESD pulse comes to PAD2 and PAD1 is grounded, the working mechanism is completely similar, wherein the parasitic PNP transistor ( Figure 2B The parasitic PNP transistor and the reverse diode (together with the first external diode D1) form a second low voltage auxiliary trigger path P2 through the second heavily doped region 212a of the first conductivity type, the first ESD injection layer 214a of the first conductivity type and the first heavily doped region 208a of the first conductivity type. Therefore, in the reverse mode, the device first passes through Figure 2A The "second low voltage auxiliary trigger path P2" shown in FIG. conducts current. At this time, Figure 2B As shown in the figure, PNP1 is turned on, while NPN2 is not turned on. After that, as the current continues to increase, when the resistor R PESD1 When the voltage drop on the NPN2 reaches 0.7V, NPN2 is also turned on and generates positive current feedback with PNP1, eventually forming a low-resistance current discharge path, that is, Figure 2A The "Reverse SCR Path" in.

[0061] Without changing Figure 2B Under the connection relationship of each circuit in the bidirectional thyristor rectifier of the present invention, the relative positions between each diode in the first and second (forward and reverse) low-voltage auxiliary trigger paths P1 and P2, and between the diode and the SCR main structure are variable (up, down, left, right), and are not limited to Figure 2A The device structure shown.

[0062] Moreover, for different ESD design windows, the bidirectional thyristor rectifier can also flexibly adapt to various protection requirements by adjusting the number of diodes in the low-voltage auxiliary trigger path. Figure 3A and Figure 3B A cross-sectional view of the structure of a bidirectional silicon controlled rectifier in the above embodiment is shown, wherein no external diode (such as Figure 2A D1, D2), but only the fourth ESD injection layer 214d of the first conductivity type and the sixth heavily doped region 220b of the second conductivity type form a forward diode, the third ESD injection layer 214c of the first conductivity type and the fourth heavily doped region 220a of the second conductivity type form a reverse diode, and these two diodes and the parasitic PNP transistor are used to form the first low voltage auxiliary trigger path P1 and the second low voltage auxiliary trigger path P2.

[0063] Figure 4A and Figure 4B A structural cross-sectional view of another bidirectional silicon controlled rectifier in the above embodiment is shown, which has a first external diode D1 and a second external diode D2.

[0064] Figure 5A and Figure 5B A structural cross-sectional view of another bidirectional silicon controlled rectifier in the above embodiment is shown, which has two first external diodes D1 and two second external diodes D2.

[0065] In summary, the bidirectional thyristor rectifier of the present invention can significantly reduce the trigger voltage of the device in the forward and reverse working modes through two low-voltage auxiliary trigger paths composed of diode strings. Moreover, for different ESD design windows, the bidirectional thyristor rectifier of the present invention can also flexibly adapt to various protection requirements by adjusting the number of diodes in the auxiliary trigger path. In addition, the bidirectional thyristor rectifier of the present invention can still realize the bidirectional ESD protection function in an N-well region, so compared with the complex isolation structure in the traditional DDSCR device, it still has the advantage of self-isolation, and it is expected to achieve very high area efficiency.

[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A bidirectional silicon controlled rectifier, characterized in that: include: a substrate of a first conductivity type; A well region of a second conductivity type is formed in the substrate; A shallow trench isolation structure is formed in the substrate and separates a first active region, a second active region, a third active region and a fourth active region arranged side by side in the well region; A first heavily doped region of the first conductivity type, a first heavily doped region of the second conductivity type, a second heavily doped region of the first conductivity type, and a first ESD injection layer of the first conductivity type are arranged in the second active region, wherein the first heavily doped region of the second conductivity type is located between the first heavily doped region of the first conductivity type and the second heavily doped region of the first conductivity type and is separated from both by a distance, the first ESD injection layer of the first conductivity type is arranged at the bottom of the first heavily doped region of the second conductivity type, the first heavily doped region of the first conductivity type, and the second heavily doped region of the first conductivity type, and the first heavily doped region of the first conductivity type is electrically connected to the first heavily doped region of the second conductivity type; A third heavily doped region of the first conductivity type, a second heavily doped region of the second conductivity type, a fourth heavily doped region of the first conductivity type, and a second ESD injection layer of the first conductivity type are arranged in the third active region adjacent to the second active region, wherein the third heavily doped region of the first conductivity type is adjacent to the first heavily doped region of the first conductivity type, the second heavily doped region of the second conductivity type is located between the third heavily doped region of the first conductivity type and the fourth heavily doped region of the first conductivity type and is separated from both by a distance, the second ESD injection layer of the first conductivity type is arranged at the bottom of the third heavily doped region of the first conductivity type, the second heavily doped region of the second conductivity type, and the fourth heavily doped region of the first conductivity type, and the third heavily doped region of the first conductivity type is electrically connected to the second heavily doped region of the second conductivity type; A fifth heavily doped region of the first conductivity type, a third heavily doped region of the second conductivity type, a fourth heavily doped region of the second conductivity type, and a third ESD injection layer of the first conductivity type are arranged in the first active region adjacent to the second active region, wherein the fifth heavily doped region of the first conductivity type is in contact with the third heavily doped region of the second conductivity type and is separated from the fourth heavily doped region of the second conductivity type by a distance, the third ESD injection layer of the first conductivity type is arranged at the bottom of the fifth heavily doped region of the first conductivity type and the fourth heavily doped region of the second conductivity type, and the fifth heavily doped region of the first conductivity type is electrically connected to the third heavily doped region of the second conductivity type, and the fourth heavily doped region of the second conductivity type is electrically connected to the second heavily doped region of the first conductivity type; as well as The sixth heavily doped region of the first conductivity type, the fifth heavily doped region of the second conductivity type, the sixth heavily doped region of the second conductivity type and the fourth ESD injection layer of the first conductivity type are arranged in the fourth active region adjacent to the third active region, wherein the sixth heavily doped region of the first conductivity type is in contact with the fifth heavily doped region of the second conductivity type and is separated from the sixth heavily doped region of the second conductivity type by a distance, and the fourth ESD injection layer of the first conductivity type is arranged at the bottom of the sixth heavily doped region of the first conductivity type and the sixth heavily doped region of the second conductivity type, and the sixth heavily doped region of the first conductivity type is electrically connected to the fifth heavily doped region of the second conductivity type, and the sixth heavily doped region of the second conductivity type is electrically connected to the fourth heavily doped region of the first conductivity type.

2. The bidirectional silicon controlled rectifier according to claim 1, characterized in that: Also includes: At least one first external diode is connected in the circuit between the fourth heavily doped region of the second conductivity type and the second heavily doped region of the first conductivity type.

3. The bidirectional silicon controlled rectifier according to claim 1, characterized in that: Also includes: At least one second external diode is connected in the circuit between the sixth heavily doped region of the second conductivity type and the fourth heavily doped region of the first conductivity type.

4. The bidirectional silicon controlled rectifier according to claim 1, characterized in that: The first conductivity type is P type, and the second conductivity type is N type.

5. The silicon controlled rectifier according to claim 1, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

6. The bidirectional silicon controlled rectifier according to claim 4, characterized in that: A parasitic PNP transistor is formed by the first heavily doped region of the first conductivity type, the first ESD injection layer of the first conductivity type, the well region, the fifth heavily doped region of the second conductivity type and the sixth heavily doped region of the first conductivity type; a forward diode is formed by the fourth ESD injection layer of the first conductivity type and the sixth heavily doped region of the second conductivity type; the parasitic PNP transistor and the forward diode form a first low-voltage auxiliary trigger path through the fourth heavily doped region of the first conductivity type, the second ESD injection layer of the first conductivity type and the third heavily doped region of the first conductivity type.

7. The bidirectional silicon controlled rectifier according to claim 4, characterized in that: A parasitic PNP transistor is formed by the third heavily doped region of the first conductivity type, the second ESD injection layer of the first conductivity type, the well region, the third heavily doped region of the second conductivity type and the fifth heavily doped region of the first conductivity type; a reverse diode is formed by the third ESD injection layer of the first conductivity type and the fourth heavily doped region of the second conductivity type; the parasitic PNP transistor and the reverse diode form a second low-voltage auxiliary trigger path through the second heavily doped region of the first conductivity type, the first ESD injection layer of the first conductivity type and the first heavily doped region of the first conductivity type.

8. The bidirectional silicon controlled rectifier according to claim 1, characterized in that: Also includes: A silicide blocking layer is formed on the surface of the first active region, the second active region, the third active region and the fourth active region which has no heavily doped region.

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