Matrix arrangement power MOS transistor and its PMOS rectangular unit layout

Abstract

The present invention discloses a matrix-arranged power MOS transistor and a PMOS rectangular cell layout thereof. The power MOS transistor includes multiple groups of repeatedly arranged PMOS matrix cells, and the PMOS rectangular cells are adjusted to the number of repetitions according to the magnitude of the current required by external components. Each group of PMOS cells contains a gate, a source, and a drain. The drains and sources of adjacent two groups of PMOS matrix cells are connected, and the gates and sources are connected. According to different magnitudes of the current required by external components, the arrangement number of PMOS can be adaptively adjusted to meet the applications of the power MOS transistor in different scenarios, without the need to re-design the power MOS transistor as a whole.

Description

Technical Field

[0001] The present invention belongs to the field of MOS architectures, specifically a matrix-arranged power MOS transistor. Background Art

[0002] With the explosive growth of smart terminal products, there is a huge demand for power management chips to support the implementation of different functional components. The power management chips used in mobile smart terminals usually include multiple working voltages. To meet the requirements of multiple working voltages, multiple DC voltage converters are needed to complete voltage conversion. Common DC voltage converter chips include various types such as DC-DC, LDO, and charge pumps. Considering the actual usage needs, it is necessary to increase its usage endurance as much as possible. Therefore, high requirements are put forward for the efficiency of DC voltage converter chips. Among DC voltage converters, the DC-DC switching power supply converter has the highest efficiency. The DC-DC switching power supply voltage converter is flexible and has various structures such as buck, boost, and buck-boost, which can achieve various functions such as step-down, step-up, and step-up / step-down, and can provide a large load driving current.

[0003] Among them, as the core device of the DC-DC converter, when the power MOS transistor is working, the input voltage and output voltage parameters are both fixed values. Facing the situation where the current parameters required by components are different, it is impossible to allocate according to the actual required current size, and it is often necessary to redesign the power MOS transistor so that the electronic components can operate normally, resulting in cumbersome work and other phenomena. Summary of the Invention

[0004] A solution is provided for the problem that the power MOS transistor in the above technology cannot be adjusted in real time according to the required current size.

[0005] To solve the above technical problems, the present invention provides a matrix-arranged power MOS transistor, which includes multiple groups of repeatedly arranged PMOS matrix units. The PMOS rectangular units are adjusted to the repeated quantity according to the current size required by external components. Among them, each group of PMOS rectangular units contains a gate, a source, and a drain. The drains and sources of adjacent two groups of PMOS matrix units are connected, and the gate and source of a single PMOS rectangular unit are connected.

[0006] Preferably, the drains and sources of adjacent two groups of PMOS matrix units are connected through a first diode; the gate and source of a single PMOS rectangular unit are connected through a second diode.

[0007] Preferably, the types of the first diode and the second diode are both bidirectional transient voltage suppression diodes.

[0008] Preferably, two adjacent groups of pmos rectangular units are welded by metal to enable the conduction of current.

[0009] Preferably, the aspect ratio of the length to the width of the pmos rectangular unit is 3:1.

[0010] The present invention also discloses a layout of a pmos rectangular unit, which is applied to the above-mentioned power mos transistor and includes an N-Well layer, a P-type implantation mask layer, a P-type active diffusion region layer, a polysilicon layer, and a metal layer formed in sequence from bottom to top.

[0011] In this embodiment, there are also a polysilicon cut layer and a diffusion region cut layer between the metal layer and the polysilicon layer. The polysilicon cut layer is used to form a connection end of the gate in the polysilicon layer; the diffusion region cut layer is used to form a drain connection end and a source connection end in the P-type active diffusion region layer.

[0012] In this embodiment, the metal layer is divided into metal side lines and multiple groups of metal connection lines. The metal side lines are located on both sides of the multiple groups of metal connection lines, and mutually engaged concave and convex portions are formed between adjacent metal side lines and metal connections.

[0013] The beneficial effects of the present invention are as follows: Compared with the prior art, a matrix-arranged power mos transistor provided by the present invention includes multiple groups of repeated pmos matrix units, and the number of repetitions of the pmos rectangular units is adjusted according to the magnitude of the current required by external components; wherein, each group of pmos units contains a gate, a source, and a drain, and the drains and sources of two adjacent groups of pmos matrix units are connected, and the gates and sources are connected; according to the different magnitudes of the current required by external components, the arrangement quantity of pmos can be adaptively adjusted to meet the application of the power mos transistor in different scenarios, without the need to re-design the power mos transistor as a whole. Description of the Drawings

[0014] Figure 1 It is a diagram of the matrix-arranged power mos transistor of the present invention;

[0015] Figure 2 It is an enlarged view of area A of the matrix-arranged power mos transistor of the present invention;

[0016] Figure 3 It is the N-Well layer of the layout of the pmos matrix unit of the present invention;

[0017] Figure 4 It is the P-type implantation mask layer of the layout of the pmos matrix unit of the present invention;

[0018] Figure 5 It is the P-type active diffusion region layer of the layout of the pmos matrix unit of the present invention;

[0019] Figure 6The polysilicon layer of the PMOS matrix cell layout of the present invention;

[0020] Figure 7 The metal layer of the PMOS matrix cell layout of the present invention;

[0021] Figure 8 The overall layout of the PMOS matrix cell of the present invention;

[0022] Figure 9 The diffusion region cut layer of the PMOS matrix cell layout of the present invention.

[0023] The main component symbols are explained as follows:

[0024] 1. PMOS rectangular cell; 2. First diode; 3. Second diode; 4. Metal layer;

[0025] 41. Metal border; 42. Metal connection line. Specific embodiments

[0026] In order to describe the present invention more clearly, the present invention will be further described below with reference to the accompanying drawings.

[0027] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

[0028] In the present application, the term "exemplary" is used to mean "serving as an example, illustration, or description". Any embodiment described as "exemplary" in the present application is not necessarily construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the present invention. In the following description, details are set forth for the purpose of explanation. It should be understood that those skilled in the art can recognize that the present invention can be implemented without the use of these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of the present invention with unnecessary details. Therefore, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles disclosed in the present application.

[0029] The present invention provides a matrix-arranged power MOS transistor. Please refer to Figures 1 to 2, including multiple groups of repetitively arranged pmos matrix units 1. The pmos rectangular units 1 are adjusted to the number of repetitions according to the magnitude of the current required by external components. Each group of pmos rectangular units 1 contains a gate, a source, and a drain. The drains and sources of adjacent groups of pmos matrix units 1 are connected. The gate and source of a single poms rectangular unit 1 are connected. By connecting the sources and drains of multiple groups of pmos rectangular units 1, it can be understood that multiple groups of pmos rectangular units 1 are arranged in a replicated or mirrored manner within the defined area. Correspondingly, the more pmos rectangular units 1 are connected within the same area, the higher the current that the power mosfet can withstand in applications. On the contrary, by reducing the number of connections of pmos rectangular units 1, the current that the power mosfet can withstand in actual applications decreases. Thus, an appropriate adjustment can be made according to the magnitude of the current flowing in actual applications.

[0030] In this embodiment, the drains and sources of adjacent groups of pmos matrix units 1 are connected through a first diode 2. The gate and source of a single pmos rectangular unit 1 are connected through a second diode 3. The first diode 2 is connected to the drains and sources of adjacent pmos matrix units 1. During the implementation and debugging stages of using the power mosfet, it is inevitable to use it under conditions of high voltage, large current, or strong electric field, and there is a certain risk of high-voltage failure, which is not conducive to applications such as power management chips. Therefore, when a high-voltage situation occurs during connection, the first diode 2 is used for effective protection. The high-energy current will directly break down the first diode 2, thereby protecting the power mosfet from being damaged by high voltage, and the first diode 2 can also be restored to achieve multiple protections for the component. The second diode 3 is used to prevent electrostatic effects on the power mos. Electronic products are threatened by electrostatic damage from production to use. The resistance of the power mosfet also increases relatively under the integrated connection of multiple pmos rectangular units, and the capacitance between the gate and the source is very small, so it is easily charged by external electromagnetic fields and static electricity. A small amount of charge can form a voltage risk, causing damage to the power mosfet. Therefore, the second diode 3 is added to prevent this situation from occurring. Furthermore, the types of the first diode 2 and the second diode 3 are both bidirectional transient voltage suppression diodes. When the first diode 2 or the second diode 3 can effectively absorb the high pulses generated by the electric field effect, avoid damage to the device, and eliminate the interference caused by the switching between buses.

[0031] In this embodiment, adjacent groups of pmos rectangular units are welded with metal to enable current conduction. It can be understood that by compressing the metal to the smallest size, the gap between multiple groups of pmos rectangular units can be shortened, thereby reducing the overall size of the power mosfet.

[0032] In this embodiment, for the convenience of subsequent packaging, the aspect ratio of the length to the width of the pmos rectangular unit is 3:1;

[0033] The present invention also discloses a layout of a pmos rectangular unit. Please refer to Figures 3 to 8 , which is applied to the above-mentioned power mosfet, and includes an N-Well layer, a P-type implantation mask layer, a P-type active diffusion region layer, a polysilicon layer, and a metal layer formed in sequence from bottom to top; an N-well is formed on the substrate to obtain the N-Well layer, and the exposure is defined through the P-type implantation mask layer. The source and drain of the pmos rectangular unit are formed at both ends of the P-type active diffusion region layer. The polysilicon layer forms the gate of the pmos rectangular unit 1. Finally, the corresponding metal layer is set. The metal layer is used for welding in the subsequent arrangement of the power mosfet and forms the overall conduction of the circuit; it can be understood that by designing a single pmos rectangular unit 1, the size parameters of the pmos rectangular unit 1 are minimized, and the required current magnitude and conversion rate of the relevant single pmos rectangular unit 1 are designed. After completing the verification steps of the above current and conversion rate parameters, the arrangement step in the power mosfet can be carried out.

[0034] In this embodiment, there are also a polysilicon cut layer and a diffusion region cut layer between the metal layer and the polysilicon layer. The polysilicon cut layer is used to form the connection end of the gate in the polysilicon layer; the diffusion region cut layer is used to form the connection end of the drain and source in the P-type active diffusion region layer; through the polysilicon cut layer and the diffusion region cut layer, the connection ends of the gate, source, and drain are exposed, so that the pmos rectangular unit 1 can be arranged and connected in subsequent applications.

[0035] In this embodiment, the metal layer is divided into a metal side line 41 and multiple groups of metal connection lines 42. The metal side line 41 is located on both sides of the multiple groups of metal connection lines 42. A concave portion and a convex portion that fit into each other are formed between the adjacent metal side line 41 and the metal connection line 42; it can be understood that the concave portion and the convex portion are fitted to each other, which can effectively compress the area of the layout, further reduce the size of the pmos rectangular unit, and more pmos rectangular units can be integrated in the same space.

[0036] The advantages of the present invention are as follows:

[0037] 1) Each group of pmos rectangular units contains a gate, a source, and a drain. The drains and sources of two adjacent groups of pmos matrix units are connected, and the gates and sources are connected; according to the different magnitudes of the current required by external components, the arrangement quantity of the pmos can be adjusted adaptively to meet the applications of the power mosfet in different scenarios, without the need to re-design the power mosfet as a whole;

[0038] 2) By connecting with a first diode between the drains and sources of two adjacent groups of pmos rectangular cells, the destruction of the power mos transistor caused by high voltage is prevented; and by connecting with a second diode between the sources and gates of individual pmos rectangular cells, the threat caused by static electricity is reduced.

[0039] The above-disclosed are only several specific embodiments of the present invention, but the present invention is not limited thereto, and any changes that can be conceived by those skilled in the art should fall within the protection scope of the present invention.

Claims

1. A matrix-arranged power MOS transistor, characterized in that It includes multiple groups of repetitively arranged pmos matrix units, and the number of repetitions of the pmos rectangular units is adjusted according to the magnitude of the current required by external components. Each group of pmos rectangular units contains a gate, a source, and a drain, and the drains and sources of adjacent two groups of pmos matrix units are connected; the gate and the source of a single poms rectangular unit are connected. Among them, the drains and sources of adjacent two groups of pmos matrix units are connected through a first diode; the gate and the source of a single pmos rectangular unit are connected through a second diode; the types of the first diode and the second diode are both bidirectional transient voltage suppression diodes.

2. The matrix-arranged power MOS transistor according to claim 1, wherein Adjacent two groups of pmos rectangular units are welded by metal to enable current conduction.

3. The matrix-arranged power MOS transistor according to claim 1, wherein The aspect ratio of the pmos rectangular unit is 3:

1.

4. A PMOS rectangular cell layout for designing the power MOS transistor of any one of claims 1 to 3, characterized in that, It includes an N-Well layer, a P-type implantation mask layer, a P-type active diffusion region layer, a polysilicon layer, and a metal layer formed successively from bottom to top.

5. The pmos rectangular cell layout according to claim 4, wherein There are also a polysilicon cut layer and a diffusion region cut layer between the metal layer and the polysilicon layer. The polysilicon cut layer is used to form a connection end of the gate in the polysilicon layer; the diffusion region cut layer is used to form connection ends of the drain and the source in the P-type active diffusion region layer.

6. The pmos rectangular cell layout according to claim 4, wherein The metal layer is divided into metal side lines and multiple groups of metal connection lines. The metal side lines are located on both sides of the multiple groups of metal connection lines, and mutually interlocking concave and convex parts are formed between adjacent metal side lines and metal connection lines.

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