Hemt device with array field plate and method of making the same

Abstract

The application discloses a HEMT device with an array field plate and a preparation method thereof, and the HEMT device comprises a substrate, a heterojunction on the substrate, the heterojunction comprising a channel layer and a barrier layer, a passivation layer structure above the heterojunction, the heterojunction and the passivation layer structure being provided with a gate region, a source region and a drain region along a first direction, the gate region being between the source region and the drain region, a gate, a source and a drain being formed in the gate region, the source region and the drain region respectively, the gate being between the source and the drain, and a plurality of field plates being inside or above the passivation layer structure between the gate and the drain, the field plates comprising a plurality of metal blocks arranged in an array along the first direction or perpendicular to the first direction. The application can balance the sharp peak electric field uniformly by arranging the array field plates, and the breakdown voltage and reliability of the device are improved significantly, and the preparation method is simple, and the width and height of each layer of the field plates do not need to be optimized carefully.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor devices and processes, and particularly relates to a HEMT device with an array field plate and a preparation method thereof. BACKGROUND

[0002] The third generation semiconductor material gallium nitride (GaN) has become a hotspot in the research of high temperature, high frequency and high power density due to its wide band gap (3.4 eV), high electron mobility and high breakdown field. At present, a gallium nitride-based high electron mobility transistor (HEMT) has a wide application prospect in the field of high-efficiency and high-voltage power electronics. When the GaN HEMT works in a high-frequency and high-voltage state, it needs to withstand an extremely high drain voltage. Electric field lines will converge between the drain and the gate of the device. However, due to the inevitable defects in the device structure, the electric field is unevenly distributed in the channel, and an extremely high peak electric field will accumulate at the edge of the gate close to the drain. Usually, the size of the peak electric field of the GaN HEMT gate determines the breakdown voltage of the entire device, which often causes the actual breakdown voltage of the device to be much lower than the theoretical breakdown voltage value of the GaN material.

[0003] In order to improve the voltage resistance characteristic of the GaN HEMT, a field plate (FP) structure is often introduced into the device in the prior art. The field plate material is metal, which is placed between the gate and the drain, can be connected with any electrode of the source, the gate or the drain, can not be connected, or multiple field plates can be placed and connected with different electrodes. The field plate can modulate the electric field distribution of the device channel by generating an additional potential between the gate and the drain, thereby significantly improving the breakdown voltage and reliability of the device. However, in the prior art, the length and height of each layer of field plates often need to be carefully optimized, which cannot effectively and uniformly balance the peak electric field.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a HEMT device with an array field plate and a preparation method thereof. SUMMARY

[0005] Therefore, in view of the above technical problems, it is necessary to provide a HEMT device with an array field plate and a preparation method thereof.

[0006] In order to achieve the above-mentioned purpose, the technical scheme provided by an embodiment of the application is as follows:

[0007] A HEMT device with an array field plate, the HEMT device comprising:

[0008] a substrate;

[0009] a heterojunction on the substrate, the heterojunction comprising a channel layer and a barrier layer;

[0010] a passivation layer structure above the heterojunction, the heterojunction and the passivation layer structure having a gate region, a source region and a drain region formed thereon along a first direction, the gate region being between the source region and the drain region;

[0011] a gate, a source and a drain formed in the gate region, the source region and the drain region respectively, the gate being between the source and the drain;

[0012] a plurality of field plates inside or above the passivation layer structure between the gate and the drain, the field plates comprising a plurality of metal blocks arrayed along the first direction or perpendicular to the first direction.

[0013] In an embodiment, the HEMT device comprises one or more layers of field plates, each layer of field plates comprising a plurality of metal blocks arrayed along the first direction or perpendicular to the first direction, and the metal blocks in different layers of field plates are partially overlapped.

[0014] When the metal blocks are arrayed along the first direction, the thickness of the metal blocks is 50-400 nm, the width of the metal blocks is 500-2500 nm, and the spacing between adjacent metal blocks is 1-3 μm.

[0015] When the metal blocks are arrayed perpendicular to the first direction, the thickness of the metal blocks is 50-400 nm, the length of the metal blocks is 3-15 μm, the width of the metal blocks is 500-2500 nm, and the spacing between adjacent metal blocks is 1-3 μm.

[0016] In an embodiment, the field plates are gate field plates electrically connected to the gate, or source field plates electrically connected to the source, or independent floating field plates.

[0017] In an embodiment, the HEMT device comprises:

[0018] a first passivation layer above the heterojunction;

[0019] a P-type semiconductor layer formed in the gate region above the heterojunction;

[0020] a second passivation layer above the first passivation layer;

[0021] a third passivation layer and a first field plate above the second passivation layer, the first field plate comprising a plurality of first metal blocks arrayed along the first direction or perpendicular to the first direction;

[0022] a fourth passivation layer and a second field plate above the third passivation layer, the second field plate comprising a plurality of second metal blocks arrayed along the first direction or perpendicular to the first direction;

[0023] a fifth passivation layer and a third field plate above the fourth passivation layer, the third field plate comprising a plurality of third metal blocks arrayed along the first direction or perpendicular to the first direction.

[0024] In one embodiment, when the metal blocks are arrayed along the first direction:

[0025] The first metal block has a thickness of 70-400 nm, a width of 500-1500 nm, and a spacing between adjacent metal blocks of 1-3 μm. When the first field plate is a gate field plate, the minimum distance between the first metal block and the P-type semiconductor layer along the first direction is 0. When the first field plate is a source field plate or a floating field plate, the minimum distance between the first metal block and the P-type semiconductor layer along the first direction is 500-1000 nm.

[0026] The second metal block has a thickness of 50-200 nm, and is partially overlapped with the first metal block. Each second metal block has an overlapped width of 250-1000 nm with one first metal block below, an un-overlapped width of 500-1500 nm, and a spacing of 500-1500 nm with another first metal block below.

[0027] The third metal block has a thickness of 50-200 nm, and is partially overlapped with the first and second metal blocks. Each third metal block has an overlapped width of 250-1000 nm with one second metal block below and one first metal block below.

[0028] When the metal blocks are arrayed perpendicular to the first direction:

[0029] The first metal block has a thickness of 70-400 nm, a length of 3-15 μm, and a width of 500-1500 nm. The spacing between adjacent metal blocks is 1-3 μm. When the first field plate is a gate field plate, the minimum distance between the first metal block and the P-type semiconductor layer along the first direction is 0. When the first field plate is a source field plate or a floating field plate, the minimum distance between the first metal block and the P-type semiconductor layer along the first direction is 500-1000 nm.

[0030] The second metal block has a thickness of 50-200 nm, and a length of 3-15 μm. The second metal block is partially overlapped with the first metal block. Each second metal block has an overlapped width of 250-1000 nm with one first metal block below, an un-overlapped width of 500-1500 nm, and a spacing of 500-1500 nm with another first metal block below.

[0031] The third metal block has a thickness of 50-200 nm, and a length of 3-15 μm. The third metal block is partially overlapped with the first and second metal blocks. Each third metal block has an overlapped width of 250-1000 nm with one second metal block below and one first metal block below.

[0032] In an embodiment, the first passivation layer is a combination of one or more of a silicon nitride passivation layer, a silicon oxide passivation layer, an aluminum oxide passivation layer, an aluminum nitride passivation layer, a gallium oxide passivation layer, and has a thickness of 20-200 nm; and / or,

[0033] The second passivation layer is a combination of one or more of a silicon nitride passivation layer, a silicon oxide passivation layer, and has a thickness of 50-300 nm; and / or,

[0034] The third passivation layer is a combination of one or more of a silicon nitride passivation layer, a silicon oxide passivation layer, and has a thickness of 50-300 nm; and / or,

[0035] The fourth passivation layer is a combination of one or more of a silicon nitride passivation layer, a silicon oxide passivation layer, and has a thickness of 50-300 nm; and / or,

[0036] The fifth passivation layer is a combination of one or more of a silicon nitride passivation layer, a silicon oxide passivation layer, a polyimide passivation layer, a benzocyclobutene passivation layer, and has a thickness of 1-5 μm.

[0037] In an embodiment, the source and / or drain is made of a metal and / or a metal compound, the metal includes a combination of one or more of gold, platinum, nickel, titanium, aluminum, palladium, tantalum, tungsten, molybdenum, and the metal compound includes a combination of one or more of titanium nitride and tantalum nitride; and / or,

[0038] The source and / or field plate is made of a metal and / or a metal compound, the metal includes a combination of one or more of gold, platinum, nickel, titanium, palladium, tantalum, tungsten, and the metal compound includes a combination of one or more of titanium nitride and tantalum nitride.

[0039] In an embodiment, the substrate is any one of a silicon substrate, a sapphire substrate, and a silicon carbide substrate; and / or,

[0040] The channel layer is a gallium nitride channel layer and has a thickness of 50 nm-2 μm; and / or,

[0041] The barrier layer is an aluminum gallium nitride (Al x GaN 1-x N, x=0.1-0.3) barrier layer and has a thickness of 10 nm-50 nm; and / or,

[0042] The P-type semiconductor layer is a P-type gallium nitride layer and has a thickness of 70 nm-120 nm; and / or,

[0043] A buffer layer is provided between the substrate and the channel layer, and the buffer layer is a nitride buffer layer.

[0044] Another embodiment of the present application provides the following technical solutions:

[0045] A preparation method of a HEMT device with an array field plate, the preparation method comprising:

[0046] providing a substrate;

[0047] epitaxially growing a channel layer and a barrier layer on the substrate to form a heterojunction;

[0048] epitaxially growing a passivation layer structure on the heterojunction, and forming a gate region, a source region and a drain region in the heterojunction and the passivation layer structure along a first direction, the gate region being located between the source region and the drain region;

[0049] forming a gate, a source and a drain in the gate region, the source region and the drain region respectively, the gate being located between the source and the drain;

[0050] forming a plurality of field plates in or above the passivation layer structure between the gate and the drain, the field plates comprising a plurality of metal blocks arrayed along the first direction or perpendicular to the first direction.

[0051] In an embodiment, the HEMT device comprises one or more layers of field plates, each layer of field plates comprising a plurality of metal blocks arrayed along the first direction or perpendicular to the first direction, and the metal blocks in different layers of field plates are partially overlapped.

[0052] When the metal blocks are arrayed along the first direction, the thickness of the metal blocks is 50-400 nm, the width of the metal blocks is 500-2500 nm, and the spacing between adjacent metal blocks is 1-3 μm;

[0053] When the metal blocks are arrayed perpendicular to the first direction, the thickness of the metal blocks is 50-400 nm, the length of the metal blocks is 3-15 μm, the width of the metal blocks is 500-2500 nm, and the spacing between adjacent metal blocks is 1-3 μm.

[0054] The present application has the following beneficial effects:

[0055] The present application can balance the peak electric field uniformly by setting the array field plates, significantly improves the breakdown voltage and reliability of the device, and the preparation method is simple and does not need to optimize the width and height of each layer of field plates carefully. BRIEF DESCRIPTION OF DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0057] Figure 1A flowchart of a preparation method of the HEMT device in the present application is shown in the figure;

[0058] Figure 2 A structure diagram of the HEMT device in the embodiment 1 of the present application is shown in the figure;

[0059] Figures 3 to 13 A process flowchart of the preparation method of the HEMT device in the embodiment 1 of the present application is shown in the figure;

[0060] Figure 14 A structure diagram of the HEMT device in the embodiment 2 of the present application is shown in the figure;

[0061] Figure 15 A planar structure diagram of the electrode and the field plate in the embodiment 2 of the present application is shown in the figure. DETAILED DESCRIPTION

[0062] In order to make the personnel in the technical field better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the person of ordinary skill in the art without creative labor should belong to the protection scope of the present application.

[0063] The present application discloses a HEMT device with array field plates, comprising:

[0064] a substrate;

[0065] a heterojunction on the substrate, the heterojunction comprising a channel layer and a barrier layer;

[0066] a passivation layer structure above the heterojunction, the heterojunction and the passivation layer structure having a gate region, a source region and a drain region formed thereon along a first direction, the gate region being between the source region and the drain region;

[0067] a gate, a source and a drain formed in the gate region, the source region and the drain region respectively, the gate being between the source and the drain;

[0068] a plurality of field plates inside or above the passivation layer structure between the gate and the drain, the field plates comprising a plurality of metal blocks arranged along the first direction or distributed perpendicular to the first direction.

[0069] Preferably, when the metal blocks are arrayed in the first direction, the thickness of the metal blocks is 50 - 400 nm, the width is 500 - 2500 nm, and the spacing between adjacent metal blocks is 1 - 3 μm; when the metal blocks are arrayed perpendicular to the first direction, the thickness of the metal blocks is 50 - 400 nm, the length is 3 - 15 μm, the width is 500 - 2500 nm, and the spacing between adjacent metal blocks is 1 - 3 μm.

[0070] As shown in Figure 1 FIG.

[0071] providing a substrate;

[0072] epitaxially growing a channel layer and a barrier layer on the substrate to form a heterojunction;

[0073] epitaxially growing a passivation layer structure on the heterojunction, and forming a gate region, a source region, and a drain region in the heterojunction and the passivation layer structure along the first direction, with the gate region located between the source region and the drain region;

[0074] forming a gate, a source, and a drain in the gate region, the source region, and the drain region respectively, with the gate located between the source and the drain;

[0075] forming a plurality of field plates inside or above the passivation layer structure between the gate and the drain, the field plates including a plurality of metal blocks arrayed along the first direction or perpendicular to the first direction.

[0076] Preferably, the passivation layer includes five layers from the first passivation layer to the fifth passivation layer, and the field plates include three layers from the first field plate to the third field plate. The first field plate includes a plurality of first metal blocks arrayed along the first direction or perpendicular to the first direction, the second field plate includes a plurality of second metal blocks arrayed along the first direction or perpendicular to the first direction, and the third field plate includes a plurality of third metal blocks arrayed along the first direction or perpendicular to the first direction.

[0077] Among them, when the metal blocks are arrayed in the first direction:

[0078] the thickness of the first metal blocks is 70 - 400 nm, the width is 500 - 1500 nm, the spacing between adjacent metal blocks is 1 - 3 μm, when the first field plate is a gate field plate, the minimum distance between the first metal blocks and the P-type semiconductor layer along the first direction is 0, and when the first field plate is a source field plate or a floating field plate, the minimum distance between the first metal blocks and the P-type semiconductor layer along the first direction is 500 - 1000 nm;

[0079] The thickness of the second metal block is 50 - 200 nm. The second metal block is partially overlapped with the first metal block. The overlapping width of each second metal block and one first metal block below is 250 - 1000 nm, the non - overlapping width is 500 - 1500 nm, and the distance from the other first metal block below is 500 - 1500 nm;

[0080] The thickness of the third metal block is 50 - 200 nm. The third metal block is partially overlapped with the first metal block and the second metal block. The overlapping width of each third metal block and one second metal block below and the first metal block below is 250 - 1000 nm;

[0081] When the metal blocks are distributed in an array perpendicular to the first direction:

[0082] The thickness of the first metal block is 70 - 400 nm, the length is 3 - 15 μm, the width is 500 - 1500 nm, the distance between adjacent metal blocks is 1 - 3 μm. When the first field plate is a gate field plate, the minimum distance between the first metal block and the P - type semiconductor layer along the first direction is 0. When the first field plate is a source field plate or a floating field plate, the minimum distance between the first metal block and the P - type semiconductor layer along the first direction is 500 - 1000 nm;

[0083] The thickness of the second metal block is 50 - 200 nm, the length is 3 - 15 μm. The second metal block is partially overlapped with the first metal block. The overlapping width of each second metal block and one first metal block below is 250 - 1000 nm, the non - overlapping width is 500 - 1500 nm, and the distance from the other first metal block below is 500 - 1500 nm;

[0084] The thickness of the third metal block is 50 - 200 nm, the length is 3 - 15 μm. The third metal block is partially overlapped with the first metal block and the second metal block. The overlapping width of each third metal block and one second metal block below and the first metal block below is 250 - 1000 nm.

[0085] The present invention will be further described below in conjunction with specific embodiments.

[0086] Embodiment 1:

[0087] Refer Figure 2 As shown, the HEMT device in this embodiment includes:

[0088] Substrate 10;

[0089] Buffer layer 20, located on the substrate 10;

[0090] The heterojunction is located on the buffer layer 20. The heterojunction includes a channel layer 30 and a barrier layer 40. A two-dimensional electron gas (2DEG) is formed at the interface between the channel layer and the barrier layer. An isolation region 90 is provided at the edge region of the heterojunction.

[0091] A passivation layer structure is located above the heterojunction. A gate region, a source region, and a drain region are formed along a first direction in the heterojunction and passivation layer structure, with the gate region located between the source region and the drain region.

[0092] Gate 71, source 72 and drain 73 are formed in the gate region, source region and drain region, respectively, with the gate located between the source and drain;

[0093] Several field plates are located inside or above the passivation layer structure between the gate and the drain, and the field plates include several metal blocks arranged in an array along a first direction.

[0094] Specifically, in this embodiment, the heterojunction includes the following:

[0095] The first passivation layer 51 is located on the heterojunction;

[0096] A P-type semiconductor layer 80 is formed in the gate region on the heterojunction;

[0097] The second passivation layer 51 is located on the first passivation layer;

[0098] The third passivation layer 52 and the first field plate 61 are located on the second passivation layer. The first field plate includes a plurality of first metal blocks arranged in an array along the first direction.

[0099] The fourth passivation layer 53 and the second field plate 62 are located on the third passivation layer. The second field plate includes a plurality of second metal blocks arranged in an array along the first direction.

[0100] The fifth passivation layer 55 and the third field plate 63 are located on the fourth passivation layer. The third field plate includes a plurality of third metal blocks distributed in an array along the first direction.

[0101] The thickness of the first metal block is 70-400 nm, the width is 500-1500 nm, and the spacing between adjacent metal blocks is 1-3 μm. When the first field plate is a gate field plate, the minimum distance between the first metal block and the P-type semiconductor layer along the first direction is 0. When the first field plate is a source field plate or a floating field plate, the minimum distance between the first metal block and the P-type semiconductor layer along the first direction is 500-1000 nm.

[0102] The thickness of the second metal block is 50 - 200 nm. The second metal block is partially overlapped with the first metal block. The overlapping width of each second metal block and one first metal block below is 250 - 1000 nm, the non-overlapping width is 500 - 1500 nm, and the distance from the other first metal block below is 500 - 1500 nm;

[0103] The thickness of the third metal block is 50 - 200 nm. The third metal block is partially overlapped with the first metal block and the second metal block. The overlapping width of each third metal block and one second metal block below and the first metal block below is 250 - 1000 nm.

[0104] The HEMT device and its manufacturing method in this embodiment will be described in detail below with reference to the accompanying drawings.

[0105] As Figure 3 shown, the epitaxial structure in this embodiment mainly includes a substrate 10, a buffer layer 20, a channel layer 30, and a barrier layer 40. The manufacturing method can also be compatible with other epitaxial structures including some epitaxial layers such as an aluminum nitride isolation layer (AlN spacer), a gallium nitride cap layer (GaN cap), or a p-type nitride.

[0106] The substrate can include materials such as silicon (Si), sapphire (AL2O3), and silicon carbide (SiC);

[0107] The buffer layer is mainly nitride, including gallium nitride, aluminum nitride, aluminum gallium nitride, etc.;

[0108] The channel layer is a gallium nitride channel layer with a thickness of 50 nm - 2 μm;

[0109] The barrier layer is an aluminum gallium nitride (Al x GaN 1-x N, x = 0.1 - 0.3) barrier layer with a thickness of 10 nm - 50 nm;

[0110] The P-type semiconductor layer 80 can be a p-type gallium nitride layer (p-GaN), a p-type aluminum gallium nitride layer (p-AlGaN), a p-type aluminum indium nitride layer (p-AlInN), etc. In this embodiment, a p-type gallium nitride layer is taken as an example. The p-type gallium nitride layer has a thickness of 70 nm - 120 nm. Due to the existence of the p-type gallium nitride layer, a two-dimensional electron gas (2DEG) cannot be formed at the interface between the gallium nitride channel layer and the aluminum gallium nitride barrier layer below the p-type gallium nitride layer.

[0111] As Figure 4As shown, the p-type gallium nitride layer outside the gate region is removed. This removal can be achieved through plasma etching, allowing the two-dimensional electron gas in the channel to be restored after the p-type gallium nitride layer is removed. Subsequently, a first passivation layer 51 is grown to protect the aluminum gallium nitride barrier layer and the surface of the p-type gallium nitride layer. The material of the first passivation layer can be silicon nitride (SiN), silicon oxide (SiO2), aluminum oxide (Al2O3), aluminum nitride (AlN), gallium oxide (Ga2O3), etc., or a composite passivation layer composed of different materials. The passivation layer thickness is 20–200 nm.

[0112] like Figure 5 As shown, holes are made in the source and drain regions. The hole-making method can be plasma gas etching or wet etching with an acidic or alkaline solution, depending on the material of the first passivation layer. The hole depth can be just enough to remove the first passivation layer 51, or it can be used to further remove part of the aluminum gallium nitride barrier layer. The preferred method for removing the aluminum gallium nitride barrier layer is plasma gas etching.

[0113] like Figure 6 As shown, a first metal layer is fabricated, forming the source electrode 72 and the drain electrode 73. The material of the first metal layer can include gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), aluminum (Al), palladium (Pd), tantalum (Ta), tungsten (W), molybdenum (Mo), etc., or metal compounds such as titanium nitride (TiN) and tantalum nitride (TaN). The metal can be formed by evaporation or sputtering. After formation, the photoresist and excess metal can be removed by stripping, or the metal in areas other than the source and drain can be removed by etching. After the first metal layer is fabricated, it needs to be rapidly annealed to form a good ohmic metal between the metal and the semiconductor. The annealing temperature can be 450–800℃, and the annealing time can be 30–300 s.

[0114] Next, a second passivation layer 52 is grown. The material of the second passivation layer 52 can be an insulating medium such as silicon nitride or silicon oxide, or a composite passivation layer composed of different insulating media. The thickness of the passivation layer is 50–300 nm. After the second passivation layer is grown, it can be planarized using chemical mechanical polishing (CMP). After the second passivation layer is grown, the passive region is isolated to form an isolation region 90. Isolation can be achieved by ion implantation of strongly negatively charged elements such as O or F, or by etching. The etching gas can be BCl3, Cl2, etc.

[0115] like Figure 7 As shown, gate vias are created. The via method can be plasma gas etching or wet etching using acidic or alkaline solutions, depending on the passivation layer material. A combination of plasma gas etching and wet etching can also be used. Simultaneously with gate vias, vias can also be created for the source and drain.

[0116] like Figure 8a , 8b As shown, a second metal layer is fabricated. This second metal layer primarily forms the gate 71, but can also form thickened layers for the source and drain, as well as the first field plate (FP1). The material of the second metal layer can include gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), tantalum (Ta), tungsten (W), etc., or metal compounds such as titanium nitride (TiN) and tantalum nitride (TaN). The metal can be formed by evaporation or sputtering. After formation, the photoresist and excess metal can be removed by stripping or by metal etching.

[0117] The thickness of the first field plate can be 70–400 nm. It can be connected to the gate to form a gate field plate, or connected to the source to form a source field plate.

[0118] Figure 8b This is a schematic diagram of the planar structure of the first field plate. The first field plate is composed of multiple first metal blocks distributed at equal intervals. The width of each first metal block can be 500-1500 nm, and the spacing between adjacent first metal blocks can be 1-3 μm.

[0119] If the first field plate is a gate field plate, the distance between its leftmost first metal block and the p-type gallium nitride layer can be 0. If the first field plate is a source field plate, the distance between its leftmost metal block and the p-type gallium nitride layer can be 500-1000nm.

[0120] Next, the third passivation layer 53 is grown. The material of the third passivation layer 53 can be an insulating medium such as silicon nitride or silicon oxide, or a composite passivation layer composed of different insulating media. The thickness of the passivation layer is 50–300 nm. After the third passivation layer is grown, it can be planarized using chemical mechanical polishing (CMP).

[0121] like Figure 9 As shown, holes are made. The hole making method can be plasma gas etching or wet etching with acidic or alkaline solutions depending on the material of the passivation layer. Alternatively, a combination of plasma gas etching and wet etching can be used.

[0122] like Figure 10a , 10b As shown, a third metal layer is fabricated to form the second field plate (FP2), and the source and drain electrodes are thickened. The material of the third metal layer can include gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), tantalum (Ta), tungsten (W), etc., or metal compounds such as titanium nitride (TiN) and tantalum nitride (TaN). The metal can be formed by evaporation or sputtering. After formation, the photoresist and excess metal can be removed by stripping or by metal etching.

[0123] The thickness of the second field plate can be 50-200 nm. It can be connected to the gate to form a gate field plate, or connected to the source to form a source field plate.

[0124] Figure 10b This is a schematic diagram of the planar structure of the first and second field plates. The distribution of the second field plate is similar to that of the first field plate. Each second metal block in the second field plate must partially overlap with its adjacent left-side first metal block in the vertical direction, with an overlap width of 250–1000 nm. The width of the portion of each second metal block in the second field plate extending beyond the first metal block in the first field plate can be 500–1500 nm. Each second metal block in the second field plate must be 500–1500 nm away from the first metal block in its adjacent right-side first field plate.

[0125] Next, the fourth passivation layer 54 is grown. The material of the fourth passivation layer can be an insulating medium such as silicon nitride or silicon oxide, or a composite passivation layer composed of different insulating media. The thickness of the passivation layer is 50–300 nm. After the fourth passivation layer is grown, it can be planarized using chemical mechanical polishing (CMP).

[0126] like Figure 11 As shown, holes are made. The hole making method can be plasma gas etching or wet etching with acidic or alkaline solutions depending on the material of the passivation layer. Alternatively, a combination of plasma gas etching and wet etching can be used.

[0127] like Figure 12a , 12b As shown, a fourth metal layer is fabricated to form the third field plate (FP3), and the source and drain electrodes are thickened. The material of the fourth metal layer can include gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), tantalum (Ta), tungsten (W), etc., or metal compounds such as titanium nitride (TiN) and tantalum nitride (TaN). The metal can be formed by evaporation or sputtering. After formation, the photoresist and excess metal can be removed by stripping or by metal etching.

[0128] The thickness of the third field plate can be 50-200 nm. It can be connected to the gate to form a gate field plate, or connected to the source to form a source field plate.

[0129] Figure 12b The diagram shows the planar structure of the first, second, and third field plates. The distribution of the third field plate is similar to that of the first and second field plates. Each third metal block in the third field plate needs to partially overlap with the second metal block in the adjacent left second field plate and the first metal block in the adjacent right first field plate in the vertical direction. The overlap width can be 250-1000 nm.

[0130] Next, the fifth passivation layer 55 is grown. The material of the fifth passivation layer can be an inorganic material such as silicon nitride or silicon oxide, or an organic material such as polyimide (PI) or benzocyclobutene (BCB), or a composite passivation layer composed of different insulating materials. The thickness of the passivation layer is 1-5 μm. After the fifth passivation layer is grown, chemical mechanical polishing (CMP) can be used to planarize it.

[0131] As Figure 13 shown, openings are made in the counter electrode. The opening method can be selected as plasma gas etching or wet etching with an acidic or alkaline solution according to the material of the passivation layer, or a combination of plasma gas etching and wet etching can also be used.

[0132] Viewed along the cross-sectional view of the GaN HEMT current direction, the field plates are arranged in a dot matrix pattern. In this embodiment, three field plates are taken as an example. In actual operation, more than three field plates can also be set according to this method, or one or two field plates can be set, which will not be elaborated here one by one.

[0133] Embodiment 2:

[0134] Refer Figure 14 shown, the HEMT device in this embodiment includes:

[0135] Substrate 10;

[0136] Buffer layer 20, located on substrate 10;

[0137] A heterojunction located on buffer layer 20. The heterojunction includes a channel layer 30 and a barrier layer 40. A two-dimensional electron gas (2DEG) is formed at the interface between the channel layer and the barrier layer, and an isolation region 90 is provided in the edge region of the heterojunction;

[0138] A passivation layer structure, located above the heterojunction. A gate region, a source region, and a drain region are formed in the heterojunction and the passivation layer structure along a first direction. The gate region is located between the source region and the drain region;

[0139] Gate 71, source 72, and drain 73 are respectively formed in the gate region, the source region, and the drain region, and the gate is located between the source and the drain;

[0140] A plurality of field plates, located inside or above the passivation layer structure between the gate and the drain. The field plates include a plurality of metal blocks arranged in an array perpendicular to the first direction.

[0141] Combined Figure 15 shown, above the heterojunction in this embodiment includes:

[0142] ​​​A P-type semiconductor layer 80 is formed in the gate region on the heterojunction;

[0144] The second passivation layer 51 is located on the first passivation layer;

[0145] The third passivation layer 52 and the first field plate 61 are located on the second passivation layer. The first field plate includes a plurality of first metal blocks arranged in an array perpendicular to the first direction.

[0146] The fourth passivation layer 53 and the second field plate 62 are located on the third passivation layer. The second field plate includes a plurality of second metal blocks arranged in an array perpendicular to the first direction.

[0147] The fifth passivation layer 55 and the third field plate 63 are located on the fourth passivation layer. The third field plate includes a plurality of third metal blocks arranged in an array perpendicular to the first direction.

[0148] The HEMT device and its fabrication method in this embodiment are basically the same as those in Embodiment 1. The difference is that the field plate in Embodiment 1 is a metal block distributed in an array along the first direction, while the field plate in this embodiment is a metal block distributed in an array perpendicular to the first direction.

[0149] In addition, when the metal blocks are distributed along the first direction array, the width of the metal blocks is 500-1500 nm, and the length is related to the width of a single finger gate, which does not need to be considered in this invention; while when the metal blocks are distributed perpendicular to the first direction array, the length of the metal blocks is 3-15 μm and the width is 500-1500 nm.

[0150] In this embodiment, a three-layer plate is used as an example. In actual operation, more than three layers of plates can also be set in this way, or one or two layers of plates can be set. These will not be described in detail here.

[0151] As can be seen from the above technical solutions, the present invention has the following advantages:

[0152] This invention can uniformly balance the peak electric field by setting up an array of field plates, which significantly improves the breakdown voltage and reliability of the device. Moreover, the fabrication method is simple and does not require detailed optimization of the width and height of each field plate.

[0153] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0154] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A HEMT device with an arrayed field plate, characterized in that, The HEMT device includes: Substrate, wherein the substrate is a silicon substrate; A heterojunction located on a substrate, the heterojunction includes a channel layer and a barrier layer; A passivation layer structure is located above the heterojunction. The heterojunction and passivation layer structure have a gate region, a source region, and a drain region formed along a first direction, with the gate region located between the source region and the drain region. The gate, source, and drain are formed in the gate region, source region, and drain region, respectively, with the gate located between the source and drain. Several field plates are located inside or above a passivation layer structure between the gate and the drain, and the field plates include several metal blocks arranged in an array along or perpendicular to a first direction. The HEMT device includes: The first passivation layer is located on the heterojunction. The first passivation layer is one or more of the following: silicon nitride passivation layer, silicon oxide passivation layer, aluminum oxide passivation layer, aluminum nitride passivation layer, and gallium oxide passivation layer, with a thickness of 20~200nm. A P-type semiconductor layer is formed in the gate region on the heterojunction; The second passivation layer is located on the first passivation layer. The second passivation layer is one or more of silicon nitride passivation layer and silicon oxide passivation layer, and the thickness is 50~300nm. The third passivation layer and the first field plate are located on the second passivation layer. The first field plate includes a plurality of first metal blocks arranged in an array along or perpendicular to the first direction. The third passivation layer is a combination of one or more of silicon nitride passivation layer and silicon oxide passivation layer, with a thickness of 50~300nm. The fourth passivation layer and the second field plate are located on the third passivation layer. The second field plate includes a plurality of second metal blocks arranged in an array along or perpendicular to the first direction. The fourth passivation layer is one or more of silicon nitride passivation layer and silicon oxide passivation layer, with a thickness of 50~300nm. The fifth passivation layer and the third field plate are located on the fourth passivation layer. The third field plate includes a plurality of third metal blocks arranged in an array along or perpendicular to the first direction. The fifth passivation layer is a polyimide passivation layer with a thickness of 1~5μm. When the metal blocks are arrayed along the first direction: The thickness of the first metal block is 70~400nm, the width is 500~1500nm, and the spacing between adjacent metal blocks is 1~3μm. When the first field plate is a gate field plate, the minimum distance between the first metal block and the P-type semiconductor layer along the first direction is 0. When the first field plate is a source field plate or a floating field plate, the minimum distance between the first metal block and the P-type semiconductor layer along the first direction is 500~1000nm. The thickness of the second metal block is 50~200nm. The second metal block is partially overlapped with the first metal block. The overlap width between each second metal block and the first metal block below it is 250~1000nm, the non-overlap width is 500~1500nm, and the distance between each second metal block and the other first metal block below it is 500~1500nm. The thickness of the third metal block is 50~200nm. The third metal block is partially overlapped with the first metal block and the second metal block. The overlap width between each third metal block and the second metal block below it and the first metal block below it is 250~1000nm. When the metal blocks are arranged in an array perpendicular to the first direction: The thickness of the first metal block is 70~400nm, the length is 3~15μm, the width is 500~1500nm, and the spacing between adjacent metal blocks is 1~3μm. When the first field plate is a gate field plate, the minimum distance between the first metal block and the P-type semiconductor layer along the first direction is 0. When the first field plate is a source field plate or a floating field plate, the minimum distance between the first metal block and the P-type semiconductor layer along the first direction is 500~1000nm. The second metal block has a thickness of 50~200nm and a length of 3~15μm. The second metal block partially overlaps with the first metal block. The overlap width between each second metal block and the first metal block below it is 250~1000nm, the non-overlap width is 500~1500nm, and the distance between each second metal block and the other first metal block below it is 500~1500nm. The thickness of the third metal block is 50~200nm and the length is 3~15μm. The third metal block is partially overlapped with the first metal block and the second metal block. The overlap width between each third metal block and the second metal block below it and the first metal block below it is 250~1000nm.

2. The HEMT device according to claim 1, characterized in that, The source and / or drain electrodes are made of metals and / or metal compounds, wherein the metals include one or more combinations of gold, platinum, nickel, titanium, aluminum, palladium, tantalum, tungsten, and molybdenum, and the metal compounds include one or more combinations of titanium nitride and tantalum nitride; and / or, The field plate is made of metal and / or metal compounds, including one or more of gold, platinum, nickel, titanium, palladium, tantalum and tungsten, and metal compounds including one or more of titanium nitride and tantalum nitride.

3. The HEMT device according to claim 1, characterized in that, The channel layer is a gallium nitride channel layer with a thickness of 50 nm to 2 μm; and / or, The barrier layer is an aluminum gallium nitride barrier layer with a thickness of 10nm~50nm; and / or, The P-type semiconductor layer is a P-type gallium nitride layer with a thickness of 70nm~120nm; and / or, A buffer layer, which is a nitride buffer layer, is provided between the substrate and the channel layer.

4. A method for fabricating a HEMT device with an array field plate as described in any one of claims 1 to 3, characterized in that, The preparation method includes: Provide a substrate; A channel layer and a barrier layer are epitaxially grown on a substrate to form a heterojunction; A passivation layer structure is epitaxially grown on the heterojunction, and a gate region, a source region, and a drain region are formed along a first direction in the heterojunction and the passivation layer structure, with the gate region located between the source region and the drain region. The gate, source, and drain are formed in the gate region, source region, and drain region, respectively, with the gate located between the source and drain. Several field plates are formed inside or above the passivation layer structure between the gate and the drain, the field plates comprising several metal blocks arranged in an array along or perpendicular to the first direction.

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