Thin film transistor, gate driver including the same, and display device including the gate driver

Abstract

A thin-film transistor (TFT) including an oxide semiconductor layer, applicable to high-resolution flat panel display devices requiring high-speed driving, is disclosed, as well as a gate driver including the TFT and a display device including the gate driver. The TFT includes a first oxide semiconductor layer composed of indium gallium zinc tin oxide (IGZTO) and a second oxide semiconductor layer having indium gallium zinc oxide (IGZO). The gallium (Ga) to indium (In) content ratio (Ga / In) of the second oxide semiconductor layer is higher than that of the first oxide semiconductor layer (Ga / In), and the zinc (Zn) to In content ratio (Zn / In) of the second oxide semiconductor layer is higher than that of the first oxide semiconductor layer (Zn / In).

Description

[0001] Cross-references to related applications

[0002] This application is a divisional application of the invention patent application with application number 201810509886.0.

[0003] This application claims the benefit of Korean Patent Application No. 10-2017-0068037, filed on May 31, 2017, and Korean Patent Application No. 10-2017-0169420, filed on December 11, 2017, which are incorporated herein by reference as if fully set forth herein. Technical Field

[0004] The present invention relates to a thin-film transistor (TFT), a gate driver including the TFT, and a display device including the gate driver. Background Technology

[0005] With the development of the information-oriented society, the demand for display devices for displaying images is gradually increasing. Therefore, various display devices are currently in use, such as liquid crystal display (LCD) devices, plasma display panel (PDP) devices, and light-emitting display devices. Examples of light-emitting display devices include organic light-emitting display devices that use organic light-emitting diodes (OLEDs) as light-emitting elements and light-emitting diode display devices that use miniature light-emitting diodes as light-emitting elements.

[0006] Each flat panel display device includes a display panel, a gate driver, a data driver, and a timing controller. The display panel includes multiple data lines, multiple gate lines, and multiple pixels disposed in multiple regions defined by the intersections of the data lines and the gate lines. When a gate signal is provided to the gate lines using a TFT as a switching element, each pixel is provided with a data voltage via the data lines. Each pixel emits light with a specific brightness using the data voltage.

[0007] Recently, a flat panel display device for displaying images at a high resolution corresponding to Ultra High Definition (UHD) has been released, and a flat panel display device for displaying images at a high resolution corresponding to 8K UHD is under development. UHD refers to a resolution of 3840×2160, and 8K UHD refers to a resolution of 7680×4320.

[0008] Flat panel displays with high resolutions such as UHD or 8K UHD require high-speed driving, thus shortening the scan time per line. The scan time per line is the time required to supply a gate signal to one gate line. The scan time per line corresponds to the data voltage supply cycle for each pixel. Therefore, when the scan time per line is shortened, each pixel is not charged with the ideal data voltage, leading to image quality degradation. To solve this problem, TFTs with high electron mobility should be used as switching elements.

[0009] When using TFTs with oxide semiconductor layers as switching elements, the manufacturing cost is reduced and the electron mobility is lower compared to using TFTs with polysilicon semiconductor layers. Therefore, high-resolution flat panel display devices requiring high-speed driving need TFTs with oxide semiconductor layers.

[0010] However, due to the high pixel per inch (PPI) required for high-resolution flat panel display devices demanding high-speed driving, the oxide semiconductor layer of the TFT must be implemented as a short channel and achieve high electron mobility. In related technologies, TFTs based on semiconductor layers including indium gallium zinc oxide (IGZO) are used, making it difficult to ensure high electron mobility. Furthermore, when using a semiconductor layer including IGZO as a single layer, the threshold voltage shifts rapidly due to variations in channel length. For this reason, it is difficult to achieve a short channel while maintaining an ideal threshold voltage value.

[0011] Figure 1 It is a graph showing the relationship between drain-source current and gate-source voltage in a TFT including an IGZO-type semiconductor layer as the channel length changes.

[0012] Figure 1 Experimental results are shown, obtained by measuring drain-source current against gate-source voltage, when the channel length of a TFT including a single-layer IGZO-type semiconductor layer is changed from 4 μm to 10 μm. Figure 1 As shown, when the channel length is shortened to 4 μm or less, the threshold voltage deviates negatively by approximately -5V compared to when the channel length is 5 μm to 10 μm. Therefore, when the channel length is shortened to 4 μm or less, it is difficult to ensure ideal drive characteristics.

[0013] When the power, pressure, and temperature of the manufacturing equipment are adjusted to a specific range during the deposition of a single-layer IGZO-type oxide semiconductor layer, such as Figure 1 The problem of negative threshold voltage offset in short channels, as shown, is solved. However, in this case, the degrees of freedom to consider other factors such as film uniformity are greatly reduced due to the conditions of the manufacturing equipment, such as power, pressure, and temperature.

[0014] Therefore, high-resolution flat panel display devices that require high-speed driving need a TFT that includes an oxide semiconductor layer, which limits the freedom of manufacturing equipment. Summary of the Invention

[0015] Therefore, the present invention aims to provide a TFT, a gate driver including the TFT, and a display device including the gate driver, which substantially overcomes one or more problems caused by the limitations and disadvantages of related technologies.

[0016] One aspect of the present invention aims to provide a TFT including an oxide semiconductor layer, a gate driver including the TFT, and a display device including the gate driver, which can be applied to a high-resolution flat panel display device requiring high-speed driving.

[0017] Other advantages and features of the invention will be set forth in part in the description which follows, some of which will become apparent to those skilled in the art upon review of the following, or will be learned by practice of the invention. These objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the specification, claims, and drawings.

[0018] To achieve these and other advantages and in accordance with the purposes of the invention, as specifically and generally described herein, a TFT is provided, comprising: a first oxide semiconductor layer containing indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O) and a second oxide semiconductor layer containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O). The gallium (Ga) to indium (In) content ratio (Ga / In) of the second oxide semiconductor layer is higher than the Ga to In content ratio (Ga / In) of the first oxide semiconductor layer, and the zinc (Zn) to In content ratio (Zn / In) of the second oxide semiconductor layer is higher than the Zn to In content ratio (Zn / In) of the first oxide semiconductor layer.

[0019] In another aspect of the invention, a gate driver is provided, the gate driver comprising a plurality of stages for outputting gate signals. Each of the plurality of stages comprises a TFT according to an embodiment of the invention.

[0020] In another aspect of the invention, a display device is provided including a display panel, the display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels respectively disposed in a plurality of regions defined by the intersection of the plurality of data lines and the plurality of gate lines. Each of the plurality of pixels includes the TFT.

[0021] It should be understood that the foregoing general description and the following detailed description of the invention are illustrative and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0022] The accompanying drawings, which provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

[0023] Figure 1 It is a graph showing the relationship between drain-source current and gate-source voltage in a TFT including an IGZO semiconductor layer as the channel length changes;

[0024] Figure 2 This is a perspective view illustrating a display device according to an embodiment of the present invention;

[0025] Figure 3 It is a diagram Figure 2 The diagram shows a plan view of the first substrate, gate driver, source driver integrated circuit (IC), flexible film, circuit board, and timing controller.

[0026] Figure 4 It is a diagram Figure 3 The circuit diagram of the pixels;

[0027] Figure 5 It is a diagram Figure 3 A circuit diagram of a portion of the gate driver;

[0028] Figure 6 This is a plan view illustrating a TFT according to an embodiment of the present invention;

[0029] Figure 7 It is a diagram along Figure 6 A cross-sectional view of an example intercepted by line I-I';

[0030] Figure 8 This is an example diagram illustrating the oxide semiconductor layer of a TFT according to an embodiment of the present invention;

[0031] Figure 9 It is a graph showing the relationship between drain-source current and gate-source voltage in a TFT according to an embodiment of the present invention, when the channel length changes;

[0032] Figure 10 It is a graph showing the change in etching rate relative to the changes in gallium (Ga) content and zinc (Zn) content of the second oxide semiconductor layer;

[0033] Figure 11A and 11B It is a diagram Figure 7An enlarged cross-sectional view of the implementation method in region A;

[0034] Figure 12 It is a graph showing the etching rate of each of the first and second oxide semiconductor layers relative to the temperature of the first substrate during the process of depositing the first and second oxide semiconductor layers.

[0035] Figure 13 The image shows a cross-sectional surface of the first and second oxide semiconductor layers relative to the temperature of the first substrate during the process of depositing the first and second oxide semiconductor layers.

[0036] Figures 14A to 14C The image shows a material property analysis of the second oxide semiconductor layer relative to changes in Zn content;

[0037] Figure 15 This indicates that when the thickness of the first oxide semiconductor layer is A graph showing the PBTS threshold voltage offset and NBTIS threshold voltage offset of the TFT relative to the thickness variation of the second oxide semiconductor layer.

[0038] Figure 16 This is a flowchart illustrating a method for manufacturing a TFT according to an embodiment of the present invention;

[0039] Figures 17A to 17E This is a cross-sectional view used to describe a method for manufacturing a TFT according to an embodiment of the present invention;

[0040] Figure 18 This is a plan view illustrating a TFT according to another embodiment of the present invention;

[0041] Figure 19 It is a diagram along Figure 18 A cross-sectional view of an example taken from line II-II';

[0042] Figure 20 This is a plan view illustrating a TFT according to another embodiment of the present invention;

[0043] Figure 21 It is a diagram along Figure 20 A cross-sectional view of an example taken from line III-III';

[0044] Figure 22 It is a diagram along Figure 20 A cross-sectional view of another example taken from line III-III'. Detailed Implementation

[0045] Reference will now be made in detail to exemplary embodiments of the invention, some examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to denote the same or similar parts.

[0046] In this application, similar numbers denote similar elements. In the following description, detailed descriptions of known functions or constructions will be omitted where such description would unnecessarily obscure the focus of the invention. The names of each element used herein have been chosen for ease of description and may differ from the names of actual products.

[0047] The advantages and features of the invention, as well as its implementation, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments listed herein. Rather, these embodiments are provided to make this disclosure comprehensive and complete, and to fully convey the scope of the invention to those skilled in the art. Furthermore, the invention is defined only by the scope of the claims.

[0048] The shapes, sizes, proportions, angles, and quantities disclosed in the accompanying drawings for the purpose of describing embodiments of the invention are merely examples, and therefore the invention is not limited to the details shown. Similar reference numerals refer to similar elements throughout. In the following description, detailed descriptions of related known functions or constructions will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention.

[0049] When interpreting a factor, even if not explicitly stated, the factor should be interpreted as including a range of error.

[0050] Those skilled in the art will fully understand that the features of the various embodiments of the present invention can be partially or entirely combined or integrated with each other, and can be technically interoperable and driven in various ways. The embodiments of the present invention can be implemented independently of each other, or implemented jointly in an interdependent relationship.

[0051] Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0052] The following describes examples of light-emitting display devices according to embodiments of the present invention, but embodiments of the present invention are not limited thereto. The display device according to embodiments of the present invention can be implemented as one of a liquid crystal display (LCD), a light-emitting display device, a field emission display device, and an electrophoretic display device. Examples of light-emitting display devices include organic light-emitting display devices using organic light-emitting diodes (OLEDs) as light-emitting elements and light-emitting diode display devices using micro-light-emitting diodes as light-emitting elements.

[0053] Figure 2 This is a perspective view illustrating a display device according to an embodiment of the present invention. Figure 3 It is a diagram Figure 2 The diagram shows a plan view of the first substrate, gate driver, source driver integrated circuit (IC), flexible film, circuit board, and timing controller.

[0054] Reference Figure 2 and 3 An organic light-emitting display device 1000 according to an embodiment of the present invention may include a display panel 1100, a gate driver 1200, a data driver, a flexible film 1400, a circuit board 1500, and a timing controller 1600.

[0055] The display panel 1100 may include a first substrate 1110 and a second substrate 1120. The first substrate 1110 and the second substrate 1120 may each be plastic, glass, or the like. For example, when the first substrate 1110 is plastic, it may be formed of polyimide, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), and / or the like. When the first substrate 1110 is formed of plastic, the organic light-emitting display device 1000 can be implemented as a flexible display device capable of bending or flexing. The second substrate 1120 may be one of glass, a plastic film, or an encapsulation film.

[0056] The first substrate 1110 may be a TFT substrate on which multiple TFTs are disposed. Multiple gate lines, multiple data lines, and multiple pixels P may be disposed on a surface of the first substrate 1110 facing the second substrate 1120. Pixels P may be respectively disposed in multiple regions defined by the intersections of the gate lines and data lines. Figure 3 As shown, the display panel 1100 can be divided into a display area DA where pixels P are set to display images and a non-display area NDA where no images are displayed. Gate lines, data lines, and pixels P can be disposed in the display area DA. Gate driver 1200, multiple pads, and multiple connections connecting the data lines to the pads can be disposed in the non-display area NDA.

[0057] Each pixel P may include at least one transistor as a switching element, which is turned on by a gate signal of a corresponding gate line and transmits the data voltage of the corresponding data line to the element of the corresponding pixel P. The transistor may be a TFT.

[0058] For example, such as Figure 4 As shown, each pixel P may include an organic light-emitting diode (OLED), a driving transistor (DT), multiple switching transistors (ST1 and ST2), and a capacitor (Cst). The multiple switching transistors ST1 and ST2 may include a first switching transistor ST1 and a second switching transistor ST2. Figure 4For ease of description, only the pixel P connected to the j-th (where j is an integer equal to or greater than 2) data line Dj, the q-th (where q is an integer equal to or greater than 2) reference voltage line Rq, the k-th (where k is an integer equal to or greater than 2) gate line Gk, and the k-th initialization line SEk is shown.

[0059] An organic light-emitting diode (OLED) emits light using the current supplied by a driving transistor (DT). The anode electrode of the OLED can be connected to the source electrode of the driving transistor (DT), and the cathode electrode can be connected to a first power supply voltage line (VSSL) that provides a first power supply voltage. The first power supply voltage line (VSSL) can be a low-level voltage line that provides a low-level power supply voltage.

[0060] Organic light-emitting diodes (OLEDs) may include an anode electrode, a hole transport layer, an organic light-emitting layer, an electron transport layer, and a cathode electrode. In an OLED, when a voltage is applied to the anode and cathode electrodes, holes and electrons move through the hole transport layer and electron transport layer, respectively, to the organic light-emitting layer and can combine in the organic light-emitting layer to emit light.

[0061] A driving transistor DT can be disposed between an organic light-emitting diode (OLED) and a second power supply voltage line VDDL that provides a second power supply voltage. The driving transistor DT can control the current flowing from the second power supply voltage line VDDL to the OLED based on the voltage difference between its source and gate electrodes. The gate electrode of the driving transistor DT can be connected to the first electrode of the first switching transistor ST1, the drain electrode can be connected to the second power supply voltage line VDDL, and the source electrode can be connected to the anode electrode of the OLED. The second power supply voltage line VDDL can be a high-level voltage line that provides a high-level power supply voltage.

[0062] The first switching transistor ST1 can be turned on by the k-th gate signal of the k-th gate line Gk and can provide the data voltage of the j-th data line Dj to the gate electrode of the driving transistor DT. The gate electrode of the first switching transistor ST1 can be connected to the k-th gate line Gk, the source electrode can be connected to the gate electrode of the driving transistor DT, and the drain electrode can be connected to the j-th data line Dj.

[0063] The second switching transistor ST2 can be turned on by the k-th initialization signal on the k-th initialization line SEk and can connect the q-th reference voltage line Rq to the source electrode of the driving transistor DT. The gate electrode of the second switching transistor ST2 can be connected to the k-th initialization line SEk, the first electrode can be connected to the q-th reference voltage line Rq, and the second electrode can be connected to the source electrode of the driving transistor DT.

[0064] A capacitor Cst can be placed between the gate electrode and the source electrode of the driving transistor DT. The capacitor Cst can store the voltage difference between the gate voltage and the source voltage of the driving transistor DT.

[0065] One electrode of capacitor Cst can be connected to the gate electrode of driving transistor DT and the source electrode of first switching transistor ST1, and the other electrode can be connected to the source electrode of driving transistor DT, the drain electrode of second switching transistor ST2 and the anode electrode of organic light-emitting diode OLED.

[0066] exist Figure 4 In this configuration, the driving transistor DT, the first switching transistor ST1, and the second switching transistor ST2 of each pixel P can each be a TFT. Furthermore, in... Figure 4 The diagram shows that the driving transistor DT, the first switching transistor ST1, and the second switching transistor ST2 of each pixel P are each implemented as an N-type semiconductor transistor with N-type semiconductor characteristics, but the embodiments of the present invention are not limited thereto. In other embodiments, the driving transistor DT, the first switching transistor ST1, and the second switching transistor ST2 of each pixel P are each implemented as a P-type semiconductor transistor with P-type semiconductor characteristics.

[0067] The gate driver 1200 provides a gate signal to the gate line according to a gate control signal input from the timing controller 1600. The gate driver 1200 may be disposed in a non-display area NDA outside one or both sides of the display area DA of the display panel 1100, in the form of an in-panel gate driver (GIP) type. In this case, the gate driver 1200 may include a plurality of transistors that output gate signals to the gate line according to the gate control signal. Here, each of the plurality of transistors may be a TFT.

[0068] For example, such as Figure 5 As shown, the gate driver 1200 may include multiple stages STT1 connected subordinate to each other, and each stage STT1 may output gate signals to the gate line in sequence.

[0069] like Figure 5 As shown, each stage STT1 may include a pull-up node NQ; a pull-down node NQB; a pull-up transistor TU, which is turned on when the pull-up node NQ is charged with a high gate voltage; a pull-down transistor TD, which is turned on when the pull-down node NQB is charged with a high gate voltage; and a node controller NC, which is used to control the charging or discharging of the pull-up node NQ and the pull-down node NQB.

[0070] The node controller NC can be connected to a start signal line that receives the start signal or carry signal from the front-end stage, and a clock line that receives one of the gate clock signals. The node controller NC controls the charging or discharging of the pull-up node NQ and the pull-down node NQB based on the start signal or carry signal from the front-end stage input via the start signal line and the gate clock signal input via the clock line. To stabilize the output of the control stage STT1, when the pull-up node NQ is charged to a high gate voltage, the node controller NC can discharge the pull-down node NQB to a low gate voltage, and when the pull-down node NQB is charged to a high gate voltage, the node controller NC can discharge the pull-up node NQ to a low gate voltage. For this purpose, the node controller NC may include multiple transistors.

[0071] When stage STT1 is pulled up, that is, when the pull-up node NQ is charged to a high gate voltage, the pull-up transistor TU turns on and outputs the gate clock signal of the clock line CL to the output terminal OT. When stage STT1 is pulled down, that is, when the pull-down node NQB is charged to a high gate voltage, the pull-down transistor TD turns on and discharges the output terminal OT to the gate low voltage of the gate low voltage terminal VGLT.

[0072] exist Figure 5 In the gate driver 1200, the pull-up transistor TU, pull-down transistor TD, and multiple transistors of each stage STT1 can each be implemented as a TFT. Furthermore, in Figure 5 The diagram shows that the pull-up transistor TU, pull-down transistor TD, and multiple transistors of the node controller NC in each stage STT1 of the gate driver 1200 are each implemented as N-type semiconductor transistors with N-type semiconductor characteristics, but embodiments of the present invention are not limited thereto. In other embodiments, the pull-up transistor TU, pull-down transistor TD, and multiple transistors of the node controller NC in each stage STT1 of the gate driver 1200 are each implemented as P-type semiconductor transistors with P-type semiconductor characteristics.

[0073] The gate driver 1200 can be implemented as a driver chip similar to an integrated circuit (IC). In this case, the gate driver 1200 can be mounted on a flexible gate film in a chip-on-film (COF) manner, and the flexible gate film can be attached to the first substrate 1110 of the display panel 1100.

[0074] The data driver may include at least one source driver IC 1300. The source driver IC 1300 may receive digital video data and source control signals from the timing controller 1600. The source driver IC 1300 may convert the digital video data into analog data voltages according to the source control signals and may provide the data voltages to the data lines respectively.

[0075] In cases where the source driver IC 1300 is implemented as a driver chip similar to an IC, the source driver IC 1300 can be as follows: Figure 2 and 3 The image shows a flexible film 1400 mounted on it. Multiple lines connecting the pads to the source driver IC 1300 and multiple lines connecting the pads to the circuit board 1500 can be disposed on the flexible film 1400. By using an anisotropic conductive film, the flexible film 1400 can be attached to pads, such as data pads, disposed in the non-display area NDA of the display panel 110, thus allowing the pads to be connected to lines on the flexible film 1400. Alternatively, the source driver IC 1300 can be directly attached to the pads of the first substrate 1110 of the display panel 1100 in a chip-on-glass (COG) or chip-on-plastic (COP) manner.

[0076] Multiple flexible films 1400 can be configured, and circuit boards 1500 can be attached to the flexible films 1400. Multiple circuits, each implemented as a driver chip, can be mounted on the circuit boards 1500. For example, a timing controller 1600 can be mounted on the circuit boards 1500. The circuit boards 1500 can be printed circuit boards (PCBs) or flexible PCBs (FPCBs).

[0077] The timing controller 1600 can receive digital video data and timing signals from an external system via a cable connected to the circuit board 1500. Based on the timing signals, the timing controller 1600 can generate gate control signals for controlling the operating timing of the gate driver 1200, and source control signals for controlling multiple source driver ICs 1300. The timing controller 1600 can provide the gate control signals to the gate driver 1200 and the source control signals to the source driver ICs 1300.

[0078] As described above, in the display device according to an embodiment of the present invention, each pixel P may include at least one TFT as a switching element. In the case where the gate driver 1200 is implemented as a GIP type, the gate driver 1200 may include a plurality of transistors for sequentially outputting gate signals to the gate lines. Therefore, in display devices requiring high-speed driving due to high resolution, the electron mobility of each of the plurality of transistors included in the gate driver 1200 should be increased so that the gate driver 1200 stably outputs gate signals.

[0079] The following will describe in detail a TFT including an oxide semiconductor layer according to an embodiment of the present invention, which can be applied to the transistors of the gate driver 1200 and the transistors of the pixel P of a display device that requires high-speed driving due to high resolution.

[0080] Figure 6 This is a plan view illustrating a TFT 100 according to an embodiment of the present invention. Figure 7 It is a diagram along Figure 6 A cross-sectional view of an example taken by line I-I'.

[0081] exist Figure 6 and 7 The image shows an example of a TFT according to an embodiment of the present invention implemented using a back channel etching (BCE) process with an anti-interlaced structure. The anti-interlaced structure may have a bottom gate structure with the gate electrode disposed below the active layer.

[0082] Reference Figure 6 and 7 According to an embodiment of the present invention, the TFT 100 may include a gate electrode 110, an oxide semiconductor layer 130, a source electrode 140, and a drain electrode 150.

[0083] TFT 100 may be disposed on first substrate 1110. First substrate 1110 may be formed of plastic, glass and / or the like.

[0084] A buffer layer 300 may be disposed on the first substrate 1110 to protect the TFT 100 from moisture that permeates through the first substrate 1110. The buffer layer 300 may comprise multiple inorganic layers stacked alternately. For example, the buffer layer 300 may be formed by a multilayer of one or more inorganic layers of silicon oxide (SiOx), silicon nitride (SiNx), and SiON stacked alternately. The buffer layer 300 may be omitted.

[0085] A gate electrode 110 may be disposed on the buffer layer 300. The gate electrode 110 may be configured to have a region wider than the oxide semiconductor layer 130 to block light incident from the first substrate 1110 onto the oxide semiconductor layer 130, thus the gate electrode 110 may cover the oxide semiconductor layer 130. Therefore, the oxide semiconductor layer 130 may be protected from light incident from the first substrate 1110. The gate electrode 110 may be formed of a single layer or multiple layers of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0086] A gate insulating layer 120 may be disposed on the gate electrode 110. The gate insulating layer 120 may be formed of an inorganic layer, such as SiOx, SiNx, or a multilayer thereof.

[0087] The oxide semiconductor layer 130 may be disposed on the gate insulating layer 120. The oxide semiconductor layer 130 may be disposed overlapping the gate electrode 110, and the gate insulating layer 120 is provided between the oxide semiconductor layer 130 and the gate electrode 110.

[0088] The oxide semiconductor layer 130 may include a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132. The conductivity of the second oxide semiconductor layer 132 may be lower than that of the first oxide semiconductor layer 131, and its bandgap may be larger than that of the first oxide semiconductor layer 131. The first oxide semiconductor layer 131 may be the main channel layer for electron movement and is therefore disposed close to the gate electrode 110. Thus, the first oxide semiconductor layer 131 can be defined as a layer disposed closer to the gate electrode 110 than the second oxide semiconductor layer 132, and the second oxide semiconductor layer 132 can be defined as a layer disposed further away from the gate electrode 110 than the first oxide semiconductor layer 131. For example, in... Figure 6 and 7 In the case where the TFT 100 shown is implemented as an anti-interlaced structure, since the gate electrode 110 is disposed below the oxide semiconductor layer 130, the first oxide semiconductor layer 131 can be disposed on the gate insulating layer 120, and the second oxide semiconductor layer 132 can be disposed on the first oxide semiconductor layer 131.

[0089] The source electrode 140 can directly contact one side of the second oxide semiconductor layer 132 and one side of the first oxide semiconductor layer 131, which serves as the main channel layer. Specifically, the source electrode 140 can directly contact one side surface of the first oxide semiconductor layer 131, and a portion of the upper surface and one side surface of the second oxide semiconductor layer 132. Furthermore, the drain electrode 150 can directly contact the other side of the first oxide semiconductor layer 131 and the other side of the second oxide semiconductor layer 132. Specifically, the drain electrode 150 can directly contact the other side surface of the first oxide semiconductor layer 131, and a portion of the upper surface and another side surface of the second oxide semiconductor layer 132. The source electrode 140 and the drain electrode 150 can each be formed from a single layer or multiple layers of one or an alloy of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu.

[0090] Passivation layer 160 may be disposed on oxide semiconductor layer 130, source electrode 140 and drain electrode 150. Passivation layer 160 may be formed of inorganic layer, such as SiOx, SiNx or multilayer thereof.

[0091] The first oxide semiconductor layer 131 can be formed of indium gallium zinc tin oxide (IGZTO) instead of indium gallium zinc oxide (IGZO) to increase electron mobility. More specifically, the electron mobility of the first oxide semiconductor layer 131 can be adjusted to 15 cm⁻¹. 2To satisfy the Positive Bias Temperature Stress (PBTS) and Negative Bias Temperature Illumination Stress (NBTIS) characteristics, the indium-gallium-zinc-tin (IGZT) content must meet the following conditions: In the first oxide semiconductor layer 131, the indium (In) to tin (Sn) ratio can be 2.5 ≤ In / Sn ≤ 5, the gallium (Ga) to Sn ratio can be 1 ≤ Ga / Sn ≤ 2, and the zinc (Zn) to Sn ratio can be 2.5 ≤ Zn / Sn ≤ 5. Meeting the PBTS and NBTIS characteristics indicates a threshold voltage offset value in the range of -5V to 2V. Here, the content of each element can be expressed as an atomic percentage.

[0092] However, when the oxide semiconductor layer 130 is formed from a monolayer based on IGZTO, the threshold voltage can shift due to variations in channel length. For this reason, it is difficult to achieve a short channel while maintaining the ideal threshold voltage value. In other words, when the oxide semiconductor layer 130 is formed from a monolayer based on IGZTO, it is difficult to achieve a short channel and ensure ideal drive characteristics due to the effect of channel length variation (CLV). CLV can represent the degree of threshold voltage shift based on changes in channel length.

[0093] Therefore, to prevent threshold voltage shift in the case where the oxide semiconductor layer 130 is implemented as a short channel, the oxide semiconductor layer 130 may further include a second oxide semiconductor layer 132, which includes indium gallium zinc oxide (IGZO). For example, the second oxide semiconductor layer 132 may be composed of IGZO or IGZTO. In the case where the second oxide semiconductor layer 132 is formed of IGZTO, the composition ratio of IGZT in the second oxide semiconductor layer 132 may be different from the composition ratio of IGZT in the first oxide semiconductor layer 131.

[0094] In the case where the oxide semiconductor layer 130 includes a first oxide semiconductor layer 131 having IGZTO and a second oxide semiconductor layer 132 having IGZO or having IGZTO with a composition ratio different from that of the first oxide semiconductor layer 131, the oxide semiconductor layer 130 may have the following characteristics: Figure 8The heterojunction structure shown is illustrated. Here, due to the Fermi level difference between the thin layers, a depletion region caused by a built-in potential is formed in the junction portion between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. This built-in potential causes band bending in the junction portion. Because of the included depletion region, the oxide semiconductor layer 130 can control the total charge density, thereby preventing the threshold voltage from shifting based on the channel length. That is, in the embodiment of the invention, due to the provision of the second oxide semiconductor layer 132, the increase in charge density is effectively controlled in the oxide semiconductor layer 130 formed of high-mobility thin layers, thereby preventing the threshold voltage from shifting based on changes in the channel length of the oxide semiconductor layer 130. As a result, in the embodiment of the invention, electron mobility is increased, and the device characteristics of the TFT are ensured.

[0095] Furthermore, the bonding force between Sn and oxygen is stronger than that between In and oxygen. Therefore, in the case where the second oxide semiconductor layer 132 is formed of IGZTO, the chemical resistance is increased and the number of oxygen vacancies is reduced compared to the case where the second oxide semiconductor layer 132 is formed of IGZO. Thus, the PBTS and NBTIS characteristics of the TFT including the second oxide semiconductor layer 132 formed of IGZTO are improved, and the reliability of the TFT is enhanced.

[0096] Figure 9 It is a graph showing the relationship between drain-source current and gate-source voltage in a TFT according to an embodiment of the present invention, when the channel length changes. Figure 9 The results shown are experimental findings obtained by measuring the drain-source current against the gate-source voltage in a TFT comprising a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132, while changing the channel length from 4 μm to 10 μm. For example, these results can be obtained by conducting experiments under the following conditions: a drain-source voltage Vds of 10 V, an IGZT composition ratio of 4:1:4:1 in the first oxide semiconductor layer 131, and an IGZT composition ratio of 4:12:16:1 in the second oxide semiconductor layer 132. Figure 9 The experimental results. That is to say, in Figure 9 The image shows an example of a second oxide semiconductor layer 132 formed by IGZTO.

[0097] Reference Figure 9 It can be seen that in the TFT according to the embodiment of the present invention, the threshold voltage hardly shifts with respect to changes in channel length. That is, in the TFT according to the embodiment of the present invention, a short channel is achieved and an ideal threshold voltage is maintained, thereby ensuring the ideal device characteristics of the TFT.

[0098] In addition, such as Figure 9 As shown, when the channel of the oxide semiconductor layer 130 has a width of 4 μm and a length of 4 μm, the electron mobility can be approximately 23 cm⁻¹. 2 / V·s. And as Figure 1 As shown, for the same channel width and channel length, the electron mobility of a TFT including an IGZO-type semiconductor layer is approximately 10 cm⁻¹. 2 Compared to the case of / V·s, the electron mobility has a higher value. As described above, in the TFT according to an embodiment of the present invention, even when the oxide semiconductor layer is implemented as a short channel, the threshold voltage does not shift, and the electron mobility is greatly improved.

[0099] Furthermore, the second oxide semiconductor layer 132 may not serve as a channel, but rather may cover and protect the first oxide semiconductor layer 131 so that the first oxide semiconductor layer 131 stably functions as a channel. For this purpose, the Ga to Sn content ratio (Ga / Sn) of the second oxide semiconductor layer 132 may be higher than that of the first oxide semiconductor layer 131. Alternatively, the second oxide semiconductor layer 132 may be formed of IGZO without Sn. In this case, the second oxide semiconductor layer 132 may have lower conductivity than the first oxide semiconductor layer 131 and a larger band gap than the first oxide semiconductor layer 131.

[0100] Figure 10 It is a graph showing the change in etch rate relative to the changes in Ga content and Zn content of the second oxide semiconductor layer.

[0101] Figure 10 The results are shown by measuring the etching rate under the same conditions while the composition ratio of the IGZT in the second oxide semiconductor layer 132 is successively changed to 4:1:4:1, 4:4:4:1, 4:8:4:1, 4:12:4:1, 4:8:8:1, 4:8:12:1, and 4:12:16:1. Figure 10 As shown, when only the Ga content in the second oxide semiconductor layer 132 increases, the etching rate of the second oxide semiconductor layer 132 decreases. For this reason, the time spent etching the second oxide semiconductor layer 132 increases.

[0102] like Figure 10As shown, the etching rate of the second oxide semiconductor layer 132 increases as the Zn content in the second oxide semiconductor layer 132 increases. Therefore, to prevent the etching time of the second oxide semiconductor layer 132 from increasing, the Zn content should be increased along with the Ga content. Thus, the Ga to In content ratio (Ga / In) of the second oxide semiconductor layer 132 can be higher than that of the first oxide semiconductor layer 131. Furthermore, the Zn to In content ratio (Zn / In) of the second oxide semiconductor layer 132 can be higher than that of the first oxide semiconductor layer 131.

[0103] To examine device characteristics for variations in the Ga and Zn content of each of the second oxide semiconductor layer 132, the IGZT composition ratio of the first oxide semiconductor layer 131 was set to 4:1:4:1, as shown in Table 1. While varying the Ga and Zn content of each of the second oxide semiconductor layer 132, the threshold voltage (CLV) and electron mobility were measured. In Table 1, CLV represents the difference between the threshold voltage with a channel length of 4 μm and the threshold voltage with a channel length of 12 μm. A smaller CLV indicates a smaller change in threshold voltage relative to changes in channel length.

[0104] [Table 1]

[0105]

[0106] Referring to Table 1, the CLV value decreases as the Ga content of the second oxide semiconductor layer 132 increases. Furthermore, even when the Ga and Zn contents are increased to adjust the etching rate, the CLV value still decreases, ensuring a 20cm etching rate. 2 Electron mobility per V·s.

[0107] However, as the Zn content in the second oxide semiconductor layer 132 continues to increase, the PBTS and NBTIS characteristics of the TFT 100 deteriorate. This deterioration should be considered when designing the Zn content. The conditions for satisfying the PBTS and NBTIS characteristics represent the case where the threshold voltage offset is in the range of -5V to 2V. This will be referred to below. Figures 14A to 14C Detailed description.

[0108] As described above, since the second oxide semiconductor layer 132 is formed of IGZO or IGZTO with a different composition ratio than the first oxide semiconductor layer 131, even when the oxide semiconductor layer 130 is implemented as a short channel, threshold voltage shift is prevented. The second oxide semiconductor layer 132 covers and protects the first oxide semiconductor layer 131 so that the first oxide semiconductor layer 131 stably acts as a channel, and the etching rate of the second oxide semiconductor layer 132 increases. In this case, when the second oxide semiconductor layer 132 is formed of IGZTO, the composition ratio of IGZT in the second oxide semiconductor layer 132 should satisfy the following conditions. In the second oxide semiconductor layer 132, the Sn to In content ratio can be 0.1 ≤ Sn / In ≤ 0.5, the Ga to In content ratio can be 2 ≤ Ga / In ≤ 4, and the Zn to In content ratio can be 2 ≤ Zn / In ≤ 8. Furthermore, when the second oxide semiconductor layer 132 is formed of IGZO, the composition ratio of IGZT in the second oxide semiconductor layer 132 should satisfy the following conditions. In the second oxide semiconductor layer 132, the Ga to In content ratio can be 2 ≤ Ga / In ≤ 4, and the Zn to In content ratio can be 2 ≤ Zn / In ≤ 8. Here, the content of each element can be expressed as an atomic percentage.

[0109] Furthermore, the In to Sn content ratio of the second oxide semiconductor layer 132 can be approximately equal to or higher than the In to Sn content ratio of the first oxide semiconductor layer 131. Furthermore, the Ga to Sn content ratio of the second oxide semiconductor layer 132 can be higher than the Ga to Sn content ratio of the first oxide semiconductor layer 131. Furthermore, the Zn to Sn content ratio of the second oxide semiconductor layer 132 can be higher than the Zn to Sn content ratio of the first oxide semiconductor layer 131.

[0110] Furthermore, the In content of the second oxide semiconductor layer 132 may be lower than the In content of the first oxide semiconductor layer 131. Furthermore, the Ga content of the second oxide semiconductor layer 132 may be higher than the Ga content of the first oxide semiconductor layer 131. Furthermore, the Zn content of the second oxide semiconductor layer 132 may be higher than the Zn content of the first oxide semiconductor layer 131. Furthermore, the Sn content of the second oxide semiconductor layer 132 may be lower than the Sn content of the first oxide semiconductor layer 131.

[0111] Figure 11A and 11B It is a diagram Figure 7 An enlarged cross-sectional view of the implementation method in region A.

[0112] Reference Figure 11A and 11BThe bevel of each side surface of the first oxide semiconductor layer 131 can be formed at an acute angle "θ1". The bevel of each side surface of the second oxide semiconductor layer 132 can be as follows: Figure 11A The second angle "θ2" shown is formed at a right angle, or it can be as follows: Figure 11B The third angle “θ3” shown is formed by an acute angle.

[0113] In detail, the oxide semiconductor layer 130 may include a first oxide semiconductor layer 131 having IGZTO and a second oxide semiconductor layer 132 having IGZO or having IGZTO with a composition ratio different from that of the first oxide semiconductor layer 131. Therefore, as... Figure 12 As shown, in the process of depositing the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, the etching rate of the first oxide semiconductor layer 131 and the etching rate of the second oxide semiconductor layer 132 can vary differently depending on the temperature of the first substrate 1110. Figure 12 In the process of depositing the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, under the conditions that the IGZT composition ratio of the first oxide semiconductor layer 131 is 4:1:4:1 and the IGZT composition ratio of the second oxide semiconductor layer 132 is 4:12:16:1, the etching rate of the first oxide semiconductor layer 131 and the etching rate of the second oxide semiconductor layer 132 are shown for the temperature of the first substrate 1110.

[0114] like Figure 12 As shown, in the process of depositing the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, when the temperature of the first substrate 1110 is below 200°C, the etching rate of the first oxide semiconductor layer 131 is... The etching rate is higher than that of the second oxide semiconductor layer 132. In such cases... Figure 7 In the case where the first oxide semiconductor layer 131 is disposed below the second oxide semiconductor layer 132, when the etching rate of the first oxide semiconductor layer 131 is higher than the etching rate of the second oxide semiconductor layer 132, such as Figure 13As shown at room temperature, 100°C, and 150°C, the bevels of each side surface of the second oxide semiconductor layer 132 can be formed at obtuse angles. That is, each side surface of the second oxide semiconductor layer 132 can be formed as an inverted conical structure. In this case, even when the source electrode 140 and drain electrode 150 are provided to cover the side surfaces of the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, a void can still be formed at the boundary between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. Therefore, the etchant used to etch the source electrode 140 and the drain electrode 150 can penetrate into this void, and the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 can be additionally etched by the etchant that has penetrated into the void. For this reason, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 can be formed with a suboptimal channel length or channel width.

[0115] However, as Figure 12 As shown, in the process of depositing the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, when the temperature of the first substrate 1110 is equal to or higher than 200°C, the etching rate of the first oxide semiconductor layer 131 is... The etching rate is approximately equal to or lower than that of the second oxide semiconductor layer 132. In this case, such as Figure 13 As shown at 200°C and 250°C, the bevels of each side surface of the second oxide semiconductor layer 132 can be formed at acute angles or right angles. That is, each side surface of the second oxide semiconductor layer 132 can be formed into a positive conical structure. In this case, even when the source electrode 140 and the drain electrode 150 are provided to cover the side surfaces of the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, no voids are formed in the boundary between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. Therefore, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 can be prevented from being additionally etched by etchant that has penetrated into the voids. Therefore, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 are formed to have an ideal channel length or channel width.

[0116] Figures 14A to 14C The image shows the material properties analysis of the second oxide semiconductor layer relative to changes in Zn content.

[0117] exist Figures 14A to 14C The image shows an example where the second oxide semiconductor layer 132 is formed of IGZTO. In this case, Figure 14A The image shows the material properties analysis of the second oxide semiconductor layer 132 when the IGZT composition ratio of the second oxide semiconductor layer 132 is 4:12:12:1. Figure 14BThe image shows the material properties analysis of the second oxide semiconductor layer 132 when the IGZT composition ratio of the second oxide semiconductor layer 132 is 4:12:16:1. Figure 14C The image shows the material properties analysis of the second oxide semiconductor layer 132 when the IGZT composition ratio of the second oxide semiconductor layer 132 is 4:12:20:1. Figures 14A to 14C Each material property analysis image shown has a transmission electron microscope fast Fourier transform (TEMFFT) pattern.

[0118] like Figure 14A As shown, when the IGZT composition ratio of the second oxide semiconductor layer 132 is 4:12:12:1, only a crystal axis (dashed line) in one direction is displayed at the material property analysis measurement point of the second oxide semiconductor layer 132. Furthermore, as... Figure 14B As shown, when the IGZT composition ratio of the second oxide semiconductor layer 132 is 4:12:16:1, only a crystal axis (dashed line) in one direction is displayed at the material property analysis measurement point of the second oxide semiconductor layer 132. However, as Figure 14C As shown, when the IGZT composition ratio of the second oxide semiconductor layer 132 is 4:12:20:1, crystal axes (dashed lines) in three directions are displayed at the material property analysis measurement points of the second oxide semiconductor layer 132.

[0119] like Figure 14C As shown, in the case where crystal axes (dashed lines) are displayed in three directions in the second oxide semiconductor layer 132, this indicates that structural phase segregation has occurred at the material property analysis measurement points of the second oxide semiconductor layer 132. That is, this indicates that deformation occurs in the stoichiometry of the second oxide semiconductor layer 132, and in this case, the PBTS and NBTIS characteristics of the TFT 100 may deteriorate. Therefore, the Zn to In content ratio (Zn / In) of the second oxide semiconductor layer 132 may be less than 5.

[0120] In addition, with Figure 14A Similar to the second oxide semiconductor layer 132 shown, the first oxide semiconductor layer 131 can be configured to display a crystal axis in only one direction at the material property analysis measurement point. In this case, the crystal axis displayed in the first oxide semiconductor layer 131 can be parallel to the crystal axis displayed in the second oxide semiconductor layer 132.

[0121] Figure 15 This indicates that when the thickness of the first oxide semiconductor layer is The graph shows the PBTS threshold voltage offset and NBTIS threshold voltage offset of the TFT relative to the thickness variation of the second oxide semiconductor layer.

[0122] Figure 15 This shows that when the thickness of the first oxide semiconductor layer 131 is fixed at... And the thickness of the second oxide semiconductor layer 132 becomes and At that time, the PBTS threshold voltage offset value "PBTSΔVth" and the NBTIS threshold voltage offset value "NBTISΔVth" of TFT 100. Furthermore, Figure 15 The diagram shows the PBTS threshold voltage offset value "PBTSΔVth" and NBTIS threshold voltage offset value "NBTISΔVth" of the TFT 100 when the first oxide semiconductor layer 131 is formed of IGZTO, the second oxide semiconductor layer 132 is formed of IGZTO, the IGZT composition ratio of the first oxide semiconductor layer 131 is 4:1:4:1 and the IGZT composition ratio of the second oxide semiconductor layer 132 is 4:12:16:1.

[0123] Based on the uniformity of thin film deposition and the characteristics of electron mobility, the first oxide semiconductor layer 131 can be formed with... Or a greater thickness, and depending on the process time, the first oxide semiconductor layer 131 can be formed with Or even a thinner thickness. Therefore, based on the threshold voltage offset and the oxygen or hydrogen concentration of the upper or lower insulating layer in contact with the first oxide semiconductor layer 131, the thickness of the first oxide semiconductor layer 131 can be preset to... arrive exist Figure 15 In the first oxide semiconductor layer 131, the thickness is The experiment was conducted under the specified conditions.

[0124] Reference Figure 15 Based on the positive offset of the threshold voltage of the TFT 100 set in the display device, the BTS threshold voltage offset value "BTSΔVth" can be in the range of -5V to 2V. The BTS threshold voltage offset value "BTSΔVth" includes the PBTS threshold voltage offset value "PBTSΔVth" and the NBTIS threshold voltage offset value "NBTISΔVth".

[0125] like Figure 15 As shown, when the thickness of the second oxide semiconductor layer 132 is At that time, the BTS threshold voltage offset value "BTSΔVth" of TFT100 is outside the range of -5V to 2V. Furthermore, when the thickness of the second oxide semiconductor layer 132 is... At that time, the BTS threshold voltage offset value "BTSΔVth" of TFT 100 is outside the range of -5V to 2V. On the other hand, when the thickness of the second oxide semiconductor layer 132 is or At that time, the BTS threshold voltage offset value "BTSΔVth" of TFT 100 is in the range of -5V to 2V.

[0126] Therefore, based on the BTS threshold voltage offset value "BTSΔVth" of TFT 100, when the thickness of the first oxide semiconductor layer 131 is At that time, the thickness of the second oxide semiconductor layer 132 can be or That is, the thickness of the second oxide semiconductor layer 132 can be set to be one-third (1 / 3) thicker than the thickness of the first oxide semiconductor layer 131 and five-thirds (5 / 3) thinner than the thickness of the first oxide semiconductor layer 131.

[0127] Figure 16 This is a flowchart illustrating a method for manufacturing a TFT according to an embodiment of the present invention. Figures 17A to 17E This is a cross-sectional view used to describe a method for manufacturing a TFT according to an embodiment of the present invention.

[0128] In the following text, reference will be made to Figure 16 and 17A A method for manufacturing a TFT according to an embodiment of the present invention is described in detail in section 17E.

[0129] First, such as Figure 17A As shown, a gate electrode 110 may be formed on the first substrate 1110, and a gate insulating layer 120 may be formed on the gate electrode 110. Figure 16 (S101)

[0130] In detail, a first metal layer can be formed on the first substrate 1110 by a sputtering process. Subsequently, a photoresist pattern can be formed on the first metal layer, and then the first metal layer can be patterned by an etching mask process to form the gate electrode 110. The gate electrode 110 can be formed from a single layer or multiple layers of one or an alloy of Mo, Al, Cr, Au, Ti, Ni, Nd and Cu.

[0131] Alternatively, a buffer layer 300 may be formed on the first substrate 1110 to protect the TFT 100 from moisture seeping through the first substrate 1110, and a gate electrode 110 may be formed on the buffer layer 300. In this case, the buffer layer 300 may comprise a plurality of alternately stacked inorganic layers. For example, the buffer layer 300 may be formed by a multilayer of one or more inorganic layers of SiOx, SiNx, and SiON stacked alternately. The buffer layer 300 may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process.

[0132] Subsequently, a gate insulating layer 120 may be formed on the gate electrode 110. The gate insulating layer 120 may be formed of an inorganic layer, such as SiOx, SiNx, or a multilayer thereof. The gate insulating layer 120 may be formed by a PECVD process.

[0133] Second, such as Figure 17B As shown, a first semiconductor material layer 131' and a second semiconductor material layer 132' can be formed on the gate insulating layer 120, and a photoresist pattern 133 can be formed on the second semiconductor material layer 132'. Figure 16 S102)

[0134] Specifically, a first semiconductor material layer 131' may be formed on the gate insulating layer 120. The first semiconductor material layer 131' may be formed of IGZTO to increase electron mobility.

[0135] Subsequently, a second semiconductor material layer 132' may be formed on the first semiconductor material layer 131'. The second semiconductor material layer 132' may include IGZO to prevent the threshold voltage from shifting rapidly due to changes in channel length. The second semiconductor material layer 132' may be formed of IGZO or IGZTO. When the second semiconductor material layer 132' is formed of IGZTO, the second semiconductor material layer 132' may have a different composition ratio than the first semiconductor material layer 131'. The first semiconductor material layer 131' and the second semiconductor material layer 132' may be deposited sequentially in the same apparatus. Furthermore, the first semiconductor material layer 131' and the second semiconductor material layer 132' may be deposited while the temperature of the first substrate 1110 is maintained at 200°C or higher.

[0136] Subsequently, a photoresist pattern 133 can be formed on the second semiconductor material layer 132'.

[0137] Third, such as Figure 17C As shown, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 can be formed by simultaneously etching the first semiconductor material layer 131' and the second semiconductor material layer 132', and the photoresist pattern 133 can be removed. Figure 16 S103)

[0138] In detail, as referenced above Figure 12 and 13 In the process of depositing the first semiconductor material layer 131' and the second semiconductor material layer 132', when the first substrate 1110 is etched at a temperature below 200°C, the etch rate of the first semiconductor material layer 131' is higher than that of the second semiconductor material layer 132', so the bevel of the side surface of the second oxide semiconductor layer 132 can be formed at an obtuse angle. In this case, even when the source electrode 140 and the drain electrode 150 are provided to cover the side surfaces of the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, a void can still be formed at the boundary between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. Therefore, the etchant used to etch the source electrode 140 and the drain electrode 150 can penetrate into this void, and the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 can be additionally etched by the etchant that has penetrated into the void. For this reason, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 may be formed with an undesirable channel length or channel width.

[0139] However, as Figure 12 As shown, in the process of depositing the first semiconductor material layer 131' and the second semiconductor material layer 132', when etching the first semiconductor material layer 131' and the second semiconductor material layer 132' under the condition that the temperature of the first substrate 1110 is maintained at 200°C or higher, because the etching rate of the first semiconductor material layer 131' is equal to or lower than the etching rate of the second semiconductor material layer 132', the bevel of the side surface of the second oxide semiconductor layer 132 can be formed at an acute angle. In this case, even when the source electrode 140 and the drain electrode 150 are provided to cover the side surfaces of the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132, no voids are formed in the boundary between the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132. Therefore, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 can be prevented from being additionally etched by the etchant that has penetrated into the voids. Therefore, the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 are formed to have an ideal channel length or channel width.

[0140] The first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 can be formed by simultaneously etching the first semiconductor material layer 131' and the second semiconductor material layer 132' using an etchant capable of simultaneously etching the first semiconductor material layer 131' and the second semiconductor material layer 132'. Subsequently, the photoresist pattern 133 can be removed by a stripping process.

[0141] Fourth, such as Figure 17D As shown, a source electrode 140 and a drain electrode 150 can be formed. Figure 16 (S104)

[0142] The source electrode 140 can directly contact one side of the second oxide semiconductor layer 132 and one side of the first oxide semiconductor layer 131, which serves as the main channel layer. Specifically, the source electrode 140 can directly contact one side surface of the first oxide semiconductor layer 131, and a portion of the upper surface and one side surface of the second oxide semiconductor layer 132. Furthermore, the drain electrode 150 can directly contact the other side of the first oxide semiconductor layer 131 and the other side of the second oxide semiconductor layer 132. Specifically, the drain electrode 150 can directly contact the other side surface of the first oxide semiconductor layer 131, and a portion of the upper surface and another side surface of the second oxide semiconductor layer 132. The source electrode 140 and the drain electrode 150 can each be formed from a single layer or multiple layers of one or an alloy of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu.

[0143] Fifth, such as Figure 17E As shown, a passivation layer 160 may be formed on the oxide semiconductor layer 130, the source electrode 140, and the drain electrode 150. Figure 16 (S105)

[0144] The passivation layer 160 may be formed from an inorganic layer, such as SiOx, SiNx, or multiple layers thereof.

[0145] Figure 18 This is a plan view illustrating a TFT according to another embodiment of the present invention. Figure 19 It is a diagram along Figure 18 A cross-sectional view of an example taken from line II-II'.

[0146] Except that the length of the first oxide semiconductor layer 131 in the first direction (X-axis direction) is set to be greater than the length of the second oxide semiconductor layer 132 in the first direction (X-axis direction), Figure 18 and 19 The description is roughly the same as the above reference. Figure 6 and 7 Since the given descriptions are identical, the duplicate descriptions are omitted.

[0147] exist Figure 18 and 19 In this configuration, the first oxide semiconductor layer 131 may have a wider region than the second oxide semiconductor layer 132, thus increasing the contact area between each of the source electrode 140 and the drain electrode 150 and the first oxide semiconductor layer 131, which serves as the main channel layer. Therefore, in Figure 18 and 19 In another embodiment of the invention shown, the contact resistance is reduced.

[0148] Figure 20 This is a plan view illustrating a TFT according to another embodiment of the present invention. Figure 21 It is a diagram along Figure 20 A cross-sectional view of an example taken from line III-III'.

[0149] exist Figure 20 and 21 In another embodiment of the present invention, the TFT 100 is illustrated as being configured in a coplanar structure. The coplanar structure may have a top gate structure in which the gate electrode is disposed on the active layer.

[0150] Reference Figure 20 and 21 According to another embodiment of the present invention, the TFT 100 may include a gate electrode 110, an oxide semiconductor layer 130, a source electrode 140, and a drain electrode 150.

[0151] TFT 100 may be disposed on first substrate 1110. First substrate 1110 may be formed of plastic, glass and / or the like.

[0152] A buffer layer 300 may be disposed on the first substrate 1110 to protect the TFT 100 from moisture that permeates through the first substrate 1110. The buffer layer 300 may comprise a plurality of alternately stacked inorganic layers. For example, the buffer layer 300 may be formed by a multilayer of one or more inorganic layers of SiOx, SiNx, and SiON stacked alternately. The buffer layer 300 may be omitted.

[0153] An oxide semiconductor layer 130 may be formed on the buffer layer 300. The oxide semiconductor layer 130 may include a first oxide semiconductor layer 131 and a second oxide semiconductor layer 132. The first oxide semiconductor layer 131 may be the main channel layer for electron movement and is therefore positioned close to the gate electrode 110. Thus, the first oxide semiconductor layer 131 can be defined as a layer positioned closer to the gate electrode 110 than the second oxide semiconductor layer 132, and the second oxide semiconductor layer 132 can be defined as a layer positioned further away from the gate electrode 110 than the first oxide semiconductor layer 131. For example, as... Figure 20 and 21 As shown, in the case where the TFT100 is implemented as a coplanar structure, since the gate electrode 110 is disposed on the oxide semiconductor layer 130, the second oxide semiconductor layer 132 can be disposed on the first substrate 1110 or the buffer layer 300 of the first substrate 1110, and the first oxide semiconductor layer 131 can be disposed on the second oxide semiconductor layer 132.

[0154] A light-shielding layer may be formed below the oxide semiconductor layer 130 to block light incident from the first substrate 1110 onto the oxide semiconductor layer 130.

[0155] The gate insulating layer 120 may be disposed on the oxide semiconductor layer 130. The gate insulating layer 120 may be formed of an inorganic layer, such as SiOx, SiNx or a multilayer thereof.

[0156] A gate electrode 110 may be formed on a gate insulating layer 120. The gate electrode 110 may be configured to overlap with an oxide semiconductor layer 130, with the gate insulating layer 120 between the gate electrode 110 and the oxide semiconductor layer 130. The gate electrode 110 may be formed of a single layer or multiple layers of one or an alloy thereof, including Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu.

[0157] exist Figure 21 The illustration shows an example where the gate insulating layer 120 is disposed only between the gate electrode 110 and the oxide semiconductor layer 130, but embodiments of the present invention are not limited thereto. In other embodiments, the gate insulating layer 120 may be formed to cover the first substrate 1110 and the oxide semiconductor layer 130.

[0158] An interlayer insulating layer 170 may be formed on the gate electrode 110 and the oxide semiconductor layer 130. The interlayer insulating layer 170 may be formed of an inorganic layer, such as SiOx, SiNx, or multiple layers thereof.

[0159] The first contact hole CT1 and the second contact hole CT2 may be formed in the interlayer insulating layer 170. The first contact hole CT1 passes through the interlayer insulating layer 170 and exposes one side of the first oxide semiconductor layer 131, and the second contact hole CT2 passes through the interlayer insulating layer 170 and exposes the other side of the first oxide semiconductor layer 131.

[0160] Source electrode 140 and drain electrode 150 may be formed on interlayer insulating layer 170. Source electrode 140 may contact one side of first oxide semiconductor layer 131 through first contact hole CT1. Drain electrode 150 may contact the other side of first oxide semiconductor layer 131 through second contact hole CT2.

[0161] Passivation layer 160 may be formed on source electrode 140 and drain electrode 150. Passivation layer 160 may be formed of inorganic layer, such as SiOx, SiNx or multilayers thereof.

[0162] The first oxide semiconductor layer 131 may be formed of IGZTO instead of IGZO to increase electron mobility.

[0163] Furthermore, the second oxide semiconductor layer 132 may be formed of IGZT. Specifically, the IGZT composition ratio of the second oxide semiconductor layer 132 may be different from that of the first oxide semiconductor layer 131, so that even when the oxide semiconductor layer 130 is implemented as a short channel, threshold voltage shift can still be prevented. The second oxide semiconductor layer 132 covers and protects the first oxide semiconductor layer 131 so that the first oxide semiconductor layer 131 can stably act as a channel, and the etching rate of the second oxide semiconductor layer 132 is increased.

[0164] The composition ratio of IGZT in the first oxide semiconductor layer 131 and the composition ratio of IGZT in the second oxide semiconductor layer 132 are approximately the same as those mentioned above. Figures 6 to 13 Since the given descriptions are identical, duplicate descriptions are omitted.

[0165] Figure 22 It is a diagram along Figure 20 A cross-sectional view of another example taken from line III-III'.

[0166] In addition to the source electrode 140 and drain electrode 150 being connected to the second oxide semiconductor layer 132 and the first oxide semiconductor layer 131, Figure 22 The description is roughly the same as the above reference. Figure 20 and 21 Since the given descriptions are identical, the duplicate descriptions are omitted.

[0167] Reference Figure 22 Each of the first contact hole CT1 and the second contact hole CT2 passes through the first oxide semiconductor layer 131 and the interlayer insulating layer 170 and can expose the second oxide semiconductor layer 132. Therefore, the source electrode 140 can be connected to the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 through the first contact hole CT1, and the drain electrode 150 can be connected to the first oxide semiconductor layer 131 and the second oxide semiconductor layer 132 through the second contact hole CT2.

[0168] As described above, according to an embodiment of the present invention, the first oxide semiconductor layer corresponding to the main channel layer can be formed of IGZO, and the second oxide semiconductor layer can be formed of IGZO. As a result, according to an embodiment of the present invention, electron mobility is increased, and threshold voltage shift based on channel length is prevented. Therefore, embodiments of the present invention can be applied to flat panel display devices requiring high-speed driving due to high resolution.

[0169] Furthermore, according to an embodiment of the present invention, the bevel of the side surface of the first oxide semiconductor layer can be formed with an acute angle, and the bevel of the side surface of the second oxide semiconductor layer can be formed with a right angle or an acute angle. When the source electrode and the drain electrode cover the side surfaces of the first oxide semiconductor layer and the second oxide semiconductor layer, no voids are formed in the boundary between the first oxide semiconductor layer and the second oxide semiconductor layer. Therefore, according to an embodiment of the present invention, the first oxide semiconductor layer and the second oxide semiconductor layer can be prevented from being additionally etched by etchant that has penetrated into the voids. Therefore, according to an embodiment of the present invention, the first oxide semiconductor layer and the second oxide semiconductor layer can be formed to have an ideal channel length or channel width.

[0170] Furthermore, according to an embodiment of the present invention, in order to prevent the degradation of the PBTS and NBTIS characteristics of the TFT, the second oxide semiconductor layer is formed such that the Zn to In content ratio (Zn / In) of the second oxide semiconductor layer is less than 5.

[0171] Furthermore, in embodiments of the present invention, based on the positive and negative offsets of the threshold voltage of the TFT, the thickness of the second oxide semiconductor layer can be set to be one-third (1 / 3) thicker than the thickness of the first oxide semiconductor layer and five-thirds (5 / 3) thinner than the thickness of the first oxide semiconductor layer.

[0172] As described above, according to embodiments of the present invention, the oxide semiconductor layer may include a first oxide semiconductor layer corresponding to the main channel layer and having IGZTO, and a second oxide semiconductor layer having IGZO. The second oxide semiconductor layer may include IGZO or IGZTO. When the second oxide semiconductor layer includes IGZTO, the composition ratio of IGZTO in the second oxide semiconductor layer may be different from that in the first oxide semiconductor layer. As a result, according to embodiments of the present invention, electron mobility is increased, and threshold voltage shift based on channel length is prevented. Therefore, embodiments of the present invention can be applied to flat panel display devices that require high-speed driving due to high resolution.

[0173] Furthermore, according to an embodiment of the present invention, the bevel of the side surface of the first oxide semiconductor layer can be formed with an acute angle, and the bevel of the side surface of the second oxide semiconductor layer can be formed with a right angle or an acute angle. When the source electrode and the drain electrode cover the side surfaces of the first oxide semiconductor layer and the second oxide semiconductor layer, no voids are formed in the boundary between the first oxide semiconductor layer and the second oxide semiconductor layer. Therefore, according to an embodiment of the present invention, the first oxide semiconductor layer and the second oxide semiconductor layer can be prevented from being additionally etched by etchant that has penetrated into the voids. Therefore, according to an embodiment of the present invention, the first oxide semiconductor layer and the second oxide semiconductor layer can be formed to have an ideal channel length or channel width.

[0174] Furthermore, according to an embodiment of the present invention, in order to prevent the degradation of the PBTS and NBTIS characteristics of the TFT, the second oxide semiconductor layer is formed such that the Zn to In content ratio (Zn / In) of the second oxide semiconductor layer is less than 5.

[0175] Various modifications and variations can be made to this invention without departing from the spirit or scope thereof, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover modifications and variations thereof within the scope of the appended claims and their equivalents.

Claims

1. A thin film transistor (TFT) comprising: a first oxide semiconductor layer comprising indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O); a second oxide semiconductor layer comprising indium (In), gallium (Ga), zinc (Zn), and oxygen (O), the second oxide semiconductor layer being provided over the first oxide semiconductor layer; and a gate electrode, the gate electrode being provided below the first oxide semiconductor layer, wherein a content ratio of Ga to In (Ga / In) of the second oxide semiconductor layer is higher than a content ratio of Ga to In (Ga / In) of the first oxide semiconductor layer, and a content ratio of Zn to In (Zn / In) of the second oxide semiconductor layer is higher than a content ratio of Zn to In (Zn / In) of the first oxide semiconductor layer.

2. The thin film transistor according to claim 1, wherein the content ratio of Zn to In (Zn / In) of the second oxide semiconductor layer is lower than 5.

3. The thin film transistor according to claim 1, wherein a thickness of the second oxide semiconductor layer is thicker than one third of a thickness of the first oxide semiconductor layer and thinner than five thirds of the thickness of the first oxide semiconductor layer.

4. The thin film transistor according to claim 1, wherein an area of the gate electrode is wider than areas of the first oxide semiconductor layer and the second oxide semiconductor layer.

5. The thin film transistor according to claim 1, wherein the gate electrode covers the first oxide semiconductor layer and the second oxide semiconductor layer.

6. The thin film transistor according to claim 1, wherein the first oxide semiconductor layer has a higher conductivity than the second oxide semiconductor layer to serve as a main channel layer.

7. The thin film transistor according to claim 1, wherein an inclination angle of one side surface of the first oxide semiconductor layer is an acute angle, and an inclination angle of one side surface of the second oxide semiconductor layer is 90 degrees or an acute angle.

8. The thin film transistor according to claim 1, further comprising: a source electrode, the source electrode contacting one side of the first oxide semiconductor layer and one side of the second oxide semiconductor layer; and a drain electrode, the drain electrode contacting another side of the first oxide semiconductor layer and another side of the second oxide semiconductor layer.

9. The thin film transistor according to claim 8, wherein a length of the first oxide semiconductor layer in a direction in which the source electrode and the drain electrode are spaced apart from each other is larger than a length of the second oxide semiconductor layer in the direction in which the source electrode and the drain electrode are spaced apart from each other.

10. The thin film transistor according to claim 1, wherein the second oxide semiconductor layer further comprises tin (Sn).

11. The thin film transistor according to claim 10, wherein a content ratio of In to Sn (In / Sn) of the second oxide semiconductor layer is equal to or higher than a content ratio of In to Sn (In / Sn) of the first oxide semiconductor layer. ​ 12. The thin film transistor according to claim 1, wherein the atomic percentage content of Ga of the second oxide semiconductor layer is higher than that of the first oxide semiconductor layer, and the atomic percentage content of Zn of the second oxide semiconductor layer is higher than that of the first oxide semiconductor layer.

13. The thin film transistor according to claim 10, wherein the atomic percentage content of In of the second oxide semiconductor layer is lower than that of the first oxide semiconductor layer, and the atomic percentage content of Sn of the second oxide semiconductor layer is lower than that of the first oxide semiconductor layer.

14. The thin film transistor according to claim 1, wherein in the second oxide semiconductor layer, the content ratio of Ga to In satisfies 2 < Ga / In < 4, and the content ratio of Zn to In satisfies 2 < Zn / In < 8.

15. The thin film transistor according to claim 10, wherein in the second oxide semiconductor layer, the content ratio of Ga to In satisfies 2 < Ga / In < 4, the content ratio of Zn to In satisfies 2 < Zn / In < 8, and the content ratio of Sn to In satisfies 0.1 < Sn / In < 0.

5.

16. A gate driver comprising a plurality of stages which output gate signals, each of the plurality of stages comprising the thin film transistor according to claim 1.

17. A display device comprising a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels each provided in a region defined by an intersection of the plurality of data lines and the plurality of gate lines, each of the plurality of pixels comprising the thin film transistor according to claim 1.

18. The display device according to claim 17, wherein the display panel further comprises a gate driver which outputs gate signals to the plurality of gate lines, and the gate driver comprises the thin film transistor according to claim 1.

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