A mini-LED chip and preparation method

Abstract

The present invention provides a mini-LED chip and a preparation method. In the mini-LED chip, the ohmic contact layer in the composite transparent conductive layer reduces the ohmic contact resistance of the composite transparent conductive layer and improves the ohmic contact with the P-type layer. The first transparent conductive layer improves the electron concentration and current expansion capability. The second transparent conductive layer improves the conductive film penetration rate. The two transparent conductive layers further improve the current conduction capability and ESD resistance. The nanolayer improves the adhesion and thrust reliability of the chip. The composite transparent conductive layer improves the heat dissipation capability of the chip and reduces the generation of thermal effects. In addition, the viscosity-enhancing cutoff layer improves the adhesion between the composite DBR reflective layer and the composite transparent conductive layer, the water vapor insulation layer improves the water vapor erosion resistance, and intermittent ion plating is used to reduce the film stress of the composite DBR reflective layer and improve the reliability of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor light emitting diodes, and more specifically, to a mini-LED chip and a preparation method thereof. Background Art

[0002] With the development of technology, small-pitch displays, as an important application of semiconductor light-emitting diodes (LEDs) in displays, are gradually maturing. Traditional small-pitch displays still suffer from problems such as insufficient viewing distance and moiré patterns due to the influence of pixel pitch and the inherent defects of discrete devices. To meet people's ever-increasing demand for display effects and further expand their application areas, small-pitch displays are constantly moving towards smaller pixel pitches, which means that chip size is constantly decreasing. Because mini-LEDs can avoid the various defects of existing chips, they have become the only option for smaller pixel pitches and have also become a hot topic of industry research in the past two years.

[0003] As the size of mini-LED chips shrinks, the contact area between the transparent conductive layer and the P-type GaN layer also gradually shrinks. If the ohmic contact between the transparent conductive layer and the P-type GaN layer is poor or insufficiently dense, local heat cannot be dissipated, resulting in a large thermal effect and causing the transparent conductive layer area to break down, that is, the anti-static discharge (ESD) capability is weak, which in turn reduces the reliability of the chip.

[0004] In addition, the DBR film layer in the mini-LED chip uses ion-assisted plating, which is a brittle material with poor step coverage. The film stress is large during thin film deposition and the water vapor isolation effect is poor. Film delamination is prone to occur in outdoor applications. Water vapor erosion of the electrodes and transparent conductive layer can easily lead to chip failure. Summary of the Invention

[0005] In view of this, in order to solve the above problems, the present invention provides a mini-LED chip and a preparation method, the technical solution is as follows:

[0006] The mini-LED chip includes:

[0007] substrate;

[0008] an epitaxial layer located on one side of the substrate; the epitaxial layer comprising an N-type layer, an active layer, and a P-type layer stacked in sequence in a first direction;

[0009] a composite transparent conductive layer located on a side of the P-type layer facing away from the substrate, the composite transparent conductive layer comprising an ohmic contact layer, a first transparent conductive layer, a second transparent conductive layer, and a nanolayer stacked in sequence in the first direction;

[0010] The first direction is perpendicular to the plane where the substrate is located, and points from the substrate to the composite transparent conductive layer.

[0011] Optionally, in the above mini-LED chip, the thickness of the ohmic contact layer is 150 angstroms to 300 angstroms;

[0012] The thickness of the first transparent conductive layer is 200 angstroms to 400 angstroms;

[0013] The thickness of the second transparent conductive layer is 200 angstroms to 2000 angstroms;

[0014] The thickness of the nanolayer is 10 angstroms to 100 angstroms.

[0015] Optionally, in the above mini-LED chip, the material of the ohmic contact layer is IWO material;

[0016] The material of the first transparent conductive layer is ITO material;

[0017] The material of the second transparent conductive layer is ITO material;

[0018] The material of the nano layer is Ti material.

[0019] Optionally, in the above mini-LED chip, the mini-LED chip further includes:

[0020] a composite DBR reflective layer located on a side of the composite transparent conductive layer facing away from the substrate; the composite DBR reflective layer comprises an etched stop layer and a first stacked layer stacked in the first direction;

[0021] The first stack includes SiO2 layers and Ti3O5 layers alternately stacked in sequence in the first direction.

[0022] Optionally, in the above-mentioned mini-LED chip, the thickness of the etching cut-off layer is 600 angstroms to 5000 angstroms.

[0023] Optionally, in the above mini-LED chip, the mini-LED chip further includes:

[0024] An adhesion-enhancing cutoff layer is located between the composite transparent conductive layer and the composite DBR reflective layer.

[0025] Optionally, in the above mini-LED chip, the material of the adhesion-enhancing cutoff layer is ZrO2 material or Y2O3 material or SiN x Material.

[0026] Optionally, in the above mini-LED chip, the mini-LED chip further includes:

[0027] A water vapor isolation layer is located on a side of the composite DBR reflective layer facing away from the substrate.

[0028] Optionally, in the above-mentioned mini-LED chip, the thickness of the water vapor isolation layer is 400 angstroms to 10,000 angstroms.

[0029] A method for preparing a mini-LED chip, for preparing any of the mini-LED chips described above, the method comprising:

[0030] providing a substrate;

[0031] forming an epitaxial layer on one side of the substrate; the epitaxial layer comprising an N-type layer, an active layer, and a P-type layer stacked in sequence in a first direction;

[0032] A composite transparent conductive layer is formed on the side of the P-type layer facing away from the substrate, wherein the composite transparent conductive layer includes an ohmic contact layer, a first transparent conductive layer, a second transparent conductive layer, and a nanolayer stacked in sequence in the first direction; the first direction is perpendicular to the plane of the substrate and points from the substrate to the composite transparent conductive layer.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] The present invention provides a mini-LED chip, which includes a substrate; an epitaxial layer located on one side of the substrate; the epitaxial layer includes an N-type layer, an active layer and a P-type layer stacked in sequence in a first direction; a composite transparent conductive layer located on the side of the P-type layer facing away from the substrate, the composite transparent conductive layer includes an ohmic contact layer, a first transparent conductive layer, a second transparent conductive layer and a nanolayer stacked in sequence in the first direction; the first direction is perpendicular to the plane of the substrate and points from the substrate to the composite transparent conductive layer.

[0035] The mini-LED chip is provided with a composite transparent conductive layer, which includes an ohmic contact layer, a first transparent conductive layer, a second transparent conductive layer, and a nanolayer stacked in sequence in a first direction. The ohmic contact layer reduces the ohmic contact resistance of the composite transparent conductive layer and improves the ohmic contact between the P-type layer and the composite transparent conductive layer. The first transparent conductive layer improves electron concentration and current expansion capability. The second transparent conductive layer improves the conductive film's transmittance. The two transparent conductive layers further improve current conduction capability and ESD resistance. The nanolayer improves adhesion and chip thrust reliability. The provision of the composite transparent conductive layer in the mini-LED chip increases the chip's heat dissipation and ESD resistance, reduces the generation of thermal effects, and improves chip reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0037] Figure 1 A schematic structural diagram of a mini-LED chip provided by an embodiment of the present invention;

[0038] Figure 2 A schematic structural diagram of another mini-LED chip provided by an embodiment of the present invention;

[0039] Figure 3 A schematic structural diagram of a composite transparent conductive layer provided in an embodiment of the present invention;

[0040] Figure 4 A schematic structural diagram of a composite DBR reflective layer provided in an embodiment of the present invention;

[0041] Figure 5 A schematic diagram of a process for preparing a mini-LED chip provided in an embodiment of the present invention;

[0042] Figure 6 A schematic diagram of a partial structure of a mini-LED chip provided by an embodiment of the present invention;

[0043] Figure 7 A schematic diagram of a partial structure of another mini-LED chip provided by an embodiment of the present invention;

[0044] Figure 8 A schematic diagram of a partial structure of another mini-LED chip provided by an embodiment of the present invention;

[0045] Figure 9 A schematic diagram of a partial structure of another mini-LED chip provided by an embodiment of the present invention;

[0046] Figure 10 A schematic diagram of a partial structure of another mini-LED chip provided by an embodiment of the present invention;

[0047] Figure 11 A schematic diagram of a partial structure of another mini-LED chip provided by an embodiment of the present invention;

[0048] Figure 12 A schematic diagram of a partial structure of another mini-LED chip provided by an embodiment of the present invention;

[0049] Figure 13 A schematic diagram of the partial structure of another mini-LED chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0050] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0051] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0052] refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a mini-LED chip provided by an embodiment of the present invention, with reference to Figure 2 , Figure 2 A schematic structural diagram of another mini-LED chip provided in an embodiment of the present invention.

[0053] The mini-LED chip includes:

[0054] A substrate 01 and an epitaxial layer 02 located on one side of the substrate 01 ; the epitaxial layer 02 includes an N-type layer 021 , an active layer 022 , and a P-type layer 023 stacked in sequence in a first direction M.

[0055] The composite transparent conductive layer 03 located on the side of the P-type layer 023 facing away from the substrate 01 includes an ohmic contact layer, a first transparent conductive layer, a second transparent conductive layer and a nanolayer stacked in sequence in the first direction M.

[0056] The first direction M is perpendicular to the plane where the substrate 01 is located, and points from the substrate 01 to the composite transparent conductive layer 03 .

[0057] Specifically, in the mini-LED chip, the material of the substrate 01 includes but is not limited to a sapphire substrate. An epitaxial layer 02 is provided on one side of the substrate 01. The epitaxial layer 02 includes an N-type layer 021, an active layer 022, and a P-type layer 023 stacked in sequence in a first direction M. In this embodiment, the N-type layer 021 can be an N-type GaN layer, the active layer 022 can be a multi-quantum well (Metallic QuantumWell, abbreviated as MQW) layer, and the P-type layer 023 can be a P-type GaN layer.

[0058] like Figure 1 As shown, there is a first groove on the epitaxial layer 02, which passes through the P-type layer 023 and the active layer 022 and exposes part of the N-type layer 021. In the first groove, an N-type metal electrode 08 is provided. The material of the N-type metal electrode 08 can be one or more combinations of metals such as Cr, Ni, Al, Ti, Pt, or Au. For example, the material of the N-type metal electrode 08 can be a separate Al electrode or a separate Pt electrode, or an electrode composed of Ni, Al, and Ti.

[0059] like Figure 2 As shown, there is also a first groove on the epitaxial layer 02, and the first groove also penetrates the P-type layer 023 and the active layer 022, exposing part of the N-type layer 021. Figure 1 The difference is that the first groove does not include the N-type metal electrode 08 .

[0060] refer to Figure 3 , Figure 3 Schematic diagram of the structure of the composite transparent conductive layer provided in an embodiment of the present invention, wherein a composite transparent conductive layer 03 is provided on the side of the P-type layer 023 facing away from the substrate 01, and the composite transparent conductive layer 03 includes an ohmic contact layer 031, a first transparent conductive layer 032, a second transparent conductive layer 033 and a nanolayer 034 stacked in sequence in a first direction M.

[0061] Optionally, in another embodiment of the present invention, the thickness of the ohmic contact layer 031 is 150 angstroms to 300 angstroms.

[0062] The thickness of the first transparent conductive layer 032 is 200 angstroms to 400 angstroms.

[0063] The thickness of the second transparent conductive layer 033 is 200 angstroms to 2000 angstroms.

[0064] The thickness of the nano-layer 034 is 10 angstroms to 100 angstroms.

[0065] Specifically, the thickness of the ohmic contact layer 031 can range from 150 angstroms to 300 angstroms, including endpoint values, for example, the thickness of the ohmic contact layer 031 can be 150 angstroms, 200 angstroms, or 250 angstroms, etc.; the thickness of the first transparent conductive layer 032 can range from 200 angstroms to 400 angstroms, including endpoint values, for example, the thickness of the first transparent conductive layer 032 can be 200 angstroms, 250 angstroms, or 400 angstroms, etc.; the thickness of the second transparent conductive layer 033 can range from 200 angstroms to 2000 angstroms, including endpoint values, for example, the thickness of the second transparent conductive layer 033 can be 200 angstroms, 1000 angstroms, or 1500 angstroms, etc.; the thickness of the nanolayer 034 can range from 10 angstroms to 100 angstroms, including endpoint values, for example, the thickness of the nanolayer 034 can be 15 angstroms, 50 angstroms, or 100 angstroms, etc.

[0066] Optionally, in another embodiment of the present invention, the material of the ohmic contact layer 031 is IWO material.

[0067] The material of the first transparent conductive layer 032 is ITO material.

[0068] The second transparent conductive layer 033 is made of ITO.

[0069] The material of the nano layer 034 is Ti material.

[0070] Specifically, in this embodiment, the material of the ohmic contact layer 031 can be an IWO material, that is, the ohmic contact layer 031 can be an IWO ohmic contact layer; the material of the first transparent conductive layer 032 can be an ITO material, and the first transparent conductive layer 032 is a high Sn target ITO layer; the material of the second transparent conductive layer 033 can be an ITO material, and the second transparent conductive layer 033 is a low Sn target ITO layer; the material of the nano layer 034 can be a Ti material, that is, the nano layer 034 is a nano Ti layer.

[0071] It should be noted that the thickness and material of the composite transparent conductive layer 03 are not specifically limited, and the above embodiment is only used as an example. Figure 1 As shown, the composite transparent conductive layer 03 is also provided with corresponding grooves at corresponding positions of the first grooves.

[0072] In the three aforementioned embodiments, the ohmic contact layer 031 in the composite transparent conductive layer 03 reduces the ohmic contact resistance of the composite transparent conductive layer 03, improving the ohmic contact between the P-type layer 023 and the composite transparent conductive layer 03. The first transparent conductive layer 032 increases electron concentration and current spreading capability, and the second transparent conductive layer 033 improves the conductive film's transmittance. Both transparent conductive layers further enhance current conduction and ESD resistance. The nanolayer 034 improves adhesion and chip thrust reliability. The inclusion of the composite transparent conductive layer in this mini-LED chip increases the chip's heat dissipation and ESD resistance, reduces thermal effects, and improves chip reliability.

[0073] Optional, reference Figure 4 , Figure 4 This is a schematic structural diagram of a composite DBR reflective layer provided in an embodiment of the present invention. In another embodiment of the present invention, the mini-LED chip further includes:

[0074] The composite DBR reflective layer 04 is located on the side of the composite transparent conductive layer 03 facing away from the substrate 01 ; the composite DBR reflective layer 04 includes an etching stop layer 041 and a first stacked layer 042 stacked in the first direction M.

[0075] The first stack 042 includes SiO 2 layers 042 a and Ti 3 O 5 layers 042 b that are alternately stacked in sequence in the first direction M.

[0076] Specifically, a composite DBR reflective layer 04 is provided on the side of the composite transparent conductive layer 03 facing away from the substrate 01. In this embodiment, the composite DBR reflective layer 04 is composed of an etching stop layer 041 and a first stack 042 stacked in a first direction M. The etching stop layer 041 is an ion isolation layer. The material of the etching stop layer 041 can be a coating material such as Y2O3 material or ZrO2 material. The first stack 042 includes SiO2 layers 042a and Ti3O5 layers 042b stacked alternately in the first direction M. The SiO2 layers 042a and the Ti3O5 layers 042b are stacked alternately multiple times in the first direction M, for example Figure 4 , SiO 2 layers 042 a and Ti 3 O 5 layers 042 b are alternately stacked N times in a first direction M, thereby forming a first stacked layer 042 .

[0077] It should be noted that the number of times N that the SiO 2 layer 042 a and the Ti 3 O 5 layer 042 b are alternately stacked is not specifically limited.

[0078] Optionally, in another embodiment of the present invention, the thickness of the etching stop layer 041 is 600 angstroms to 5000 angstroms.

[0079] Specifically, the thickness of the etching stop layer 041 may range from 600 angstroms to 5000 angstroms, including end points. For example, the thickness of the etching stop layer 041 may be 600 angstroms, 2000 angstroms, or 3500 angstroms.

[0080] In the above two embodiments, the etching stop layer 041 improves the coating ion energy of the Ti3O5 layer 042b when the composite DBR reflective layer 04 is coated and the plasma cleaning energy of the coating process, thereby improving adhesion. In addition, the etching stop layer 041 can also improve the etching process window, reduce the consumption of precious metals as a cutoff layer, and reduce costs.

[0081] Optionally, in another embodiment of the present invention, the mini-LED chip further includes:

[0082] The adhesion-enhancing cutoff layer 05 is located between the composite transparent conductive layer 03 and the composite DBR reflective layer 04 .

[0083] Optionally, in another embodiment of the present invention, the material of the adhesion-enhancing cut-off layer 05 is ZrO2 material or Y2O3 material or SiN x Material.

[0084] Specifically, the adhesion cutoff layer 05 is adjacent to the composite transparent conductive layer 03 and only covers the composite transparent conductive layer 03. The thickness of the adhesion cutoff layer 05 ranges from 100 angstroms to 600 angstroms, including end points. For example, the thickness of the adhesion cutoff layer 05 can be 100 angstroms, 250 angstroms, or 500 angstroms.

[0085] like Figure 1 As shown, the adhesion-enhancing cutoff layer 05 includes a second groove, which penetrates the adhesion-enhancing cutoff layer 05 and exposes the composite transparent conductive layer 03. In the second groove, a P-type metal electrode 09 is provided. The material of the P-type metal electrode 09 can be one or more combinations of metals such as Cr, Ni, Al, Ti, Pt, or Au. For example, the material of the P-type metal electrode 09 can be a separate Al electrode or a separate Pt electrode, or an electrode composed of Ni, Al, and Ti.

[0086] like Figure 2 As shown, the adhesion-enhancing cut-off layer 05 also includes a second groove, and the second groove also penetrates the adhesion-enhancing cut-off layer 05, exposing the composite transparent conductive layer 03. Figure 1 The difference is that the second groove does not include the P-type metal electrode 09 .

[0087] Optionally, in another embodiment of the present invention, the mini-LED chip further includes:

[0088] A water vapor isolation layer 06 is located on the side of the composite DBR reflective layer 03 facing away from the substrate 01 .

[0089] Specifically, the water vapor isolation layer 06 can prevent water vapor from penetrating and corroding the composite transparent conductive layer 03, which can not only improve the reverse voltage aging capability, but also improve the reliability of the chip. The material of the water vapor isolation layer 06 can be SiN x material or AlN material or TaN material or TiN material, etc.

[0090] Optionally, in another embodiment of the present invention, the thickness of the water vapor insulation layer 06 is 400 angstroms to 10,000 angstroms.

[0091] Specifically, the thickness of the water vapor barrier layer 06 ranges from 400 angstroms to 10,000 angstroms, including endpoint values. For example, the thickness of the water vapor barrier layer 06 can be 400 angstroms, 5,000 angstroms, or 9,000 angstroms.

[0092] Optionally, based on the two different mini-LED chips described in all the above embodiments of the present invention, namely Figure 1 The mini-LED chips shown and Figure 2 The mini-LED chip shown in FIG. 1 is a mini-LED chip. In another embodiment of the present invention, a method for preparing a mini-LED chip is provided. Figure 1 The mini-LED chips shown and Figure 2 The preparation process of the mini-LED chip shown.

[0093] Example 1, for Figure 1 The preparation process of the mini-LED chip shown is explained below:

[0094] refer to Figure 5 , Figure 5 A schematic flow chart of a method for preparing a mini-LED chip provided in an embodiment of the present invention, the method comprising:

[0095] S101: Provide a substrate 01.

[0096] In this step, the provided substrate 01 may be a sapphire substrate.

[0097] S102 : forming an epitaxial layer 02 on one side of the substrate 01 ; the epitaxial layer includes an N-type layer 021 , an active layer 022 , and a P-type layer 023 stacked in sequence in a first direction M.

[0098] In this step, refer to Figure 6 , Figure 6 A schematic diagram of a portion of the structure of a mini-LED chip provided by an embodiment of the present invention is shown in FIG. Figure 6As shown, based on the substrate 01 provided in step S101, an epitaxial layer 02 is prepared on one side thereof. The preparation of the epitaxial layer 02 includes stacking an N-type layer 021, an active layer 022 and a P-type layer 023 in sequence in a first direction M. In this embodiment, the N-type layer 021 can be an N-type GaN layer, the active layer 022 can be an MQW layer, and the P-type layer 023 can be a P-type GaN layer.

[0099] refer to Figure 7 , Figure 7 This is a partial structural diagram of another mini-LED chip provided by an embodiment of the present invention. After the epitaxial layer 02 is prepared, Figure 7 As shown, a photolithography is performed once to form a first groove, which penetrates the P-type layer 023 and the active layer 022 and exposes part of the N-type layer 021. For example, the epitaxial layer 02 is etched in a ratio of Cl2:Ar:O2=5:1:2 to obtain the first groove, i.e., the MESA (Miniature Electrostatic Accelerometer) table, wherein the etching includes but is not limited to dry etching such as ICP (Inductively coupled plasma), and the etching includes but is not limited to etching with Cl2, Ar, O2, etc.

[0100] refer to Figure 8 , Figure 8 This is a schematic diagram of a partial structure of another mini-LED chip provided by an embodiment of the present invention, and then another photolithography is performed, such as Figure 8 As shown, a photoresist is used as a mask to perform ICP deep etching, which includes but is not limited to dry etching such as ICP. This etching exposes a portion of the substrate 01.

[0101] S103: forming a composite transparent conductive layer 03 on the side of the P-type layer 023 facing away from the substrate 01, wherein the composite transparent conductive layer 03 includes an ohmic contact layer 031, a first transparent conductive layer 032, a second transparent conductive layer 033, and a nanolayer 034 stacked in sequence in the first direction M; the first direction M is perpendicular to the plane of the substrate 01 and points from the substrate 01 to the composite transparent conductive layer 03.

[0102] In this step, based on the epitaxial layer 02 obtained in step S102 , a composite transparent conductive layer 03 is prepared on the side of the P-type layer 023 of the epitaxial layer 02 facing away from the substrate 01 .

[0103] In this embodiment, the ohmic contact layer 031 is prepared by activated plasma deposition (Rapid Plasma Deposition, referred to as RPD). The ohmic contact layer 031 is an IWO ohmic contact layer, wherein the IWO target material In2O3:W2O3 is 90%:10%-98.5%:1.5%. At this time, the flow rate of Ar introduced into the reactive ion gun can be 70sccm-100sccm, the current of the magnetic coil is 50A-75A, the process gas introduced into the target position of the cavity can be O2, and the flow rate of O2 can be 0sccm-5sccm, and the flow rate of Ar can be 40sccm-60sccm. At this time, The thickness is preferably 250 angstroms to 400 angstroms, followed by a deposition process, followed by annealing at a temperature of 100°C to 300°C, followed by an alloying process for 5 minutes to 15 minutes. After the alloying, the surface of the IWO ohmic contact layer is heat-treated in a 50°C water bath with 0.5% to 3% NaOH for 30 seconds to 100 seconds. After the treatment, the Ra of the surface of the IWO ohmic contact layer is less than 0.4 nm, resulting in an IWO ohmic contact layer with a thickness of 150 angstroms to 300 angstroms, inclusive. For example, the thickness of the ohmic contact layer 031 can be 150 angstroms, 200 angstroms, or 250 angstroms.

[0104] Then, based on the processed IWO ohmic contact layer, a first transparent conductive layer 032, a second transparent conductive layer 033 and a nanolayer 034 are prepared by multi-target co-sputtering, wherein the first transparent conductive layer 032 is a first target position, and the ITO target In2O3:SnO2 of the first target position is 90%:10%. The sputtering thickness of the first target position ranges from 200 angstroms to 400 angstroms, including end points. For example, the thickness of the first transparent conductive layer 032 can be 200 angstroms, 250 angstroms or 400 angstroms, etc. The O2 flow rate introduced during the coating process can be 0.1 sccm-0.5 sccm, the RF power can be 200W-900W, and the DC power supply can be 100W. The second transparent conductive layer 033 is a second target, the ratio of In2O3:SnO2 in the second target ITO target is 95%:5%, and the sputtering thickness of the second target ranges from 200 angstroms to 2000 angstroms, including endpoint values. For example, the thickness of the second transparent conductive layer 033 can be 200 angstroms, 1000 angstroms, or 1500 angstroms. The O2 flow rate introduced during the coating process can be 2sccm-50sccm, the RF power can be 200W-900W, and the DC power can be 200W-600W. The nano layer 034 is a third target, the third target is a Ti target, the RF power can be 200W-900W, O2 is not passed during the coating process, and the thickness of the third target ranges from 10 angstroms to 100 angstroms, including endpoint values. For example, the thickness of the nano layer 034 can be 15 angstroms, 50 angstroms, or 100 angstroms.

[0105] It should be noted that the ohmic contact layer 031 is an IWO ohmic contact layer. Its IWO target (work function 4.7eV-5.2eV) has a work function closer to that of the P-type layer 023, making it easier to form ohmic contact at lower temperatures. In addition, the use of RPD preparation does not generate high-energy ions, causing less damage to the epitaxial layer 02. The ohmic contact layer 031 prepared by RPD has a low roughness after treatment, which can improve ESD resistance. The first transparent conductive layer 032 is a high-Sn content ITO target, which can increase the electron concentration and current expansion capability. The second transparent conductive layer 033 is a low-Sn content ITO target, which can increase the conductive film penetration rate, thereby further improving the performance of the composite transparent conductive film. The nanolayer 034 prepared by ITO doping with Ti has good adhesion after annealing and oxidation.

[0106] refer to Figure 9 , Figure 9A schematic diagram of a partial structure of another mini-LED chip provided in an embodiment of the present invention. After obtaining the composite transparent conductive layer 03, high-temperature annealing is performed. At this time, the alloy temperature can be 450°C-600°C, and the O2 flow rate can be 0.5sccm-4sccm. After annealing, a plasma enhanced chemical vapor deposition method (Plasma Enhanced Chemical Vapor Deposition, referred to as PECVD) is used to prepare an adhesion-enhancing cutoff layer 05. The chamber pressure can be 600mTorr-1000mTorr, the power can be 65W-100W, and the material of the adhesion-enhancing cutoff layer 05 can be ZrO2 material, Y2O3 material, or SiN x Materials, such as Y2O3 materials, etc., as the adhesion-enhancing cut-off layer 05 have both the effect of plasma etching resistance and can increase adhesion. The thickness of the adhesion-enhancing cut-off layer 05 ranges from 100 angstroms to 600 angstroms, including end point values. For example, the thickness of the adhesion-enhancing cut-off layer 05 can be 100 angstroms, 250 angstroms, or 500 angstroms.

[0107] Photolithography is used again to expose the adhesion-enhancing stop layer 05, and wet etching is used to expose the first groove and the second groove area. Figure 9 As shown, an N-type metal electrode 08 is evaporated in the first groove, and a P-type metal electrode 09 is evaporated in the second groove. The material of the N-type metal electrode 08 or the P-type metal electrode 09 can be one or more combinations of metals such as Cr, Ni, Al, Ti, Pt, or Au. For example, the material of the N-type metal electrode 08 or the P-type metal electrode 09 can be a single Al electrode or a single Pt electrode, or an electrode composed of Ni, Al, and Ti.

[0108] Based on the film layer obtained above, a composite DBR reflective layer 04 is prepared on the side of the adhesion-promoting cut-off layer 05 facing away from the substrate 01 .

[0109] refer to Figure 10 , Figure 10 A schematic diagram of a partial structure of another mini-LED chip provided by an embodiment of the present invention is shown in FIG. Figure 10 As shown, in this embodiment, ion-assisted plating is used to prepare the etching stop layer 041. The etching stop layer 041 is a plasma isolation layer. The plasma isolation layer can be made of materials such as Y2O3 or ZrO2. The coating temperature can be 120°C-150°C, the O2 flow rate can be 10sccm-20sccm, and the thickness of the coating is 600 angstroms-5000 angstroms. That is, the thickness of the etching stop layer 041 ranges from 600 angstroms to 5000 angstroms, including endpoint values. For example, the thickness of the etching stop layer 041 can be 600 angstroms, 2000 angstroms, or 4500 angstroms.

[0110] It should be noted that materials such as Y2O3 or ZrO2 are plasma etching resistant materials, and have very slow etching rates in gases such as CF4 or CHF3, and can be used as the etching stop layer 041.

[0111] After preparing the etching stop layer 041, the first stack 042 is prepared by ion source assisted coating. First, 1000W-2000W ionized high energy Ar + / O 2- The bombardment etching stop layer 041 is cleaned by the etching stop layer 041 to improve adhesion. The first stack 042 includes SiO2 layers 042a and Ti3O5 layers 042b stacked alternately in the first direction M. When preparing the SiO2 layer 042a, the ion source baffle is opened intermittently, and the interruption time can be 2s-5s. The O2 flow rate can be 10sccm-40sccm, the ion source power can be 400W-600W, and the process vacuum pressure can be 1.0E -4 -1.0E -5 Pa, the coating temperature can be 120℃-150℃; when preparing Ti3O5 layer 042b, the ion source baffle is often opened, the O2 flow rate can be 40sccm-60sccm, the ion source power can be 600W-1000W, and the process vacuum pressure can be 2.0-9.0E -2 Pa, the coating temperature can be 120℃-150℃, and after each layer of Ti3O5 layer 042b is evaporated, O 2- The surface of the Ti3O5 layer 042b is bombarded to fully oxidize the Ti3O5 layer 042b and reduce the stress of the Ti3O5 layer 042b. At this time, the O2 flow rate can be 20sccm-30sccm, and the ion source power can be 200W-400W. After multiple alternating preparations, the first stack 042 is obtained. The high refractive index Ti3O5 layer 042 and the low refractive index and low stress SiO2 layer 042a are prepared by controlling the ion energy, vacuum environment and O2 flow rate of the SiO2 layer 042a or the Ti3O5 layer 042b.

[0112] During the preparation of the composite DBR reflective layer 04, the high-refractive-index Ti3O5 layer 042b is prepared by controlling the normally-open ion source to give Ti3O5 high ion energy, low vacuum, and high oxygen content, and the low-refractive-index and low-stress SiO2 layer 042a is prepared by intermittently opening the ion source baffle to give SiO2 low ion energy and high vacuum. This allows the prepared first stack 042 to have a high differential refractive index, thereby improving the reflectivity of the composite DBR reflective layer 04 while reducing the film stress of the composite DBR reflective layer 04, thereby preventing the composite DBR reflective layer 04 from cracking and falling off.

[0113] refer to Figure 11 , Figure 11A schematic diagram of a partial structure of another mini-LED chip provided by an embodiment of the present invention is shown in FIG. Figure 11 As shown, after the composite DBR reflective layer 04 is prepared, a water vapor isolation layer 06 is prepared on the side of the composite DBR reflective layer 04 facing away from the substrate 01. The water vapor isolation layer 06 can be prepared by PECVD. The material of the water vapor isolation layer 06 can be SiN x Materials or AlN materials or TaN materials or TiN materials, etc., with SiN x For example, SiH4, NH3 and N2 can be used as reaction gases, where SiH4 accounts for more than 30% of the three gases, the chamber pressure can be selected from 600mTorr to 1000mTorr, the power can be selected from 65W to 100W, and the thickness of the water vapor isolation layer 06 ranges from 400 angstroms to 10000 angstroms, including endpoint values. For example, the thickness of the water vapor isolation layer 06 can be 400 angstroms, 5000 angstroms, or 9000 angstroms, etc.

[0114] It should be noted that SiN x Materials or ALN materials are ceramic materials with better water vapor isolation effect. SiN is deposited after the composite DBR reflective layer 04. x Can improve water vapor isolation capabilities.

[0115] refer to Figure 12 , Figure 12 A schematic diagram of a partial structure of another mini-LED chip provided by an embodiment of the present invention is shown in FIG. Figure 12 As shown, after preparing the water vapor barrier layer 06, etching gases such as CF4 or CHF3 can be used to etch the water vapor barrier layer 06 and the composite DBR reflective layer 04 using a multi-stage ICP process to form the first and second grooves. The etching stop layer 041 serves as an etching stop layer for etching the composite DBR reflective layer 04, preventing the CF4 or CHF3 gases from corroding the N-type metal electrode 08 or the P-type metal electrode 09. The etching stop layer 041 is then etched using a dry etching method such as HBr or BCl3.

[0116] Finally, a photolithography mask is used to prepare the above structure. Figure 1 The pad 07 shown in the figure, wherein one pad 07 in the first groove is in contact with the N-type metal electrode 08, and the other pad 07 in the second groove is in contact with the P-type metal electrode 09. The material of the pad 07 can be one or more combinations of metals such as Cr or Ni or Al or Ti or Pt or Au. For example, the material of the pad 07 can be a separate Al electrode or a separate Pt electrode, or an electrode composed of Ni, Al and Ti.

[0117] The ohmic contact layer 031 in the composite transparent conductive layer 03 of Example 1 reduces the ohmic contact resistance of the composite transparent conductive layer 03 and improves the ohmic contact between the P-type layer 023 and the composite transparent conductive layer 03. The first transparent conductive layer 032 increases electron concentration and current spreading capability, while the second transparent conductive layer 033 improves the conductive film's transmittance. Both transparent conductive layers further enhance current conduction and ESD resistance. The nanolayer 034 improves adhesion and chip thrust reliability. The adhesion-enhancing stop layer 05, formed after the composite transparent conductive layer 03, not only provides an etch-stop effect but also enhances adhesion between the composite transparent conductive layer 03 and the composite DBR reflective layer 04. The etch-stop layer 041 in the composite DBR reflective layer 04 increases the ion energy of the TiO layer 042b in the composite DBR reflective layer 04 coating and the plasma cleaning energy during the coating process, improving adhesion. Furthermore, the etch-stop layer 041 increases the etching process window, reduces the consumption of precious metals used as a stop layer, and reduces costs. A water vapor barrier layer (06) is formed behind the composite DBR reflective layer (04) to prevent water vapor from penetrating and corroding the composite transparent conductive layer (03). This not only improves the reverse voltage aging resistance but also enhances chip reliability. These features increase the mini-LED chip's heat dissipation and ESD resistance, reducing thermal effects and improving chip reliability.

[0118] Example 2, for Figure 2 The preparation process of the mini-LED chip shown is explained below:

[0119] like Figure 5 As shown, the preparation method comprises:

[0120] S101: Provide a substrate 01.

[0121] In this step, the provided substrate 01 may be a sapphire substrate.

[0122] S102 : forming an epitaxial layer 02 on one side of the substrate 01 ; the epitaxial layer includes an N-type layer 021 , an active layer 022 , and a P-type layer 023 stacked in sequence in a first direction M.

[0123] In this step, if Figure 6 As shown, based on the substrate 01 provided in step S101, an epitaxial layer 02 is prepared on one side thereof. The epitaxial layer 02 includes an N-type layer 021, an active layer 022, and a P-type layer 023 stacked in sequence in a first direction M. In this embodiment, the N-type layer 021 can be an N-type GaN layer, the active layer 022 can be an MQW layer, and the P-type layer 023 can be a P-type GaN layer.

[0124] After the epitaxial layer 02 is prepared, Figure 7As shown, a photolithography is performed to form a first groove, which penetrates the P-type layer 023 and the active layer 022 and exposes a portion of the N-type layer 021. For example, Cl2:Ar:O 2＝ The epitaxial layer 02 is etched in a ratio of 5:1:2 to obtain a first groove, namely a MESA table, wherein the etching includes but is not limited to dry etching such as ICP, and the etching includes but is not limited to etching with Cl2, Ar, O2, etc.

[0125] Then perform another photolithography, such as Figure 8 As shown, a photoresist is used as a mask to perform ICP deep etching, which includes but is not limited to dry etching such as ICP. This etching exposes a portion of the substrate 01.

[0126] S103: forming a composite transparent conductive layer 03 on the side of the P-type layer 023 facing away from the substrate 01, wherein the composite transparent conductive layer 03 includes an ohmic contact layer 031, a first transparent conductive layer 032, a second transparent conductive layer 033, and a nanolayer 034 stacked in sequence in the first direction M; the first direction M is perpendicular to the plane of the substrate 01 and points from the substrate 01 to the composite transparent conductive layer 03.

[0127] In this step, based on the epitaxial layer 02 obtained in step S102 , a composite transparent conductive layer 03 is prepared on the side of the P-type layer 023 of the epitaxial layer 02 facing away from the substrate 01 .

[0128] refer to Figure 13 , Figure 13 This is a partial structural diagram of another mini-LED chip provided by an embodiment of the present invention. The steps of preparing the composite transparent conductive layer 03, the adhesion-enhancing cutoff layer 05, the composite DBR reflective layer 04, and the water vapor isolation layer 06 in Example 2 are the same as those in Example 1. However, in Example 1, after etching the adhesion-enhancing cutoff layer 05, the first groove exposes the N-type metal electrode 08, and the second groove exposes the P-type metal electrode 09; Figure 13 As shown, in Example 2, after etching the adhesion-enhancing cutoff layer 05, the first groove exposes the N-type layer 021, and the second groove exposes the composite transparent conductive layer 03. The difference is that Example 1 is provided with an N-type metal electrode 08 in the first groove and a P-type metal electrode 09 in the second groove, while Example 2 does not.

[0129] It should be noted that in Example 2, since the adhesion-enhancing cutoff layer 05 has both the effect of being resistant to plasma etching and increasing adhesion, it can not only accurately etch the required thickness during etching, but also increase its adhesion with other film layers, thereby reducing the setting of metal electrodes, reducing the structural complexity of the chip, and reducing costs.

[0130] Finally, a photolithography mask is used to prepare Figure 2 As shown in the figure, one pad 07 in the first groove contacts the N-type layer 021, and the other pad 07 in the second groove contacts the composite transparent conductive layer 03. The material of the pad 07 can be one or more combinations of metals such as Cr, Ni, Al, Ti, Pt, or Au. For example, the material of the pad 07 can be a single Al electrode or a single Pt electrode, or an electrode composed of Ni, Al, and Ti.

[0131] The ohmic contact layer 031 in the composite transparent conductive layer 03 of Example 2 reduces the ohmic contact resistance of the composite transparent conductive layer 03 and improves the ohmic contact between the P-type layer 023 and the composite transparent conductive layer 03. The first transparent conductive layer 032 increases the electron concentration and current spreading capability, and the second transparent conductive layer 033 improves the conductive film's transmittance. Both transparent conductive layers further enhance current conduction and ESD resistance. The nanolayer 034 improves adhesion and chip thrust reliability. The adhesion-enhancing cutoff layer 05, prepared after the composite transparent conductive layer 03, not only provides an etching cutoff effect but also enhances the adhesion of the composite transparent conductive layer 03 to the composite DBR reflective layer 04 and to other film layers, thereby reducing the need for metal electrodes, reducing the chip's structural complexity, and lowering costs. The etch stop layer 041 in the composite DBR reflective layer 04 increases the ion energy of the Ti3O5 layer 042b in the composite DBR reflective layer 04 coating and the plasma cleaning energy during the coating process, thereby improving adhesion. Furthermore, the etch stop layer 041 can increase the etching process window, reduce the consumption of precious metals as a stop layer, and reduce costs. A water vapor barrier layer 06 is prepared after the composite DBR reflective layer 04 to prevent water vapor from penetrating and corroding the composite transparent conductive layer 03, which not only improves the reverse voltage aging capability but also improves the chip reliability. These settings increase the heat dissipation capacity and ESD resistance of the mini-LED chip, reduce the occurrence of thermal effects, and improve the reliability of the chip.

[0132] The above is a detailed introduction to a mini-LED chip and preparation method provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

[0133] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0134] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that the process, method, article, or apparatus comprising a series of elements inherent to the elements, or also including elements inherent to these processes, methods, articles, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0135] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A mini-LED chip, characterized in that: The mini-LED chip includes: substrate; an epitaxial layer located on one side of the substrate; the epitaxial layer comprising an N-type layer, an active layer, and a P-type layer stacked in sequence in a first direction; a first groove being formed on the epitaxial layer, wherein the first groove exposes a portion of the N-type layer; a composite transparent conductive layer located on a side of the P-type layer facing away from the substrate, the composite transparent conductive layer comprising an ohmic contact layer, a first transparent conductive layer, a second transparent conductive layer, and a nanolayer stacked in sequence in the first direction; The first direction is perpendicular to the plane of the substrate and points from the substrate to the composite transparent conductive layer; an adhesion-enhancing cutoff layer located on a side of the composite transparent conductive layer facing away from the substrate, the adhesion-enhancing cutoff layer comprising a second groove, the second groove exposing the composite transparent conductive layer, and the adhesion-enhancing cutoff layer being made of ZrO2 material, Y2O3 material, or SiNx material; a composite DBR reflective layer located on a side of the adhesion-enhancing cutoff layer facing away from the substrate; the composite DBR reflective layer includes an etching cutoff layer and a first stacked layer stacked in the first direction; the first stacked layer includes SiO2 layers and Ti3O5 layers stacked alternately in the first direction; The pads are one of which passes through the composite DBR reflective layer and directly contacts the N-type layer in the first groove, and the other pad passes through the composite DBR reflective layer and directly contacts the composite transparent conductive layer in the second groove.

2. The mini-LED chip according to claim 1, wherein: The thickness of the ohmic contact layer is 150 angstroms to 300 angstroms; The thickness of the first transparent conductive layer is 200 angstroms to 400 angstroms; The thickness of the second transparent conductive layer is 200 angstroms to 2000 angstroms; The thickness of the nanolayer is 10 angstroms to 100 angstroms.

3. The mini-LED chip according to claim 1, wherein: The material of the ohmic contact layer is IWO material; The material of the first transparent conductive layer is ITO material; The material of the second transparent conductive layer is ITO material; The material of the nano layer is Ti material.

4. The mini-LED chip according to claim 1, wherein: The thickness of the etching stop layer is 600 angstroms to 5000 angstroms.

5. The mini-LED chip according to claim 1, wherein: The mini-LED chip further includes: A water vapor isolation layer is located on a side of the composite DBR reflective layer facing away from the substrate.

6. The mini-LED chip according to claim 5, wherein: The thickness of the water vapor isolation layer is 400 angstroms to 10,000 angstroms.

7. A method for preparing a mini-LED chip, characterized in that: For preparing the mini-LED chip according to any one of claims 1 to 6, the preparation method comprising: providing a substrate; An epitaxial layer is formed on one side of the substrate; the epitaxial layer includes an N-type layer, an active layer, and a P-type layer stacked in sequence in a first direction; a first groove is formed on the epitaxial layer, and the first groove exposes a portion of the N-type layer; forming a composite transparent conductive layer on a side of the P-type layer facing away from the substrate, the composite transparent conductive layer comprising an ohmic contact layer, a first transparent conductive layer, a second transparent conductive layer, and a nanolayer stacked in sequence in the first direction; the first direction is perpendicular to the plane of the substrate and points from the substrate to the composite transparent conductive layer; forming an adhesion-enhancing cutoff layer on a side of the composite transparent conductive layer facing away from the substrate, the adhesion-enhancing cutoff layer comprising a second groove, the second groove exposing the composite transparent conductive layer, and the material of the adhesion-enhancing cutoff layer being ZrO2 material, Y2O3 material, or SiNx material; A composite DBR reflective layer is formed on the side of the adhesion-enhancing cutoff layer facing away from the substrate; the composite DBR reflective layer includes an etched cutoff layer and a first stacked layer stacked in the first direction; the first stacked layer includes SiO2 layers and Ti3O5 layers stacked alternately in sequence in the first direction; A photolithography mask is used to prepare pads, wherein one pad passes through the composite DBR reflective layer and directly contacts the N-type layer in the first groove, and the other pad passes through the composite DBR reflective layer and directly contacts the composite transparent conductive layer in the second groove.

Images