A high-stability flip-chip LED chip and its manufacturing method

Abstract

The present invention discloses a preparation method of a high-stability flip-chip LED chip, which includes: forming an N-GaN layer, an MQW layer and a P-GaN layer on a substrate; etching to form a first channel penetrating through the N-GaN layer, and continuously etching to form a second channel penetrating through the substrate; sequentially forming a current spreading layer, a passivation protection layer, a metal reflection layer, a metal conductive layer, a first insulating layer, an N electrode layer, a second insulating layer and a pad layer, and then splitting after grinding and thinning to obtain the high-stability flip-chip LED chip. Implementing the present invention can improve the chip yield and stability.

Description

Technical Field

[0001] The present invention relates to the technical field of optoelectronic manufacturing, and in particular, to a flip-chip LED chip with high stability and a preparation method thereof. Background Art

[0002] An LED is a light-emitting device that emits light through a PN junction. As a new generation of solid cold light source, it has the advantages of high electro-optical conversion efficiency, low energy consumption, long life, energy conservation and environmental protection, high reliability, etc., and is widely used in various places such as indoor lighting, photovoltaics, medical lighting, automotive headlights, LCD displays, etc.

[0003] Traditional LED chips generally use sapphire substrates, and problems such as uneven light emission in the active layer, poor heat dissipation, large angles of some film layers, and high junction temperature seriously affect the reliable performance of LED chips.

[0004] Classified by chip structure, LED chips can be divided into three types: front-mounted chips, flip-chip chips, and vertical chips. Among them, front-mounted chips have problems such as poor current expansion, uneven light emission, and poor heat dissipation; vertical chips have problems such as extremely complex manufacturing processes and high manufacturing costs, so there are relatively few vertical chips in the current market; while flip-chip chips have better performance than front-mounted chips and lower costs than vertical chips, and are widely concerned by the market. However, currently, flip-chip LED chips have problems of poor chip stability caused by factors such as uneven chip current distribution, large angles of some film layers, high chip junction temperature, and relatively complex processes, which seriously affect the application of flip-chip LED chips. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a preparation method for a flip-chip LED chip with high stability, which can improve the chip yield and stability.

[0006] Another technical problem to be solved by the present invention is to provide a flip-chip LED chip with high stability.

[0007] To solve the above technical problems, the present invention provides a preparation method for a flip-chip LED chip with high stability, which includes:

[0008] (1) Providing a substrate, and forming an N-GaN layer, an MQW layer, and a P-GaN layer on the substrate;

[0009] (2) Using a first photoresist as a mask, etching to form a plurality of first channels, and removing the first photoresist after etching; wherein, the first channels penetrate to the N-GaN layer;

[0010] (3) Using a second photoresist as a mask, etching the first channels in a preset area to form a plurality of second channels; removing the second photoresist after etching; wherein, the second channels penetrate to the substrate;

[0011] (4) Form a current spreading layer on the first channel, the second channel, the substrate, and the P-GaN layer;

[0012] (5) Using a third photoresist as a mask, etch and remove the current spreading layer on the surfaces of the first channel, the second channel, and the substrate, as well as a preset amount of the current spreading layer on the P-GaN layer; after etching, remove the third photoresist;

[0013] (6) Form a passivation protection layer on the first channel, the second channel, the substrate, the P-GaN layer, and the current spreading layer;

[0014] (7) Using a fourth photoresist as a mask, etch and remove the passivation protection layer on the current spreading layer;

[0015] (8) Using a fourth photoresist as a mask, form a metal reflective layer on the current spreading layer, and then remove the fourth photoresist;

[0016] (9) Using a fifth photoresist as a mask, form a metal conductive layer on the metal reflective layer and on the passivation protection layer close to the metal reflective layer, and then remove the fifth photoresist;

[0017] (10) Form a first insulating layer on the passivation protection layer and the metal conductive layer;

[0018] (11) Using a sixth photoresist as a mask, form a third channel at the bottom of the first channel; then remove the sixth photoresist; wherein, the third channel penetrates through the first insulating layer and the passivation protection layer, exposing the N-GaN layer;

[0019] (12) Using a seventh photoresist as a mask, form an N electrode layer at a preset position in the first channel and the first insulating layer, and then remove the seventh photoresist;

[0020] (13) Form a second insulating layer on the N electrode layer and the first insulating layer;

[0021] (14) Using an eighth photoresist as a mask, form a fourth channel and a fifth channel, and then remove the eighth photoresist; the fourth channel penetrates through to the N electrode layer, and the fifth channel penetrates through to the metal conductive layer;

[0022] (15) Using a ninth photoresist as a mask, form a pad layer in the fourth channel and the fifth channel, and then remove the ninth photoresist;

[0023] (16) Grind and thin the substrate, and cleave along the second channel to obtain a finished flip-chip LED chip with high stability.

[0024] As an improvement of the above technical solution, in step (4), the current spreading layer is formed by magnetron sputtering or electron beam evaporation, and the current spreading layer is made of one or more of ITO, IZO, and AZO;

[0025] In step (5), the current spreading layer is etched and removed by using an ITO etching solution.

[0026] As an improvement of the above technical solution, in step (6), the passivation protection layer is formed by magnetron sputtering, electron beam evaporation or PECVD method, and the passivation protection layer is made of one or more of SiO2, SiN x 、SiN x O y The thickness of the passivation protection layer is

[0027] In step (7), the fourth photoresist is a positive photoresist, and the passivation protection layer on the current spreading layer is removed by wet etching, and over-etching is 5-10 μm, so that there is a 5-10 μm gap between both sides of the metal reflective layer and the passivation protection layer, and the film layer angle of the passivation protection layer is 20-40°.

[0028] As an improvement of the above technical solution, in step (8), the metal reflective layer is formed by magnetron sputtering or electron beam evaporation;

[0029] The metal reflective layer includes an Ag layer and a protection layer, and the protection layer is made of one or more of Ti, W, and Pt; the thickness of the metal reflective layer is The film layer angle of the metal reflective layer is 20-40°, and the thickness of the protection layer is

[0030] As an improvement of the above technical solution, in step (9), the metal conductive layer is formed by electron beam evaporation, and the metal conductive layer is made of one or more of Cr, Al, Ti, Pt, and Au; the thickness of the metal conductive layer is The film layer angle of the metal conductive layer is 20-40°.

[0031] As an improvement of the above technical solution, the passivation protection layer includes a SiO2 layer; the metal conductive layer covers a part of the passivation protection layer close to the metal conductive layer, so that the metal conductive layer and the SiO2 layer are combined to form an omnidirectional mirror structure;

[0032] The top layer of the metal conductive layer is a Pt layer and / or a Ni layer; wherein, the thickness of the Pt layer and / or the Ni layer is The Pt layer and / or the Ni layer is a dry etching barrier layer to prevent etching damage to the metal conductive layer by subsequent dry etching techniques.

[0033] As an improvement of the above technical solution, in step (10), the first insulating layer is formed by PECVD method; the first insulating layer is made of one or more of SiO2, SiN x , SiN x O y , Ti2O5; the film layer angle of the first insulating layer is 20 - 40°;

[0034] In step (11), the third channel is formed by ICP etching; wherein, the etching gases are CF4 and O2, and the etching power is 100 - 500 W. Using a lower etching power can achieve the purpose of non-destructive etching of N-type GaN.

[0035] As an improvement of the above technical solution, in step (12), the N electrode layer is formed by electron beam evaporation method, and the N electrode layer is made of one or more of Cr, Al, Ni, Ti, Pt, Au; the film layer angle of the N electrode layer is 20 - 40°;

[0036] In step (13), the second insulating layer is formed by PECVD method; the second insulating layer is made of one or more of SiO2, SiN x , SiN x O y , Ti2O5; the film layer angle of the second insulating layer is 20 - 40°.

[0037] As an improvement of the above technical solution, in step (14), the fourth channel and the fifth channel are formed by ICP etching; wherein, the etching gases are CF4 and O2, and the etching power is 100 - 500 W; using a lower etching power can reduce the etching damage to the top layer of the metal conductive layer which is the Pt layer and / or the Ni layer.

[0038] In step (15), the pad layer is formed by electron beam evaporation method, and the pad layer is made of one or more of Cr, Ni, Ti, Pt, Au, Sn, AuSn.

[0039] Correspondingly, the present invention also discloses a flip-chip LED chip with high stability, which is prepared by the above preparation method.

[0040] Implementing the present invention has the following beneficial effects:

[0041] 1. Preparation method of high-stability flip-chip LED chip. By using a fourth photoresist, a passivation protection layer and a metal reflection layer are simultaneously formed, effectively reducing the number of process steps of the flip-chip LED chip, reducing material consumption, and lowering labor costs. Moreover, through this preparation method, an etching step of the passivation protection layer with a relatively gentle slope (20 - 40°) can be obtained, enabling a smooth transition of the metal conductive layer, and making the distance between the metal mirror and the passivation protection layer 5 - 10 μm (one-sided), solving the problems of the metal mirror climbing and warping caused by depositing the metal mirror on the passivation protection layer, and greatly improving the chip yield and stability.

[0042] 2. Preparation method of high-stability flip-chip LED chip. The method of dry etching is used to etch the passivation protection layer and the first insulating layer together to form a third channel; the dry etching process replaces the wet etching process, which can solve the problems of unstable etching processes such as over-etching and incomplete etching that often occur in the existing wet etching process; the above dry etching process can make the overall etching angle single, and the etching step is relatively gentle (30 - 50°), so as to facilitate the smooth transition of the N electrode layer, avoid the phenomenon of voids and disconnections in the subsequent film layers, improve the stability of the chip. At the same time, the dry etching process can stably produce passivation holes with a smaller aperture, which can further improve the chip brightness.

[0043] 3. Preparation method of high-stability flip-chip LED chip. The method of dry etching is used to etch and remove the first insulating layer and the second insulating layer together to form a fifth channel. This merging technology can significantly reduce production costs, effectively prevent damage to the metal reflection layer caused by wet etching, and the P electrode region fabricated by this technology has a simple structure, a gentle angle, a low void ratio, high solderability, and high overall chip stability.

[0044] 4. Preparation method of high-stability flip-chip LED chip. A metal conductive layer is introduced, which significantly improves the lateral current spreading ability, reduces the chip junction temperature, enhances the chip aging performance, improves the overall chip stability, and can protect the metal mirror from oxidation and damage caused by wet etching, improving the chip AOI yield. At the same time, the metal conductive layer helps to form an ODR structure, which can further improve the chip brightness. Description of the Drawings

[0045] Figure 1 It is a schematic structural diagram of the LED chip after step S1 in the preparation method of the high-stability flip-chip LED chip;

[0046] Figure 2 It is a schematic structural diagram of the LED chip after step S2 in the preparation method of the high-stability flip-chip LED chip;

[0047] Figure 3It is a schematic structural diagram of an LED chip after step S3 in the preparation method of a high-stability flip-chip LED chip;

[0048] Figure 4 It is a schematic structural diagram of an LED chip after step S5 in the preparation method of a high-stability flip-chip LED chip;

[0049] Figure 5 It is a schematic structural diagram of an LED chip after step S7 in the preparation method of a high-stability flip-chip LED chip;

[0050] Figure 6 It is a schematic structural diagram of an LED chip after step S8 in the preparation method of a high-stability flip-chip LED chip;

[0051] Figure 7 It is a schematic structural diagram of an LED chip after step S9 in the preparation method of a high-stability flip-chip LED chip;

[0052] Figure 8 It is a schematic structural diagram of an LED chip after step S11 in the preparation method of a high-stability flip-chip LED chip;

[0053] Figure 9 It is a schematic structural diagram of an LED chip after step S12 in the preparation method of a high-stability flip-chip LED chip;

[0054] Figure 10 It is a schematic structural diagram of an LED chip after step S14 in the preparation method of a high-stability flip-chip LED chip;

[0055] Figure 11 It is a schematic structural diagram of an LED chip after step S15 in the preparation method of a high-stability flip-chip LED chip. Detailed implementation manners

[0056] To make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. It is hereby declared that the directional terms such as up, down, left, right, front, back, inside, outside, etc. that appear or will appear in the present invention are only based on the accompanying drawings of the present invention, and they are not specific limitations on the present invention.

[0057] The present invention discloses a method for preparing a flip-chip LED chip, which includes the following steps:

[0058] S1: Provide a substrate, and form an N-GaN layer, an MQW layer and a P-GaN layer on the substrate;

[0059] Specifically, an N-GaN layer 11, an MQW layer 12 and a P-GaN layer 13 are formed on the substrate 10 by using the MOCVD method, but it is not limited thereto.

[0060] S2: Using the first photoresist as a mask, etch to form a plurality of first channels, and remove the first photoresist after etching;

[0061] Among them, the photoresist is a positive photoresist or a negative photoresist, but not limited thereto. The etching is wet etching or dry etching, but not limited thereto. Preferably, it is ICP etching.

[0062] Specifically, the first channels 14 formed by etching penetrate through to the N-GaN layer 11, exposing the sidewall surfaces of the N-GaN layer 11, the MQW layer 12, and a part of the P-GaN layer 13 (the first sidewalls 141, Figure 2 ).

[0063] S3: Using the second photoresist as a mask, etch the first channels in a preset area to form a plurality of second channels; remove the second photoresist after etching;

[0064] Among them, the second photoresist is a thick photoresist, but not limited thereto; the etching is wet etching or dry etching, but not limited thereto. Preferably, it is ICP etching.

[0065] Specifically, further etch the bottom of the first channels at the subsequent wafer cleavage positions to form second channels 15, and the second channels 15 penetrate through to the substrate 10, exposing the entire sidewall of the P-GaN layer 13 (the second sidewalls 151, Figure 3 ).

[0066] S4: Form a current spreading layer on the first channels, the second channels, the substrate, and the P-GaN layer;

[0067] Among them, a current spreading layer 16 is formed on the first channels 14, the second channels 15, the substrate 10, and the P-GaN layer 13 (i.e., on the entire surface of the substrate obtained in step S3) by electron beam evaporation or magnetron sputtering. The current spreading layer 16 is made of one or more of ITO, IZO, and AZO, but not limited thereto. Preferably, the current spreading layer 16 is an ITO layer.

[0068] S5: Using the third photoresist as a mask, etch and remove the current spreading layer on the surfaces of the first channels, the second channels, and the substrate, and a preset amount of the current spreading layer on the P-GaN layer; remove the third photoresist after etching;

[0069] Among them, the second photoresist is a positive photoresist or a negative photoresist, preferably a positive photoresist. The etching is dry etching or wet etching. Preferably, it is wet etching. Specifically, use chemical solutions such as ITO etchant to etch and remove the current spreading layer 16 in the first channels 14 (including on the first sidewalls 141), in the second channels 15 (including on the second sidewalls 151), on the substrate 10, and a preset amount of the current spreading layer on the P-GaN layer ( Figure 4) Among them, the etched removal amount of the current spreading layer 16 on the P-GaN layer 13 is 1-5% of the width of the P-GaN layer 13. After step S5 is completed, the mask formed by the third photoresist is removed.

[0070] S6: Form a passivation protection layer on the first channel, the second channel, the substrate, the P-GaN layer, and the current spreading layer;

[0071] Among them, a passivation protection layer 17 is integrally formed on the surface of the substrate obtained in step S6 (i.e., inside the first channel 14, inside the second channel 15, on the substrate 10, on the P-GaN layer 13, and on the current spreading layer 16) by magnetron sputtering, electron beam evaporation, or PECVD method. Among them, the passivation protection layer 17 covering the first sidewall 141 and the second sidewall 151 forms a sidewall protection structure 171, which can play a role in blocking metals and prevent the Ag in the subsequent metal reflection layer 18 from migrating to the MQW layer 12 and causing leakage due to the exposure of the MQW layer 12.

[0072] Among them, the passivation protection layer 17 is made of one or more of SiO2, SiN x 、SiN x O y , and its thickness is Using the passivation protection layer with this thickness can reduce the height difference of the chip and improve the stability of the chip. Exemplarily, the thickness of the passivation protection layer 17 is or but not limited thereto. Based on the passivation protection layer 17 with the above composition and thickness, its film layer has good compactness, insulation, and light transmittance.

[0073] S7: Use the fourth photoresist as a mask to etch and remove the passivation protection layer on the current spreading layer;

[0074] Among them, the fourth photoresist is a negative photoresist or a positive photoresist, but not limited thereto; preferably, it is a positive photoresist; it can effectively avoid problems such as large photolithography undercut and unstable process in the negative photoresist process, and the positive photoresist is cheap and the photoresist removal process is relatively simple.

[0075] The etching is dry etching or wet etching, but not limited thereto. Preferably, the etching is wet etching. Specifically, the passivation protection layer 17 on the current spreading layer 16 can be removed by BOE etching solution. Further, by using the wet etching process, the passivation protection layer 17 can be over-etched without damaging the mask formed by the fourth photoresist, that is, part of the passivation protection layer 17 under the mask is removed. Specifically, in an embodiment of the present invention, the over-etching is 5-10 μm, so that there is a gap 2 of 5-10 μm between both sides of the metal reflection layer 18 (current spreading layer 16) and the passivation protection layer 17 (see Figure 5)。This gap 2 can not only prevent the subsequent deposition of the metal reflective layer 18 on the passivation protection layer 17, which may cause phenomena such as the climbing and warping of the metal reflective layer 18, resulting in abnormal metal protrusions at the edge of the passivation protection layer 17 and poor chip ESD yield; but also reserve sufficient space for the subsequent deposition of the metal conductive layer 19 thereon to completely cover the metal reflective layer 18, prevent the migration of Ag in the metal reflective layer 18, and improve the chip stability.

[0076] In addition, through wet etching, it can be ensured that the film layer angles of both the chip passivation protection layer 17 and the metal reflective layer 18 are 20° - 40°, ensuring a smooth transition of the subsequent metal conductive layer 19 that needs to cover the passivation protection layer 17 and the metal reflective layer 18 and other film layers that need to cover the metal conductive layer 19, avoiding phenomena such as voids and disconnections, and improving the chip stability.

[0077] After step S7 is completed, the mask 1 formed by the fourth photoresist is not removed ( Figure 5 ), and directly enter step S8.

[0078] S8: Using the fourth photoresist as a mask, form a metal reflective layer on the current spreading layer, and then remove the fourth photoresist;

[0079] Among them, the metal reflective layer 18 is formed on the current spreading layer 16 by magnetron sputtering or electron beam evaporation, but not limited thereto. The metal reflective layer 18 includes an Ag layer 181 and a protection layer 182, and the protection layer 182 is made of one or more of Ti, W, and Pt. The overall thickness of the metal reflective layer 18 is equivalent to the thickness of the passivation protection layer 17, that is Adopting this solution can reduce the height difference of the chip and improve the chip stability. Among them, the thickness of the protection layer is

[0080] S9: Using the fifth photoresist as a mask, form a metal conductive layer on the metal reflective layer and on the passivation protection layer near the metal reflective layer, and then remove the fifth photoresist;

[0081] Among them, the fifth photoresist is a positive photoresist or a negative photoresist, but not limited thereto. The metal conductive layer 19 is formed by electron beam evaporation. The metal conductive layer 19 is composed of one or more of Cr, Al, Ti, Pt, Au, but not limited thereto. The metal conductive layer 19 can improve the adhesion of the metal reflective layer 18 and reduce the die shedding. Preferably, the metal conductive layer 19 is a laminated structure, which uses Cr or Ti as the bottom layer, and the main body can use laminated structures such as AlTi / AlTi / AlTi, AlTiPt / AlTiPt / AlTiPt, etc. The metal conductive layer with this structure can effectively reduce the metal stress, reduce the film porosity, and improve the chip stability; at the same time, the Al layer of the metal conductive layer 19 and the SiO2 layer of the passivation protection layer 17 form an omnidirectional mirror structure, which further improves the chip brightness; it also ensures that the angle of the metal conductive layer 19 film is gentle, about 20-40°, so as to avoid the phenomenon of voids and disconnections in the subsequent film during this transition, and improve the chip stability. Further, in another preferred embodiment of the present invention, in the laminated structure of the metal conductive layer 19, the top layer uses a Pt layer and / or a Ni layer, and this top layer can play a role in blocking dry etching; thus blocking the damage to the metal conductive layer 19 during the subsequent dry etching process.

[0082] Among them, the position where the metal conductive layer 19 is formed is on the metal reflective layer and on the passivation protection layer close to the metal reflective layer. That is, the metal conductive layer 19 completely covers the metal reflective layer 18 and covers a part of the passivation protection layer 17 ( Figure 7 ), specifically, the coverage amount is 1-3% of the area of the passivation protection layer 17. Based on this structure, it not only effectively protects the metal reflective layer 18 from oxidation, damage by wet etching, and prevents Ag migration in the metal reflective layer 18 to improve the chip stability. Moreover, the metal conductive layer 19 can play a role in improving the current lateral expansion ability, that is, when the current passes through the metal conductive layer 19, it will first laterally expand inside the metal conductive layer 19 to all areas covered by the metal conductive layer 19, and then vertically expand downward into the metal reflective layer 18 and then vertically expand into the current expansion layer 16 below the metal reflective layer 18, which can make up for the disadvantage of the poor internal lateral expansion ability of the metal reflective layer 18 under large current conditions, improve the large current lateral expansion ability of the chip, increase the current expansion uniformity, and further reduce the chip junction temperature and improve the chip aging performance.

[0083] Preferably, in an embodiment of the present invention, the passivation protection layer 17 includes a SiO2 layer, and the metal conductive layer 19 and the SiO2 layer form an omnidirectional mirror structure, which further improves the light output efficiency in the area without the metal reflective layer 18 and improves the chip brightness.

[0084] S10: Form a first insulating layer on the passivation protection layer and the metal conductive layer;

[0085] Wherein, a first insulating layer 20 is formed on the surface of the substrate 10 obtained in step S9 by PECVD (i.e., on the passivation protection layer 17 and the metal conductive layer 19), and the first insulating layer 20 is made of one or more of SiO2, SiN x SiN x O y Ti2O5, and the formed first insulating layer 20 has a dense film, good insulation and high light transmittance.

[0086] S11: Using the sixth photoresist as a mask, a third channel is formed at the bottom of the first channel, and then the sixth photoresist is removed;

[0087] Wherein, the sixth photoresist can be a positive photoresist or a negative photoresist. The etching process is wet etching or dry etching. Preferably, it is ICP dry etching. Wherein, the etching gas is CF4 and O2. The formed third channel 21 penetrates through the first insulating layer 20 and the passivation protection layer 17, exposing the N-GaN layer 11( Figure 8 ).

[0088] Specifically, in this step, the etching power needs to be controlled within a suitable range; too high etching power will lead to too high etching rate and etching damage to the N-type GaN layer, resulting in the problem of voltage increase, while too low etching power will result in small etching rate, long process time and low efficiency; the etching power is generally controlled at 100W-500W, or in the way of multi-stage etching power, such as the two-stage type of high power in the early stage + low power in the later stage, that is, the etching of the first insulating layer 20 uses high power etching (400-500W), and the etching of the passivation protection layer 17 close to the N-GaN layer uses low power etching (100-150W); further, when etching with low power, the etching rate can be further reduced by means of increasing the O2 flow rate and reducing the CF4 flow rate, etc., to achieve non-destructive etching of the N-GaN layer 11 and ensure the normal chip voltage.

[0089] In step S11 of the present invention, the first insulating layer 20 and the passivation protection layer 17 are etched simultaneously, and this process is called the "merged" dry etching process. This "merged" dry etching process not only avoids the problems of unstable etching processes such as over-etching and incomplete etching that often occur in the BOE wet etching process, but also avoids the phenomenon of different etching angles when the first insulating layer 20 and the passivation protection layer 17 are etched separately by BOE, resulting in voids and disconnections when the subsequent film layers transition here, improving the chip stability. The "merged" dry etching process is stable, and the etching angle produced by this process is relatively gentle (30-50°), which can further make the subsequent N electrode layer 22 transition smoothly here, improving the chip stability. At the same time, the dry etching process can stably produce a third channel with a smaller aperture (5-20μm), so as to further increase the light-emitting area of the chip and improve the brightness.

[0090] S12: Using the seventh photoresist as a mask, form the N electrode layer at the preset positions of the first channel and the first insulating layer, and then remove the seventh photoresist;

[0091] Among them, the seventh photoresist is a positive photoresist or a negative photoresist. The N electrode layer 22 is formed by electron beam evaporation. The N electrode layer 22 is formed at the preset positions of the first channel 14 and the first insulating layer 20 ( Figure 9 ). Specifically, the preset positions refer to other areas except for a circular hole reserved in the middle of every 4 adjacent first channels 14 within the chip P electrode region. The N electrode layer distributed in this way will make the chip current expansion more uniform, reduce the chip voltage, and further improve the chip heat dissipation.

[0092] Among them, the N electrode layer 22 is made of one or several of Cr, Al, Ni, Ti, Pt, and Au. Preferably, the N electrode layer 22 is a laminated structure, and its bottom layer metal uses Cr and / or Ti, which can ensure good adhesion between the bottom layer metal of the N electrode layer 22 and the metal conductive layer 19 and the N-GaN layer 11 in the middle part of the chip. The middle structure can adopt forms such as AlTi / AlTi / AlTi / ... etc., but is not limited to this. The metal laminated structure can enhance the flexibility of the metal layer, reduce the overall internal stress of the metal layer; it can also make full use of the advantages and disadvantages of the laminated metals, improve the conductivity, and reduce the cost. Further preferably, the top layer of the laminated structure uses Pt and / or Ni, which can block the etching damage of the N electrode layer 22 by the subsequent second "merging" dry etching technology.

[0093] Specifically, the film layer angle of the N electrode layer 22 is 20 - 40°, which can avoid the phenomenon of voids and disconnections when the subsequent film layers transition here, and improve the chip stability.

[0094] S13: Form the second insulating layer on the N electrode layer and the first insulating layer;

[0095] Among them, the second insulating layer 23 is formed on the substrate obtained in step S12 (that is, on the N electrode layer 22 and the first insulating layer 20) by PECVD. The second insulating layer 23 is made of one or more of SiO2, SiN x 、SiN x O y 、Ti2O5. This kind of second insulating layer 23 has a dense film layer, good insulation and high light transmittance.

[0096] S14: Using the eighth photoresist as a mask, form the fourth channel and the fifth channel, and then remove the eighth photoresist;

[0097] Among them, the eighth photoresist is a positive photoresist or a negative photoresist, preferably a positive photoresist. The fourth channel and the fifth channel are formed by a dry etching process. Specifically, the fourth channel 24 penetrates through to the N electrode layer 22, and the fifth channel 25 penetrates through to the metal conductive layer 19. The fifth channel 25 serves as a P electrode window ( Figure 10 ).

[0098] Among them, the etching gas used in the dry etching process is CF4 and O2, and the etching power is 100-500W. Through the above dry etching process, openings are simultaneously made in the first insulating layer 20 and the second insulating layer 23 on the metal conductive layer 19. This process is called the second "merging" dry etching technique. This second "merging" dry etching technique shortens the process time, saves materials, reduces labor costs, improves the ESD yield, and enhances the stability of the chip. Specifically, this second "merging" dry etching technique can effectively prevent damage to the metal reflective layer 18 by wet etching, avoid chip structure damage, and improve chip stability; and the P electrode region fabricated by this technique is extremely simple. The film layer angles of the first insulating layer 20 and the second insulating layer 23 on the metal conductive layer 19 are the same and gentle at 20-40°, which can avoid the phenomenon of voids and disconnections when the subsequent film layers transition here, and improve chip stability. In addition, the chiplet fabricated by this technique has a one-way slope, which helps the flow of the solder flux, improves the chip soldering process, greatly reduces the chip void rate, and improves the solderability of the chip.

[0099] Furthermore, since the surfaces of the metal conductive layer 19 and the N electrode layer 22 of the present invention both use Pt and / or Ni as dry etching barrier layers, it can effectively protect other structures of the metal lower layer from being damaged by dry etching. Therefore, the present invention can adopt a multi-stage etching method, for example, a method of high power in the early stage + low power in the later stage. Exemplarily, when etching the second insulating layer 23, high power (400-500W) is used; when etching the first insulating layer 20, low power (100-150W) is used. Based on the above process, the production efficiency can be further improved.

[0100] S15: Using the ninth photoresist as a mask, a pad layer is formed in the fourth channel and the fifth channel, and then the ninth photoresist is removed;

[0101] Among them, the ninth photoresist is a positive photoresist or a negative photoresist. By means of electron beam evaporation, a pad layer is formed in the fourth channel 24 and the fifth channel 25. Specifically, the pad layer includes a first pad layer 26 and a second pad layer 27. Among them, the first pad layer 26 is electrically connected to the N electrode layer 22, and the second pad layer 27 is electrically connected to the metal conductive layer 19.

[0102] Specifically, the pad layer is made of one or more of metal elements with good electrical conductivity such as Cr, Ni, Ti, Pt, Au, Sn, AuSn, etc. Preferably, the pad layer is a laminated structure, and its bottom layer uses Cr and / or Ti to enhance adhesion. The intermediate laminated structure can be TiPt / TiPt / TiPt / ..., but is not limited thereto. The metal laminated structure can enhance the flexibility of the pad layer, reduce the overall internal stress of the pad layer; and can also make full use of the advantages and disadvantages of the laminated metals, improve electrical conductivity, and reduce costs.

[0103] S16: Grind and thin the substrate, and cleave along the second channel to obtain a high-stability flip-chip LED chip product.

[0104] In summary, based on the preparation method of the present invention, first, the passivation protection layer and the metal reflection layer are simultaneously formed by the fourth photoresist, effectively reducing the number of process steps of the flip-chip LED chip, reducing material consumption, and reducing labor costs. And through this preparation method, a passivation protection layer etching step with a relatively gentle slope (20-40°) can be obtained, enabling a smooth transition of the metal conductive layer, and greatly improving the chip yield and stability. Secondly, the dry etching method is used to etch the passivation protection layer and the first insulating layer together to form the third channel; this process can make the overall etching step relatively gentle (30-50°), facilitating the smooth transition of the N electrode layer, avoiding the phenomenon of voids and disconnections in the subsequent film layers, improving the stability of the chip. At the same time, the dry etching process can stably produce passivation holes with a smaller aperture, further improving the chip brightness. Furthermore, the dry etching method is used to etch and remove the first insulating layer and the second insulating layer together to form the fifth channel. This combined technology can significantly reduce production costs, effectively prevent damage to the metal reflection layer by wet etching, and the P electrode region fabricated by this technology has a simple structure, a gentle angle, a low void ratio, high solderability, and high overall chip stability. Finally, the present invention introduces a metal conductive layer, which can improve the lateral current spreading ability, reduce the chip junction temperature, improve the chip aging performance, enhance the overall chip stability, protect the metal mirror from oxidation and damage by wet etching, improve the chip AOI yield, and at the same time the metal conductive layer helps to form an ODR structure, further improving the chip brightness.

[0105] The above is the preferred implementation manner of the invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements are also regarded as the protection scope of the present invention.

Claims

1. A preparation method of a high-stability flip-chip LED chip, characterized in that, Comprising: (1) Providing a substrate, and forming an N-GaN layer, an MQW layer, and a P-GaN layer on the substrate; (2) Using a first photoresist as a mask, etching to form a plurality of first channels, and removing the first photoresist after etching; wherein, the first channels penetrate through to the N-GaN layer; (3) Using a second photoresist as a mask, etching the first channels in a preset area to form a plurality of second channels; removing the second photoresist after etching; wherein, the second channels penetrate through to the substrate; (4) Forming a current spreading layer on the first channels, second channels, substrate, and P-GaN layer; (5) Using a third photoresist as a mask, etching to remove the current spreading layer on the surfaces of the first channels, second channels, and substrate, and a preset amount of the current spreading layer on the P-GaN layer; removing the third photoresist after etching; (6) Forming a passivation protection layer on the first channels, second channels, substrate, P-GaN layer, and current spreading layer; wherein, the passivation protection layer is formed by magnetron sputtering, electron beam evaporation, or PECVD, the passivation protection layer is made of SiO2, and the thickness of the passivation protection layer is 2000 - 5000 Å; (7) Using a fourth photoresist as a mask, etching to remove the passivation protection layer on the current spreading layer; wherein, the fourth photoresist is a positive photoresist, and the passivation protection layer on the current spreading layer is removed by wet etching, and over-etching is 5 - 10 μm, so that there is a gap with a width of 5 - 10 μm between both sides of the metal reflective layer and the passivation protection layer, and the film layer angle of the passivation protection layer is 20 - 40°; (8) Using a fourth photoresist as a mask, forming a metal reflective layer on the current spreading layer, and then removing the fourth photoresist; (9) Using a fifth photoresist as a mask, forming a metal conductive layer on the metal reflective layer and on the passivation protection layer close to the metal reflective layer, and then removing the fifth photoresist; wherein, the metal conductive layer covers a part of the passivation protection layer close to the metal reflective layer, so that the metal conductive layer and the passivation protection layer are combined to form an omnidirectional mirror structure; the top layer of the metal conductive layer is a Pt layer and / or a Ni layer; (10) Forming a first insulating layer on the passivation protection layer and the metal conductive layer; (11) Using a sixth photoresist as a mask, forming a third channel at the bottom of the first channel; and then removing the sixth photoresist; wherein, the third channel penetrates through the first insulating layer and the passivation protection layer, exposing the N-GaN layer; (12) Using a seventh photoresist as a mask, forming an N electrode layer at a preset position in the first channel and the first insulating layer, and then removing the seventh photoresist; (13) Forming a second insulating layer on the N electrode layer and the first insulating layer; (14) Using an eighth photoresist as a mask, forming a fourth channel and a fifth channel, and then removing the eighth photoresist; the fourth channel penetrates through to the N electrode layer, and the fifth channel penetrates through to the metal conductive layer; (15) Using a ninth photoresist as a mask, forming a pad layer in the fourth channel and the fifth channel, and then removing the ninth photoresist; (16)Grind and thin the substrate, and cleave along the second channel to obtain a finished flip-chip LED chip with high stability.

2. The preparation method according to claim 1, characterized in that, In step (4), the current spreading layer is formed by magnetron sputtering or electron beam evaporation, and the current spreading layer is made of one or more of ITO, IZO, and AZO; In step (5), the current spreading layer is etched and removed by using an ITO etching solution.

3. The preparation method according to claim 1, characterized in that, In step (8), the metal reflective layer is formed by magnetron sputtering or electron beam evaporation; The metal reflective layer includes an Ag layer and a protective layer, and the protective layer is made of one or more of Ti, W, and Pt; the thickness of the metal reflective layer is 2000 - 5000 Å, the film layer angle of the metal reflective layer is 20 - 40°, and the thickness of the protective layer is 1000 - 3000 Å.

4. The preparation method according to claim 1, characterized in that, In step (9), the metal conductive layer is formed by electron beam evaporation, and the metal conductive layer is made of one or more of Cr, Al, Ti, Pt, and Au; the thickness of the metal conductive layer is 10000 - 20000 Å; the film layer angle of the metal conductive layer is 20 - 40°.

5. The preparation method according to claim 1, characterized in that, In step (10), the first insulating layer is formed by PECVD; the first insulating layer is made of one or more of SiO2, SiN x , SiN x O y , and Ti2O5; the film layer angle of the first insulating layer is 20 to 40°; In step (11), the third channel is formed by ICP etching; wherein, the etching gas is CF4 and O2, and the etching power is 100 - 500 W.

6. The preparation method according to claim 1, characterized in that, In step (12), the N electrode layer is formed by electron beam evaporation, and the N electrode layer is made of one or more of Cr, Al, Ni, Ti, Pt, and Au; the film layer angle of the N electrode layer is 20 - 40°; In step (13), the second insulating layer is formed by PECVD; the second insulating layer is made of one or more of SiO2, SiN x , SiN x O y , and Ti2O5; the film angle of the second insulating layer is 20 to 40°.

7. The preparation method according to claim 3, characterized in that, In step (14), the fourth channel and the fifth channel are formed by ICP etching; wherein, the etching gas is CF4 and O2, and the etching power is 100 - 500 W; In step (15), the pad layer is formed by electron beam evaporation, and the pad layer is made of one or more of Cr, Ni, Ti, Pt, Au, Sn, and AuSn.

8. A high-stability flip-chip LED chip, characterized in that, It is prepared by the preparation method according to any one of claims 1 - 7.

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