Surface-emitting semiconductor light emitting device

Abstract

A surface-emitting semiconductor light emitting device is provided, which has improved light output. The surface-emitting semiconductor light emitting device has a first semiconductor layer; a light emitting layer provided on the first semiconductor layer; a second semiconductor layer provided on the light emitting layer; a concavo-convex structure provided on the second semiconductor layer; a first metal layer covering the concavo-convex structure; and a second metal layer provided between the concavo-convex structure and the first metal layer. The second metal layer is provided on one of a bottom surface of a concave portion, an upper surface of a convex portion, and a side surface of the convex portion of the concavo-convex structure. The reflectivity of the second metal layer with respect to light emitted from the light emitting layer is lower than the reflectivity of the first metal layer with respect to the light.

Description

TECHNICAL FIELD

[0001] The present application relates to a surface-emission type semiconductor light emitting device. BACKGROUND

[0002] A surface-emission type semiconductor light emitting device is required to have high light output.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT DOCUMENTS

[0005] Patent Document 1: Japanese Patent Application Publication No. 2020-68330 SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] The present application provides a surface-emission type semiconductor light emitting device having improved light output.

[0008] MEANS FOR SOLVING THE PROBLEMS

[0009] A surface-emission type semiconductor light emitting device according to an embodiment has a first semiconductor layer, a light emitting layer provided on the first semiconductor layer, a second semiconductor layer provided on the light emitting layer, a concavo-convex structure provided on the second semiconductor layer, a first metal layer covering the concavo-convex structure, and a second metal layer provided between the concavo-convex structure and the first metal layer. The second metal layer is provided on one of a bottom surface of a concave portion, an upper surface of a convex portion, and a side surface of the convex portion of the concavo-convex structure. The reflectance of the second metal layer with respect to light emitted from the light emitting layer is lower than the reflectance of the first metal layer with respect to the light. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a schematic cross-sectional view showing a surface-emission type semiconductor light emitting device according to an embodiment.

[0011] Figure 2 is a schematic oblique view showing a surface-emission type semiconductor light emitting device according to an embodiment.

[0012] Figure 3 is a schematic cross-sectional view showing a structure of a photonic crystal of a surface-emission type semiconductor light emitting device according to an embodiment.

[0013] Figure 4 is a schematic cross-sectional view showing a method of manufacturing a photonic crystal according to an embodiment.

[0014] Figure 5 is a schematic cross-sectional view showing a method of manufacturing a photonic crystal according to a first modified example of the embodiment.

[0015] Figure 6This is a schematic cross-sectional view showing a method for manufacturing a photonic crystal according to a second variation of the embodiment.

[0016] Figure 7 This is a schematic cross-sectional view showing a method for manufacturing a photonic crystal according to a third variation of the embodiments.

[0017] Figure 8 This is a schematic cross-sectional view of a photonic crystal representing a modified example of the implementation method.

[0018] Figure 9 This is a schematic cross-sectional view of a surface-emitting semiconductor light-emitting device, showing a variation of the embodiment. Detailed Implementation

[0019] The following is a reference to the appendix. Figure 1 The implementation method will be described below. Identical parts in the figures will be given the same reference numerals, and detailed descriptions will be omitted where appropriate; different parts will be described. Furthermore, the figures are schematic or conceptual, and the relationship between the thickness and width of each part, the proportions between parts, etc., may not necessarily be the same as in reality. Moreover, even when representing the same parts, there may be cases where the dimensions or proportions are shown differently depending on the figures.

[0020] Furthermore, the configuration and structure of each part are explained using the X, Y, and Z axes shown in each figure. The X, Y, and Z axes are orthogonal to each other, representing the X, Y, and Z directions, respectively. Additionally, there are cases where the Z direction is set as upward and its opposite direction as downward in the explanation.

[0021] Figure 1 This is a schematic cross-sectional view showing a surface-emitting semiconductor light-emitting device 1 according to an embodiment. The surface-emitting semiconductor light-emitting device 1 is, for example, a surface-emitting QCL (Quantum Cascade Laser).

[0022] The surface-emitting semiconductor light-emitting device 1 has a semiconductor substrate 10, a first semiconductor layer 20, a light-emitting layer 30, a second semiconductor layer 40, a third semiconductor layer 50, a surface electrode 60, an insulating film 70, and a back electrode 80.

[0023] The semiconductor substrate 10 is, for example, an n-type InP substrate. Alternatively, the semiconductor substrate 10 may also be an n-type GaAs substrate.

[0024] The first semiconductor layer 20 is disposed on the semiconductor substrate 10. The first semiconductor layer 20 is, for example, an n-type InP layer. A buffer layer may be disposed between the semiconductor substrate 10 and the first semiconductor layer 20.

[0025] The light emitting layer 30 is provided on the first semiconductor layer 20. The light emitting layer 30 has, for example, a quantum well structure that generates a subband transition of a carrier. The light emitting layer 30 contains, for example, an n-type III-V compound semiconductor doped with silicon, and emits light by a subband transition of an electron.

[0026] The light emitting layer 30 has, for example, a quantum well structure in which the quantum well layer 33 and the barrier layer 35 are alternately stacked in a direction orthogonal to the upper surface of the first semiconductor layer 20, for example, the Z direction. The quantum well layer 33 is composed of, for example, a first compound semiconductor (InGaAs), and the barrier layer 35 is composed of, for example, a second compound semiconductor (AlInAs).

[0027] Here, InGaAs is a compound semiconductor represented by the composition formula In x Ga 1－x As (0 < x < 1). Further, AlInAs is another compound semiconductor represented by the composition formula Al y In 1－y As (0 < y < 1).

[0028] The light emitting layer 30 includes, for example, a light emitting multi-quantum well region composed of the first compound semiconductor and the second compound semiconductor, and an injection multi-quantum well region composed of the first compound semiconductor and the second compound semiconductor. Further, the light emitting layer 30 has a structure in which pairs of the light emitting multi-quantum well region and the injection multi-quantum well region are stacked in multiple layers.

[0029] The second semiconductor layer 40 is provided on the light emitting layer 30. The second semiconductor layer 40 is, for example, an n-type InP layer.

[0030] The third semiconductor layer 50 is provided on the second semiconductor layer 40. The third semiconductor layer 50 is, for example, an n-type InGaAs layer. A photonic crystal (PC) is provided in the third semiconductor layer 50. The photonic crystal (hereinafter referred to as PC 50f) includes a concave-convex structure having a certain periodicity. The PC 50f guides light radiated from the light emitting layer 30 in a direction perpendicular to the upper surface of the semiconductor substrate 10.

[0031] The PC 50f has a function of selecting a wavelength and controlling an emission angle of laser light as a photonic crystal. According to the design of the PC 50f, light of a desired wavelength resonates within the light emitting layer 30, and laser light oscillates. The laser light is emitted in a direction substantially perpendicular to the boundary between the light emitting layer 30 and the first semiconductor layer 20. "Substantially perpendicular" here means that the angle with respect to the boundary between the light emitting layer 30 and the first semiconductor layer 20 is 81° or more and 99° or less.

[0032] The PC 50f is a two-dimensional diffraction grating, for example, having a plurality of recesses arranged periodically. The recesses of the PC 50f have a shape of a right triangle, for example, in a plan view of the third semiconductor layer 50. In addition, the shape and arrangement of the recesses or protrusions are not limited to the example shown here.

[0033] The surface electrode 60 is provided on the third semiconductor layer 50. The surface electrode 60 covers the PC 50f. The surface electrode 60 reflects light radiated from the light-emitting layer 30.

[0034] The surface-emitting semiconductor light-emitting device 1 has a mesa structure including the first semiconductor layer 20, the light-emitting layer 30, the second semiconductor layer 40, and the third semiconductor layer 50. The insulating film 70 covers the side surface of the mesa structure. The insulating film 70 is, for example, a silicon oxide film. In addition, the insulating film 70 covers the surface of the semiconductor substrate 10 through a portion of the first semiconductor layer 20.

[0035] The back surface electrode 80 is provided on the back surface 10B of the semiconductor substrate 10. The back surface electrode 80 includes, for example, a titanium (Ti) layer 81 and a gold (Au) layer 83. The Ti layer 81 is provided between the semiconductor substrate 10 and the Au layer 83.

[0036] The surface-emitting semiconductor light-emitting device 1 injects carriers (electrons) into the light-emitting layer 30 by causing a current to flow between the surface electrode 60 and the back surface electrode 80. The light-emitting layer 30 generates QCL light by light generated by energy relaxation of carriers at the quantum well layer 33 and stimulated emission by light guided through the PC 50f. The QCL light is radiated from the back surface 10B of the semiconductor substrate 10 to the outside. The wavelength of the QCL light is, for example, 4.5 micrometers (μm).

[0037] Figure 2 (a) of FIG. 1 is a schematic view of the surface-emitting semiconductor light-emitting device 1 according to the embodiment. Figure 2 (b) of FIG. 1 is a schematic view of the surface-emitting semiconductor light-emitting device 1 according to the embodiment. Figure 2 (a) of FIG. 1 is a schematic view of the surface-emitting semiconductor light-emitting device 1 according to the embodiment. Figure 2 (b) of FIG. 1 is a schematic view of the surface-emitting semiconductor light-emitting device 1 according to the embodiment.

[0038] As shown in (a) of FIG. 1, QCL light is radiated from the back surface 10B of the semiconductor substrate 10. The back surface electrode 80 is provided in a manner of surrounding a region from which the QCL light is radiated. Figure 2

[0039] As shown in (b) of FIG. 1, a mesa-shaped light-emitting region LER is provided on the surface side of the semiconductor substrate 10. The insulating film 70 is formed in a manner of covering the side surface of the light-emitting region LER and the surface side of the semiconductor substrate 10. Figure 3

[0040] ​​The light emitting region LER includes the first semiconductor layer 20, the light emitting layer 30, the second semiconductor layer 40, and the third semiconductor layer 50. The surface electrode 60 is provided at the upper surface of the light emitting region LER in a manner of covering the PC 50f. The upper surface of the light emitting region LER has, for example, a shape of a square with a length of one side of 500 μm.

[0041] Figure 3 (a) to (c) of FIG. 10 Figure 3 (c) is a schematic cross-sectional view illustrating a configuration of the PC 50f of the surface-emitting semiconductor light emitting device 1 according to the embodiment. The PC 50f has Figure 3 (a) to (c) of FIG. 10 Figure 3 (c) of FIG. 10.

[0042] The PC 50f is provided at the upper surface of the third semiconductor layer 50 on the side opposite to the second semiconductor layer 40. The PC 50f includes the protruding portions 50a and the recessed portions 50b. The protruding portions 50a are provided in plurality, and the recessed portions 50b are provided between the adjacent protruding portions 50a. The plurality of protruding portions 50a are arranged in a direction along the upper surface of the second semiconductor layer 40, for example, the X direction. The protruding portions 50a are arranged in the X direction at a certain period. Further, the protruding portions 50a are also arranged in a Y direction not shown at a certain period. The period width of the protruding portions 50a in the X direction and the Y direction is, for example, shorter than the wavelength of the QCL light, respectively.

[0043] The surface electrode 60 includes the first metal layer 63 and the second metal layer 65, and covers the PC 50f. The first metal layer 63 is, for example, an Au layer. The second metal layer 65 is, for example, a Ti layer. The second metal layer 65 can also be, for example, a nickel (Ni) layer or a chromium (Cr) layer.

[0044] The second metal layer 65 is provided between the third semiconductor layer 50 and the first metal layer 63. The adhesion strength of the second metal layer 65 to the third semiconductor layer 50 is higher than the adhesion strength of the first metal layer 63 to the third semiconductor layer 50. In other words, the adhesion strength of the second metal layer 65 to the concave-convex configuration including the protruding portions 50a and the recessed portions 50b is higher than the adhesion strength of the first metal layer 63 to the concave-convex configuration.

[0045] If the layer thickness of the second metal layer 65 is thinned, the adhesion strength to the concave-convex configuration decreases. For example, if the layer thickness of the Ti layer becomes 25 nanometers (nm) or less, the adhesion strength of the second metal layer 65 to the concave-convex configuration is insufficient.

[0046] On the other hand, the reflectivity of the first metal layer 63 to the QCL light emitted from the light emitting layer 30 is higher than the reflectivity of the second metal layer 65 to the QCL light. That is, the absorption rate of the QCL light by the second metal layer 65 is higher than the absorption rate of the QCL light by the first metal layer 63.

[0047] For example, in a case where the layer thickness of the Ti layer (the second metal layer 65) is 50 nm, the reflectance of the electrode in which the Ti layer and the Au layer (the first metal layer 63) are stacked with respect to QCL light is 40% lower than the reflectance of the electrode in which the Au layer is not sandwiched by the Ti layer.

[0048] In Figure 3 In the example shown in (a) of FIG. 10, the second metal layer 65 is provided on the upper surface of the convex portion 50a, and is not provided on the side surface of the convex portion 50a and the bottom surface of the concave portion 50b. The layer thickness of the second metal layer 65 is, for example, 50 nm. Further, the first metal layer 63 is in contact with the side surface of the convex portion 50a and the bottom surface of the concave portion 50b. For example, compared to a case where the layer thickness of the second metal layer 65 is set to 50 nm and the second metal layer 65 is provided so as to cover the entire surface of the concave-convex structure, Figure 3 The reflectance of the surface electrode 60 shown in (a) of FIG. 10 is increased by about 20%.

[0049] In Figure 3 In the example shown in (b) of FIG. 10, the second metal layer 65 is provided on the bottom surface of the concave portion 50b, and is not provided on the upper surface and the side surface of the convex portion 50a. The layer thickness of the second metal layer 65 is, for example, 50 nm. The first metal layer 63 is in contact with the upper surface and the side surface of the convex portion 50a. In this example, the reflectance of the surface electrode 60 can also be increased by about 20% compared to a case where the second metal layer 65 is provided so as to cover the entire surface of the concave-convex structure.

[0050] In Figure 3 In the example shown in (c) of FIG. 10, the second metal layer 65 is provided on the side surface of the convex portion 50a, and is not provided on the upper surface of the convex portion 50a and the bottom surface of the concave portion 50b. The layer thickness of the second metal layer 65 is, for example, 50 nm. The first metal layer 63 is in contact with the upper surface of the convex portion 50a and the bottom surface of the concave portion 50b. In this example, the reflectance of the surface electrode 60 can also be increased compared to a case where the second metal layer 65 is provided so as to cover the entire surface of the concave-convex structure.

[0051] Further, in the example shown in (a) of FIG. 10 and Figure 4 the example shown in (c) of FIG. 10, by partially providing the second metal layer 65, the effective refractive index difference between the convex portion 50a and the concave portion 50b of the PC 50f can be increased. Thereby, the function of the PC 50f can be improved. Figure 4

[0052] (a) and Figure 4 (b) of FIG. 10 are schematic cross-sectional views showing a manufacturing method of the PC 50f according to the embodiment. Figure 4 As

[0053] Figure 3 ​As shown in (a) of FIG. 6, a plurality of second metal layers 65 are formed over the third semiconductor layer 50. The second metal layers 65 are, for example, arranged with a certain periodicity in the X direction and the Y direction along the upper surface of the third semiconductor layer 50, respectively.

[0054] As shown in (a) of FIG. 6, a plurality of second metal layers 65 are formed over the third semiconductor layer 50. The second metal layers 65 are, for example, arranged with a certain periodicity in the X direction and the Y direction along the upper surface of the third semiconductor layer 50, respectively. Figure 5 As shown in (b) of FIG. 6, the second metal layers 65 are used as etching masks to selectively remove the third semiconductor layer 50, thereby forming the convex portions 50a and the concave portions 50b. Subsequently, the first metal layer 63 is formed so as to cover the second metal layers 65 and the inner surfaces of the concave portions 50b. Thus, the PC 50f and the surface electrode 60 shown in (c) of FIG. 6 can be formed. Figure 5 As shown in (a) of FIG. 6, a plurality of second metal layers 65 are formed over the third semiconductor layer 50. The second metal layers 65 are, for example, arranged with a certain periodicity in the X direction and the Y direction along the upper surface of the third semiconductor layer 50, respectively.

[0055] Figure 5 As shown in (a) of FIG. 6, a plurality of second metal layers 65 are formed over the third semiconductor layer 50. The second metal layers 65 are, for example, arranged with a certain periodicity in the X direction and the Y direction along the upper surface of the third semiconductor layer 50, respectively. Figure 5 As shown in (c) of FIG. 6, the second metal layers 65 formed over the etching mask 53 are removed together with the etching mask 53. Thus, the second metal layers 65 can be left on the bottom surfaces of the concave portions 50b, while the upper surfaces and the side surfaces of the convex portions 50a are exposed.

[0056] As shown in (a) of FIG. 6, a plurality of second metal layers 65 are formed over the third semiconductor layer 50. The second metal layers 65 are, for example, arranged with a certain periodicity in the X direction and the Y direction along the upper surface of the third semiconductor layer 50, respectively. Figure 5 As shown in (a) of FIG. 6, a plurality of second metal layers 65 are formed over the third semiconductor layer 50. The second metal layers 65 are, for example, arranged with a certain periodicity in the X direction and the Y direction along the upper surface of the third semiconductor layer 50, respectively.

[0057] As shown in (a) of FIG. 6, a plurality of second metal layers 65 are formed over the third semiconductor layer 50. The second metal layers 65 are, for example, arranged with a certain periodicity in the X direction and the Y direction along the upper surface of the third semiconductor layer 50, respectively. Figure 3 As shown in (b) of FIG. 6, the second metal layers 65 are formed over the third semiconductor layer 50. The second metal layers 65 are, for example, formed using a deposition method such as vacuum evaporation, which has a high directivity. Thus, the second metal layers 65 are formed over the etching mask 53 and on the bottom surfaces of the concave portions 50b. In this process, deposition of the second metal layers 65 onto the side surfaces of the convex portions 50a is suppressed.

[0058] As shown in (c) of FIG. 6, the second metal layers 65 formed over the etching mask 53 are removed together with the etching mask 53. Thus, the second metal layers 65 can be left on the bottom surfaces of the concave portions 50b, while the upper surfaces and the side surfaces of the convex portions 50a are exposed. Figure 6 As shown in (c) of FIG. 6, the second metal layers 65 formed over the etching mask 53 are removed together with the etching mask 53. Thus, the second metal layers 65 can be left on the bottom surfaces of the concave portions 50b, while the upper surfaces and the side surfaces of the convex portions 50a are exposed.

[0059] As shown in (b) of FIG. 6, the second metal layers 65 are used as etching masks to selectively remove the third semiconductor layer 50, thereby forming the convex portions 50a and the concave portions 50b. Subsequently, the first metal layer 63 is formed so as to cover the second metal layers 65 and the inner surfaces of the concave portions 50b. Thus, the PC 50f and the surface electrode 60 shown in (c) of FIG. 6 can be formed. Figure 6 As shown in (a) of FIG. 6, a plurality of second metal layers 65 are formed over the third semiconductor layer 50. The second metal layers 65 are, for example, arranged with a certain periodicity in the X direction and the Y direction along the upper surface of the third semiconductor layer 50, respectively.

[0060] Figure 6 As shown in (a) of FIG. 6, a plurality of second metal layers 65 are formed over the third semiconductor layer 50. The second metal layers 65 are, for example, arranged with a certain periodicity in the X direction and the Y direction along the upper surface of the third semiconductor layer 50, respectively. Figure 5 As shown in (c) of FIG. 6, the second metal layers 65 formed over the etching mask 53 are removed together with the etching mask 53. Thus, the second metal layers 65 can be left on the bottom surfaces of the concave portions 50b, while the upper surfaces and the side surfaces of the convex portions 50a are exposed.

[0061] As shown in (a) of FIG. 6, a plurality of second metal layers 65 are formed over the third semiconductor layer 50. The second metal layers 65 are, for example, arranged with a certain periodicity in the X direction and the Y direction along the upper surface of the third semiconductor layer 50, respectively. Figure 6The second metal layer 65 is formed so as to cover the convex portions 50a and the concave portions 50b as shown in (a) of FIG. 6. The second metal layer 65 is formed so as to leave a space inside the concave portions 50b.

[0062] The convex portions 50a and the concave portions 50b are formed by selectively removing the third semiconductor layer 50 using an etching mask 53 as shown in (a) of FIG. 5. Figure 3 The second metal layer 65 is formed after the etching mask 53 is removed. The second metal layer 65 is formed using a step coverage deposition method such as a sputtering method.

[0063] As shown in (b) of FIG. 5, the portion formed on the side surface of the convex portion 50a is left, and the second metal layer 65 is removed. The second metal layer 65 is removed using anisotropic RIE (Reactive Ion Etching). Subsequently, the first metal layer 63 is formed so as to cover the bottom surface of the convex portions 50a and the concave portions 50b. Thus, the PC 50f and the surface electrode 60 shown in (c) of FIG. 5 can be formed. Figure 7 Figure 7

[0064] Figure 7 (a) to (d) of FIG. 6 are schematic cross-sectional views showing a manufacturing method of the PC 50f according to the third modification. Figure 7 As shown in (a) of FIG. 6, the insulating film 55 is formed so as to cover the convex portions 50a and the concave portions 50b. The insulating film 55 is formed so as to leave a space inside the concave portions 50b. The insulating film 55 is, for example, a silicon oxide film. Subsequently, the sacrificial film 57 is formed on the insulating film 55. The sacrificial film 57 is formed so as to fill the concave portions 50b. The sacrificial film 57 is, for example, a silicon nitride film.

[0065] Figure 7 As shown in (b) of FIG. 6, the portion filled in the inside of the concave portions 50b is left, and the insulating film 55 and the sacrificial film 57 are removed so as to expose the upper surface of the convex portions 50a.

[0066] Subsequently, after the sacrificial film 57 is removed, the second metal layer 65 is formed as shown in (c) of FIG. 6. The second metal layer 65 is formed using a deposition method with high directivity such as vacuum evaporation. The second metal layer 65 is formed on the upper surface of the convex portions 50a and the bottom surface of the concave portions 50b. The portion of the second metal layer 65 formed on the bottom surface of the concave portions 50b is formed on the insulating film 55. Figure 7

[0067] Subsequently, after the sacrificial film 57 is removed, the second metal layer 65 is formed as shown in (c) of FIG. 6. The second metal layer 65 is formed using a deposition method with high directivity such as vacuum evaporation. The second metal layer 65 is formed on the upper surface of the convex portions 50a and the bottom surface of the concave portions 50b. The portion of the second metal layer 65 formed on the bottom surface of the concave portions 50b is formed on the insulating film 55. Figure 3

[0068] As shown in (b) of FIG. 6, the portion filled in the inside of the concave portions 50b is left, and the insulating film 55 and the sacrificial film 57 are removed so as to expose the upper surface of the convex portions 50a. Figure 8 ​​​​​The portion of the second metal layer 65 formed on the bottom surface of the recessed portion 50b is removed together with the insulating film 55 as shown in (d) of FIG. 6. The insulating film 55 is removed by wet etching, for example. Subsequently, the first metal layer 63 is formed so as to cover the bottom surfaces of the convex portion 50a and the recessed portion 50b. Thus, the PC 50f shown in (d) of FIG. 6 can be formed. Figure 8 The PC 50f shown in (a) of FIG. 6 and the surface electrode 60.

[0069] Figure 8 (a) to Figure 8 (c) of FIG. 6 is a schematic cross-sectional view showing a PC 50f according to a modification of the embodiment.

[0070] In Figure 8 In the example shown in (a) of FIG. 6, the third semiconductor layer 50 is etched so as to expose the second semiconductor layer 40 on the bottom surface of the recessed portion 50b of the PC 50f. The second metal layer 65 is provided on the upper surface of the convex portion 50a of the PC 50f. The first metal layer 63 is provided so as to cover the convex portion 50a and the recessed portion 50b, and is in contact with the second semiconductor layer 40 exposed on the bottom surface of the recessed portion 50b.

[0071] In Figure 8 In the example shown in (b) of FIG. 6, the second metal layer 65 is provided on the upper surface of the convex portion 50a of the PC 50f. Further, the third metal layer 67 is provided on the side surface of the convex portion 50a and on the bottom surface of the recessed portion 50b. The third metal layer 67 is provided between the first metal layer 63 and the third semiconductor layer 50. The layer thickness of the third metal layer 67 is thinner than that of the second metal layer 65. The third metal layer 67 contains the same material as the second metal layer 65, for example.

[0072] In this example, the reflectance of the surface electrode 60 can be improved by making the layer thickness of the third metal layer 67 thinner than that of the second metal layer 65. For the PC 50f according to the embodiment, by providing the second metal layer 65, it is possible to ensure a prescribed adhesion strength between the PC 50f and the surface electrode 60, but it is not possible to avoid a decrease in the local adhesion strength due to the direct contact of the first metal layer 63 with the third semiconductor layer 50. In this example, by providing the third metal layer 67 between the first metal layer 63 and the third semiconductor layer 50, it is possible to moderate the decrease in the local adhesion strength of the side surface of the convex portion 50a and the bottom surface of the recessed portion 50b.

[0073] In Figure 8 In the example shown in (c) of FIG. 6, the third semiconductor layer 50 is not provided, and the PC 50f is provided on the upper surface of the second semiconductor layer 40 on the side opposite to the light-emitting layer 30.

[0074] In addition, Figure 8 The third metal layer 67 shown in (b) of FIG. 6 can also be applied to Figure 8 (a) and Figure 8of (c) of FIG. 1. Further, in Figure 8 of (a) to Figure 9 In (c) of FIG. 1, an example in which the second metal layer 65 is provided on the upper surface of the convex portion 50a of the PC 50f is shown, but the embodiment is not limited thereto. That is, Figure 9 of (a) to Figure 9 The characteristic structure of (c) of FIG. 1 can also be applied to a case in which the second metal layer 65 is provided on the bottom surface of the concave portion 50b or the side surface of the convex portion 50a.

[0075] Figure 9 of (a) and ​ of (b) are schematic cross-sectional views of surface-emitting semiconductor light emitting devices 2 and 3 according to a modification of the embodiment.

[0076] For the surface-emitting semiconductor light emitting device 2 shown in (a) of FIG. 2, the surface electrode 60 is provided in a manner of covering the side surface of the mesa-structured light emitting region LER with the insulating film 70 interposed therebetween. Thereby, light radiated from the side surface of the light emitting region LER toward the outside can be sent back to the inside of the light emitting region LER, and the intensity of the QCL light can be increased. ​ For the surface-emitting semiconductor light emitting device 3 shown in (b) of FIG. 2, the surface electrode 60 is also provided in a manner of covering the side surface of the mesa-structured light emitting region LER with the insulating film 70 interposed therebetween. In this example, the portion of the surface electrode 60 provided on the side surface of the light emitting region LER does not include the second metal layer 65, and the first metal layer 63 is in direct contact with the insulating film 70. Thereby, the reflectance of the portion of the surface electrode 60 provided on the side surface of the light emitting region LER can be increased, and the intensity of the QCL light can be made higher.

[0077] ​ Several embodiments of the present application are described, but these embodiments are presented as examples, and are not intended to limit the scope of the application. These new embodiments can be implemented in other various forms, and various omissions, substitutions, and modifications can be made within the scope of the gist of the application. These embodiments and modifications thereof are included in the scope or gist of the application, and are included in the scope of the application and equivalents thereof recited in the claims.

[0078] Explanation of Reference Numerals

[0079] Explanation of Reference Numerals

[0080] ​1, 2, 3… surface-emitting semiconductor light emitting device; 10… semiconductor substrate; 10B… back surface; 20… first semiconductor layer; 30… light emitting layer; 33… quantum well layer; 35… barrier layer; 40… second semiconductor layer; 50… third semiconductor layer; 50a… convex portion; 50b… concave portion; 53… etching mask; 55, 70… insulating film; 57… sacrificial film; 60… surface electrode; 63… first metal layer; 65… second metal layer; 67… third metal layer; 80… back surface electrode; 81… Ti layer; 83… Au layer; LER… light emitting region; 50f… PC.

Claims

1. A surface-emitting semiconductor light-emitting device, comprising: First semiconductor layer; A light-emitting layer is disposed on the first semiconductor layer; A second semiconductor layer is disposed on the light-emitting layer; An uneven structure is provided on the second semiconductor layer; The first metal layer covers the uneven structure; as well as The second metal layer is disposed between the concave-convex structure and the first metal layer. It is disposed on one of the bottom surface of the concave portion, the upper surface of the convex portion, and the side surface of the convex portion in the concave-convex structure. The reflectivity of the second metal layer relative to light radiated from the light-emitting layer is lower than that of the first metal layer relative to light. The concave-convex structure has a plurality of protrusions, which are arranged periodically along the upper surface of the second semiconductor layer to form a photonic crystal structure.

2. The surface-emitting semiconductor light-emitting device as described in claim 1, wherein, The second metal layer has a higher bonding strength with respect to the uneven structure than the first metal layer has with respect to the uneven structure.

3. The surface-emitting semiconductor light-emitting device as described in claim 1, wherein, The first metal layer is in contact with one or more of the following surfaces: the bottom surface of the recess, the upper surface of the protrusion, and the side surface of the protrusion.

4. The surface-emitting semiconductor light-emitting device as described in claim 1, wherein, It also has a third metal layer disposed on a surface other than one of the bottom surface of the recess, the upper surface of the convex portion, and the side surface of the convex portion, located between the concave-convex structure and the first metal layer, and having a thickness thinner than the second metal layer.

5. The surface-emitting semiconductor light-emitting device as described in claim 4, wherein, The third metal layer is made of the same metal material as the second metal layer.

6. The surface-emitting semiconductor light-emitting device as described in claim 1, wherein, It also has a third semiconductor layer disposed on the second semiconductor layer; The uneven structure is disposed in the third semiconductor layer.

7. The surface-emitting semiconductor light-emitting device as described in claim 1, wherein, The period of the plurality of protrusions is shorter than the wavelength of the light radiated from the light-emitting layer.

8. The surface-emitting semiconductor light-emitting device according to any one of claims 1 to 7, wherein, The light-emitting layer includes a first layer and a second layer, the first layer comprising a first compound semiconductor, and the second layer comprising a second compound semiconductor different from the first compound semiconductor, the first layer and the second layer being alternately stacked in a direction from the first semiconductor layer toward the second semiconductor layer; When operating as a quantum cascade laser, it includes a light-emitting multiple quantum well region composed of the first compound semiconductor and the second compound semiconductor, and an injection multiple quantum well region composed of the first compound semiconductor and the second compound semiconductor. It has a structure consisting of multiple layers of pairs composed of the light-emitting multi-quantum-well region and the injected multi-quantum-well region.

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