Chip output current control method and control circuit

Abstract

The application discloses a chip output current control method and a control circuit. The chip output current control method comprises the following steps: generating an output bias current according to an input reference voltage and outputting the output bias current to an output end of a chip; generating an input bias current according to the input reference voltage; and adjusting the current of the output end according to the input bias current, so that the current of the output end is a difference current of the output bias current and the input bias current. According to the application, the output bias current is generated according to the input reference voltage and outputted to the output end of the chip, and the input bias current is generated according to the input reference voltage to adjust the current of the output end, so that the current of the output end is the difference current of the output bias current and the input bias current. Therefore, the chip can adjust the chip output current in the form of differential current output, so as to ensure the precision requirement of the chip output current and output a small current.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a chip output current control method and control circuit. Background Technology

[0002] The operating bias current of the internal MOS circuit of an integrated circuit chip needs to meet a certain value. If the bias current is too small, it will cause poor consistency or noise interference, which will affect the stability of the current.

[0003] To allow the chip to output a small current (on the order of 100nA), the chip's internal circuitry must also operate in a small current bias state (on the order of 100nA), at which point the MOSFET operates in the subthreshold region. The operating current formula for a MOSFET is as follows. When V GS -V t When the current approaches 0, it becomes infinitesimally small, at which point a tiny current bias can be achieved.

[0004] In reality, the threshold voltage Vt of a MOSFET can vary due to manufacturing process variations. t =V0+dV t V0 is the ideal threshold voltage of the device, dV t This is the mismatch threshold voltage caused by process deviation. Ideally, V... GS -V t =V GS -V0 = 0, that is

[0005] In fact V GS -V t =V GS -(V0+dV t )=-dV t , It can be seen that dV t The impact is severe, meaning that process mismatch in the device causes a large deviation in the bias current of the MOSFET. When the bias current of the MOSFET is set to 100nA, the actual output current may be 0 or 200nA, failing to meet the ±5% deviation requirement. Consequently, the output current of the chip produced cannot be precisely controlled.

[0006] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0007] In view of the shortcomings of the prior art, the purpose of this invention is to provide a chip output current control method and control circuit to solve the problem that the chip output current cannot be accurately controlled due to the manufacturing process deviation of the MOSFET in the existing chip output current control circuit.

[0008] The technical solution of the present invention is as follows:

[0009] A chip output current control method, comprising:

[0010] The output bias current is generated based on the input reference voltage and output to the chip's output terminal;

[0011] The input bias current is generated based on the input reference voltage;

[0012] The output current is adjusted according to the input bias current so that the output current is the difference between the output bias current and the input bias current.

[0013] In a further embodiment of the present invention, the step of generating an output bias current based on the input reference voltage and outputting it to the output terminal of the chip includes:

[0014] A first adjustable current is generated based on the reference voltage;

[0015] The output bias current is output to the output terminal according to the first adjustable current.

[0016] In a further embodiment of the present invention, the step of generating an input bias current based on the accessed reference voltage includes:

[0017] A second adjustable current is generated based on the reference voltage;

[0018] An output current is generated based on the second adjustable current;

[0019] The input bias current is generated based on the output current.

[0020] Based on the same inventive concept, the present invention also provides a chip output current control circuit, which includes:

[0021] A bias current output module is connected to a reference voltage and is used to generate an output bias current based on the reference voltage and output it to the output terminal of the chip.

[0022] A bias current input module is connected to the reference voltage and is used to generate an input bias current according to the reference voltage to adjust the current at the output terminal;

[0023] The current at the output terminal is the difference between the output bias current and the input bias current.

[0024] In a further embodiment of the present invention, the bias current output module includes: a first adjustable current output unit and a first MOS transistor;

[0025] The first adjustable current output unit is connected to the reference voltage and generates a first adjustable current according to the reference voltage;

[0026] The gate of the first MOS transistor is connected to the first adjustable current output unit, the drain of the first MOS transistor is connected to the output terminal, and the source of the first MOS transistor is connected to the power supply. The first MOS transistor is used to output the output bias current to the output terminal according to the first adjustable current.

[0027] In a further embodiment of the present invention, the first adjustable current output unit includes: a first operational amplifier, a second MOSFET, and a first resistor; wherein,

[0028] The inverting input terminal of the first operational amplifier is connected to the reference voltage, the non-inverting input terminal of the first operational amplifier is connected to one end of the first resistor, and the output terminal of the first operational amplifier is connected to the gate of the second MOS transistor.

[0029] The gate of the second MOS transistor is also connected to the gate of the first MOS transistor, the drain of the second MOS transistor is connected to one end of the first resistor, and the source of the second MOS transistor is connected to the power supply.

[0030] The other end of the first resistor is grounded.

[0031] In a further embodiment of the present invention, the first MOSFET and the second MOSFET constitute a current mirror structure, wherein the first MOSFET proportionally replicates the current of the second MOSFET.

[0032] In a further embodiment of the present invention, the bias current input module includes: a second adjustable current output unit, a third MOSFET, and an input bias current unit; wherein,

[0033] The second adjustable current output unit is connected to the reference voltage and generates a second adjustable current according to the reference voltage;

[0034] The gate of the third MOS transistor is connected to the second adjustable current output unit, the drain of the third MOS transistor is connected to the input bias current unit, the source of the third MOS transistor is connected to the power supply, and the third MOS transistor is used to generate an output current to the input bias current unit according to the second adjustable current.

[0035] The input bias current unit is connected to the drain of the third MOS transistor and is used to convert the output current into the input bias current.

[0036] In a further embodiment of the present invention, the second adjustable current output unit includes: a second operational amplifier, a fourth MOSFET, and a second resistor; wherein,

[0037] The inverting input terminal of the second operational amplifier is connected to the reference voltage, the non-inverting input terminal of the second operational amplifier is connected to one end of the second resistor, and the output terminal of the second operational amplifier is connected to the gate of the fourth MOS transistor.

[0038] The gate of the fourth MOS transistor is also connected to the gate of the third MOS transistor, the drain of the fourth MOS transistor is connected to one end of the second resistor, and the source of the fourth MOS transistor is connected to a power supply.

[0039] The other end of the second resistor is grounded.

[0040] In a further embodiment of the present invention, the input bias current unit includes: a fifth MOSFET and a sixth MOSFET; wherein,

[0041] The gate of the fifth MOS transistor is connected to the gate of the sixth MOS transistor, the drain of the fifth MOS transistor is connected to the drain of the third MOS transistor, and the source of the fifth MOS transistor is grounded; wherein, the drain of the fifth MOS transistor is connected to the gate.

[0042] The drain of the sixth MOS transistor is connected to the output terminal, and the source of the sixth MOS transistor is grounded.

[0043] In a further embodiment of the present invention, the third MOS transistor and the fourth MOS transistor form a current mirror structure, wherein the third MOS transistor proportionally replicates the current of the fourth MOS transistor; the fifth MOS transistor and the sixth MOS transistor form a current mirror structure, wherein the sixth MOS transistor proportionally replicates the current of the fifth MOS transistor.

[0044] This invention provides a chip output current control method and control circuit. The chip output current control method includes: generating an output bias current based on an input reference voltage and outputting it to the chip's output terminal; generating an input bias current based on the input reference voltage; and adjusting the current at the output terminal based on the input bias current so that the current at the output terminal is the difference between the output bias current and the input bias current. This invention generates an output bias current based on an input reference voltage and adjusts the current at the output terminal based on the input bias current, ensuring that the current at the output terminal is the difference between the output bias current and the input bias current. In other words, by employing differential current output, the chip can adjust its output current to ensure the required accuracy of the chip's output current, enabling the output of even small currents. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0046] Figure 1 This is a block diagram illustrating the principle of the chip output current control circuit in this invention.

[0047] Figure 2 This is a circuit diagram of the chip output current control circuit in this invention.

[0048] Figure 3 This is a flowchart illustrating the chip output current control method of the present invention.

[0049] The labels in the attached diagram are as follows: 100, bias current output module; 110, first adjustable current output unit; 200, bias current input module; 210, second adjustable current output unit; 220, input bias current unit. Detailed Implementation

[0050] This invention provides a chip output current control method and control circuit. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0051] In the implementation methods and claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of the present invention involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0052] It should be further understood that the term "comprising" as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any unit and all combinations of one or more associated listed items.

[0053] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0054] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0055] The inventors discovered that the operating bias current of the internal MOS circuit of an integrated circuit chip needs to meet certain requirements. Excessive current leads to increased power consumption and chip overheating, while insufficient bias current results in poor consistency or noise interference, affecting current stability. This is because the small bias current of the MOS transistor makes it susceptible to power supply noise and internal signal interference, all of which severely impact current stability. Furthermore, to enable the chip to output a small current (around 100nA), the internal circuitry must also operate in a small current bias state (around 100nA), where the MOS transistor operates in the subthreshold region. However, process mismatches cause significant deviations in the MOS transistor's bias current. When the bias current is set to 100nA, the actual output current may be 0 or 200nA, failing to meet the ±5% tolerance requirement. Consequently, the output current of the manufactured chips cannot be precisely controlled.

[0056] To address the aforementioned technical problems, this invention provides a chip output current control method and control circuit. The method generates an output bias current based on an input reference voltage and outputs it to the chip's output terminal. It also generates an input bias current based on the input reference voltage to adjust the output current, ensuring that the output current is the difference between the output bias current and the input bias current. In other words, by employing differential current output, the chip can regulate its output current to ensure a small output current while maintaining required accuracy. Furthermore, by using a microamp-level current for biasing, this invention reduces interference from internal chip signals or power supply noise jitter, thus ensuring the stability of the chip's output current.

[0057] Please also refer to Figures 1 to 2 The present invention provides a preferred embodiment of a chip output current control circuit.

[0058] like Figure 1 As shown, the present invention provides a chip output current control circuit, comprising: a bias current output module 100 and a bias current input module 200. The bias current output module 100 is connected to a reference voltage Vref and to the output terminal OUT of the chip output current control circuit. The bias current output module 100 generates an output bias current based on the reference voltage Vref and outputs it to the output terminal of the chip output current control circuit. The bias current input module 200 is connected to the reference voltage Vref and to the output terminal OUT. The bias current input module 200 generates an input bias current based on the reference voltage Vref to adjust the current at the output terminal OUT. The current at the output terminal OUT is the difference between the output bias current and the input bias current.

[0059] Specifically, both the output bias current generated by the bias current output module 100 and the input bias current generated by the bias current input module 200 are adjustable. The output current at the chip's output terminal is the difference between the output bias current and the input bias current. That is, by using differential current output, the chip can adjust its output current to ensure the required accuracy of the output current and can output a very small current. Therefore, the chip output current control circuit provided by this invention can obtain a highly accurate, small current.

[0060] It should be noted that when the input bias current is greater than the output bias current, the chip is in the input current state. That is, the chip can also adjust the chip input current by using differential current input to ensure the accuracy requirements of the chip input current.

[0061] In some embodiments, the output bias current and the input bias current are biased using microamp-level currents, typically above 1 microamp, such as 10 microamp, 100 microamp, or 1000 microamp, generally between 1 and 10 microamps, although close to 1 microamp, such as 0.9 microamp, is also possible. This embodiment, by using a large current for biasing, can reduce interference from internal chip signals or power supply noise jitter, and the gate-source voltage V of the MOSFET... GS The difference between the threshold voltage Vt of the MOSFET and the threshold voltage dVt is much greater than the mismatch threshold voltage dVt caused by process deviation, so the impact of process mismatch is small. Therefore, the consistency and stability of the bias current can be guaranteed, thereby ensuring the accuracy of the chip output current.

[0062] Please see Figure 1 and Figure 2 In a further embodiment of one example, the bias current output module 100 includes: a first adjustable current output unit 110 and a first MOSFET M1; the first adjustable current output unit 110 is connected to the reference voltage Vref and generates a first adjustable current Irp according to the reference voltage Vref; the gate of the first MOSFET M1 is connected to the first adjustable current output unit 110, the drain of the first MOSFET M1 is connected to the output terminal OUT, the source of the first MOSFET M1 is connected to the power supply VCC, and the first MOSFET M1 is used to output the output bias current Ip to the output terminal OUT according to the first adjustable current Irp.

[0063] Specifically, the first adjustable current output unit 110 includes: a first operational amplifier OP1, a second MOSFET M2, and a first resistor Rp; wherein, the inverting input terminal of the first operational amplifier OP1 is connected to the reference voltage Vref, the non-inverting input terminal of the first operational amplifier OP1 is connected to one end of the first resistor Rp, the output terminal of the first operational amplifier OP1 is connected to the gate of the second MOSFET M2; the gate of the second MOSFET M2 is also connected to the gate of the first MOSFET M1, the drain of the second MOSFET M2 is connected to one end of the first resistor Rp, and the source of the second MOSFET M2 is connected to the power supply VCC; the other end of the first resistor Rp is grounded to GND.

[0064] In this circuit, the first operational amplifier OP1 and the second MOSFET M2 form a voltage follower. The reference voltage Vref serves as the input voltage of the first operational amplifier OP1, and the node voltage Vp serves as the output voltage. Since Vref = Vp, the current through the first resistor Rp is... The first MOSFET M1 and the second MOSFET M2 form a current mirror structure. The first MOSFET M1 proportionally replicates the current output of the second MOSFET M2. Therefore, the output bias current of the second MOSFET M2 is... Where m(M1) represents the number of first MOSFETs M1, and m(M2) represents the number of second MOSFETs M2. Assuming the length L and width W of the first MOSFETs M1 and the second MOSFETs M2 are equal, the output bias current Ip can be adjusted by changing the ratio of the first MOSFETs M1 to the second MOSFETs M2. For example, if the number of first MOSFETs M1 is 2 and the number of second MOSFETs M2 is 1, then the ratio of m(M1) to m(M2) is 2:1. Simultaneously, the output bias current Ip can also be adjusted by changing the value of the first resistor Rp. When the number of first MOSFETs M1 and the number of second MOSFETs M2 are equal, the output bias current Ip can be precisely controlled by setting an appropriate value for the first resistor Rp. The values ​​of current Irp and current Ip are both above 1 microamp to avoid a large mismatch between the first MOSFET M1 and the second MOSFET M2. The second MOSFET M2 still has a small bias current, while the first MOSFET M1 is either turned off or outputs a large bias current, making it impossible to accurately control the magnitude of the output bias current by adjusting the first resistor Rp.

[0065] Please see Figure 1 and Figure 2 In a further embodiment of one example, the bias current input module 200 includes: a second adjustable current output unit 210, a third MOSFET M3, and an input bias current unit 220; wherein, the second adjustable current output unit 210 is connected to the reference voltage Vref and generates a second adjustable current Irn according to the reference voltage Vref; the gate of the third MOSFET M3 is connected to the second adjustable current output unit 210, the drain of the third MOSFET M3 is connected to the input bias current unit 220, the source of the third MOSFET M3 is connected to the power supply VCC, and the third MOSFET M3 is used to generate an output current I3 to the input bias current unit 220 according to the second adjustable current Irn; the input bias current unit 220 is connected to the drain of the third MOSFET M3 and is used to convert the output current I3 into the input bias current In.

[0066] The second adjustable current output unit 210 includes: a second operational amplifier OP2, a fourth MOSFET M4, and a second resistor Rn; wherein the inverting input terminal of the second operational amplifier OP2 is connected to the reference voltage Vref, the non-inverting input terminal of the second operational amplifier OP2 is connected to one end of the second resistor Rn, the output terminal of the second operational amplifier OP2 is connected to the gate of the fourth MOSFET M4; the gate of the fourth MOSFET M4 is also connected to the gate of the third MOSFET M3, the drain of the fourth MOSFET M4 is connected to one end of the second resistor Rn, and the source of the fourth MOSFET M4 is connected to the power supply VCC; the other end of the second resistor Rn is grounded to GND.

[0067] The input bias current unit 220 includes a fifth MOSFET M5 and a sixth MOSFET M6; wherein the gate of the fifth MOSFET M5 is connected to the gate of the sixth MOSFET M6, the drain of the fifth MOSFET M5 is connected to the drain of the third MOSFET M3, and the source of the fifth MOSFET M5 is grounded to GND; wherein the drain of the fifth MOSFET M5 is connected to the gate; the drain of the sixth MOSFET M6 is connected to the output terminal OUT, and the source of the sixth MOSFET M6 is grounded to GND.

[0068] Specifically, the second operational amplifier OP2 and the fourth MOS transistor M4 form a voltage follower. The reference voltage Vref is the input voltage of the second operational amplifier OP2, and the node voltage Vn is the output voltage. Therefore, the current in the second resistor Rn... The third MOSFET M3 and the fourth MOSFET M4 form a current mirror structure. The third MOSFET M3 proportionally replicates the current of the fourth MOSFET M4. Therefore, the output current of the third MOSFET M3 is... Where m(M3) represents the number of third MOSFETs M3, and m(M4) represents the number of fourth MOSFETs M4, assuming that the length and width of the third MOSFETs M3 and the fourth MOSFETs M4 are equal, the output current I3 can be adjusted by changing the number of third MOSFETs M3 and fourth MOSFETs M4. For example, if the number of fourth MOSFETs M4 is 1 and the number of third MOSFETs M3 is 2, then the ratio of m(M3) to m(M4) is 2:1. Simultaneously, the output current Irn can also be adjusted by changing the resistance value of the second resistor Rn. When the number of third MOSFETs M3 and fourth MOSFETs M4 is equal, the output current Irn can be precisely controlled by setting an appropriate value for the second resistor Rn.

[0069] The fifth MOSFET M5 and the sixth MOSFET M6 constitute an input bias current unit 220. The sixth MOSFET M6 is connected to the output terminal OUT, and the fifth MOSFET M5 and the sixth MOSFET M6 form a current mirror structure. The sixth MOSFET M6 proportionally replicates the current of the fifth MOSFET M5, converting the output current I3 of the third MOSFET M3 into the input current of the sixth MOSFET M6, i.e., the input bias current In. This allows adjustment of the current Io at the output terminal OUT, ensuring that the output current Io at the chip's output terminal OUT is the difference between the output bias current Ip and the input bias current In. The input bias current... m(M5) represents the number of fifth MOSFETs M5, and m(M6) represents the number of sixth MOSFETs M6. The lengths and widths of the fifth and sixth MOSFETs M5 are equal. Therefore, the output current In can be adjusted by changing the number of fifth and sixth MOSFETs M5. For example, if the number of fifth MOSFETs is 1 and the number of sixth MOSFETs M6 is 2, then the ratio of m(M6) to m(M5) is 2:1. It can be seen that the input bias current In can be adjusted by changing the ratio of the third MOSFET M3 to the fourth MOSFET M4, and the ratio of the fifth MOSFET M5 to the sixth MOSFET M6. When the number of third MOSFETs M3 and fourth MOSFETs M4 are equal, and the number of fifth MOSFETs M5 and sixth MOSFETs M6 are also equal, the magnitude of the input bias current In can be precisely controlled by setting the resistance value of the second resistor Rn.

[0070] Therefore, the output current of the chip's output terminal OUT

[0071]

[0072] As can be seen, the output current Io at the chip's output terminal can be set by adjusting the ratio of the MOSFETs or by adjusting the value of the resistors (first resistor Rp or second resistor Rn) to precisely control the magnitude of the output current Io, thereby enabling precise control of the chip's minute current output.

[0073] If the number of the first MOSFET M1 and the second MOSFET M2, the number of the third MOSFET M3 and the fourth MOSFET M4, and the number of the fifth MOSFET M5 and the sixth MOSFET M6 are all equal, the output current Io can be precisely controlled by setting the resistance values ​​of the first resistor Rp and the second resistor Rn. Therefore, the output current at the chip output terminal OUT will be...

[0074]

[0075] With a reference voltage Vref = 1.2V, a first resistor Rp = 120kΩ, and a second resistor Rn = 118.8kΩ,

[0076] At this point, Ip >> Io, In >> Io.

[0077] As can be seen, the output bias current Ip and output bias current In of the MOSFET of the chip are both in the 10 microamp level, which can ensure the current consistency of the bias circuit, and the output Io = 100nA can meet the actual accuracy requirements of small current.

[0078] It should be noted that because excessive operating bias current of the MOS transistor inside the chip will cause power consumption to increase, the present invention sets the magnitude of the output bias current and the input bias current to 1-10uA, for example, 10uA.

[0079] Please see Figure 3 In some embodiments, the present invention also provides a chip output current control method applied to the chip output current control circuit described above, which includes the following steps:

[0080] S100 generates an output bias current based on the input reference voltage and outputs it to the chip's output terminal.

[0081] S200: Generates input bias current based on the input reference voltage;

[0082] S300. Adjust the current at the output terminal according to the input bias current, so that the current at the output terminal is the difference between the output bias current and the input bias current.

[0083] Specifically, the bias current output module is connected to a reference voltage and generates an output bias current based on the reference voltage, which is then output to the output terminal of the chip's output current control circuit. The bias current input module is connected to a reference voltage and generates an input bias current based on the reference voltage to adjust the current at the output terminal, so that the current at the output terminal is the difference between the output bias current and the input bias current. In other words, by using differential current output, the chip can adjust its output current to ensure that it can output a small current while maintaining the required current accuracy.

[0084] In some embodiments, step S100 includes the following steps:

[0085] S110. Generate a first adjustable current based on the reference voltage;

[0086] S120. Output the output bias current to the output terminal according to the first adjustable current.

[0087] Specifically, the first adjustable current output unit is connected to the reference voltage and generates a first adjustable current according to the reference voltage. Then, the first MOS transistor outputs the output bias current to the output terminal according to the first adjustable current.

[0088] In some embodiments, step S200 includes the following steps:

[0089] S210. Generate a second adjustable current based on the reference voltage;

[0090] S220. Generate an output current according to the second adjustable current;

[0091] S230. Generate the input bias current based on the output current.

[0092] Specifically, the second adjustable current output unit is connected to the reference voltage and generates a second adjustable current according to the reference voltage. The gate of the third MOS transistor is connected to the second adjustable current output unit and generates an output current to the input bias current unit according to the second adjustable current. Then, the input bias current unit converts the output current into the input bias current.

[0093] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A chip output current control method, characterized in that, include: The chip generates an output bias current based on the input reference voltage and outputs it to the chip's output terminal, including generating a first adjustable current based on the reference voltage. The output bias current is output to the output terminal according to the first adjustable current; The input bias current is generated based on the accessed reference voltage, including the generation of a second adjustable current based on the reference voltage; An output current is generated based on the second adjustable current; The input bias current is generated based on the output current; The output current is adjusted according to the input bias current so that the output current is the difference between the output bias current and the input bias current. The output bias current and the input bias current are biased using microamp-level currents.

2. A chip output current control circuit, characterized in that, include: A bias current output module is connected to a reference voltage Vref and to the output terminal OUT of the chip's output current control circuit. It is used to generate an output bias current according to the reference voltage and output it to the chip's output terminal. A bias current input module is connected to the reference voltage Vref and the output terminal OUT, and is used to generate an input bias current according to the reference voltage to adjust the current of the output terminal; The output current is the difference between the output bias current and the input bias current, and the output bias current and the input bias current are biased using microamp-level currents.

3. The chip output current control circuit according to claim 2, characterized in that, The bias current output module includes: a first adjustable current output unit and a first MOSFET; The first adjustable current output unit is connected to the reference voltage and generates a first adjustable current according to the reference voltage; The gate of the first MOS transistor is connected to the first adjustable current output unit, the drain of the first MOS transistor is connected to the output terminal, and the source of the first MOS transistor is connected to the power supply. The first MOS transistor is used to output the output bias current to the output terminal according to the first adjustable current.

4. The chip output current control circuit according to claim 3, characterized in that, The first adjustable current output unit includes: a first operational amplifier, a second MOSFET, and a first resistor; wherein, The inverting input terminal of the first operational amplifier is connected to the reference voltage, the non-inverting input terminal of the first operational amplifier is connected to one end of the first resistor, and the output terminal of the first operational amplifier is connected to the gate of the second MOS transistor. The gate of the second MOS transistor is also connected to the gate of the first MOS transistor, the drain of the second MOS transistor is connected to one end of the first resistor, and the source of the second MOS transistor is connected to the power supply. The other end of the first resistor is grounded; wherein, the first MOSFET and the second MOSFET form a current mirror structure, and the first MOSFET proportionally replicates the current of the second MOSFET.

5. The chip output current control circuit according to claim 2, characterized in that, The bias current input module includes: a second adjustable current output unit, a third MOSFET, and an input bias current unit; wherein... The second adjustable current output unit is connected to the reference voltage and generates a second adjustable current according to the reference voltage; The gate of the third MOS transistor is connected to the second adjustable current output unit, the drain of the third MOS transistor is connected to the input bias current unit, the source of the third MOS transistor is connected to the power supply, and the third MOS transistor is used to generate an output current to the input bias current unit according to the second adjustable current. The input bias current unit is connected to the drain of the third MOS transistor and is used to convert the output current into the input bias current.

6. The chip output current control circuit according to claim 5, characterized in that, The second adjustable current output unit includes: a second operational amplifier, a fourth MOSFET, and a second resistor; wherein, The inverting input terminal of the second operational amplifier is connected to the reference voltage, the non-inverting input terminal of the second operational amplifier is connected to one end of the second resistor, and the output terminal of the second operational amplifier is connected to the gate of the fourth MOS transistor. The gate of the fourth MOS transistor is also connected to the gate of the third MOS transistor, the drain of the fourth MOS transistor is connected to one end of the second resistor, and the source of the fourth MOS transistor is connected to a power supply. The other end of the second resistor is grounded.

7. The chip output current control circuit according to claim 6, characterized in that, The input bias current unit includes a fifth MOSFET and a sixth MOSFET; wherein... The gate of the fifth MOS transistor is connected to the gate of the sixth MOS transistor, the drain of the fifth MOS transistor is connected to the drain of the third MOS transistor, and the source of the fifth MOS transistor is grounded; wherein, the drain of the fifth MOS transistor is connected to the gate. The drain of the sixth MOS transistor is connected to the output terminal, and the source of the sixth MOS transistor is grounded.

8. The chip output current control circuit according to claim 7, characterized in that, The third MOSFET and the fourth MOSFET form a current mirror structure, and the third MOSFET proportionally replicates the current of the fourth MOSFET; the fifth MOSFET and the sixth MOSFET form a current mirror structure, and the sixth MOSFET proportionally replicates the current of the fifth MOSFET.

Images