A PGA circuit and a method for increasing the dynamic range of PGA input

Abstract

The present invention discloses a PGA circuit and a method for increasing the dynamic range of PGA input, and relates to the field of integrated sensor circuit driving. The PGA circuit includes a modulator, a first-stage amplifier and a demodulator, wherein the first-stage amplifier is AC-coupled with the modulator, and the demodulator is AC-coupled with the first-stage amplifier. The demodulator is provided with a non-zero reference level; the local oscillator frequencies of the modulator and the demodulator are the same. The modulator performs up-conversion on the received signal; the first-stage amplifier amplifies or attenuates the up-converted signal; and the demodulator performs down-conversion on the gain-processed signal. A second-stage amplifier may also be provided to be DC-coupled with the demodulator to amplify the signal outputted therefrom. The present invention can realize level shifting of the input signal while ensuring that the input signal is not distorted, so as to increase the dynamic range of the signal, and the circuit parameters can be adjusted according to actual needs, and has good universality.

Description

Technical Field

[0001] The present invention relates to the field of integrated sensor circuit driving, in particular to a PGA (programmable gain amplifier) ​​circuit with a large dynamic range input used in conjunction with an A / D circuit in an integrated sensor circuit, and a method for increasing the dynamic range of the PGA input. Background Art

[0002] In the field of industrial control, measurement and control sensors usually need to adapt to a large dynamic range, from a few uV to a few V (even tens of V, hundreds of V), with a dynamic range of more than 100dB. Amplifying or attenuating low-frequency analog signals with such a large dynamic range and providing them to A / D circuits for sampling poses new challenges to the traditional PGA structure composed of operational amplifiers.

[0003] The traditional PGA design structure consists of an operational amplifier plus a feedback resistor network. Since the operational amplifier is an active circuit, each MOS tube needs to be in the saturation zone when working, and it needs to meet the following conditions at the same time: Vgs>Vth (conduction threshold), Vgs-Vth=Vdsat>Vds. In the cmos process, the overdrive voltage Vdsat of nmos usually requires 200mV, and the overdrive voltage of pmos usually requires 300mV. When Vdsat<Vds, the MOS tube enters the linear region, the output signal will be distorted, and high-quality small signals cannot be output. In particular, when the input and output signals need to be as small as a few uV to tens of mV, the traditional PGA structure basically loses its signal processing capabilities, and even the rail-to-rail input and output amplifier is powerless. In other words, when the input signal is as small as uV, its output signal is also distorted.

[0004] In addition, since the frequency of such signals that need to be measured and controlled in the industrial control field does not reach the RF frequency band, it is also impossible to amplify them through the RF amplifier by adding DC blocking capacitors (AC coupling). Summary of the invention

[0005] The object of the present invention is to provide a new PGA circuit design to process input signals with a large dynamic range in order to solve the above-mentioned problems.

[0006] The technical solution adopted by the present invention is as follows:

[0007] The present invention provides a PGA circuit, which includes a modulator, a first-stage amplifier and a demodulator, wherein the first-stage amplifier is AC-coupled with the modulator, and the demodulator is AC-coupled with the first-stage amplifier;

[0008] The modulator is configured to up-convert the received signal;

[0009] The first stage amplifier is configured to amplify or attenuate the received signal;

[0010] The demodulator is configured to down-convert a received signal, the demodulator being provided with a non-zero reference level;

[0011] Wherein, the local oscillator frequencies of the modulator and the demodulator are the same.

[0012] Furthermore, a second-stage amplifier is connected after the demodulator, and the second-stage amplifier is DC-coupled with the demodulator; the second-stage amplifier is configured to amplify the received signal.

[0013] Furthermore, the modulator includes NMOS tubes MN0, MN1, MN2 and MN3, and PMOS tubes MP0, MP1, MP2 and MP3; one local oscillator signal access end of the modulator is respectively connected to the gates of the MN0, MP1, MP2 and MN3, and another local oscillator signal access end of the modulator is respectively connected to the gates of the MP0, MN1, MN2 and MP3; one signal input end of the modulator is respectively connected to the source of the MN0 and MN1, and the drain of the MP0 and MP1; another signal input end of the modulator is respectively connected to the source of the MN2 and MN3, and the drain of the MP2 and MP3; the drain of the MN0, MN2, and the source of the MP0, MP2 are connected in parallel to a signal output end of the modulator; the source of the MP1, MP3, and the drain of the MN1, MN3 are connected in parallel to another signal output end of the modulator.

[0014] Furthermore, the first-stage amplifier includes two first amplifying circuits, each of which is respectively connected to a signal output terminal of the modulator and a signal input terminal of the demodulator.

[0015] Furthermore, the first amplifier circuit includes resistors R0, R1, R2, and R3, capacitors C0 and C1, and an NMOS tube MN4 and a PMOS tube MP4; the gate of the MP4 is respectively connected to the first ends of the R0, R1, and C0, the gate of the MN4 is respectively connected to the first ends of the R2, R3, and C1, the source of the MP4 and the second end of the R0 are both connected to the first driving voltage VDD, the source of the MN4 and the second end of the R3 are both connected to the second driving voltage VSS, the second ends of the C0 and C1 are connected in parallel to the signal input end of the first amplifier circuit, and the drain of the MN4, the drain of the MP4, the second end of the R1, and the second end of the R2 are connected in parallel to the signal output end of the first amplifier circuit.

[0016] Further, the demodulator includes NMOS tubes MN5, MN6, MN7 and MN8, PMOS tubes MP5, MP6, MP7 and MP8, and resistors R4 and R5; a local oscillator signal access terminal of the demodulator is respectively connected to the gates of the MN5, MP6, MP7 and MN8, and another local oscillator signal access terminal of the demodulator is respectively connected to the gates of the MP5, MN6, MN7 and MP8; a signal input terminal of the demodulator is respectively connected to the source of the MN5 and MN6, and the source of the MP5 and MP8. The drain of P6; the other signal input end of the demodulator is connected to the source of MN7 and MN8, and the drain of MP7 and MP8 respectively; the drain of MN5 and MN7, and the source of MP5 and MP7 are connected in parallel to a signal output end of the demodulator; the source of MP6 and MP8, and the drain of MN6 and MN8 are connected in parallel to another signal output end of the demodulator; the resistors R4 and R5 are connected in series between the two signal output ends of the output signal, and the reference level V is connected between the resistors R4 and R5 cm .

[0017] Furthermore, the second-stage amplifier includes resistors R6, R7, R8, and a first operational amplifier and a second operational amplifier, the two ends of the resistor R6 are respectively connected to the inverting input of the first operational amplifier and the inverting input of the second operational amplifier, the two ends of the resistor R7 are respectively connected to the inverting input and output of the first operational amplifier, the two ends of the resistor R8 are respectively connected to the inverting input and output of the second operational amplifier, the non-inverting input of the first operational amplifier is connected to a signal input of the second-stage amplifier, the non-inverting input of the second operational amplifier is connected to another signal input of the second-stage amplifier, the output of the first operational amplifier is connected to a signal output of the second-stage amplifier, and the output of the second operational amplifier is connected to another signal output of the second-stage amplifier.

[0018] The present invention also provides a method for increasing the PGA input dynamic range, the method comprising:

[0019] Up-convert the input signal using a modulator;

[0020] The up-converted signal is input into the first-stage amplifier through AC coupling to be amplified or attenuated;

[0021] The amplified or attenuated signal is input to a demodulator through AC coupling for down-conversion, and the operating point potential of the demodulator is not zero.

[0022] Furthermore, the method also includes:

[0023] The down-converted signal is input to the second-stage amplifier through DC coupling for amplification.

[0024] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0025] 1. The solution of the present invention can achieve level shifting of the input signal while ensuring that the input signal is not distorted, so as to increase the dynamic range of the signal.

[0026] 2. The solution of the present invention can also amplify the signal to increase the power of the signal to facilitate subsequent sampling, etc.

[0027] 3. The present invention can adjust the circuit parameters according to actual needs, such as adjusting the reference level Vcm, the gain multiple, etc., so that the present invention has good universality. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0029] Figure 1 This is a circuit diagram of a PGA circuit.

[0030] Figure 2 It is the circuit structure diagram of the modulator.

[0031] Figure 3 This is the circuit diagram of the first stage amplifier.

[0032] Figure 4 It is the circuit structure diagram of the demodulator.

[0033] Figure 5 This is the circuit diagram of the second stage amplifier.

[0034] In the figure, mixer_up is a modulator, mixer_down is a demodulator, ap1 is a first-stage amplifier, ap2 is a second-stage amplifier, am1 is a first operational amplifier, am2 is a second operational amplifier, inn1 and inp1 are two signal input terminals of the modulator, inn2 and inp2 are two signal input terminals of the demodulator, inn3 and inp3 are two signal input terminals of the second-stage amplifier, outn1 and outp1 are two signal output terminals of the modulator, outn2 and outp2 are two signal output terminals of the demodulator, outn and outp are two signal output terminals of the second-stage amplifier, flon1 and flop1 are two local oscillator signal access terminals of the modulator, flon2 and flop2 are two local oscillator signal access terminals of the demodulator, in is the signal input terminal of the first amplifier circuit, and out is the signal output terminal of the first amplifier circuit. DETAILED DESCRIPTION

[0035] All features disclosed in this specification, or steps in all methods or processes disclosed, except mutually exclusive features and / or steps, can be combined in any manner.

[0036] Any feature disclosed in this specification (including any additional claims and abstract), unless otherwise stated, may be replaced by other equivalent or alternative features having similar purposes. That is, unless otherwise stated, each feature is only an example of a series of equivalent or similar features.

[0037] Embodiment 1

[0038] like Figure 1 As shown, this embodiment discloses a PGA circuit, which can process input signals with a large dynamic range. The PGA circuit includes a modulator mixer_up, a first-stage amplifier ap1, and a demodulator mixer_down. The two signal input terminals inn1 and inp1 of the modulator mixer_up are connected to the signal Vin to be processed. The two signal input terminals of the first-stage amplifier ap1 are AC-coupled with the two output terminals of the modulator mixer_up. The two signal output terminals of the first-stage amplifier ap1 are AC-coupled with the two output terminals of the demodulator mixer_down. The two signal output terminals of the demodulator mixer_down output the processed signals to the subsequent circuits.

[0039] The modulator mixer_up and demodulator mixer_down are both implemented by mixers. The mixers may be passive mixers or active mixers. The PGA circuit is described in detail below by taking a mixer with a passive complementary structure as an example.

[0040] The modulator mixer_up performs mixing processing on a signal to be processed Vin (hereinafter referred to as signal Vin), flon1 and flop1 are two local oscillator signal access terminals of the modulator mixer_up, and the modulator mixer_up performs up-conversion on the signal Vin based on the first local oscillator signal flo1.

[0041] The first stage amplifier ap1 amplifies or attenuates the signal output by the modulator mixer_up, which depends on the amplitude of the signal Vin. When the amplitude of the signal Vin is too large, the first stage amplifier ap1 is in the attenuation mode (negative gain). On the contrary, when the amplitude of the signal Vin is small, the first stage amplifier ap1 is in the amplification mode (positive gain). Whether the amplitude of the signal Vin is too large or small is judged by a set threshold value, which is a conventional method. The specific threshold value is an empirical value based on actual needs, so it is not described in detail here.

[0042] The demodulator mixer_down also performs mixing processing on the received signal. flon2 and flop2 are two local oscillator signal access terminals of the demodulator mixer_down. The demodulator mixer_down performs down-conversion on the received signal based on the second local oscillator signal flo2.

[0043] The local oscillator signal flo1=flo2, so that the frequency of the signal after down-conversion by the demodulator mixer_down is consistent with the frequency of the signal Vin input to the modulator mixer_up, and the demodulator mixer_down has a non-zero reference level Vcm, thereby realizing the shift of the signal Vin level. The reference level Vcm is adapted to the working range of the subsequent A / D circuit. In this way, signals from a few uV to tens of V (or even higher voltages) can be processed, and the PGA circuit has the ability to process input signals with a large dynamic range.

[0044] Embodiment 2

[0045] The PGA circuit can be applied to SOC chips designed with CMOS technology, and is also applicable to integrated circuit chips or monolithic circuits designed with other technologies, and can also be implemented by building a circuit with discrete devices. This embodiment takes CMOS_55nm technology as an example to introduce the design circuit of the present invention.

[0046] Still like Figure 1 As shown, the signal Vin is input into the modulator mixer_up through the two signal input terminals inn1 and inp1 of the modulator mixer_up, and the range of the signal Vin is -0.5V to 3.3V. flon1 and flop1 are the two local oscillator signal access terminals of the modulator mixer_up, and the two local oscillator signal access terminals flon1 and flop1 of the modulator mixer_up are connected to the first local oscillator and access the local oscillator signal flo1. flon2 and flop2 are the two local oscillator signal access terminals of the demodulator mixer_down, and the two local oscillator signal access terminals flon2 and flop2 of the demodulator mixer_down are connected to the second local oscillator and access the local oscillator signal flo2, and the frequency of the local oscillator signal flo1 is the same as the frequency of the local oscillator signal flo2. The modulator mixer_up up-converts the signal Vin based on the local oscillator signal flo1, and the demodulator mixer_down down-converts the received signal (i.e., the signal after the gain processing of the first-stage amplifier ap1) based on the local oscillator signal flo2.

[0047] The two signal input terminals of the first-stage amplifier ap1 are AC-coupled with the two signal output terminals of the modulator mixer_up. After the modulator mixer_up performs up-conversion, the first-stage amplifier ap1 performs amplification or attenuation processing on the signal, which depends on the amplitude of the signal Vin, which is the same as the case of the first embodiment. The two output terminals of the first-stage amplifier ap1 are AC-coupled with the two input terminals of the demodulator mixer_down. The signal processed by the first-stage amplifier ap1 for gain is input to the demodulator mixer_down for down-conversion. The back end of the demodulator mixer_down is connected to the A / D circuit. The working point of the demodulator mixer_down (i.e., the reference level Vcm) can be set according to the working range of the A / D circuit of the subsequent stage.

[0048] In addition, a second-stage amplifier ap2 can be connected to the rear end of the demodulator mixer_down. The two signal input terminals of the second-stage amplifier ap2 and the two signal output terminals of the demodulator mixer_down are DC coupled. The second-stage amplifier ap2 amplifies the signal converted by the demodulator mixer_down, provides a certain gain, and strengthens the driving capability, so as to facilitate sampling by the A / D circuit connected to the rear end. Whether to use the second-stage amplifier ap2 depends on the requirements of the rear-stage circuit.

[0049] Assume the frequency of signal Vin is f in , the amplitude is represented by itself, then the frequency and amplitude of the signal after being processed by the modulator mixer_up are:

[0050] Frequency: f out_mixer_up =f lo1 ±f in ; (1)

[0051] Amplitude: V out_mixer_up =Vin*G mixer_up ; (2)

[0052] f out_mixer_up Indicates the frequency of the modulator mixer_up output signal, V out_mixer_up Indicates the amplitude of the modulator mixer_up output signal, G mixer_up The gain multiple of the modulator mixer_up. This is to explain the result of the mixing process of the modulator mixer_up. Up-conversion or down-conversion is achieved by controlling the frequency difference between flo1 and fin. The same is true for the demodulator mixer_down.

[0053] The first-stage amplifier ap1 performs gain processing (amplification or attenuation) on the up-converted signal. When the amplitude Vin of the input signal is too large, the signal is processed with negative gain. On the contrary, when the amplitude Vin of the input signal is small, the signal is processed with positive gain. The frequency f of the signal after up-conversion by the modulator mixer_up out_mixer_up The frequency of adding DC blocking capacitors in the integrated circuit has been reached. The first-stage amplifier ap1 is AC-coupled with the modulator mixer_up to amplify / attenuate the up-converted signal. The frequency of its output signal is f ap1 The frequency f of the modulator mixer_up output out_mixer_up Keeping unchanged, the amplitude of the output signal is:

[0054] Amplitude: V out_ap1 =V out_mixer_up *G ap1 =Vin*G mixer_up *G ap1 ; (3)

[0055] V out_ap1 is the amplitude of the output signal of the first stage amplifier ap1, G ap1 It is the gain multiple of the first stage amplifier ap1.

[0056] The demodulator mixer_down is AC coupled with the first-stage amplifier ap1, and the frequency and amplitude of its output signal are:

[0057] Frequency: f out_mixer_down =f lo2 ±f ap1 ; (4)

[0058] Amplitude: V out_mixer_down =V cm +V out_ap1 *G mixer_down ; (5)

[0059] f out_mixer_down is the frequency of the demodulator mixer_down output signal, V out_mixer_down is the amplitude of the demodulator mixer_down output signal, V cm is the reference level, G mixer_down It is the gain multiplier of the demodulator mixer_down.

[0060] Combining the above formulas (1)-(5), we have:

[0061] Frequency: f out_mixer_down =f in ; (6)

[0062] Amplitude: V out_mixer_down =Vcm +Vin*G mixer_up *G ap1 *G mixer_down ; (7)

[0063] At this point, the input signal Vin has been converted into an output signal V out_mixer_down , the two have the same frequency, but a reference voltage V is superimposed on the signal Vin cm , and amplifies or attenuates the signal, so when the signal Vin is very small (several mV level or even uV level), the circuit structure of this embodiment can still effectively process the signal.

[0064] Furthermore, after the demodulator, the second-stage amplifier ap2 can be DC-coupled as needed to amplify the signal gain and enhance the driving capability. The frequency of the signal output by the two signal output terminals outn and outp of the second-stage amplifier ap2 remains unchanged from that received, and the amplitude becomes:

[0065] Amplitude:

[0066] V out_ap2 =V out_mixer_down *G ap2 =(V cm +Vin*G mixer_up *G ap1 *G mixer_down )*G ap2 (9)

[0067] V out_ap2 is the amplitude of the output signal of the second stage amplifier, G ap2 is the gain multiple of the second stage amplifier.

[0068] Embodiment 3

[0069] This embodiment introduces the circuit structures of the modulator mixer_up, the demodulator mixer_down, the first-stage amplifier ap1 and the second-stage amplifier ap2 respectively.

[0070] like Figure 2As shown, the modulator mixer_up includes NMOS transistors MN0, MN1, MN2, MN3, PMOS transistors MP0, MP1, MP2 and MP3. The local oscillator signal access terminal flon1 is connected to the gates of MN0, MP1, MP2 and MN3 respectively, and the local oscillator signal access terminal flop1 is connected to the gates of MP0, MN1, MN2 and MP3 respectively; of the two signal input terminals inn1 and inp1 for receiving the input signal Vin, one signal input terminal inn1 is connected to the source of MN0 and MN1, and the drain of MP0 and MP1 respectively, and the other signal input terminal inp1 is connected to the source of MN2 and MN3, and the drain of MP2 and MP3 respectively. The drain of MN0, the source of MP0, the drain of MN2 and the source of MP2 are connected in parallel to a signal output terminal outn1, and the source of MP1, the drain of MN1, the source of MP3 and the drain of MN3 are connected in parallel to another signal output terminal outp1.

[0071] By designing the modulator mixer_up of the above circuit structure, the input signal Vin is mixed with the first local oscillation signal flo1. For the up-conversion design, the phases of the two signals are set to be the same.

[0072] like Figure 3 The first-stage amplifier ap1 includes two first amplifier circuits, and the two first amplifier circuits are used to implement gain processing of output signals at both ends of the modulator mixer_up.

[0073] The first amplifier circuit includes a resistor R0, a resistor R1, a resistor R2, a resistor R3, a capacitor C0, a capacitor C1, an NMOS transistor MN4, and a PMOS transistor MP4. The gate of MP4 is connected to the first ends of R0, R1, and C0 respectively, the gate of MN4 is connected to the first ends of R2, R3, and C1 respectively, the source of MP4 and the second end of R0 are both connected to the first driving voltage VDD, the source of MN4 and the second end of R3 are both connected to the second driving voltage VSS, the second ends of C0 and C1 are connected in parallel to the signal input terminal in, the signal input terminal is used to connect to the signal output terminal outn1 or outp1 of the modulator mixer_up, the drain of MN4, the drain of MP4, the second end of R1, and the second end of R2 are connected in parallel to the signal output terminal out, the signal output terminal out is used to connect to a signal input terminal (inn2 or inp2) of the demodulator mixer_down.

[0074] like Figure 4The circuit structure diagram of the demodulator mixer_down is shown in FIG. 1 , which is similar to the circuit structure of the modulator mixer_up, except that a reference level circuit is configured between the two output terminals, and the reference level circuit is connected through resistors R4 and R5. Specifically:

[0075] The demodulator mixer_down includes NMOS tube MN5, NMOS tube MN6, NMOS tube MN7, NMOS tube MN8, PMOS tube MP5, PMOS tube MP6, PMOS tube MP7, PMOS tube MP8, resistor R4 and resistor R5. The local oscillator signal access terminal flon2 is respectively connected to the gates of MN5, MP6, MP7 and MN8, and the local oscillator signal access terminal flop2 is respectively connected to the gates of MP5, MN6, MN7 and MP8. Of the two signal input terminals inn2 and inp2 for receiving signals, one signal input terminal inn2 is respectively connected to the source of MN5 and MN6, and the drain of MP5 and MP6, and the other signal input terminal inp2 is respectively connected to the source of MN7 and MN8, and the drain of MP7 and MP8. The drain of MN5, the source of MP5, the drain of MN7, and the source of MP7 are connected in parallel to a signal output terminal outn2; the source of MP6, the source of MP8, the drain of MN6, and the drain of MN8 are connected in parallel to another signal output terminal outp2. The reference level Vcm is connected to the outn2 terminal via the resistor R4 and to the outp2 terminal via the resistor R5, and the resistance values ​​of the resistors R4 and R5 are equal.

[0076] like Figure 5 As shown, the second-stage amplifier ap2 includes a resistor R6, a resistor R7, a resistor R8, a first operational amplifier am1, and a second operational amplifier am2. A signal input terminal inn3 is connected to the non-inverting input terminal of the first operational amplifier am1, and another signal input terminal inp3 is connected to the non-inverting input terminal of the second operational amplifier am2. The two ends of the resistor R6 are respectively connected to the inverting input terminal of the first operational amplifier am1 and the inverting input terminal of the second operational amplifier am2. The two ends of the resistor R7 are respectively connected to the inverting input terminal and the output terminal of the first operational amplifier circuit am1, and the two ends of the resistor R8 are respectively connected to the inverting input terminal and the output terminal of the second operational amplifier circuit am2; the output terminals of the two operational amplifier circuits serve as the two signal output terminals of the second-stage amplifier ap2. Specifically, the output terminal of the first operational amplifier circuit am1 is connected to a signal output terminal outn of the second-stage amplifier ap2, and the output terminal of the second operational amplifier circuit am2 is connected to another signal output terminal outp of the second-stage amplifier ap2.

[0077] It should be noted that each resistor (R0-R3, R6-R8) in the above amplifier is designed as an adjustable resistor so as to achieve the adjustment of circuit parameters (such as gain multiple, etc.).

[0078] Embodiment 4

[0079] This embodiment discloses a method for increasing the dynamic range of a PGA input, the method comprising:

[0080] The input signal is up-converted using a modulator.

[0081] The up-converted signal is input to the first-stage amplifier through AC coupling for amplification or attenuation. Whether it is amplified or attenuated depends on the amplitude of the input signal. When the input signal amplitude is too large, it is attenuated (negative gain). On the contrary, when the input signal amplitude is small, it is amplified (positive gain). The excessive or small amplitude is judged by the corresponding threshold.

[0082] The amplified or attenuated signal is input to a demodulator through AC coupling for down-conversion, and the operating point potential of the demodulator is not zero.

[0083] The method may further include: inputting the down-converted signal into a second-stage amplifier for amplification through a DC coupling method.

[0084] The modulator, demodulator, first-stage amplifier, and second-stage amplifier used in the above method may adopt the circuit structure in the above-mentioned embodiment.

[0085] The present invention is not limited to the above-mentioned specific embodiments, but extends to any new features or any new combination disclosed in this specification, as well as any new method or process steps or any new combination disclosed.

Claims

1. A PGA circuit, characterized in that: The invention comprises a modulator (mixer_up), a first-stage amplifier (ap1) and a demodulator (mixer_down), wherein the first-stage amplifier (ap1) is AC-coupled with the modulator (mixer_up), and the demodulator (mixer_down) is AC-coupled with the first-stage amplifier (ap1); the modulator (mixer_up) is configured to perform up-conversion on the received signal; the modulator (mixer_up) comprises NMOS tubes MN0, MN1, MN2 and MN3, and PMOS tubes MP0, MP1, MP2 and MP3; a local oscillator signal access terminal (flon1) of the modulator (mixer_up) is respectively connected to the gates of the MN0, MP1, MP2 and MN3, and another ...2) of the modulator (mixer_up) is respectively connected to the gates of the MN0, MP1, MP2 and MN3, and another local oscillator signal access terminal (flon3) of the modulator (mixer_up) is respectively connected to the gates of the MN0, MP1, MP2 and MN3, and another local oscillator signal access terminal (flon4) of the modulator (mixer_up) is respectively connected to the gates of the MN0, MP1, MP2 and MN3, and another local oscillator signal access terminal (flon5) of the modulator (mixer_up) is respectively connected to the gates of the MN0, MP1, MP2 and MN3, and another local oscillator signal access terminal (flon6) of the modulator (mixer_up) is respectively connected to the gates of the MN0, MP1, MP2 and MN3, and another local oscillator signal access terminal (flon7) of A local oscillator signal access terminal (flop1) is respectively connected to the gates of the MP0, MN1, MN2 and MP3; a signal input terminal (inn1) of the modulator (mixer_up) is respectively connected to the source of the MN0 and MN1, and the drain of the MP0 and MP1; another signal input terminal (inp1) of the modulator (mixer_up) is respectively connected to the source of the MN2 and MN3, and the drain of the MP2 and MP3; the drain of the MN0 and MN2, and the source of the MP0 and MP2 are connected in parallel to a signal output terminal (outn1) of the modulator (mixer_up); the source of the MP1 and MP3, and the drain of the MN1 and MN3 are connected in parallel to another signal output terminal (outp1) of the modulator (mixer_up); The first stage amplifier (ap1) is configured to amplify or attenuate the received signal; The demodulator (mixer_down) is configured to down-convert the received signal, and the demodulator (mixer_down) is set with a non-zero reference level; The local oscillator frequencies of the modulator (mixer_up) and the demodulator (mixer_down) are the same.

2. The PGA circuit according to claim 1, wherein: A second-stage amplifier (ap2) is connected behind the demodulator (mixer_down), and the second-stage amplifier (ap2) is DC-coupled with the demodulator (mixer_down); the second-stage amplifier (ap2) is configured to amplify the received signal.

3. The PGA circuit according to claim 1, wherein: The first-stage amplifier (ap1) comprises two first amplifying circuits, each of which is respectively connected to a signal output terminal of the modulator (mixer_up) and a signal input terminal of the demodulator (mixer_down).

4. The PGA circuit according to claim 3, characterized in that: The first amplifier circuit includes resistors R0, R1, R2, and R3, capacitors C0 and C1, and an NMOS tube MN4 and a PMOS tube MP4; the gate of the MP4 is respectively connected to the first ends of the R0, R1, and C0, the gate of the MN4 is respectively connected to the first ends of the R2, R3, and C1, the source of the MP4 and the second end of the R0 are both connected to the first driving voltage VDD, the source of the MN4 and the second end of the R3 are both connected to the second driving voltage VSS, the second ends of the C0 and C1 are connected in parallel to the first amplifier circuit signal input terminal (in), and the drain of the MN4, the drain of the MP4, the second end of the R1, and the second end of the R2 are connected in parallel to the first amplifier circuit signal output terminal (out).

5. The PGA circuit according to claim 1, wherein: The demodulator (mixer_down) includes NMOS tubes MN5, MN6, MN7 and MN8, PMOS tubes MP5, MP6, MP7 and MP8, and resistors R4 and R5; a local oscillator signal access terminal (flon2) of the demodulator (mixer_down) is respectively connected to the gates of the MN5, MP6, MP7 and MN8, and another local oscillator signal access terminal (flop2) of the modulator (mixer_up) is respectively connected to the gates of the MP5, MN6, MN7 and MP8; a signal input terminal (inn2) of the demodulator (mixer_down) is respectively connected to the source of the MN5 and MN6, and the drain of the MP5 and MP6; the demodulator (mixer_up) is respectively connected to the source of the MN5 and MN6, and the drain of the MP5 and MP6. The other signal input terminal (inp2) of the demodulator (mixer_down) is respectively connected to the source of the MN7 and MN8, and the drain of the MP7 and MP8; the drain of the MN5 and MN7, and the source of the MP5 and MP7 are connected in parallel to a signal output terminal (outn2) of the demodulator (mixer_down); the source of the MP6 and MP8, and the drain of the MN6 and MN8 are connected in parallel to another signal output terminal (outp2) of the demodulator (mixer_down); the resistors R4 and R5 are connected in series between the two signal output terminals (outn2, outp2) of the demodulator (mixer_down), and the reference level Vcm is connected between the resistors R4 and R5.

6. The PGA circuit according to claim 2, wherein: The second-stage amplifier (ap2) comprises resistors R6, R7, and R8, and a first operational amplifier (am1) and a second operational amplifier (am2); two ends of the resistor R6 are respectively connected to an inverting input end of the first operational amplifier (am1) and an inverting input end of the second operational amplifier (am2); two ends of the resistor R7 are respectively connected to an inverting input end and an output end of the first operational amplifier (am1); two ends of the resistor R8 are respectively connected to an inverting input end and an output end of the second operational amplifier (am2); a non-inverting input end of the first operational amplifier (am1) is connected to a signal input end (inn3) of the second-stage amplifier (ap2); a non-inverting input end of the second operational amplifier (am2) is connected to another signal input end (inp3) of the second-stage amplifier (ap2); an output end of the first operational amplifier (am1) is connected to a signal output end (outn) of the second-stage amplifier (ap2); and an output end of the second operational amplifier (am2) is connected to another signal output end (outp) of the second-stage amplifier (ap2).

7. A method for increasing the dynamic range of a PGA input, characterized in that: include: The input signal is up-converted by using a modulator; the modulator (mixer_up) includes NMOS tubes MN0, MN1, MN2 and MN3, and PMOS tubes MP0, MP1, MP2 and MP3; a local oscillator signal access terminal (flon1) of the modulator (mixer_up) is respectively connected to the gates of the MN0, MP1, MP2 and MN3, and another local oscillator signal access terminal (flop1) of the modulator (mixer_up) is respectively connected to the gates of the MP0, MN1, MN2 and MP3; a signal input terminal (in n1) are respectively connected to the sources of MN0 and MN1, and the drains of MP0 and MP1; another signal input terminal (inp1) of the modulator (mixer_up) is respectively connected to the sources of MN2 and MN3, and the drains of MP2 and MP3; the drains of MN0 and MN2, and the sources of MP0 and MP2 are connected in parallel to a signal output terminal (outn1) of the modulator (mixer_up); the sources of MP1 and MP3, and the drains of MN1 and MN3 are connected in parallel to another signal output terminal (outp1) of the modulator (mixer_up); The up-converted signal is input into the first-stage amplifier through AC coupling to be amplified or attenuated; The amplified or attenuated signal is input to a demodulator through AC coupling for down-conversion, and the operating point potential of the demodulator is not zero.

8. The method for increasing the PGA input dynamic range as claimed in claim 7, characterized in that: Also includes: The down-converted signal is input to the second-stage amplifier through DC coupling for amplification.

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