Oscillator and communication method

Abstract

Oscillator and communication method. It is necessary to express 1 and 0 of serial communication by different lengths of pulses. The oscillator includes a vibrator and a circuit device including a first terminal, a storage circuit which stores data corresponding to an external signal input from the first terminal, an oscillation circuit which generates an oscillation signal using the vibrator, a counter circuit which counts a period in which the external signal is a first polarity and a period in which the external signal is a second polarity using a clock signal generated from the oscillation signal, and a processing circuit which writes the data into the storage circuit according to a count result of the counter circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to an oscillator and a communication method. BACKGROUND

[0002] In the past, a technique has been known in which a signal can be input from the outside to an oscillator that generates an oscillation signal using a vibrator. For example, Patent Literature 1 discloses an oscillator that can implement single-wire serial communication.

[0003] Patent Literature 1: Japanese Patent Application Publication No. 2014-190961

[0004] In 1-WIRE (registered trademark) that is single-wire serial communication, 0 and 1 are distinguished by changing the width of a low pulse. Also, generally, in the case where binary 1 is transmitted from a master device, a short low pulse (for example, 1 to 15 μs) is transmitted. In the case where binary 0 is transmitted, a long low pulse (for example, 60 μs) is transmitted. In this way, in the past single-wire serial communication, it is necessary to distinguish the length of the low pulse, so, in order not to be affected by an error, it is necessary to impart a large difference to the length of the low pulse corresponding to 1 and 0. SUMMARY

[0005] An oscillator for solving the above problem includes a vibrator and a circuit device, the circuit device having: a first terminal; a storage circuit that stores data corresponding to an external signal input from the first terminal; an oscillation circuit that generates an oscillation signal using the vibrator; a counter circuit that counts a period in which the external signal is of a first polarity and a period in which the external signal is of a second polarity using a clock signal generated in accordance with the oscillation signal; and a processing circuit that writes the data into the storage circuit in accordance with a count result of the counter circuit.

[0006] In addition, a communication method for solving the above problem uses an oscillator including a vibrator and a circuit device, including: an external device inputting an external signal to a first terminal of the circuit device; the oscillator generating a clock signal using the vibrator; counting a period in which the external signal is of a first polarity and a period in which the external signal is of a second polarity using the clock signal; and writing data corresponding to the external signal into a storage circuit in accordance with a count result. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block diagram of an oscillator of one embodiment of the present application.

[0008] Figure 2 is a diagram showing a counter circuit, a processing circuit, and a storage circuit.

[0009] Figure 3 is a diagram showing an example of the relationship between a count result and an sftreg signal.

[0010] Figure 4 is a diagram showing the format of data corresponding to an external signal.

[0011] Figure 5 is a timing chart of a single-wire serial communication mode.

[0012] Figure 6 is a timing chart of a single-wire serial communication mode.

[0013] Explanation of reference numerals

[0014] 1 oscillator; 2 circuit device; 3 vibrator; 4 container; 10 oscillation circuit; 21 to 23 buffer circuit; 30 frequency division circuit; 40 power-on reset circuit; 50 control circuit; 51 output register; 52 counter circuit; 53 shift register circuit; 54 latch signal generating circuit; 55a to 55c synchronization flip-flop; 56 exclusive OR circuit; 58 processing circuit; 59 single-wire communication circuit; 61 to 63 regulator; 70 temperature sensor; 100 external device; 110 acquisition circuit; 120 frequency division circuit; 130 external signal generating circuit. DETAILED DESCRIPTION

[0015] Here, the embodiments of the present application are described in the following order.

[0016] (1) Structure of oscillator:

[0017] (2) Single-wire serial communication mode:

[0018] (2-1) Action example:

[0019] (3) Other embodiments:

[0020] (1) Structure of oscillator:

[0021] Figure 1 is a block diagram of an oscillator 1 of one embodiment of the present application. The oscillator 1 has a container 4 that houses a circuit device 2 and a vibrator 3. In the present embodiment, the vibrator 3 is a quartz vibrator that uses quartz as a substrate material, such as a quartz vibrator using AT cut or SC cut. The vibrator 3 can also be a SAW (Surface Acoustic Wave) resonator, a MEMS (Micro Electro Mechanical Systems) vibrator. In addition, as the substrate material of the vibrator 3, in addition to quartz, a piezoelectric material such as lithium tantalate, lithium niobate, or the like, piezoelectric ceramics such as lead zirconate titanate, or the like, or a silicon semiconductor material, or the like can be used. As the excitation means of the vibrator 3, an excitation means based on piezoelectric effect can be used, or electrostatic driving based on Coulomb force can be used.

[0022] The container 4 has a space inside, which is hermetically sealed by a reduced pressure atmosphere such as vacuum or an inert gas atmosphere of nitrogen, argon, helium, or the like. External terminals are provided on the outer surface of the container 4. In Figure 1 In the present embodiment, the external terminals are schematically indicated by white circles overlapping lines indicating the rectangle of the container 4. Terminals for inputting or outputting various signals are provided on the outer surface of the circuit device 2. The terminals provided on the circuit device 2 are also schematically indicated by white circles. The external terminals provided on the container 4 are mostly electrically connected to the terminals provided on the circuit device 2. However, the vibrator 3 fixed inside the container 4 is connected to the terminals XI and XO, which are terminals connected to the vibrator 3, and is not connected to the external terminals.

[0023] The circuit device 2 has, in addition to the terminals connected to the vibrator 3, a high-potential power supply terminal VDD, a low-potential power supply terminal GND, a pull-down terminal XEN, output enable terminals CLK2_EN and CLK3_EN of two kinds of oscillation signals, a temperature data output terminal TDATA, and output terminals CLK1, CLK2, and CLK3 of three kinds of oscillation signals. In the present embodiment, the output enable terminal CLK3_EN of the oscillation signal is connected to the external terminal provided on the container 4. Here, the output enable terminal CLK3_EN of the oscillation signal is a first terminal, and the external terminal connected to the output enable terminal CLK3_EN of the oscillation signal is a first external terminal. That is, in the present embodiment, the output enable terminal CLK3_EN of the oscillation signal is also used as an input terminal of an external signal. In addition, the first terminal, that is, the output enable terminal CLK3_EN of the oscillation signal in the present embodiment is electrically connected to the external terminal provided on the container 4, and thus an external signal can be easily supplied to the terminal CLK3_EN provided in the circuit device 2 from the outside of the container 4.

[0024] The circuit device 2 can operate in a plurality of modes. The modes are not limited, but in the present embodiment, the circuit device 2 has at least a normal mode in which oscillation signals are output, a two-wire serial communication mode in which two-wire serial communication is performed, and a one-wire serial communication mode in which one-wire serial communication is performed. In the normal mode, the circuit device 2 can output an oscillation signal selected from among the three kinds of oscillation signals.

[0025] That is, in a case where neither of the output enable terminals CLK2_EN and CLK3_EN of the oscillation signal is input with a signal indicating enable, the circuit device 2 outputs a prescribed oscillation signal from the output terminal CLK1 of the oscillation signal. Hereinafter, the oscillation signal output from the output terminal CLK1 will be referred to as a first clock signal.

[0026] In a case where an enable-indicative signal is input to the oscillation signal output enable terminal CLK2_EN, the circuit device 2 outputs a prescribed oscillation signal from the oscillation signal output terminal CLK2. Hereinafter, the oscillation signal output from the output terminal CLK2 is referred to as a second clock signal.

[0027] In a case where an enable-indicative signal is input to the oscillation signal output enable terminal CLK3_EN, the circuit device 2 outputs a prescribed oscillation signal from the oscillation signal output terminal CLK3. Hereinafter, the oscillation signal output from the output terminal CLK3 is referred to as a third clock signal.

[0028] The characteristics of the first clock signal, the second clock signal, and the third clock signal can be different, and in the present embodiment, at least one of the frequency, the amplitude, and the noise characteristic can be different. Furthermore, the frequency and the amplitude can be adjusted by changing the circuit structure, the capacity, and the like of the buffer circuit described later, and the noise characteristic can be adjusted by the layout of the buffer circuit and the like. In addition, the layout refers to, for example, whether the layout is performed in the vicinity of a large ground pad or the like.

[0029] The use of each terminal in the circuit device 2 is the use in the normal mode. In other modes, at least a part of each terminal is changed to a different use. The two-wire serial communication mode can be implemented by communication based on various standards, but the I2C standard is adopted in the present embodiment. Also, in the two-wire serial communication mode, the oscillation signal output enable terminal CLK2_EN becomes an input terminal of a serial clock SCL. The oscillation signal output enable terminal CLK3_EN becomes an input terminal of a serial data SDA. In addition, in the two-wire serial communication mode of the present embodiment, a signal is input to the circuit device 2 from the outside of the circuit device 2 by serial communication, and thus, writing to a register possessed by the control circuit 50 and the like can be performed. As a result, various settings can be performed by serial communication.

[0030] In the present embodiment, in the one-wire serial communication mode, the oscillation signal output enable terminal CLK3_EN becomes an input terminal for inputting a serial signal. In addition, in the one-wire serial communication mode of the present embodiment, a signal is input to the circuit device 2 from the outside of the circuit device 2 by serial communication, and thus, writing to a register possessed by the control circuit 50 and the like can be performed. As a result, various settings can be performed. In addition, in the present embodiment, the circuit device 2 can output the first clock signal from the output terminal CLK1 even in the one-wire serial communication mode.

[0031] In the present embodiment, the circuit device 2 includes an oscillation circuit 10, buffer circuits 21 to 23, a frequency division circuit 30, a power-on reset circuit 40, a control circuit 50, regulators 61 to 63, and a temperature sensor 70. In addition, the circuit device 2 of the present embodiment can also be a structure in which a part of these elements is omitted or changed, or other elements are added. In the present embodiment, the circuit device 2 is a single-chip semiconductor integrated circuit (IC: integrated circuit).

[0032] The regulators 61 to 63 convert the voltage of the power supply connected to the high-potential power supply terminal VDD to a predetermined voltage and supply it to each circuit within the circuit device 2. The voltage value is not limited, and for example, in the case where the voltage of the power supply connected to the high-potential power supply terminal VDD is 1.5 V, the regulators 61 to 63 convert it to a voltage of 1.2 V or 1.0 V, or the like. In the present embodiment, the output voltage of the regulator 61 is 1.2 V, which is supplied to the control circuit 50, for example. The output voltage of the regulators 62 and 63 is 1.0 V, which is supplied to the buffer circuits 21 to 23, for example.

[0033] The oscillation circuit 10 is a circuit that generates an oscillation signal using the vibrator 3. In the present embodiment, the oscillation circuit 10 amplifies and feeds back the output signal of the vibrator 3 to the vibrator 3, and outputs an oscillation signal based on the oscillation of the vibrator 3. The oscillation mode of the oscillation circuit 10 can be various modes. For example, the oscillation circuit constituted by the vibrator 3 and the oscillation circuit 10 can also be a Pierce oscillation circuit, an Inverter-type oscillation circuit, a Colpitts oscillation circuit, a Hartley oscillation circuit, or the like.

[0034] The buffer circuits 21 to 23 are circuits that buffer and output the oscillation signal output from the oscillation circuit 10. Each of the buffer circuits 21 to 23 outputs the buffered signal to the output terminals CLK1, CLK2, and CLK3 of the oscillation signal, respectively. That is, the first clock signal, the second clock signal, and the third clock signal are output from each of the output terminals CLK1, CLK2, and CLK3. Each of the output terminals is electrically connected to the external terminal of the oscillator 1, and thus these oscillation signals are output from the oscillator 1 to the outside.

[0035] In the present embodiment, the oscillation signal output from the oscillation circuit 10 is 76.8 MHz. The buffer circuit 21 is a circuit that adjusts the frequency of this oscillation signal to 1 / 2 and outputs an oscillation signal of a predetermined amplitude of 38.4 MHz. The buffer circuit 22 is a circuit that outputs an oscillation signal of an amplitude set by the user without changing the frequency of the oscillation signal output from the oscillation circuit 10. The buffer circuit 23 is a circuit that outputs an oscillation signal of an amplitude set by the user without changing the frequency of the oscillation signal output from the oscillation circuit 10. However, the noise level is different in the buffer circuits 22 and 23.

[0036] The above buffer circuits 21 to 23 can be implemented by various known circuits. For example, the adjustment of the frequency can be implemented by various frequency dividing circuits. The circuit for performing the amplitude adjustment, for example, a circuit that performs gain adjustment, can also be implemented by various known circuits.

[0037] The frequency dividing circuit 30 frequency-divides the oscillation signal output from the oscillation circuit 10 at a predetermined frequency division ratio to generate a clock signal. In the present embodiment, the oscillation signal output from the oscillation circuit 10 is 76.8 MHz, and is frequency-divided at a ratio of 1 / 16. Thus, in the present embodiment, the clock signal is 4.8 MHz. Hereinafter, this clock signal will be referred to as a clock signal CLK. Note that the frequency of the clock signal CLK is one example, and can be other frequencies. Also, in the frequency dividing circuit 30, the frequency of the output clock signal CLK can be made variable by instructing the frequency division ratio.

[0038] The power-on reset circuit 40 is a circuit that outputs a signal indicating that the voltage output from the regulator 61 has stabilized. For example, the output signal of the power-on reset circuit 40 is not stable immediately after the power supply of the circuit device 2 is turned on, but becomes a signal at a low level thereafter, and outputs a signal at a high level in the case where the output voltage of the regulator 61 is stabilized. In the present embodiment, the signal output from the power-on reset circuit 40 is input to the control circuit 50. The output of the power-on reset circuit 40 can be used for various purposes. For example, a structure in which a register provided in the control circuit 50 is reset on the basis of the signal output from the power-on reset circuit 40 in the case where the output voltage of the regulator 61 is stabilized, or the like, can be employed.

[0039] The temperature sensor 70 is a circuit that outputs a signal corresponding to the temperature of the surroundings of the temperature sensor 70, and can be configured by various known circuits. For example, a circuit that outputs a signal of a voltage corresponding to the temperature using various diodes, or the like, can be employed. Of course, the signal corresponding to the temperature can be a current, and the temperature can be detected by both the voltage and the current. The signal corresponding to the temperature output from the temperature sensor 70 is supplied to the control circuit 50.

[0040] The control circuit 50 is a circuit that performs processing on the basis of various input signals and outputs a signal corresponding to the processing result. The control circuit 50 can implement various processing. For example, the control circuit 50 can be configured to output a digital value indicating the temperature from the temperature data output terminal TDATA by performing a predetermined arithmetic processing on the basis of the output signal of the temperature sensor 70. The control circuit 50 is configured to be able to perform various processing in addition to the output processing of the digital value indicating the temperature. For example, the control circuit 50 can perform an arithmetic processing corresponding to the reception of the mode change instruction and the input signal in the changed mode.

[0041] (2) Single-wire serial communication mode:

[0042] As described above, the circuit device 2 is capable of operating in a mode other than the normal mode, and in the present embodiment, the control circuit 50 operates in the normal mode when a certain time (for example, 0.8 ms) elapses after the power supply.

[0043] On the other hand, in the normal mode, if a prescribed signal is input to the output enable terminals CLK2_EN, CLK3_EN of the oscillation signal, the control circuit 50 shifts to the two-wire serial communication mode. That is, when a prescribed signal is input to the output enable terminals CLK2_EN, CLK3_EN of the oscillation signal, the value of the shift register possessed by the control circuit 50 is rewritten. Also, in the case where the value of this shift register is a specific value, the control circuit 50 operates in the two-wire serial communication mode.

[0044] Further, in the two-wire serial communication mode, by inputting the serial clock SCL, the serial data SDA to the output enable terminals CLK2_EN, CLK3_EN of the oscillation signal, respectively, the value of the shift register possessed by the control circuit 50 can be rewritten. Also, in the case where the value of this shift register is a specific value, the control circuit 50 operates in the single-wire serial communication mode. The control circuit 50 possesses a single-wire communication circuit 59 that performs signal processing in the single-wire serial communication mode. When operating in the single-wire serial communication mode, the control circuit 50 electrically connects the single-wire communication circuit 59 to the terminal CLK3_EN, becoming a state of performing signal processing based on the single-wire communication circuit 59.

[0045] Further, in the single-wire serial communication mode, by inputting a pulse of a width corresponding to a digital value to the output enable terminal CLK3_EN of the oscillation signal, the value of the shift register possessed by the control circuit 50 can be rewritten. Then, the oscillation signal output is selected in accordance with the value of this shift register.

[0046] As described above, the control circuit 50 is capable of operating in various modes. Also, when the various modes are different, the functions of the terminals (CLK2_EN, CLK3_EN, TDATA) electrically connected to the control circuit 50 change. This change in function is realized by configuring the circuit electrically connected inside the control circuit 50 to switch in accordance with the mode.

[0047] Figure 2 is a block diagram showing the single-wire communication circuit 59. The single-wire communication circuit 59 includes an output register 51, a counter circuit 52, and a processing circuit 58. The processing circuit 58 includes a shift register circuit 53, a latched signal generation circuit 54, synchronization flip-flops 55a to 55c, and an exclusive OR circuit 56.

[0048] The output register 51 is a circuit that stores data corresponding to the external signal OS input from the terminal CLK3_EN. The counter circuit 52 is a circuit that counts the period during which the external signal OS is at a high level and the period during which the external signal OS is at a low level using the clock signal CLK output from the frequency division circuit 30. The shift register circuit 53 and the latch signal generation circuit 54 are circuits that write the bit value corresponding to the external signal OS to the output register 51 in accordance with the count result of the counter circuit 52.

[0049] Therefore, in the present embodiment, the output register 51 is a storage circuit, and the terminal CLK3_EN is the first terminal. Also, the clock signal CLK output from the frequency division circuit 30 is a clock signal generated in accordance with the oscillation signal of the vibrator 3. Furthermore, in the present embodiment, the high level of the external signal OS is the first polarity, and the low level is the second polarity.

[0050] The frequency division circuit 30 is electrically connected to the clock terminals of the synchronization flip-flops 55a to 55c, and the clock signal CLK output from the frequency division circuit 30 is input as a clock. In addition, the synchronization flip-flops 55a to 55c are connected in cascade. That is, the terminal CLK3_EN is electrically connected to the input terminal of the synchronization flip-flop 55a, and the external signal OS becomes an input signal. The output of the synchronization flip-flop 55a is input to the synchronization flip-flop 55b, and the output of the synchronization flip-flop 55b is input to the synchronization flip-flop 55c. The outputs of the synchronization flip-flops 55b and 55c are input to the exclusive OR circuit 56.

[0051] With the above structure, the synchronization flip-flops 55a to 55c function as a shift register that transfers the level of the external signal OS to the flip-flops in the subsequent stage in the order of the synchronization flip-flops 55a, 55b, and 55c in synchronization with the clock signal CLK. Therefore, when the level of the external signal OS is constant for four or more clocks of the clock signal CLK, the outputs of the synchronization flip-flops 55a to 55c all become the same level. On the other hand, after the level of the external signal OS changes, during the period until the clock signal CLK is input three times, it is possible to become a state in which the outputs of the synchronization flip-flops 55a to 55c are different from each other.

[0052] Then, after the level of the external signal OS changes, when the 2 clock signals CLK are input, the outputs of the synchronization flip-flops 55b, 55c become different levels. Since the outputs of the synchronization flip-flops 55b, 55c are input to the same exclusive OR circuit 56, the exclusive OR circuit 56 outputs a high level in the case where the outputs of the synchronization flip-flops 55b, 55c are different levels. On the other hand, in the other state, that is, in the case where the outputs of the synchronization flip-flops 55b, 55c are the same, the exclusive OR circuit 56 outputs a low level. Thus, the synchronization flip-flops 55a to 55c and the exclusive OR circuit 56 constitute a circuit that outputs a pulse (a pulse generated at a timing delayed by several clocks) that is synchronized with the level change of the external signal OS. In the present embodiment, this pulse is referred to as a polarity inversion detection signal LD. In addition, in the present embodiment, the synchronization flip-flops 55a to 55c are 3 flip-flop circuits in total, but the number of flip-flop circuits is not limited to this number as long as it is 2 or more.

[0053] The counter circuit 52 is a circuit that inputs the clock signal CLK and the polarity inversion detection signal LD and outputs a count signal cnt that indicates the count result of the clock signal CLK. Such a circuit can be constituted by, for example, a known shift register. In the present embodiment, the counter circuit 52 outputs the 8-bit count signal cnt in parallel from the output. In the drawing, the output signal line is represented by one line. Figure 2

[0054] Specifically, the counter circuit 52 starts counting the clock signal CLK in response to the input of the polarity inversion detection signal LD. Further, the counter circuit 52 changes the value of the least significant bit each time the clock signal CLK is input and shifts this value to the higher bits in turn. As a result, the counter circuit 52 counts the number of times the clock signal CLK is input within the range of 0 to 255 counts and outputs this as the count signal cnt in parallel. For example, if the clock signal CLK is counted 2 times, the count signal cnt becomes 00000010, and if the clock signal CLK is counted 15 times, the count signal cnt becomes 00001111.

[0055] The counter circuit 52 starts counting the clock signal CLK in response to the input of the polarity inversion detection signal LD, and thus, if the polarity inversion detection signal LD is input before reaching 255 counts, the counting is restarted. That is, the external signal OS is a signal that repeatedly changes between a high level and a low level, and thus, the counter circuit 52 starts counting each time the level of the external signal OS changes. As a result, the counter circuit 52 repeatedly performs the following processes in turn: outputting the count result indicating the period during which the external signal OS is at a high level as the count signal cnt, and next, outputting the count result indicating the period during which the external signal OS is at a low level as the count signal cnt.​

[0056] The shift register circuit 53 is a circuit that is input with the clock signal CLK, the external signal OS, the count signal cnt output from the counter circuit 52, and outputs a parallel signal of the same value in the number of bits corresponding to the value indicated by the count signal cnt. That is, the shift register circuit 53 outputs a parallel signal of the same level as the level of the external signal OS in the number of bits corresponding to the size of the count value indicated by the count signal cnt. Here, this output is referred to as the sftreg signal.

[0057] Figure 3 is a diagram showing an example of the relationship between the count result and the sftreg signal. When the count result is in the mth range during the period in which the external signal OS is at the high level, the shift register circuit 53 outputs a parallel signal in which m bits from the lowest bit to the higher bits are at the high level. On the other hand, when the count result is in the nth range during the period in which the external signal OS is at the low level, the shift register circuit 53 outputs a parallel signal in which n bits from the lowest bit to the higher bits are at the low level. Note that in the present embodiment, the mth range and the nth range are the same range, but can be different ranges from each other.

[0058] Here, the mth range is defined by a lower threshold value and an upper threshold value that determine the number of bits that change depending on the count result. Specifically, in the present embodiment, when k is a unit count value that is a natural number, and Δk is a unit allowable error number that is a natural number, the mth range is a range in which the count result is any one of m x (k - Δk) to m x (k + Δk). As long as k is a natural number and Δk is a natural number smaller than k, but in the present embodiment, k is 31 and Δk is 2. Thus, the 1st range is 31 ± 2, and the 2nd range is 62 ± 4. Note that the unit allowable error is a value for defining a range in which the number of counts is allowed to deviate from k, and can be various values.

[0059] In the present embodiment, the shift register circuit 53 outputs a parallel signal in which m bits from the lowest bit to the higher bits are at the high level when the count result is in the mth range during the period in which the external signal OS is at the high level or the low level. Thus, for example, in the case where the count result is 31 during the period in which the external signal OS is at the high level, the count result is in the 1st range, and thus the shift register circuit 53 outputs the sftreg signal in which the lowest bit is at the level 1. Thereafter, when the period in which the external signal OS is at the high level continues and the count result becomes 62, the count result is in the 2nd range, and thus the shift register circuit 53 outputs the sftreg signal in which the 2 lowest bits are at the level 1.

[0060] When the count result during the period in which the external signal OS is at the low level is 31, the count result is in the 1st range, and therefore the shift register circuit 53 outputs the sftreg signal of which the lowest bit is 0. After that, when the period in which the external signal OS is at the low level continues and the count result becomes 62, the count result is in the 2nd range, and therefore the shift register circuit 53 outputs the sftreg signal of which the lower 2 bits are 0.

[0061] The shift register circuit 53 as described above can be implemented by a known circuit such as a flip-flop circuit that outputs the value of each bit and a selector circuit that controls the input of a signal to each flip-flop circuit, and the like. That is, eight flip-flop circuits are connected in cascade by the selector circuit. Here, the output of the 1st flip-flop circuit is the value of the lowest bit, and the outputs of the 8th flip-flop circuit connected in cascade are taken as the sftreg signals in parallel, respectively.

[0062] The input of the 1st flip-flop circuit that outputs the value of the lowest bit of the sftreg signal is input with the external signal OS via a selection circuit. This selection circuit inputs the external signal OS to the flip-flop circuit when the value of the count signal cnt is in the 1st range. Therefore, the output of the 1st flip-flop circuit becomes the same level as the level of the external signal OS.

[0063] Further, the input of the Lth flip-flop circuit that outputs the value of the Lth bit of the sftreg signal is input with the output of the (L-1)th flip-flop circuit via a selector circuit (where L is a natural number from 2 to 8). In this structure, the selection circuit corresponding to the Lth flip-flop circuit inputs the output of the (L-1)th flip-flop circuit to the flip-flop circuit when the value of the count signal cnt is in the Lth range. Therefore, when the period in which the level of the external signal OS is constant reaches the Lth range in the number of counts of the clock signal, the output of the Lth flip-flop circuit becomes the same level as the output of the (L-1)th flip-flop circuit.

[0064] As described above, in the shift register circuit 53, depending on the count result of the count signal cnt, the number of bits in which the level of the external signal OS is shifted in the flip-flop circuit is decided, and the result of the shift is output as the sftreg signal. As a result, a parallel signal in which the bit values of the same level as the level of the external signal OS are continuous is output, and the number of the continuous bits is the number of bits corresponding to the magnitude of the count value indicated by the count signal cnt. In addition, the trigger for outputting the sftreg signal from each flip-flop circuit can be generated at various timings, and in the present embodiment, the sftreg signal is configured to be output from each flip-flop circuit in synchronization with the timing at which the polarity inversion detection signal LD becomes the high level.

[0065] The latch signal generating circuit 54 is a circuit for controlling whether or not to write the sftreg signal output from the shift register circuit 53 into the output register 51. In the single-wire serial communication mode of the present embodiment, the communication rule is defined so that the external signal OS is input to the control circuit 50 in units of 8-bit information. Therefore, the latch signal generating circuit 54 outputs an output enable signal for storing the sftreg signal to the output register 51 when the clock signal CLK is counted by 8 bits. In the present embodiment, this signal is referred to as out_EN.

[0066] Such a latch signal generating circuit 54 can be implemented by a well-known circuit such as an 8-bit flip-flop circuit in which the bit corresponding to the count result of the clock signal CLK is set to the high level, a selector circuit for controlling the signal input to each flip-flop circuit, an AND gate, or the like.

[0067] That is, the selector circuit is connected to the input of each of the 8 flip-flop circuits. The outputs of the 8 flip-flop circuits are input to the AND gate. The input of the selector circuit is a signal fixed to the high level or the low level. In the selector circuit, in the initial state, the input of the low level is selected and output. On the other hand, the selector circuit corresponding to the flip-flop circuit outputting the value of the Lth bit selects the signal of the high level when the value of the count signal cnt is in the Lth range (L is a natural number from 1 to 8). In addition, each selector circuit becomes the initial state when the polarity inversion detection signal LD becomes the high level, and thereafter, does not return to the initial state until the next clock signal CLK is counted by 8 bits after the output signal is selected.

[0068] Therefore, the flip-flop circuit outputting the value of the 1st bit (the bit of the lowest level) is input with the signal of the high level when the value of the count signal cnt is in the 1st range. Similarly, the flip-flop circuit outputting the value of the Lth bit is input with the signal of the high level when the value of the count signal cnt is in the Lth range. Therefore, if the clock signal CLK is input to the flip-flop circuit after the value of the count signal cnt becomes the 8th range, it becomes a state in which the parallel signal in which all the bits of 8 bits are the high level is output.

[0069] The outputs of the flip-flop circuits are input to the AND gate, so the signal of the high level is output from the AND gate only when all the bits of 8 bits as the output of the flip-flop circuit are the high level. Therefore, the latch signal generating circuit 54 outputs the out_EN signal to the output register 51 when the clock signal CLK is counted by 8 bits.

[0070] The output register 51 is a storage circuit that stores the sftreg signal. That is, the output register 51 has a plurality of flip-flop circuits that store the bit values of the sftreg signal triggered by the out_EN signal. The out_EN signal is output in synchronization with the timing of the clock signal CLK counted by 8 bits, and therefore the output register 51 holds the bit values of the sftreg signal by the flip-flop circuits in synchronization with the timing of the clock signal CLK counted by 8 bits.

[0071] In addition, in the present embodiment, the counter circuit 52 is configured to obtain a count value of 8 bits, and therefore the number of bits that can be used for the sftreg signal output from the shift register circuit 53 is at most 8 bits. However, the amount of information of the data recorded in the output register 51 and referred to can be less than 8 bits. In this case, in the output register 51, the number of flip-flop circuits that store the values of the sftreg signal can be less than 8.

[0072] Hereinafter, an example of using the lower 6 bits of the sftreg signal will be described. When the values are stored in the flip-flop circuits of the output register 51, the control circuit 50 performs an operation corresponding to the values of the bits. In the present embodiment, the control circuit 50 determines whether the buffer circuits 22, 23 can output depending on the values of the bits, and adjusts the capabilities of the buffer circuits 22, 23.

[0073] Figure 4 The functions of the values of the bits in the present embodiment will be described, with the function of the lowest bit being described at the bottom, and the functions of the higher bits being described upward. That is, the lowest bit is a bit that specifies whether to output the second clock signal. In the case where the lowest bit is 1, the control circuit 50 outputs the second clock signal from the buffer circuit 22. In the case where the lowest bit is 0, the control circuit 50 does not cause the buffer circuit 22 to output the second clock signal. The second and third bits are bits that specify the amplitude of the second clock signal. The control circuit 50 causes the second clock signal to change in four stages depending on the value of the two bits represented by the second and third bits.

[0074] The fourth bit is a bit that specifies whether to output the third clock signal. In the case where the fourth bit is 1, the control circuit 50 causes the buffer circuit 22 to output the third clock signal. In the case where the fourth bit is 0, the control circuit 50 does not cause the buffer circuit 22 to output the second clock signal. The fifth and sixth bits are bits that specify the amplitude of the third clock signal. The control circuit 50 causes the third clock signal to change in four stages depending on the value of the two bits represented by the fifth and sixth bits.

[0075] With the above structure, the oscillator 1 of the present embodiment can receive data adjusting the capabilities of the buffer circuits 22, 23 through the single-wire serial communication mode, and adjust the capabilities of the buffer circuits 22, 23. According to the oscillator 1 of the present embodiment, by determining the period during which the external signal OS is high and the period during which the external signal OS is low using the number of counts of the clock signal CLK, it is possible to determine the data represented by the external signal OS. Therefore, in the present embodiment, it is not necessary to impart a large difference in the pulse length of the external signal OS in order to distinguish between the values of 0 and 1 of the data represented by the external signal OS. Therefore, when inputting either of 0 and 1 of the data represented by the external signal OS, it is not necessary to wait for an excessively long time compared to the other, and it is possible to efficiently input serial data. Furthermore, it is possible to distinguish between 0 and 1 of the data represented by the external signal OS by the level of the external signal OS. Therefore, even if a large difference is not imparted to the pulse length, it is possible to clearly distinguish between 0 and 1 of the data.

[0076] Furthermore, in the present embodiment, when the count result of the period during which the polarity is fixed is in a predetermined mth range, the value of m consecutive bits is written to the output register 51. Therefore, by adjusting the size of the mth range, it is possible to adjust the responsiveness to noise and the accuracy with respect to the external signal. That is, if the mth range is narrowed, the range of the count for changing the data becomes small, so it is less likely to be affected by noise. However, if the mth range is narrowed, it is necessary to more accurately control the period during which the polarity is fixed.

[0077] Therefore, according to the size of the mth range, it is possible to adjust the responsiveness to noise and the accuracy with respect to the external signal. In addition, even if the mth range used for counting the period during which the polarity is the first polarity is different from the nth range used for counting the period during which the polarity is the second polarity, the same effect is obtained.

[0078] Furthermore, in the present embodiment, the mth range (or the nth range) is a range in which the count result is any one of m x (k - Δk) to m x (k + Δk). Therefore, the larger the size of m (or n) is, the wider the mth range is. The larger the count value is, the more likely the count value is to be affected by noise. However, if a structure in which the larger m is, the wider the mth range is, is adopted, it is possible to suppress the degree to which the influence by noise increases as the count value increases.

[0079] (2-1) Action Example:

[0080] As explained above, in the single-wire serial communication mode of the present embodiment, a bit value is expressed by the level of the external signal OS and the period during which the external signal OS is at a certain level. Also, in the present embodiment, the external signal OS is a signal input from the terminal CLK3_EN. Therefore, a user who inputs the external signal OS in the single-wire serial communication mode needs to input a pulse signal to the terminal CLK3_EN from an external device present outside the oscillator 1.

[0081] The external device only needs to be able to input a pulse signal to the terminal CLK3_EN so that the voltage level varies within a predetermined range. In Figure 1 In the present embodiment, an external device 100 for inputting this pulse signal to the terminal CLK3_EN is exemplified. The external device 100 of the present example includes a taking circuit 110, a frequency dividing circuit 120, and an external signal generating circuit 130. The taking circuit 110 accepts input of 8-bit data from a user. The taking circuit 110 accepts input from a user through an input interface not shown, and determines data that should be stored in the output register 51.

[0082] The frequency dividing circuit 120 is connected to the output terminal CLK1, and divides the oscillation signal output from the buffer circuit 21, that is, the first clock signal. In the present embodiment, the frequency dividing circuit 120 is the same circuit as the frequency dividing circuit 30, and converts the first clock signal of 76.8 MHz into a signal of the same frequency as the frequency dividing circuit 30, that is, a clock signal of 4.8 MHz.

[0083] The external signal generating circuit 130 is a circuit that generates an external signal OS corresponding to data input from a user, based on the clock signal of 4.8 MHz output from the frequency dividing circuit 120. That is, the taking circuit 110 outputs a signal indicating data input from a user to the external signal generating circuit 130. The external signal generating circuit 130 outputs, as the external signal OS, a signal of a level corresponding to a bit value of 8-bit data input from a user and a signal of a level that is maintained for a number of bits × a unit count value k of a signal of the same period as the clock signal CLK of 4-bit × k times, corresponding to the bit value.

[0084] For example, assume a case where data input from a user is 11110000. In this case, the external signal generating circuit 130 outputs, as the external signal OS, a signal of a high level corresponding to a bit value of 1 for a period that is the same as the clock signal CLK of 4-bit × k times, and a signal of a low level corresponding to a bit value of 0 for a period that is the same as the clock signal CLK of 4-bit × k times. Further, the external device 100 corresponds to, for example, a processor or the like in a case where the oscillator 1 is mounted on an electronic device such as a smartphone.

[0085] According to the above structure, a user can perform single-wire serial communication by only instructing data to the taking circuit 110, and adjust the capacity of the buffer circuits 22, 23. Also, according to the present embodiment, the external signal OS is a signal that is input from the terminal CLK3_EN, and thus the user can easily input the external signal OS.Figure 1 As shown in the structure, the external signal OS can be adjusted in the period in which the polarity is fixed, based on the oscillation signal of the vibrator 3 and the oscillation circuit 10 which are the same signal source as the frequency dividing circuit 30. Therefore, when counting the period in which the polarity of the external signal OS is fixed, the period can be accurately measured based on the clock signal CLK output from the frequency dividing circuit 30.

[0086] Figure 5 and Figure 6 are timing charts showing examples of the count signal cnt or the sftreg signal obtained based on the external signal OS in the single-wire serial communication mode. In these charts, x indicates that the value of the signal is not fixed. In Figure 5 and Figure 6 In Figure 6 is a timing chart in which the count signal cnt obtained based on the external signal OS is shown in the time series. Figure 5 is a timing chart in which the sftreg signal obtained based on the external signal OS is shown in the time series. Figure 5 the last part of Figure 6 the initial part of

[0087] When the polarity of the external signal OS is changed from the low level to the high level at the time tO, the polarity inversion detection signal LD is output from the "exclusive OR" circuit 56 at the time tl after the clock signal CLK is input a prescribed number of times from the time of the change of the polarity. The counter circuit 52 starts counting with the polarity inversion detection signal LD as a trigger. In Figure 5 and Figure 6 In

[0088] In addition, Figure 5 the external signal OS shown in

[0089] In addition, the count 29 is in the first range, and therefore the value of 1 bit output from the shift register circuit 53 becomes the sftreg signal which is the value indicating that the external signal OS is the high level, that is, 1. The shift register circuit 53 outputs the sftreg signal in synchronization with the time at which the polarity inversion detection signal LD becomes the high level. Therefore, in the example shown in Figure 5 the shift register circuit 53 outputs the sftreg signal in which the lowest bit is set to 1 at the time t3.

[0090] During this stage, no 8-bit counting is performed, so the latch signal generation circuit 54 does not output the out_EN signal. Therefore, no writing is performed to the output register 51 during this stage.

[0091] exist Figure 5 In the example shown, from time t2, after the external signal OS changes to a low level, until time t4, i.e., during the period when the clock signal CLK has counted 124 times, it remains at a low level. In this case, the counter circuit 52 counts until it reaches 124. Since 124 is the fourth range, the shift register circuit 53 shifts the value of the least significant bit (1) to the high-order bits while outputting the lower 4 bits as a sftreg signal representing a low level (0). The shift register circuit 53 outputs the sftreg signal synchronously with the moment the polarity inversion detection signal LD ​​goes high. Therefore, in... Figure 5 In the example shown, the shift register circuit 53 outputs the sftreg signal xxx1_0000 at time t5, with the 5th bit set to 1 and the lower 4 bits set to 0.

[0092] During this stage, since no 8-bit counting is performed, the latch signal generation circuit 54 does not output the out_EN signal. Therefore, no writing is performed to the output register 51 during this stage.

[0093] In this example, at time t4, after the external signal OS changes to a high level, as follows: Figure 6 As shown, the clock signal CLK remains high during the period up to time t6, i.e., when it has counted 93 times. In this case, the counter circuit 52 counts to count 93. Since count 93 is the third value, the shift register circuit 53 shifts the existing 5-bit value 1_0000 up while outputting the lower 3 bits as an sftreg signal indicating a high level. The shift register circuit 53 outputs the sftreg signal synchronously with the polarity inversion detection signal LD ​​going high. Therefore, in... Figure 6 In the example shown, the shift register circuit 53 outputs an sftreg signal 1000_0111 at time t7, with the 5 high bits being 1_0000 and the 3 low bits being 111.

[0094] During this stage, an 8-bit count is performed, so the latch signal generation circuit 54 outputs the out_EN signal at time t8. Therefore, during this stage, data identical to the 1000_0111 bit value of the sftreg signal is written to the output register 51. In this embodiment, data can be written to the output register 51 in this order. By adjusting the lower 6 bits of the sftreg signal, the user can specify whether the output buffer circuits 22 and 23 are enabled, and also specify the capability of the buffer circuits 22 and 23. Afterwards, by inputting a predetermined signal to a predetermined terminal, such as switching the control circuit 50 to normal mode, the user causes the buffer circuits 22 and 23 to output an oscillation signal with the set capability.

[0095] (3) Other implementation methods:

[0096] The above-described embodiments are examples for implementing the present invention, and various other embodiments may also be employed. Furthermore, the application of the circuit device 2 of one embodiment of the present invention is not limited, and it can be used in various devices, such as various electronic devices, electrical installations in vehicles, etc. Moreover, the circuitry of the oscillator 1 is not limited to the above-described embodiments. Figure 1 The circuit shown can be supplemented with various other circuits, or parts of the circuit can be omitted. For example, oscillator 1 can include a PLL circuit, and the oscillation signal output from oscillation circuit 10 can be processed by various buffer circuits such as waveform shaping buffer circuits before being input to buffer circuits 21-23. Furthermore, the oscillation signals that can be output from circuit device 2 do not have to be three types. For example, the oscillation signals output from the buffer circuits can be any one type, two types, or four or more types, and the circuit has the ability to adjust at least one type of oscillation signal in a single-wire serial communication mode.

[0097] Furthermore, the components or circuits constituting the above-described embodiment are just one example, and can also be composed of various alternative components or circuits. Additionally, each circuit, such as output register 51, counter circuit 52, shift register circuit 53, and latch signal generation circuit 54, can be designed using various methods. For example, the function of the circuit can be described using a hardware description language, and the components or connections of each circuit can be determined through methods such as simulation or verification, or automatic circuit design.

[0098] Furthermore, the above implementation is an SPXO (Simple Packaged Crystal Oscillator), but it can also be an oscillator of other types, such as a TCXO (Temperature Compensated Crystal Oscillator) or a VCXO (Voltage Controlled Crystal Oscillator).

[0099] Further, the functions of the terminals possessed by the circuit device 2 are one example, and can be different, and terminals for specific functions can be assigned to terminals different from those shown. Also, the functions in each mode are not limited to the above functions. Further, in the single-wire serial communication mode, in addition to the terminal that inputs the external signal OS, various functions can be used in various terminals. For example, it can be a structure that can output temperature data, or a structure that outputs an oscillation signal from at least one of the buffer circuits 21 to 23 by inputting an enable signal to a terminal. Figure 1

[0100] Further, the mth range for deciding whether to increase the number of bits based on the count result of the clock signal CLK is not limited to the range defined as described above. That is, as long as m is set to a natural number, the mth range can be defined in a manner such that the count included in the (m+1)th range is a value larger than the count included in the mth range. Therefore, for example, the mth range and the (m+1)th range can be discrete as in the above embodiment, or can be continuous. As the latter, for example, each range can be set in a manner such that the upper limit value and the lower limit value of adjacent ranges are consecutive natural numbers, such as 1 to 34 as the first range, 35 to 67 as the second range, and so on. Such a range, even when it is the nth range used when counting the period of the second polarity, can be set similarly.

[0101] Further, in the single-wire serial communication mode, it can be confirmed whether communication in the single-wire serial communication mode can be started. For example, the circuit device 2 can be configured to, in a case where the data corresponding to the external signal OS is prescribed data, perform an operation corresponding to the data corresponding to the external signal OS that is input next. In this structure, the circuit device 2 does not perform an operation corresponding to the data corresponding to the external signal OS that is input next in a case where the data corresponding to the external signal OS is not prescribed data.

[0102] That is, if prescribed data is not input as the external signal OS, communication based on the single-wire serial communication mode does not hold. According to this structure, the circuit device 2 can perform an operation corresponding to the data corresponding to the external signal OS after confirming that communication in the single-wire serial communication mode is being properly implemented based on the prescribed data. Therefore, it is possible to prevent a case where improper data is stored in the output register 51 due to an improper external signal, and an operation corresponding to the improper data is performed.

[0103] ​The above configuration can be implemented by, for example, the control circuit 50 monitoring the data stored in the output register 51, and causing the output register 51 to store the data corresponding to the next external signal in the case where the stored data is predetermined data. In this case, if the data stored in the output register 51 is not the predetermined data, the data corresponding to the next external signal is not stored in the output register 51.

[0104] Of course, this configuration is an example, and regardless of whether the data stored in the output register 51 is the predetermined data, the data corresponding to the next external signal is stored in the output register 51, but it is also possible to adopt a configuration in which, if the stored data is not the predetermined data, the processing corresponding to the data stored in the output register 51 is not started. Furthermore, the processing of confirming the data in accordance with the prescribed data to determine whether the communication is appropriate can be implemented in any unit. For example, it can be a configuration in which the confirmation of the prescribed data is performed every time the communication of 8 bits is performed, or the confirmation of the prescribed data is not performed after the confirmation of the prescribed data is performed until the communication of the prescribed bits is performed.

Claims

1. An oscillator, characterized in that, It includes an oscillator and circuitry. The circuit device has: Terminal 1; A storage circuit that stores data corresponding to an external signal input from the first terminal; An oscillating circuit that uses the oscillator to generate an oscillating signal; A counter circuit that uses a clock signal generated based on the oscillation signal to count the periods when the external signal is of the first polarity and the periods when the external signal is of the second polarity; as well as The processing circuit writes the data into the storage circuit based on the counting result of the counter circuit. When the counting result during the period when the external signal is of the first polarity is in the m-th range, the processing circuit writes a continuous m-bit first value to the storage circuit, where m is a natural number, and the number of counts contained in the (m+1)-th range is a value larger than the number of counts contained in the m-th range.

2. The oscillator according to claim 1, wherein, When k is the unit count value as a natural number and Δk is the unit allowable error number as a natural number, the m-th range is the range that makes the counting result any one of m×(k-Δk) to m×(k+Δk).

3. An oscillator, characterized in that, It includes an oscillator and circuitry. The circuit device has: Terminal 1; A storage circuit that stores data corresponding to an external signal input from the first terminal; An oscillating circuit that uses the oscillator to generate an oscillating signal; A counter circuit that uses a clock signal generated based on the oscillation signal to count the periods when the external signal is of the first polarity and the periods when the external signal is of the second polarity; as well as The processing circuit writes the data into the storage circuit based on the counting result of the counter circuit. When the counting result during the period when the external signal becomes the second polarity is in the nth range, the processing circuit writes a second value of n consecutive bits to the storage circuit, where n is a natural number and the number of counts contained in the (n+1)th range is a value larger than the number of counts contained in the nth range.

4. The oscillator according to claim 3, wherein, When k is the unit count value as a natural number and Δk is the unit allowable error number as a natural number, the nth range is the range that makes the counting result any one of n×(k-Δk) to n×(k+Δk).

5. The oscillator according to any one of claims 1 to 3, wherein, When the data corresponding to the external signal is predetermined data, the circuit device performs an action corresponding to the data corresponding to the subsequently input external signal. If the data corresponding to the external signal is not the specified data, the action corresponding to the data of the subsequently input external signal will not be performed.

6. The oscillator according to any one of claims 1 to 3, wherein, The circuit device also includes a buffer circuit for buffering and outputting the oscillation signal. The data stored in the storage circuit includes data on the ability to adjust the buffer circuit.

7. The oscillator according to any one of claims 1 to 3, wherein, The data stored in the storage circuit includes data indicating whether to output the oscillation signal.

8. The oscillator according to any one of claims 1 to 3, wherein, The oscillator also includes a container for housing the oscillator and the circuitry. The container has a first external terminal that is electrically connected to the first terminal.

9. The oscillator according to any one of claims 1 to 3, wherein, The oscillation circuit supplies the oscillation signal to an external device. The external signal is a signal generated by the external device using a clock signal generated based on the oscillation signal.

10. A communication method using an oscillator comprising an oscillator and circuitry, comprising: An external device inputs an external signal to the first terminal of the circuit device; The oscillator uses the oscillator to generate a clock signal; The clock signal is used to count the periods during which the external signal is of the first polarity and the periods during which the external signal is of the second polarity; as well as Based on the counting results, the data corresponding to the external signal is written into the storage circuit. When the counting result during the period when the external signal is of the first polarity is in the m-th range, the first value of m consecutive bits is written to the storage circuit, where m is a natural number, and the number of counts contained in the (m+1)-th range is a value larger than the number of counts contained in the m-th range.

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