A capacitor cross-charge and discharge oscillation circuit

Abstract

The present invention discloses a capacitor cross-charge and discharge type oscillator circuit, which belongs to the field of analog circuits, and includes a charge and discharge circuit, a switch control logic circuit, a level conversion circuit and a three-level inverter circuit; the charge and discharge circuit generates a clock oscillation waveform through capacitor cross-charge and discharge and under the control of the switch control logic circuit, and is converted into a pair of complementary input signals and transmitted to the switch control logic circuit; the switch control logic circuit generates a pair of complementary control signals for controlling the opening and closing of the charging and discharging paths in the charge and discharge circuit, thereby realizing an independent cross-charge and discharge path; the three-level inverter circuit is used for logic inversion and waveform shaping at the same time; the level conversion circuit converts the oscillation signal to a power supply voltage output. The present invention can not only solve the problem of unstable oscillation period, but also break through the limitation that the capacitance in the integrated chip is only about pF, and obtain a lower frequency and stable oscillation signal.

Description

Technical Field

[0001] The present invention relates to the technical field of analog circuits, and in particular to a capacitor cross-charging and discharging oscillating circuit. Background Art

[0002] At present, the mainstream voltage-controlled oscillators are divided into LC oscillators and ring oscillators. LC oscillators are usually composed of on-chip capacitors, inductors and active devices, with high quality factors and good phase noise characteristics; however, the limited tuning range, large on-chip inductor area, and difficulty in compatibility with CMOS processes are also key defects of LC oscillators. In contrast, ring oscillators have the advantages of large tuning range, support for multi-phase output, small footprint, simple circuits, easy integration, and low cost. With the rapid development of CMOS processes and on-chip systems, they have become a very attractive choice and are widely used.

[0003] The basic structure of a ring oscillator is a closed loop formed by connecting multiple delay units in series. It has poor noise suppression capability and is greatly affected by the power supply voltage, resulting in an unstable oscillation period. It is not suitable for designing high-performance ring oscillators. Summary of the invention

[0004] The purpose of the present invention is to provide a capacitor cross-charge and discharge oscillation circuit to solve the problem that the traditional ring oscillator has poor noise suppression ability and is greatly affected by the power supply voltage, resulting in unstable oscillation period; at the same time, the capacitor Cj in the circuit can be replaced by an off-chip capacitor to break through the limitation that the conventional integrated chip internal capacitor is only about pF level, and obtain a lower frequency oscillation period, and the off-chip Cj capacitor can reach nF level.

[0005] In order to solve the above technical problems, the present invention provides a capacitor cross-charge and discharge oscillation circuit, comprising a charge and discharge circuit, a switch control logic circuit, a level conversion circuit and a three-level inverter circuit;

[0006] The charging and discharging circuit generates a clock oscillation waveform through capacitor cross-charging and discharging and under the control of the switch control logic circuit, and is converted into a pair of complementary input signals and transmitted to the switch control logic circuit;

[0007] The switch control logic circuit generates a pair of complementary control signals for controlling the opening and closing of the charging and discharging paths in the charging and discharging circuit, thereby realizing independent cross-charging and discharging paths;

[0008] The level conversion circuit converts the oscillation signal into a power supply voltage output;

[0009] The three-stage inverter circuit is used for logic inversion and waveform shaping at the same time.

[0010] In one embodiment of the present invention, the charging and discharging circuit includes a capacitor C, PMOS tubes MP0-MP5, MP10, MP12, MP14 and NMOS tubes MN6-MN9, MN11, MN13;

[0011] The source terminals of the PMOS tubes MP1, MP3, and MP5 are connected to the input terminal PB, and the drain terminals are connected to the source terminals of the PMOS tubes MP0, MP2, and MP4 respectively. The drain terminal of the PMOS tube MP0 is connected to the input terminal Vin, the drain terminal of the PMOS tube MP2 is connected to the drain terminal of the NMOS tube MN6, the drain terminal of the PMOS tube MP4 is connected to the drain terminal of the NMOS tube MN7, and the source terminals of the NMOS tubes MN6 and MN7 are both grounded;

[0012] The source end of the PMOS tube MP10 and one end of the capacitor C are connected to the input end PB, the other end of the capacitor C is connected to the drain end of the PMOS tube MP10, the drain end of the NMOS tube MN9, the drain end of the NMOS tube MN11 and the source end of the PMOS tube MP12, the source end of the NMOS tube MN9 is connected to the drain end of the PMOS tube MN8, the gate ends of the NMOS tubes MN9, MN8 and MN7 are connected to the drain end of MN7, and the source end of the NMOS tube MN8 is grounded;

[0013] One end of the capacitor Cj, the drain end of the NMOS tube MN6, the drain end of MN13 and the source end of the PMOS tube MP14 are connected, the source ends of the NMOS tubes MN11 and MN13 and the drain ends of the PMOS tubes MP12 and MP14 are connected to the output end Vout, and the other end of the capacitor Cj is grounded;

[0014] The gate ends of the NMOS transistors MN13 and MP12 are connected to the input end IN2 , and the gate ends of the NMOS transistor MN11 , the PMOS transistor MP10 , the NMOS transistor MN6 , and the PMOS transistor MP14 are connected to the input end IN1 .

[0015] In one embodiment of the present invention, the switch control logic circuit includes three switch control units X1, X2 and X3, and an inverter INV4;

[0016] Each switch control unit has the same structure, and includes NAND gates NAND1, NAND2 and an inverter INV5, wherein input terminals a and b of the switch control unit are respectively connected to one input terminal of the NAND gates NAND1 and NAND2, the other input terminals of the NAND gates NAND1 and NAND2 are respectively connected to the output terminals of the NAND gates NAND2 and NAND1, and the output terminal of the NAND gate NAND1 is connected to the output terminal y through the inverter INV5;

[0017] The input terminal D of the switch control logic circuit is connected to the a input terminal of the switch control unit X1 and the b input terminal of the switch control unit X2, and the input terminal DN of the switch control logic circuit is connected to the b input terminal of the switch control unit X1 and the a input terminal of the switch control unit X2; the outputs of the switch control units X1 and X2 are respectively connected to the a and b input terminals of the switch control unit X3, and the output terminal of the switch control unit X3 is connected to the output terminal EN of the switch control logic circuit through the inverter INV4.

[0018] In one embodiment of the present invention, the level conversion circuit includes PMOS tubes MP15, MP17, MP19, MP21 and NMOS tubes MN16, MN18, MN20, MN22;

[0019] The input terminal Vp of the level conversion circuit is connected to the gate terminals of the PMOS tube MP15, the NMOS tube MN16 and the NMOS tube MN20, the drain terminal of the PMOS tube MP15 and the drain terminal of the NMOS tube MN16 are connected to the gate terminal of the NMOS tube MN18, the drain terminal of the PMOS tube MP17 and the drain terminal of the NMOS tube MN18 are connected to the gate terminal of the PMOS tube MP19, the drain terminal of the PMOS tube MP19, the drain terminal of the NMOS tube MN20, the gate terminal of the PMOS tube MP17, the gate terminal of the PMOS tube MP21 and the gate terminal of the NMOS tube MN22 are connected, and the drain terminal of the PMOS tube MP21 and the drain terminal of the NMOS tube MN22 are connected to the output terminal VO;

[0020] The input terminal PB of the level conversion circuit is connected to the source terminal of the PMOS tube MP15, the source terminals of the PMOS tubes MP17, MP19, and MP21 are connected to the power supply VDD, and the source terminals of the NMOS tubes MN16, MN18, MN20, and MN22 are grounded.

[0021] In one embodiment of the present invention, the three-stage inverter circuit includes inverters INV1, INV2 and INV3; the output end of the charge and discharge circuit is connected to the input end of the inverter INV1, and the inverters INV1 and INV2 are connected in series; the output end of the inverter INV1 and the output end of the inverter INV2 are both connected to the switch control logic circuit; the output end of the switch control logic circuit is connected to the input end of the inverter INV3, and the output end of the inverter INV3 is connected to the level conversion circuit.

[0022] In the capacitor cross-charge and discharge oscillation circuit provided by the present invention, it includes a charge and discharge circuit, a switch control logic circuit, a level conversion circuit and a 3-level inverter circuit; the charge and discharge circuit generates a clock oscillation waveform under the control of the switch control logic circuit, which is converted into a pair of complementary input signals and transmitted to the switch control logic circuit; the switch control logic circuit generates a pair of complementary control signals for controlling the opening and closing of the charging and discharging paths in the charge and discharge circuit, thereby realizing an independent cross-charge and discharge path; the level conversion circuit converts the oscillation signal to a power supply voltage output; the 3-level inverter circuit is used for logic inversion and waveform shaping at the same time. The present invention has an independent charge and discharge channel, and a stable oscillation frequency is formed by cross-charging and discharging of two different capacitors, which can not only solve the problem of unstable oscillation period, but also can adopt the method of external nF-level off-chip capacitors to break through the limitation that the integrated chip capacitor is only about pF-level, and obtain a lower frequency and stable oscillation signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the principle structure of a capacitor cross-charge and discharge oscillation circuit provided by the present invention;

[0024] Figure 2 It is a schematic diagram of the charging and discharging circuit structure provided by the present invention;

[0025] Figure 3 It is a schematic diagram of the structure of the switch control logic circuit provided by the present invention;

[0026] Figure 4 It is a schematic diagram of the structure of the level conversion circuit provided by the present invention;

[0027] Figure 5 It is a schematic diagram of the structure of a three-stage inverting circuit provided by the present invention. DETAILED DESCRIPTION

[0028] The following is a further detailed description of a capacitor cross-charge and discharge oscillator circuit proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0029] The present invention provides a capacitor cross-charge and discharge oscillation circuit, the structure of which is as follows: Figure 1 As shown, it includes a charge and discharge circuit, a switch control logic circuit, a level conversion circuit and a three-level inverter circuit (inverter INV1, inverter INV2 and inverter INV3).

[0030] A pair of complementary input signals A and AN generate a switch control signal TN1 after passing through a switch control logic circuit, and the same pair of complementary input signals A and AN generate a switch control signal TN2 after passing through the switch control logic circuit and inverter INV3 in sequence. The switch control signal TN1 and the switch control signal TN2 are a pair of complementary signals, which are used to control the opening or closing of the charge and discharge paths in the charge and discharge circuit, thereby realizing independent cross-charge and discharge paths; and control the oscillation circuit to select and output the charge or discharge path signal. The source of the complementary input signals A and AN is the oscillation output of the charge and discharge circuit, and the oscillation output of the charge and discharge circuit passes through inverter INV1 to form a complementary input signal A, and the oscillation output of the charge and discharge circuit passes through inverter INV1 and inverter INV2 in sequence to form a complementary input signal AN. Finally, the amplitude of the oscillation signal is converted to the power supply voltage output through a level conversion circuit.

[0031] like Figure 2The structure diagram of the charging and discharging circuit is shown, which includes a capacitor C, PMOS tubes MP0-MP5, MP10, MP12, MP14 and NMOS tubes MN6-MN9, MN11, MN13. The source ends of the PMOS tubes MP1, MP3, and MP5 are connected to the input end PB, and the drain ends are respectively connected to the source ends of the PMOS tubes MP0, MP2, and MP4, the drain end of the PMOS tube MP0 is connected to the input end Vin, the drain end of the PMOS tube MP2 is connected to the drain end of the NMOS tube MN6, the drain end of the PMOS tube MP4 is connected to the drain end of the NMOS tube MN7, and the source ends of the NMOS tubes MN6 and MN7 are both grounded. The source end of the PMOS tube MP10 and one end of the capacitor C are connected to the input end PB, the other end of the capacitor C is connected to the drain end of the PMOS tube MP10, the drain end of the NMOS tube MN9, the drain end of the NMOS tube MN11 and the source end of the PMOS tube MP12, the source end of the NMOS tube MN9 is connected to the drain end of the PMOS tube MN8, the gate ends of the NMOS tubes MN9, MN8 and MN7 are connected to the drain end of MN7, and the source end of the NMOS tube MN8 is grounded. One end of the capacitor Cj, the drain end of the NMOS tube MN6 and the drain end of MN13 are connected to the source end of the PMOS tube MP14, the source ends of the NMOS tubes MN11 and MN13 and the drain ends of the PMOS tubes MP12 and MP14 are connected to the output end Vout, and the other end of the capacitor Cj is grounded. The gate terminals of NMOS transistors MN13 and MP12 are connected to the input terminal IN2 (i.e., TN2), and the gate terminals of NMOS transistors MN11, PMOS transistors MP10, NMOS transistors MN6, and PMOS transistors MP14 are connected to the input terminal IN1 (i.e., TN1). When the control signal TN1=1, NMOS transistor MN6 is turned on as a switch tube, and capacitor Cj is discharged to the ground. At the same time, the switch tube of PMOS transistor MP10 is turned off, and capacitor C is charged at a fixed slope; when the control signal TN1=0, capacitor C is discharged to the ground, and capacitor Cj is charged at a fixed slope. The V1 and Vj node signals pass through the transmission gates controlled by the complementary signals TN1 and TN2 to the Vout output respectively. When TN1=1, the charge and discharge circuit selects to open the charging path of capacitor C to the Vout output; when TN1=0, the charge and discharge circuit selects to open the charging path of capacitor Cj to the Vout output. So far, a capacitor cross-charging and discharging type path controlled by the complementary signals TN1 and TN2 is realized.

[0032] like Figure 3The schematic diagram of the structure of the switch control logic circuit is shown, which includes three switch control units X1, X2 and X3, and an inverter INV4. Each switch control unit has the same structure, including NAND gates NAND1, NAND2 and inverter INV5, wherein input terminal a and input terminal b are respectively connected to one input terminal of NAND gates NAND1 and NAND2, and the other input terminals of NAND gates NAND1 and NAND2 are respectively connected to the output terminals of NAND gates NAND2 and NAND1, and the output terminal of NAND gate NAND1 is connected to output terminal y through inverter INV5. Input terminal D (i.e. Figure 1 The input signal A in the input terminal is connected to the a input terminal of X1 and the b input terminal of X2. The input terminal DN (i.e. Figure 1 The input signal AN in the circuit is connected to the b input terminal of X1 and the a input terminal of X2. The outputs of X1 and X2 are connected to the a and b input terminals of X3 respectively, and the output terminal of X3 is connected to the output terminal EN (i.e., TN1) through the inverter INV4. The switch control logic circuit generates a pair of complementary switch control signals for controlling the oscillation circuit to select the output charging or discharging path signal.

[0033] like Figure 4 The structure diagram of the level conversion circuit is shown, including PMOS tubes MP15, MP17, MP19, MP21 and NMOS tubes MN16, MN18, MN20, MN22. The input terminal Vp (i.e., TN2) is connected to the gate terminals of the PMOS tubes MP15, NMOS tubes MN16, and NMOS tubes MN20, the drain terminal of the PMOS tube MP15 and the drain terminal of the NMOS tube MN16 are connected to the gate terminal of the NMOS tube MN18, the drain terminal of the PMOS tube MP17 and the drain terminal of the NMOS tube MN18 are connected to the gate terminal of the PMOS tube MP19, the drain terminal of the PMOS tube MP19, the drain terminal of the NMOS tube MN20, the gate terminal of the PMOS tube MP17, the gate terminal of the PMOS tube MP21 and the gate terminal of the NMOS tube MN22 are connected, and the drain terminal of the PMOS tube MP21 and the drain terminal of the NMOS tube MN22 are connected to the output terminal VO. The input terminal PB is connected to the source terminal of the PMOS tube MP15, the source terminals of the PMOS tubes MP17, MP19, and MP21 are connected to the power supply VDD, and the source terminals of the NMOS tubes MN16, MN18, MN20, and MN22 are grounded. The level conversion circuit is used to convert the amplitude of the oscillation signal to the power supply voltage output. The signal at the input terminal PB is connected to the power supply voltage VDD. Figure 2 The middle input terminal PB is the same, which is a fixed reference voltage inside the chip and a fixed voltage value.

[0034] like Figure 5 As shown, the inverter INV1, the inverter INV2 and the inverter INV3 form a three-stage inversion circuit for realizing partial logic inversion and shaping the waveform at the same time.

[0035] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A capacitor cross-charge and discharge oscillation circuit, characterized in that: It includes a charging and discharging circuit, a switch control logic circuit, a level conversion circuit and a three-level inverter circuit; The charging and discharging circuit generates a clock oscillation waveform through capacitor cross-charging and discharging and under the control of the switch control logic circuit, and is converted into a pair of complementary input signals and transmitted to the switch control logic circuit; wherein, The charging and discharging circuit includes a capacitor C, PMOS tubes MP0-MP5, MP10, MP12, MP14 and NMOS tubes MN6-MN9, MN11, MN13; the source ends of the PMOS tubes MP1, MP3, MP5 are connected to the input end PB, and the drain ends are respectively connected to the source ends of the PMOS tubes MP0, MP2, MP4, the drain end of the PMOS tube MP0 is connected to the input end Vin, the drain end of the PMOS tube MP2 is connected to the drain end of the NMOS tube MN6, the drain end of the PMOS tube MP4 is connected to the drain end of the NMOS tube MN7, and the source ends of the NMOS tubes MN6 and MN7 are both grounded; The source end of the PMOS tube MP10 and one end of the capacitor C are connected to the input end PB, the other end of the capacitor C is connected to the drain end of the PMOS tube MP10, the drain end of the NMOS tube MN9, the drain end of the NMOS tube MN11 and the source end of the PMOS tube MP12, the source end of the NMOS tube MN9 is connected to the drain end of the PMOS tube MN8, the gate ends of the NMOS tubes MN9, MN8 and MN7 are connected to the drain end of MN7, and the source end of the NMOS tube MN8 is grounded; One end of the capacitor Cj, the drain end of the NMOS tube MN6, the drain end of MN13 and the source end of the PMOS tube MP14 are connected, the source ends of the NMOS tubes MN11 and MN13 and the drain ends of the PMOS tubes MP12 and MP14 are connected to the output end Vout, and the other end of the capacitor Cj is grounded; The gate ends of the NMOS tubes MN13 and MP12 are connected to the input terminal IN2, and the gate ends of the NMOS tube MN11, the PMOS tube MP10, the NMOS tube MN6, and the PMOS tube MP14 are connected to the input terminal IN1; The switch control logic circuit generates a pair of complementary control signals for controlling the opening and closing of the charging and discharging paths in the charging and discharging circuit, thereby realizing independent cross-charging and discharging paths; wherein, The switch control logic circuit includes three switch control units X1, X2 and X3, and an inverter INV4; each switch control unit has the same structure, and includes NAND gates NAND1, NAND2 and an inverter INV5, wherein the input terminal a and the input terminal b of the switch control unit are respectively connected to one input terminal of the NAND gates NAND1 and NAND2, the other input terminals of the NAND gates NAND1 and NAND2 are respectively connected to the output terminals of the NAND gates NAND2 and NAND1, and the output terminal of the NAND gate NAND1 is connected to the output terminal y through the inverter INV5; The input terminal D of the switch control logic circuit is connected to the a input terminal of the switch control unit X1 and the b input terminal of the switch control unit X2, and the input terminal DN of the switch control logic circuit is connected to the b input terminal of the switch control unit X1 and the a input terminal of the switch control unit X2; the outputs of the switch control units X1 and X2 are respectively connected to the a and b input terminals of the switch control unit X3, and the output terminal of the switch control unit X3 is connected to the output terminal EN of the switch control logic circuit through the inverter INV4. The level conversion circuit converts the oscillation signal into a power supply voltage output; The three-stage inverter circuit is used for logic inversion and waveform shaping at the same time; wherein, the three-stage inverter circuit includes inverters INV1, INV2 and INV3; the output end of the charge and discharge circuit is connected to the input end of inverter INV1, and inverters INV1 and INV2 are connected in series; the output end of inverter INV1 and the output end of inverter INV2 are both connected to the switch control logic circuit; the output end of the switch control logic circuit is connected to the input end of inverter INV3, and the output end of inverter INV3 is connected to the level conversion circuit.

2. The capacitor cross-charge and discharge oscillation circuit according to claim 1, wherein: The level conversion circuit includes PMOS tubes MP15, MP17, MP19, MP21 and NMOS tubes MN16, MN18, MN20, MN22; The input terminal Vp of the level conversion circuit is connected to the gate terminals of the PMOS tube MP15, the NMOS tube MN16 and the NMOS tube MN20, the drain terminal of the PMOS tube MP15 and the drain terminal of the NMOS tube MN16 are connected to the gate terminal of the NMOS tube MN18, the drain terminal of the PMOS tube MP17 and the drain terminal of the NMOS tube MN18 are connected to the gate terminal of the PMOS tube MP19, the drain terminal of the PMOS tube MP19, the drain terminal of the NMOS tube MN20, the gate terminal of the PMOS tube MP17, the gate terminal of the PMOS tube MP21 and the gate terminal of the NMOS tube MN22 are connected, and the drain terminal of the PMOS tube MP21 and the drain terminal of the NMOS tube MN22 are connected to the output terminal VO; The input terminal PB of the level conversion circuit is connected to the source terminal of the PMOS tube MP15, the source terminals of the PMOS tubes MP17, MP19, and MP21 are connected to the power supply VDD, and the source terminals of the NMOS tubes MN16, MN18, MN20, and MN22 are grounded.

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