CDR Control Loop Frequency Correction Method, Apparatus, Loop, and Receiver

Abstract

This application relates to a CDR control loop frequency correction method, device, loop and receiver. The method includes: after the receiver chip is powered on and operates, obtaining a control word pre-stored in a register; using the control word to adjust the internal oscillator to output a target reference frequency to the PLL loop of the CDR control loop; after the PLL loop is locked, sending the multiplexed multi-phase clock output by the voltage-controlled oscillator into the FD / PD loop of the CDR control loop; after the FD / PD loop is stable, performing error code detection on the data output by the serializer / deserializer; if no error code is detected, the frequency correction of the FD / PD loop is completed. By using an on-chip ring oscillator to provide a reference clock, the defect that the FD / PD loop cannot be normally locked due to the frequency offset of the reference clock is overcome, and the FD / PD loop is quickly locked on-chip, achieving the purpose of efficient frequency deviation correction.

Description

Technical Field

[0001] The invention belongs to the technical field of interface circuits and relates to a CDR control loop frequency correction method, device, loop and receiver. Background Art

[0002] High-speed interface circuits include two parts: a transmitter and a receiver, and are widely used in various data transmission scenarios. In the chip design of the receiver, the industry commonly uses high-precision quartz crystal oscillators, high-precision RC oscillators, and LC-tank oscillators to generate reference clocks. For receiver chips that use an on-chip reference clock, the on-chip reference clock is greatly affected by environmental factors such as process, voltage, and temperature, and usually has a frequency deviation of more than ±20%. Such a large deviation exceeds the acceptable operating range of the FD / PD (Frequency Detector / Phase Detector) loop in the clock data recovery circuit (CDR). This frequency used in the FD / PD loop will cause the loop to lose lock, and thus the clock recovery and data retiming cannot be completed.

[0003] In this regard, in the chip design technology of the conventional receiver, there are traditional calibration methods such as using an off-chip reference frequency, adding off-chip components, and providing an on-chip memory to calibrate the clock to correct the above frequency deviation. However, in the process of implementing the present invention, the inventors found that in the actual application environment where the above traditional calibration methods cannot be used, there is a technical problem that the frequency deviation cannot be corrected directly based on the on-chip conditions. Summary of the invention

[0004] In view of the problems existing in the above-mentioned traditional methods, the present invention proposes a CDR control loop frequency correction method, a CDR control loop frequency correction device, a CDR control loop and a receiver which can realize efficient frequency deviation correction.

[0005] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0006] On the one hand, a CDR control loop frequency correction method is provided, comprising the steps of:

[0007] After the receiver chip is powered on, the control word pre-stored in the register is obtained;

[0008] Using the control word to adjust the internal oscillator to output the target reference frequency to the PLL loop of the CDR control loop;

[0009] After the PLL loop is locked, the multi-channel multi-phase clocks output by the voltage-controlled oscillator are sent to the FD / PD loop of the CDR control loop;

[0010] After the FD / PD loop is stable, error detection is performed on the data output by the serial-to-parallel converter;

[0011] If no bit errors are detected, the frequency correction of the FD / PD loop is completed.

[0012] In one of the embodiments, the pre-stored control words include at least two, each control word corresponding to a different target reference frequency;

[0013] The above method further comprises the steps of:

[0014] If a bit error is detected, the next control word pre-stored in the register is sent to the internal oscillator;

[0015] Return to the step of using the control word to adjust the internal oscillator to output the target reference frequency to the PLL loop of the CDR control loop.

[0016] In one embodiment, the method further comprises the steps of:

[0017] After traversing all control words, all control words corresponding to undetected bit errors are detected as candidate control words;

[0018] From each candidate control word, a control word with a corresponding target reference frequency in the middle is selected as the optimal control word; the optimal control word is used to perform frequency correction on the CDR control loop.

[0019] In one embodiment, the determination method of whether a bit error is not detected is:

[0020] If a synchronization code is detected in the data output from the serial-to-parallel converter and no bit error is detected in the data output from the serial-to-parallel converter within a set time period after the synchronization code, the bit error detection result is determined to be no bit error detected.

[0021] On the other hand, a CDR control loop frequency correction device is also provided, comprising:

[0022] The register module is used to output a pre-stored control word to an internal oscillator of a CDR control loop after the receiver chip is powered on; the control word is used to instruct the internal oscillator to output a target reference frequency to a PLL loop of the CDR control loop;

[0023] The bit error detection module is used to perform bit error detection on the data output by the serial-to-parallel converter after the FD / PD loop of the CDR control loop is stable, and to complete the frequency correction of the FD / PD loop when no bit error is detected; the FD / PD loop enters loop stability under the action of the multi-channel multi-phase clocks output after the PLL loop completes locking.

[0024] In yet another aspect, there is provided a CDR control loop, comprising an internal oscillator, a PLL loop, an FD / PD loop, an error detection circuit and a register;

[0025] The internal oscillator is used to read the control word pre-stored in the register and adjust the frequency using the control word after the chip is powered on, so as to output the target reference frequency to the PLL loop;

[0026] The PLL loop is used to send the multi-channel multi-phase clocks output by the voltage-controlled oscillator into the FD / PD loop after completing locking;

[0027] The error detection circuit is used to perform error detection on the data output by the serial-to-parallel converter after the FD / PD loop is stable. If no error is detected, the frequency correction of the FD / PD loop is completed.

[0028] In one embodiment, the registers for pre-storing control words include at least two, each register is used to pre-store a control word, and each control word corresponds to a different target reference frequency;

[0029] The internal oscillator is also used to read the control word pre-stored in the next register and use it to perform the next round of output frequency adjustment when the error detection circuit detects an error.

[0030] In one of the embodiments, the error detection circuit is further used to detect all control words corresponding to undetected errors as candidate control words after traversing all control words, and select a control word with a corresponding target reference frequency in the middle from the candidate control words as the optimal control word; the optimal control word is used to perform frequency correction on the CDR control loop through an internal oscillator.

[0031] In one of the embodiments, the error detection circuit determines that the error detection result is no error detected when a synchronization code is detected in the data output by the serial-to-parallel converter and no error is detected in the data output by the serial-to-parallel converter within a set time period after the synchronization code.

[0032] On the other hand, a receiver is provided, comprising the above-mentioned CDR control loop.

[0033] One of the above technical solutions has the following advantages and beneficial effects:

[0034] The above-mentioned CDR control loop frequency correction method, device and receiver pre-store a control word in an on-chip register, send the control word to an internal oscillator to set the output frequency of the internal oscillator, and then use the adjusted output target reference frequency as the reference frequency of the PLL loop. After the PLL loop is locked, the FD / PD loop works. After the FD / PD loop works stably, error detection is performed on the data output by the serial-to-parallel converter to detect whether there is any error in the data output by the CDR; when no error is detected, the frequency correction of the FD / PD loop is completed.

[0035] Compared with the frequency deviation correction method in the chip design technology of traditional receivers, this method uses an on-chip ring oscillator to provide the reference clock while meeting the design requirements of not using an off-chip reference frequency, not adding off-chip components, not providing on-chip memory to calibrate the clock, and keeping the chip power consumption and area as small as possible. The correction loop overcomes the defect that the FD / PD loop cannot be locked normally due to the frequency deviation of the reference clock, and quickly locks the FD / PD loop on the chip, achieving the purpose of efficient frequency deviation correction. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 It is a schematic diagram of the structure of the traditional CDR control loop;

[0038] Figure 2 is a schematic diagram of a circuit structure of a receiver in one embodiment;

[0039] Figure 3 1 is a flow chart of a method for frequency correction of a CDR control loop in one embodiment;

[0040] Figure 4 is a flow chart of a CDR control loop frequency correction method according to another embodiment;

[0041] Figure 5 Schematic diagram of the module structure of a CDR control loop frequency correction device in one embodiment. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0044] It should be noted that the reference to "embodiment" in this document means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of the phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments.

[0045] Those skilled in the art will appreciate that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the present specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0046] The high-speed interface circuit includes two parts, a transmitter and a receiver. The design scheme provided in the present application is applied in the receiver chip. In the chip design of the receiver, the high-precision quartz crystal oscillator, high-precision RC oscillator and LC-tank oscillator commonly used in the industry generate the reference clock. For the receiver chip using the on-chip reference clock, the on-chip reference clock is greatly affected by environmental factors such as process, voltage and temperature, and usually has a large frequency deviation. Under the design requirements that the off-chip reference frequency cannot be used, off-chip components cannot be added, on-chip memory is not provided to calibrate the clock, and the chip power consumption and area are as small as possible, the above-mentioned traditional calibration method cannot be applied to the frequency correction of the receiver chip using the on-chip reference clock.

[0047] In summary, the design scheme provided in this application uses an on-chip ring oscillator to provide a reference clock and proposes a new frequency correction scheme. When the FD / PD loop does not work properly, the correction process is started to correct the reference frequency to the working range of the FD / PD, thereby ensuring that the CDR can work normally under various process, temperature and voltage conditions.

[0048] like Figure 1As shown in the figure, it is a partial structural diagram of the main body of the traditional receiver (chip) circuit. The commonly used phase-locked loop (PLL) type CDR with an on-chip reference clock includes two loops, PLL and FD / PD. After the system is powered on, the PLL first establishes and outputs multiple multi-phase clocks. Then the FD / PD loop starts to work. At first, the FD dominates the loop, uses the clock generated by the PLL to sample the serial data, and recovers a clock that is almost equal to the PLL frequency from the serial data. After that, the PD dominates the loop, and the recovered clock is aligned with the data edge. The edge of another clock orthogonal to the clock is aligned with the data center position to retime the data. The retimed serial data is converted into parallel data through a serial-to-parallel conversion circuit and sent to the digital unit circuit.

[0049] In order to meet the design requirements and overcome the problem that the FD / PD loop cannot be locked normally due to the frequency deviation of the reference clock, the design scheme provided in this application adds a new frequency correction method based on the above commonly used design.

[0050] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0051] See also Figure 2 In one embodiment, the embodiment of the present application provides a CDR control loop 100, including an internal oscillator 12, a PLL loop, an FD / PD loop, an error detection circuit 14 and a register 16. Register 16 is used to pre-store control words. The internal oscillator 12 is used to read the control word pre-stored in the register 16 and adjust the frequency using the control word after the chip is powered on, so as to output the target reference frequency to the PLL loop. The PLL loop is used to send the multi-channel multi-phase clock output by the voltage-controlled oscillator to the FD / PD loop after locking is completed. The error detection circuit 14 is used to perform error detection on the data output by the serial-to-parallel converter after the FD / PD loop is stable. If no error is detected, the frequency correction of the FD / PD loop is completed.

[0052] It is understandable that Figure 1 and Figure 2 As shown, in the receiver chip, the internal oscillator 12, the PLL loop and FD / PD loop of the CDR control loop, and the digital unit circuit at the loop data output end can be divided. The internal oscillator 12 can be used to provide an internal reference clock to the PLL loop. The PLL loop and the FD / PD loop can specifically include a frequency detector, a charge pump 1, a frequency detector, a charge pump 2, a phase detector / decision device, a charge pump 3, a loop filter, a voltage-controlled oscillator, a frequency divider, and a serial-to-parallel converter. The connection relationship between the components and the data flow relationship are shown in FIG. Figure 1 and Figure 2As shown in , the functions implemented by each component can be understood by referring to the functions of each corresponding component in the existing CDR control loop in the art.

[0053] This embodiment can construct an on-chip error detection circuit 14 by utilizing on-chip digital circuit elements, and can utilize on-chip registers (more than two) to provide a register 16 for pre-stored control words. The internal oscillator 12 can call the value of the corresponding register 16 (corresponding to the pre-stored control word) to adjust the output frequency, so as to achieve frequency deviation calibration.

[0054] Specifically, after the chip is powered on and starts working, the internal oscillator 12 reads the control word in the register 16. The control word is used to reset the frequency adjustment switch of the internal oscillator 12 so that the internal oscillator 12 oscillates a new frequency, which can be called the target reference frequency. This frequency is sent to the PLL loop as a new reference frequency. The PLL loop completes loop locking at the new reference frequency, and sends the multi-channel multi-phase clock output by the locked voltage-controlled oscillator to the FD / PD loop. Then the FD / PD loop is started, and after the loop is stable, the error detection circuit 14 detects whether there is an error output in the data output by the serial-to-parallel converter. If there is no error output, the frequency offset correction of the FD / PD loop is completed; if there is an error output, another pre-stored control word can be read for another correction process until the error detection circuit 14 detects that there is no error output in the data output by the serial-to-parallel converter, thereby completing the frequency offset correction of the FD / PD loop.

[0055] The CDR control loop 100 stores a control word in the register 16 on the chip, sends the control word to the internal oscillator 12 to set the output frequency of the internal oscillator 12, and then uses the adjusted output target reference frequency as the reference frequency of the PLL loop. After the PLL loop is locked, the FD / PD loop works. After the FD / PD loop works stably, the data output by the serial-to-parallel converter is error-checked to detect whether there is any error in the data output by the CDR; when no error is detected, the frequency correction of the FD / PD loop is completed.

[0056] Compared with the frequency deviation correction method in the chip design technology of traditional receivers, the on-chip ring oscillator is directly used to provide the reference clock while meeting the design requirements of not using an off-chip reference frequency, not adding off-chip components, not providing on-chip memory to calibrate the clock, and keeping the chip power consumption and area as small as possible. The correction loop overcomes the defect that the FD / PD loop cannot be locked normally due to the frequency deviation of the reference clock, and quickly locks the FD / PD loop on the chip, achieving the purpose of efficient frequency deviation correction.

[0057] In one embodiment, the registers 16 for pre-storing control words include at least two, each register 16 is used to pre-storing a control word, and each control word corresponds to a different target reference frequency. The internal oscillator 12 is also used to read the control word pre-stored in the next register 16 and use it for the next round of output frequency adjustment when the error detection circuit 14 detects an error.

[0058] It can be understood that the pre-stored control words may include more than two, each of which is used to set the frequency adjustment switch in the internal oscillator 12 so that the internal oscillator 12 oscillates a new frequency. The target reference frequencies corresponding to the control words are different, and each control word is used to adjust the output corresponding to each target reference frequency.

[0059] Specifically, after the chip is powered on and starts working, the frequency offset correction process is started, and the internal oscillator 12 reads the control word in the first register 16. The first control word is used to reset the frequency adjustment switch of the internal oscillator 12 so that the internal oscillator 12 oscillates a new frequency, which can be called the target reference frequency. This frequency is sent to the PLL loop as a new reference frequency. The PLL loop completes loop locking at the new reference frequency, and sends the multi-channel multi-phase clock output by the locked voltage-controlled oscillator to the FD / PD loop. The FD / PD loop is then started, and after the loop is stable, the error detection circuit 14 detects whether there is an error output in the data output by the serial-to-parallel converter. If so, the internal oscillator 12 reads the control word in the next register 16 and uses the next control word to perform frequency correction processing. If not, the frequency offset correction of the FD / PD loop is completed.

[0060] By setting a plurality of control words for performing frequency offset correction of the FD / PD loop, the reliability of the correction can be effectively improved.

[0061] In one embodiment, the error detection circuit 14 is further used to detect all control words corresponding to undetected error codes as candidate control words after traversing all control words, and select a control word with a corresponding target reference frequency as the optimal control word from the candidate control words. The optimal control word is used to perform fast frequency correction on the CDR control loop 100 through the internal oscillator 12.

[0062] It can be understood that in this embodiment, a round of frequency deviation correction processing can be performed for each control word. For example, after the chip is powered on, the correction process starts, and the control word stored in the current register 16 is sent to the internal oscillator 12 to reset the oscillation frequency of the internal oscillator 12 and output a new reference frequency. The new reference frequency is used as the reference frequency of the PLL loop. After the PLL loop is locked, the FD / PD loop works, and the error detection circuit 14 detects whether there is an error output in the data output by the serial-to-parallel converter. Next, the next register 16 sends the next control word stored in it to the internal oscillator 12, and repeats the above correction process. Until all control words are traversed. In each round of the above correction process, the error detection circuit 14 detects whether there is an error in the data output by the loop after each round of reference frequency adjustment.

[0063] Thereafter, the error detection circuit 14 can list all the control words detected without errors as candidate control words, and then select the control word with the middle corresponding frequency as the optimal control word, and the correction is completed.

[0064] In this way, when the correction method using the on-chip reference clock is adopted, the on-chip reference clock is greatly affected by the application environment, such as but not limited to the operating temperature, production process or operating voltage. Changes in the application environment will cause corresponding frequency deviations. Therefore, through the detection of the above-mentioned optimal control word, the optimal control word corresponding to each application environment can be selected for the CDR control loop 100 under different application environments, so that in actual applications, the optimal control word under the current application environment can be directly called to perform the most efficient frequency deviation correction of the FD / PD loop, thereby achieving the optimal correction effect.

[0065] In one embodiment, the error detection circuit 14 determines that the error detection result is no error detected when a synchronization code is detected in the data output by the serial-to-parallel converter and no error is detected in the data output by the serial-to-parallel converter within a set time period after the synchronization code.

[0066] Specifically, in the above embodiment, whether a bit error is detected can be determined by directly detecting whether a synchronization code is detected in the data output by the serial-to-parallel converter. In this embodiment, the bit error detection circuit 14 can detect whether the data output by the loop contains a synchronization code after the FD / PD loop is started and stabilized. If the synchronization code is found and there is no bit error in the data within a fixed period of time (i.e., a set time period) after the synchronization code, it means that no bit error is detected; otherwise, it means that a bit error is detected.

[0067] Through the above-mentioned bit error judgment processing, the judgment accuracy of whether a bit error is detected can be further improved, thereby further improving the reliability and accuracy of the frequency offset correction of the FD / PD loop.

[0068] See also Figure 3 In one embodiment, the present application provides a CDR control loop frequency correction method, which can be applied to the frequency offset correction of a CDR control loop without a reference clock. The method may include the following processing steps S12 to S20:

[0069] S12, after the receiver chip is powered on, obtaining the control word pre-stored in the register;

[0070] S14, using the control word to adjust the internal oscillator to output a target reference frequency to a PLL loop of the CDR control loop;

[0071] S16, after the PLL loop is locked, the multi-channel multi-phase clocks output by the voltage-controlled oscillator are sent to the FD / PD loop of the CDR control loop;

[0072] S18, after the FD / PD loop is stable, error detection is performed on the data output by the serial-to-parallel converter;

[0073] S20: If no bit error is detected, the frequency correction of the FD / PD loop is completed.

[0074] It can be understood that the explanation of the above-mentioned reference clock-free CDR control loop and various characteristic terms can be understood by referring to the corresponding explanations in the various embodiments of the above-mentioned CDR control loop 100, and will not be repeated here.

[0075] Specifically, after the receiver chip is powered on and starts working, the control word in the register can be read by the internal oscillator. The control word is used to reset the frequency adjustment switch of the internal oscillator so that the internal oscillator oscillates a new frequency, which can be called the target reference frequency. This frequency is sent to the PLL loop as a new reference frequency. The PLL loop completes loop locking at the new reference frequency, and sends the multi-channel multi-phase clock output by the locked voltage-controlled oscillator to the FD / PD loop. Then the FD / PD loop is started, and after the loop is stable, the error detection circuit detects whether there is an error output in the data output by the serial-to-parallel converter. If there is no error output, the frequency offset correction of the FD / PD loop is completed; if there is an error output, another pre-stored control word can be read for another correction process until the error detection circuit detects that there is no error output in the data output by the serial-to-parallel converter, thereby completing the frequency offset correction of the FD / PD loop.

[0076] The above CDR control loop frequency correction method pre-stores a control word in an on-chip register, sends the control word to an internal oscillator to set the output frequency of the internal oscillator, and then uses the adjusted output target reference frequency as the reference frequency of the PLL loop. After the PLL loop is locked, the FD / PD loop works. After the FD / PD loop works stably, error detection is performed on the data output by the serial-to-parallel converter to detect whether there is an error in the data output by the CDR; when no error is detected, the frequency correction of the FD / PD loop is completed.

[0077] Compared with the frequency deviation correction method in the chip design technology of traditional receivers, the on-chip ring oscillator is directly used to provide the reference clock while meeting the design requirements of not using an off-chip reference frequency, not adding off-chip components, not providing on-chip memory to calibrate the clock, and keeping the chip power consumption and area as small as possible. The correction loop overcomes the defect that the FD / PD loop cannot be locked normally due to the frequency deviation of the reference clock, and quickly locks the FD / PD loop on the chip, achieving the purpose of efficient frequency deviation correction.

[0078] In one embodiment, the pre-stored control words include at least two, and each control word corresponds to a different target reference frequency. The above method may also include:

[0079] When a bit error is detected, the next control word pre-stored in the register is sent to the internal oscillator; and the process returns to the above step S14.

[0080] It can be understood that the pre-stored control words may include more than two, each of which is used to set the frequency adjustment switch in the internal oscillator so that the internal oscillator oscillates a new frequency. The target reference frequencies corresponding to the control words are different, and each control word is used to adjust the output corresponding to each target reference frequency.

[0081] Specifically, after the receiver chip is powered on and starts working, the frequency offset correction process is started, and the internal oscillator reads the control word in the first register. The first control word is used to reset the frequency adjustment switch of the internal oscillator so that the internal oscillator oscillates a new frequency, which can be called the target reference frequency. This frequency is sent to the PLL loop as a new reference frequency. The PLL loop is locked at the new reference frequency, and the multi-channel multi-phase clock output by the locked voltage-controlled oscillator is sent to the FD / PD loop. The FD / PD loop is then started, and after the loop is stable, the error detection circuit detects whether there is an error output in the data output by the serial-to-parallel converter. If so, the internal oscillator reads the control word in the next register and uses the next control word to perform frequency correction processing. If not, the frequency offset correction of the FD / PD loop is completed.

[0082] By setting a plurality of control words for performing frequency offset correction of the FD / PD loop, the reliability of the correction can be effectively improved.

[0083] In one embodiment, Figure 4 As shown, the above method may further include the following processing steps:

[0084] After traversing all control words, all control words corresponding to undetected bit errors are detected as candidate control words;

[0085] From each candidate control word, a control word with a corresponding target reference frequency in the middle is selected as the optimal control word; the optimal control word is used to perform frequency correction on the CDR control loop.

[0086] It can be understood that in this embodiment, a round of frequency deviation correction processing can be performed for each control word. For example, after the chip is powered on, the correction process starts, and the control word stored in the current register is sent to the internal oscillator to reset the oscillation frequency of the internal oscillator and output a new reference frequency. The new reference frequency is used as the reference frequency of the PLL loop. After the PLL loop is locked, the FD / PD loop works, and the error detection circuit detects whether there is an error output in the data output by the serial-to-parallel converter. Next, the next register sends the next control word stored in it to the internal oscillator, and repeats the above correction process. Until all control words are traversed. In each round of the above correction process, the error detection circuit detects whether there is an error in the data output by the loop after each round of reference frequency adjustment.

[0087] Afterwards, the error detection circuit can list all the control words detected without errors as candidate control words, and then select the control word with the middle corresponding frequency as the optimal control word, and the correction is completed.

[0088] In this way, when the on-chip reference clock is used for correction, the on-chip reference clock is greatly affected by the application environment, such as but not limited to the operating temperature, production process or operating voltage. Changes in the application environment will cause corresponding frequency deviations. Therefore, through the detection of the above-mentioned optimal control word, the optimal control word corresponding to each application environment can be selected for the CDR control loop under different application environments, so that in actual applications, the optimal control word under the current application environment can be directly called to perform the most efficient frequency deviation correction of the FD / PD loop, thereby achieving the optimal correction effect.

[0089] In one embodiment, the determination method of whether a bit error is not detected is:

[0090] If a synchronization code is detected in the data output from the serial-to-parallel converter and no bit error is detected in the data output from the serial-to-parallel converter within a set time period after the synchronization code, the bit error detection result is determined to be no bit error detected.

[0091] Specifically, in the above embodiment, whether a bit error is detected can be determined by directly detecting whether a synchronization code is detected in the data output by the serial-to-parallel converter. In this embodiment, the bit error detection circuit can detect whether the data output by the CDR control loop contains a synchronization code after the FD / PD loop is started and stabilized. If the synchronization code is found and there is no bit error in the data within a fixed period of time (i.e., a set time period) after the synchronization code, it means that no bit error is detected; otherwise, it means that a bit error is detected.

[0092] Through the above-mentioned bit error judgment processing, the judgment accuracy of whether a bit error is detected can be further improved, thereby further improving the reliability and accuracy of the frequency offset correction of the FD / PD loop.

[0093] It should be understood that although Figure 3 and Figure 4 The steps in the flowchart are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 3 and Figure 4 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0094] See also Figure 5 In one embodiment, a CDR control loop frequency correction device 200 is provided, which can be applied to the frequency correction of the CDR control loop on a receiver chip using an on-chip reference clock. The CDR control loop frequency correction device 200 includes a register module 201 and a bit error detection module 203. The register module 201 is used to output a pre-stored control word to the internal oscillator of the CDR control loop after the receiver chip is powered on; the control word is used to instruct the internal oscillator to output the target reference frequency to the PLL loop of the CDR control loop. The bit error detection module 203 is used to perform bit error detection on the data output by the serial-to-parallel converter after the FD / PD loop of the CDR control loop is stable, and to complete the frequency correction of the FD / PD loop when no bit error is detected; the FD / PD loop enters loop stability under the action of the multi-channel multi-phase clock output after the PLL loop completes locking.

[0095] The CDR control loop frequency correction device 200 stores a control word in the register module 201 on the chip, sends the control word to the internal oscillator to set the output frequency of the internal oscillator, and then uses the adjusted output target reference frequency as the reference frequency of the PLL loop. After the PLL loop is locked, the FD / PD loop works. After the FD / PD loop works stably, the error detection module 203 performs error detection on the data output by the serial-to-parallel converter to detect whether there is an error in the data output by the CDR; when no error is detected, the frequency correction of the FD / PD loop is completed.

[0096] Compared with the frequency deviation correction method in the chip design technology of traditional receivers, this method uses an on-chip ring oscillator to provide the reference clock while meeting the design requirements of not using an off-chip reference frequency, not adding off-chip components, not providing on-chip memory to calibrate the clock, and keeping the chip power consumption and area as small as possible. The correction loop overcomes the defect that the FD / PD loop cannot be locked normally due to the frequency deviation of the reference clock, and quickly locks the FD / PD loop on the chip, achieving the purpose of efficient frequency deviation correction.

[0097] In one embodiment, the pre-stored control words include at least two, each corresponding to a different target reference frequency. The register module 201 can also be used to send the next pre-stored control word to the internal oscillator to adjust the output frequency again when a bit error is detected.

[0098] In one embodiment, the above-mentioned error detection module 203 can also be used to detect all control words corresponding to undetected errors as candidate control words after traversing all control words; from each candidate control word, select the control word corresponding to the target reference frequency as the optimal control word; the optimal control word is used to perform fast frequency correction on the CDR control loop.

[0099] In one embodiment, the above-mentioned judgment method of no bit error being detected is: if a synchronization code is detected in the data output by the serial-to-parallel converter, and no bit error is detected in the data output from the serial-to-parallel converter within a set time period after the synchronization code, then the bit error detection result is determined to be no bit error being detected.

[0100] For the specific definition of the CDR control loop frequency correction device 200, please refer to the corresponding definition of the CDR control loop frequency correction method above, which will not be repeated here. Each module in the above CDR control loop frequency correction device 200 can be implemented in whole or in part by software, hardware and a combination thereof. The above modules can be embedded in or independent of the receiver chip in the form of hardware, or can be stored in the memory on the chip in the form of software, so that the controller can call and execute the operations corresponding to the above modules.

[0101] In one embodiment, a receiver is further provided, comprising the above-mentioned CDR control loop 100 .

[0102] It can be understood that the specific explanation of the CDR control loop 100 in this embodiment can be understood by referring to the corresponding explanations in the above-mentioned embodiments of the CDR control loop 100, and will not be repeated here. It should be noted that the receiver in this embodiment, in addition to the above-mentioned improved CDR control loop 100, can include other existing components not described in this specification, which can be understood by referring to the structure of the existing receiver chip in the art, and will not be listed in detail in this specification.

[0103] The above-mentioned receiver, by applying the above-mentioned CDR control loop 100, uses the on-chip ring oscillator to provide a reference clock. The frequency correction loop overcomes the defect that the FD / PD loop cannot be locked normally due to the frequency deviation of the reference clock, and quickly locks the FD / PD loop on the chip, thereby achieving the purpose of efficient frequency deviation correction in the receiver chip.

[0104] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and all of them belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A CDR control loop frequency correction method, It is characterized in that Includes steps: After the receiver chip is powered on, the control word pre-stored in the register is obtained; Using the control word to adjust the internal oscillator to output a target reference frequency to a PLL loop of a CDR control loop; After the PLL loop is locked, the multi-channel multi-phase clocks output by the voltage-controlled oscillator are sent to the FD / PD loop of the CDR control loop; After the FD / PD loop is stable, error detection is performed on the data output by the serial-to-parallel converter; wherein whether an error is detected is determined by directly detecting a synchronization code in the data output by the serial-to-parallel converter; If no bit error is detected, the frequency correction of the FD / PD loop is completed.

2. The CDR control loop frequency correction method according to claim 1, It is characterized in that The pre-stored control words include at least two, each of which corresponds to a different target reference frequency; The method further comprises the steps of: If a bit error is detected, the next control word pre-stored in the register is sent to the internal oscillator; Return to the step of using the control word to adjust the internal oscillator to output the target reference frequency to the PLL loop of the CDR control loop.

3. The CDR control loop frequency correction method according to claim 2, It is characterized in that The method further comprises the steps of: After traversing all the control words, all control words corresponding to undetected bit errors are detected as candidate control words; From each of the candidate control words, select a control word with a corresponding target reference frequency in the middle as the optimal control word; The optimal control word is used to perform frequency correction on the CDR control loop.

4. The CDR control loop frequency correction method according to any one of claims 1 to 3, It is characterized in that The judgment method of not detecting bit errors is: If a synchronization code is detected in the data output by the serial-to-parallel converter, and no bit error is detected in the data output by the serial-to-parallel converter within a set time period after the synchronization code, the bit error detection result is determined to be no bit error detected.

5. A CDR control loop frequency correction device, It is characterized in that include: A register module is used to output the pre-stored control word to the internal oscillator of the CDR control loop after the receiver chip is powered on; The control word is used to instruct the internal oscillator to output a target reference frequency to a PLL loop of the CDR control loop; The bit error detection module is used to perform bit error detection on the data output by the serial-to-parallel converter after the FD / PD loop of the CDR control loop is stable, and to complete the frequency correction of the FD / PD loop when no bit error is detected; wherein, whether a bit error is detected is determined by directly detecting a synchronization code in the data output by the serial-to-parallel converter, and the FD / PD loop enters loop stability under the action of the multi-channel multi-phase clocks output after the PLL loop completes locking.

6. A CDR control loop, It is characterized in that Includes internal oscillator, PLL loop, FD / PD loop, error detection circuit and register; The internal oscillator is used to read the control word pre-stored in the register and adjust the frequency using the control word after the chip is powered on, so as to output the target reference frequency to the PLL loop; The PLL loop is used to send the multi-channel multi-phase clocks output by the voltage-controlled oscillator into the FD / PD loop after completing locking; The bit error detection circuit is used to perform bit error detection on the data output by the serial-to-parallel converter after the FD / PD loop is stabilized. If no bit error is detected, the frequency correction of the FD / PD loop is completed; wherein, whether a bit error is detected is determined by directly detecting a synchronization code in the data output by the serial-to-parallel converter.

7. The CDR control loop according to claim 6, It is characterized in that The registers for pre-storing control words include at least two, each register is used to pre-store one control word, and each control word corresponds to a different target reference frequency; The internal oscillator is also used to read the next control word pre-stored in the register and use it to perform the next round of output frequency adjustment when the error detection circuit detects an error.

8. The CDR control loop according to claim 7, It is characterized in that The error detection circuit is further used to detect all control words corresponding to undetected errors as candidate control words after traversing all the control words, and select a control word with a corresponding target reference frequency in the middle from the candidate control words as the optimal control word; The optimal control word is used to perform frequency correction on the CDR control loop through the internal oscillator.

9. The CDR control loop according to any one of claims 6 to 8, It is characterized in that The error detection circuit detects a synchronization code in the data output by the serial-to-parallel converter, and determines that the error detection result is no error is detected when no error is detected from the data output by the serial-to-parallel converter within a set time period after the synchronization code.

10. A receiver, It is characterized in that Comprising the CDR control loop as claimed in any one of claims 6 to 9.

Images