Hardware automatic frequency modulation device and method based on clock division and multiplexing

Abstract

The present invention relates to the field of clock frequency modulation technology, and provides a hardware automatic frequency modulation device and method based on clock division and multiplexing. The device includes: a clock source; a frequency modulation control unit for outputting a clock selection signal; a clock frequency division circuit; a selection output; the selection output can output the clock source signal received at the first input end of the selection output or the first clock signal received at the second input end of the selection output according to the clock selection signal received at the control end. The present invention can obtain more low-frequency signals for chip use by dividing a single clock source signal without occupying additional clock source output resources, and further improve the adjustment flexibility of the clock source signal; in addition, the frequency division signal based on the logic circuit has a higher response rate than the software frequency modulation, which can improve the immediacy of chip frequency reduction.

Description

Technical Field

[0001] The present invention relates to the technical field of clock frequency modulation, and in particular to a hardware automatic frequency modulation device and method based on clock frequency division and multiplexing. Background Art

[0002] Given the same operating time, a chip's power consumption is positively correlated with its clock frequency. That is, a high-frequency chip experiences more high- and low-level transitions within the same timeframe, resulting in higher power consumption. Consequently, a chip with higher power consumption can execute more instructions and achieve better efficiency. However, since actual chip operation doesn't require constant high efficiency, adjusting the clock frequency at appropriate times to reduce overall chip power consumption is a viable solution.

[0003] In some existing applications, multiple clock frequencies are uniformly obtained from the output of a clock source. Frequency modulation is achieved by switching between clocks of different frequencies (i.e., switching to different outputs of the clock source) through software-controlled clock multiplexers to achieve the purpose of reducing overall power consumption.

[0004] In similar existing applications, the clock source needs to generate all the clock frequencies required by the target clock. As a shared clock source across all modules in the chip, its output resources are relatively limited. Furthermore, given that the required clock frequencies of each module may vary, adjusting the clock source output frequency is inflexible, as adjusting a single adjustment can have a ripple effect across the entire chip. Furthermore, software-controlled clock frequency adjustment suffers from slow response and poor immediacy. If the CPU responsible for frequency regulation becomes overloaded and unable to respond to frequency regulation requirements, it can easily cause a protective thermal shutdown, hindering chip reliability.

[0005] Therefore, how to achieve clock frequency modulation with faster response speed and less occupation of top-level clock source output resources has become a technical problem that needs to be solved urgently in the industry. Summary of the Invention

[0006] The present invention provides a hardware automatic frequency modulation device and method based on clock division and multiplexing, which is used to solve the defects of the prior art such as limited clock source output resources, insufficient flexibility in clock output frequency adjustment, and poor immediacy of clock output frequency adjustment, and conveniently realizes clock frequency modulation with faster response speed and less occupation of top-level clock source output resources.

[0007] The present invention provides a hardware automatic frequency modulation device based on clock frequency division and multiplexing, comprising:

[0008] A clock source, the clock source comprising a clock source output terminal for outputting a clock source signal;

[0009] A frequency modulation control unit, the frequency modulation control unit comprising a frequency modulation control unit input terminal for receiving a hardware frequency modulation request and a first frequency modulation control unit output terminal for outputting a clock selection signal;

[0010] a clock frequency dividing circuit, the clock frequency dividing circuit comprising a first clock frequency dividing circuit input terminal electrically connected to the clock source output terminal and a clock frequency dividing circuit output terminal for outputting a first clock signal; the first clock signal having a frequency lower than that of the clock source signal;

[0011] A selection output device, wherein a first input terminal of the selection output device is electrically connected to the output terminal of the clock source, a second input terminal of the selection output device is electrically connected to the output terminal of the clock frequency division circuit, and a control terminal of the selection output device is electrically connected to the first output terminal of the frequency modulation control unit;

[0012] The selection outputter can output the clock source signal received at the first input terminal of the selection outputter or the first clock signal received at the second input terminal of the selection outputter according to the clock selection signal received at the control terminal.

[0013] According to a hardware automatic frequency modulation device based on clock frequency division and multiplexing provided by the present invention, the frequency modulation control unit further includes a second output terminal of the frequency modulation control unit for outputting a preset frequency division parameter; the clock frequency division circuit further includes a second input terminal of the clock frequency division circuit electrically connected to the second output terminal of the frequency modulation control unit;

[0014] The frequency division parameters include a frequency division period, a high-level duration, a frequency increase step, and a frequency decrease step; wherein the frequency division period refers to the period of the first clock signal; the high-level duration refers to the duration of the first clock signal at a high level in a single period; the frequency decrease step refers to the step in the process of step-by-step frequency reduction of the clock source signal to the first clock signal; the frequency increase step refers to the step in the process of step-by-step frequency increase of the first clock signal to the clock source signal when the clock frequency division circuit stops working.

[0015] According to the hardware automatic frequency modulation device based on clock frequency division and multiplexing provided by the present invention, the frequency division parameters are loaded into the frequency modulation control unit during the initialization process.

[0016] According to a hardware automatic frequency modulation device based on clock frequency division and multiplexing provided by the present invention, the duty cycle of the first clock signal can be adjusted by the frequency division period and high level duration in the frequency division parameters.

[0017] The present invention also provides the above-mentioned hardware automatic frequency regulation device based on clock frequency division and multiplexing, and the hardware automatic frequency regulation device is used for power consumption control in a chip.

[0018] The present invention further provides a hardware automatic frequency modulation method based on clock frequency division and multiplexing, which is applied to the above-mentioned hardware automatic frequency modulation device based on clock frequency division and multiplexing, comprising:

[0019] Receive hardware frequency modulation request;

[0020] generating a clock selection signal according to the hardware frequency modulation request;

[0021] The clock selection signal is used to select a set clock signal from at least two clock signals as a clock output signal; the at least two clock signals include a first clock signal corresponding to a low-frequency band hardware frequency modulation request; the low-frequency band hardware frequency modulation request is a hardware frequency modulation request in which the target frequency is not higher than a set threshold;

[0022] The first clock signal is an output signal of a clock frequency dividing circuit; the clock frequency dividing circuit is a logic circuit that takes a clock source signal as input and obtains a first clock signal with a frequency lower than that of the clock source signal.

[0023] According to a hardware automatic frequency modulation method based on clock division and multiplexing provided by the present invention, the at least two clock signals further include a second clock signal; the second clock signal is a clock source signal output by a clock source;

[0024] The step of generating a clock selection signal according to the hardware frequency modulation request comprises:

[0025] If it is determined that the hardware frequency modulation request is a high-band hardware frequency modulation request and the target frequency is the same as the second clock signal, a clock selection signal corresponding to the second clock signal is generated; the high-band hardware frequency modulation request refers to a hardware frequency modulation request with a target frequency higher than a set threshold.

[0026] According to a hardware automatic frequency modulation method based on clock division and multiplexing provided by the present invention, the at least two clock signals further include a second clock signal; the second clock signal is a clock source signal output by a clock source;

[0027] The step of generating a clock selection signal according to the hardware frequency modulation request comprises:

[0028] If it is determined that the hardware frequency modulation request is a high-frequency band hardware frequency modulation request and the target frequency is different from the second clock signal, a clock source frequency modulation signal is generated and sent for the clock source frequency modulation unit to adjust the clock source signal output by the clock source; the clock source frequency modulation signal includes the target frequency of the hardware frequency modulation request.

[0029] According to a hardware automatic frequency modulation method based on clock frequency division and multiplexing provided by the present invention, after the step of determining that the hardware frequency modulation request is a high-band hardware frequency modulation request and the target frequency is different from the second clock signal, generating a clock source frequency modulation signal and sending it for the clock source frequency modulation unit to adjust the clock source signal output by the clock source, the method further includes:

[0030] determining that the adjusted clock source signal frequency is the same as the target frequency, and generating a clock selection signal corresponding to the second clock signal;

[0031] If it is determined that the adjusted clock source signal frequency is different from the target frequency and the ratio of the target frequency to the adjusted clock source signal frequency is less than a set low frequency band threshold ratio, a clock selection signal corresponding to the first clock signal is generated.

[0032] According to a hardware automatic frequency modulation method based on clock division and multiplexing provided by the present invention, the step of generating a clock selection signal according to the hardware frequency modulation request includes:

[0033] If it is determined that the hardware frequency modulation request is a low-frequency band hardware frequency modulation request, a clock selection signal and a clock division signal corresponding to the first clock signal are generated, and the clock division signal is sent to the clock division circuit so that the clock division circuit is connected to perform hardware division on the clock source signal to obtain the first clock signal.

[0034] According to a hardware automatic frequency modulation method based on clock division and multiplexing provided by the present invention, the hardware frequency modulation request refers to a signal generated when the operating parameters of the chip meet a preset frequency modulation range; the chip operating parameters include any one or any combination of operating temperature, operating voltage and operating power consumption.

[0035] The present invention also provides an application of a clock output signal obtained by the hardware automatic frequency modulation method based on clock frequency division and multiplexing in chip power consumption control.

[0036] The present invention also provides a hardware automatic frequency modulation system based on clock frequency division and multiplexing, comprising:

[0037] A receiving module, used for receiving hardware frequency modulation requests;

[0038] A selection module, configured to generate a clock selection signal according to the hardware frequency modulation request;

[0039] The clock selection signal is used to select a set clock signal from at least two clock signals as an output; the at least two clock signals include a first clock signal corresponding to a low-frequency band hardware frequency modulation request; the low-frequency band hardware frequency modulation request is a hardware frequency modulation request in which the target frequency is not higher than a set threshold;

[0040] The first clock signal is an output signal of a clock frequency dividing circuit; the clock frequency dividing circuit is a logic circuit that takes a clock source signal as input and obtains a first clock signal with a frequency lower than that of the clock source signal.

[0041] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and runnable on the processor, wherein when the processor executes the program, the steps of any of the above-described hardware automatic frequency modulation methods based on clock division and multiplexing are implemented.

[0042] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of any of the above-mentioned hardware automatic frequency modulation methods based on clock division and multiplexing are implemented.

[0043] The present invention also provides a computer program product, comprising a computer program, which, when executed by a processor, implements the steps of any of the above-mentioned hardware automatic frequency modulation methods based on clock division and multiplexing.

[0044] The hardware automatic frequency modulation device and method based on clock division and multiplexing provided by the present invention generate a clock selection signal according to a hardware frequency modulation request, and select a first clock signal in a low-frequency band as a clock output signal; since the first clock signal is obtained by dividing a clock source signal by a clock division circuit based on a hardware logic circuit, this method can obtain more low-frequency signals for chip use by dividing a single clock source signal without occupying additional clock source output resources, and further improve the adjustment flexibility of the clock source signal; in addition, the frequency division signal based on the logic circuit has a higher response rate than software frequency modulation, which can improve the immediacy of chip frequency reduction. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 This is one of the flow charts of the hardware automatic frequency modulation method based on clock division and multiplexing provided by the present invention;

[0047] Figure 2 This is the second flow chart of the hardware automatic frequency modulation method based on clock division and multiplexing provided by the present invention;

[0048] Figure 3This is one of the structural diagrams of the hardware automatic frequency modulation device based on clock division and multiplexing provided by the present invention;

[0049] Figure 4 This is the second structural diagram of the hardware automatic frequency modulation device based on clock frequency division and multiplexing provided by the present invention;

[0050] Figure 5 Schematic diagram of the structure of the DFS system provided by an embodiment of the present invention;

[0051] Figure 6 This is a basic timing diagram of DFS provided by an embodiment of the present invention;

[0052] Figure 7 It is a structural diagram of the hardware automatic frequency modulation system based on clock division and multiplexing provided by the present invention;

[0053] Figure 8 It is a structural schematic diagram of the electronic device provided by the present invention.

[0054] Reference numerals:

[0055] 701: receiving module;

[0056] 702: Select module;

[0057] 810: processor;

[0058] 820: Communication interface;

[0059] 830: memory;

[0060] 840: Communication bus. DETAILED DESCRIPTION

[0061] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0062] like Figure 3 As shown, an embodiment of the present invention provides a hardware automatic frequency modulation device based on clock division and multiplexing, which can apply the above-mentioned hardware automatic frequency modulation method based on clock division and multiplexing, including:

[0063] A frequency modulation control unit, the frequency modulation control unit comprising a frequency modulation control unit input terminal for receiving a hardware frequency modulation request and a first frequency modulation control unit output terminal for outputting a clock selection signal;

[0064] a clock frequency dividing circuit, the clock frequency dividing circuit comprising a first clock frequency dividing circuit input terminal electrically connected to the clock source output terminal and a clock frequency dividing circuit output terminal for outputting a first clock signal; the first clock signal having a frequency lower than that of the clock source signal;

[0065] A selection output device, wherein a first input terminal of the selection output device is electrically connected to the output terminal of the clock source, a second input terminal of the selection output device is electrically connected to the output terminal of the clock frequency division circuit, and a control terminal of the selection output device is electrically connected to the first output terminal of the frequency modulation control unit;

[0066] The selection outputter can output the clock source signal received at the first input terminal of the selection outputter or the first clock signal received at the second input terminal of the selection outputter according to the clock selection signal received at the control terminal.

[0067] In a preferred embodiment, the selection output device is a selection circuit or a multiplexer.

[0068] like Figure 4 As shown, the frequency modulation control unit further includes a second output terminal of the frequency modulation control unit for outputting a preset frequency division parameter; the clock frequency division circuit further includes a second input terminal of the clock frequency division circuit electrically connected to the second output terminal of the frequency modulation control unit;

[0069] The frequency division parameters include a frequency division period, a high-level duration, a frequency increase step, and a frequency decrease step; wherein the frequency division period refers to the period of the first clock signal; the high-level duration refers to the duration of the first clock signal at a high level in a single period; the frequency decrease step refers to the step in the process of step-by-step frequency reduction of the clock source signal to the first clock signal; the frequency increase step refers to the step in the process of step-by-step frequency increase of the first clock signal to the clock source signal when the clock frequency division circuit stops working.

[0070] In a preferred embodiment, the frequency division parameters are loaded into the frequency modulation control unit during initialization. The duty cycle of the first clock signal can be adjusted by the frequency division period and high level duration in the frequency division parameters.

[0071] The beneficial effects of this embodiment are:

[0072] A clock selection signal is generated according to the hardware frequency modulation request, and the first clock signal is selected as the clock output signal in the low-frequency band; since the first clock signal is obtained by dividing the clock source signal by the clock frequency division circuit based on the hardware logic circuit, more low-frequency signals can be obtained for chip use by dividing a single clock source signal without occupying additional clock source output resources, and the adjustment flexibility of the clock source signal can be further improved; in addition, the frequency division signal based on the logic circuit has a higher response rate than the software frequency modulation, which can improve the immediacy of the chip frequency reduction.

[0073] The following combination Figure 1-Figure 2 The present invention describes a hardware automatic frequency adjustment method based on clock division and multiplexing.

[0074] like Figure 1 As shown, an embodiment of the present invention provides a hardware automatic frequency modulation method based on clock division and multiplexing, comprising:

[0075] Step 102: The frequency modulation control unit receives a hardware frequency modulation request;

[0076] Step 104: The frequency modulation control unit generates a clock selection signal according to the hardware frequency modulation request;

[0077] The clock selection signal is used to select a set clock signal from at least two clock signals as a clock output signal; the at least two clock signals include a first clock signal corresponding to a low-frequency band hardware frequency modulation request; the low-frequency band hardware frequency modulation request is a hardware frequency modulation request in which the target frequency is not higher than a set threshold;

[0078] The first clock signal is an output signal of a clock frequency dividing circuit; the clock frequency dividing circuit is a logic circuit that takes a clock source signal as input and obtains a first clock signal with a frequency lower than that of the clock source signal.

[0079] In this embodiment, the low frequency band threshold of the low frequency band hardware frequency modulation request is a proportional threshold, that is, if the ratio of the target frequency to the clock source signal is less than the set low frequency band threshold ratio, then the hardware frequency modulation request corresponding to the target frequency is a low frequency band hardware frequency modulation request.

[0080] Since the clock source has the ability to output multiple clock source signals simultaneously, in a preferred embodiment, the low frequency band threshold refers to the ratio of the target frequency to the highest frequency clock source signal being less than the low frequency band threshold ratio.

[0081] It is worth noting that the low-frequency threshold ratio is set based on the physical properties of the clock divider circuit. For example, for a clock divider circuit that can reduce the frequency of the clock source signal by an integer multiple to obtain the first clock signal, the low-frequency threshold ratio can be set to 0.5. In other words, the low-frequency threshold ratio is the ratio of the highest frequency that the clock divider circuit can output to the clock source frequency.

[0082] The beneficial effects of this embodiment are:

[0083] A clock selection signal is generated according to the hardware frequency modulation request, and the first clock signal is selected as the clock output signal in the low-frequency band; since the first clock signal is obtained by dividing the clock source signal by a clock division circuit based on a hardware logic circuit, this method can obtain more low-frequency signals for chip use by dividing a single clock source signal without occupying additional clock source output resources, and further improve the adjustment flexibility of the clock source signal; in addition, the frequency division signal based on the logic circuit has a higher response rate than the software frequency modulation, which can improve the immediacy of the chip frequency reduction.

[0084] According to the above embodiment, in this embodiment:

[0085] The at least two clock signals further include a second clock signal; the second clock signal is a clock source signal output by a clock source;

[0086] It is worth noting that since the clock source has the ability to output multiple clock source signals at the same time, the number of second clock signals may be more than one. In the case of multiple second clock signals, different second clock signals can be recorded in sequence from high to low according to frequency as the first clock source signal, the second clock source signal, the third clock source signal, etc.

[0087] like Figure 2 As shown, the step of generating a clock selection signal according to the hardware frequency modulation request includes:

[0088] Step 1042: If it is determined that the hardware frequency modulation request is a low-frequency band hardware frequency modulation request, a clock selection signal and a clock division signal corresponding to the first clock signal are generated, and the clock division signal is sent to the clock division circuit so that the clock division circuit is connected and performs hardware division on the clock source signal to obtain the first clock signal.

[0089] Step 1044: Determine that the hardware frequency modulation request is a high-frequency band hardware frequency modulation request, and the target frequency is the same as the second clock signal, then generate a clock selection signal corresponding to the second clock signal; the high-frequency band hardware frequency modulation request refers to a hardware frequency modulation request with a target frequency higher than a set threshold.

[0090] Step 1046: Determine that the hardware frequency modulation request is a high-frequency band hardware frequency modulation request, and the target frequency is different from the second clock signal, then generate a clock source frequency modulation signal and send it for the clock source frequency modulation unit to adjust the clock source signal output by the clock source; the clock source frequency modulation signal includes the target frequency of the hardware frequency modulation request.

[0091] After the step of determining that the hardware frequency modulation request is a high-band hardware frequency modulation request and the target frequency is different from the second clock signal, generating and sending a clock source frequency modulation signal for the clock source frequency modulation unit to adjust the clock source signal output by the clock source (i.e., after step 1046), the method further includes:

[0092] Step 10462: Determine that the adjusted clock source signal frequency is the same as the target frequency, and then generate a clock selection signal corresponding to the second clock signal;

[0093] Step 10464: Determine that the adjusted clock source signal frequency is different from the target frequency, and the ratio of the target frequency to the adjusted clock source signal frequency is less than the set low frequency band threshold ratio, then generate a clock selection signal corresponding to the first clock signal.

[0094] In a preferred embodiment, the hardware frequency modulation request refers to a signal generated when the chip's operating parameters meet a preset frequency modulation range; the chip operating parameters include any one or any combination of operating temperature, operating voltage, and operating power consumption.

[0095] The execution timing of step 10462 and step 10464 depends on the execution logic of the clock source frequency modulation unit, that is, after step 1046 is executed, the clock source frequency modulation unit adjusts at least one of the clock source signals output by the clock source. If the logic of the clock source frequency modulation unit is to adjust at least one of the clock source signals output by the clock source to the target frequency, step 10462 is executed after the frequency adjustment is completed. If the logic of the clock source frequency modulation unit is to adjust at least one of the clock source signals output by the clock source to a larger value, so that the product of the larger value and the low frequency band threshold ratio is not less than the target frequency, step 10464 is executed after the frequency adjustment is completed.

[0096] That is to say, in an optional embodiment, the determination process in step 10462 and step 10464 cannot be understood as executing a judgment logic once, but rather as following the execution of the matching steps selected according to the preset clock source frequency modulation unit logic.

[0097] The beneficial effects of this embodiment are:

[0098] With the addition of a small amount of logic, the occupation of the top-level clock source output resources is reduced, and the response speed of the hardware automatic frequency modulation is improved; further, by not calling the clock source frequency modulation unit when the frequency band is low and the target frequency is the same as the second clock signal, and calling the clock source frequency modulation unit only in other cases, the clock source frequency modulation unit only works when necessary, reducing the CPU pressure while enabling more targeted frequency modulation.

[0099] In addition, the frequency reduction description used in the above method embodiments cannot be understood as meaning that the frequency modulation task with the frequency increase as the goal cannot be achieved. For example, the maximum output frequency of the clock source is 1200MHz. In the initial state, the clock frequency output inside the chip has been divided into 300MHz. At this time, a hardware frequency modulation request with a target frequency of 600MHz is received. Then, executing any of the above embodiment methods can complete the frequency increase task from 300MHz to 600MHz.

[0100] According to any of the above embodiments, a more comprehensive embodiment scheme description will be provided below in combination with the method and the device.

[0101] This embodiment provides a DFS (automatic dynamic frequency scaling, i.e., the hardware automatic frequency adjustment device of the present invention, some documents use the abbreviation AFS) system.

[0102] The DFS system is widely used in low-power chip designs, enabling SOC chips to reduce power consumption by automatically adjusting their clock frequency through hardware. However, the DFS in this embodiment uses a phased approach to reduce the clock frequency, making it unsuitable for circuits with latency requirements.

[0103] In some applications, the clock frequency is uniformly obtained by a PLL (phase-locked loop, a feasible clock source) and a POSTDIV (clock postdivider). Then, software controls the clock mux (clock multiplexer) to switch between clocks of different frequencies to achieve frequency modulation and achieve the purpose of reducing power consumption.

[0104] The disadvantage of the above application is that the PLL needs to generate all the clock frequencies required by the target clock, which occupies more of the PLL's fout (output) resources. In addition, the PLL output frequencies are usually shared with other modules, so these frequencies cannot be flexibly adjusted. The adjustment process requires software participation, and its response speed is also slow. When the CPU responsible for the frequency modulation task cannot respond to the frequency modulation requirements in time, it is easy to cause overheating and shutdown.

[0105] like Figure 5 As shown, the DFS system of this embodiment includes:

[0106] The phase-locked loop PLL as a clock source can receive the clock reference signal CLK_REF and output the first clock source signal Clk_fout0, the second clock source signal Clk_fout1, and the third clock source signal Clk_fout2 to the multiplexer gfmux, wherein the first clock source signal Clk_fout0 is also output to the frequency division module FDIV;

[0107] The DFS supporting software interface CR is capable of receiving software information BUS and outputting instructions Cfg corresponding to the software information BUS to the DFS control module dfs_ctrl (in a preferred embodiment, both BUS and Cfg include frequency division parameters);

[0108] The DFS control module dfs_ctrl (in an optional solution, corresponding to the execution subject of the above method embodiment) can receive the hardware frequency modulation request fredu_req, output the frequency division parameter and the operation instruction Ckg_en of the frequency division module FDIV to the frequency division module FDIV, and can also output the clock selection signal clk_sel to the control terminal of the multiplexer;

[0109] The frequency division module FDIV (corresponding to the clock frequency division circuit in the above embodiment, in this embodiment, the frequency division module FDIV uses a configurable divider), which can receive the frequency division parameter and the operation instruction Ckg_en sent by the DFS control module dfs_ctrl, and can also receive the first clock source signal Clk_fout0 output by the PLL, and output the first clock signal clk_div_out;

[0110] The multiplexer (a glitch-free multiplexer gfmux is selected in this embodiment) can receive the first clock source signal Clk_fout0, the second clock source signal Clk_fout11, the third clock source signal Clk_fout2 and the first clock signal clk_div_out, and output a specific received signal according to the clock selection signal clk_sel. The output signal of the multiplexer is recorded as clk_mc.

[0111] The operation steps of the DFS system are as follows:

[0112] The DFS supporting software is initialized once when the machine is turned on to load the frequency division parameters. The frequency division parameters include:

[0113] Frequency reduction step size;

[0114] Frequency up-conversion step size;

[0115] Frequency division period (Div_denom0~Div_denom2);

[0116] High level duration (Div_num0~Div_num2);

[0117] Number of frequency increase / decrease steps (number of STEPs);

[0118] When the monitoring module detects that a threshold (temperature / voltage / power consumption threshold required by the system) is reached, a DFS request is triggered. DFS_ctrl automatically controls the switching of the system clock frequency. Compared with the full-clock mux, a configurable FDIV (frequency division module) is added.

[0119] The processor core's main clock, clk_mc, is implemented using a combination of a gfmux (glitch-free multiplexer) and a configurable clock divider (FDIV). In the high-frequency DFS range (where the configured clock divider cannot divide by fractions between 0.5 and 1), the gfmux selects the frequency. In the low-frequency range (less than 0.5 times the maximum frequency), the configurable clock divider circuit performs DFS.

[0120] DFS only needs to initialize the module once when the system starts. No software intervention is required during the operation phase, and everything is implemented through hardware logic circuits.

[0121] In a preferred embodiment:

[0122] Low-performance chips can use the clock source frequency modulation unit to reduce the frequency to avoid the clock frequency division circuit idling and generating additional power consumption; or,

[0123] The clock frequency division circuit only operates after receiving the operation instruction Ckg_en to avoid idling and generating additional power consumption.

[0124] Figure 6 Schematic diagram of the basic timing of DFS in this embodiment is shown;

[0125] The operation process of the DFS system in this embodiment is implemented in parts. When the hardware frequency modulation request fredu_req is at a low level, the DFS system is not running and is in an idle state IDLE. When the hardware frequency modulation request fredu_req is at a high level and remains high:

[0126] First, execute STEP1. dfs_ctrl outputs the clock selection signal Clk_sel with a value of 0, and the multiplexer uses clk_fout0 as the output value clk_mc.

[0127] Execute STEP2, dfs_ctrl outputs the clock selection signal Clk_sel with a value of 1, and the multiplexer uses clk_fout1 as the output value clk_mc;

[0128] Execute STEP3, dfs_ctrl outputs the clock selection signal Clk_sel with a value of 2, and the multiplexer uses clk_fout2 as the output value clk_mc;

[0129] Execute STEP 3. dfs_ctrl outputs the clock selection signal Clk_sel with a value of 3. The multiplexer uses the first clock signal clk_div_out from FDIV as the output value clk_mc. At this time, FDIV performs frequency division based on the parameter Div_denom0. The frequency of clk_mc is equal to the ratio of the frequency of clk_fout0 to Div_denom0.

[0130] Execute STEP 4. dfs_ctrl outputs the clock selection signal Clk_sel with a value of 3. The multiplexer uses the first clock signal clk_div_out from FDIV as the output value clk_mc. At this time, FDIV performs frequency division based on the parameter Div_denom1. The frequency of clk_mc is equal to the ratio of the frequency of clk_fout0 to Div_denom1.

[0131] Execute STEP 5. dfs_ctrl outputs the clock selection signal Clk_sel with a value of 3. The multiplexer uses the first clock signal clk_div_out from FDIV as the output value clk_mc. At this time, FDIV performs frequency division based on the parameter Div_denom2. The frequency of clk_mc is equal to the ratio of the frequency of clk_fout0 to Div_denom2.

[0132] The following table shows the generation comparison of the clk_mc frequency F_clk_mc.

[0133] Table 1: F_clk_mc generation comparison table

[0134]

[0135] The following table gives examples of parameter values ​​when clk_fout0 = 1200 MHz.

[0136] Table 2: Values ​​of various parameters when clk_fout0 = 1200MHz

[0137] FSM_STA F_clk_mc(MHz) Clk_sel Div_denom Div_num IDLE 1200 0 x(N / A) x(N / A) STEP 1 1000 1 x(N / A) x(N / A) SETP2 800 2 x(N / A) x(N / A) STEP 3 600 3 2 1 STEP 4 400 3 3 1 STEP 5 200 3 6 3

[0138] In the above two tables, F_x refers to the frequency of x, and FSM_STA refers to the operating status of the DFS system.

[0139] It is worth noting that although the above step description only shows STEP 1 to STEP 5, it does not constitute a limitation on the number of steps. According to the preset number of frequency increase / decrease steps (number of steps) N, the above process can be executed to STEP N at a time.

[0140] When STEP N is completed and the hardware frequency modulation request fredu_req is still at a high level and maintained, FDIV continues to work, the clock selection signal Clk_sel remains unchanged, and the multiplexer maintains the output frequency until the hardware frequency modulation request fredu_req transitions to a low level. Then, STEP N to STEP1 are executed in reverse, thereby stopping the DFS system and maintaining the idle state IDLE.

[0141] The beneficial effects of this embodiment are:

[0142] With a small amount of logic added, the occupation of top-level PLL clock resources is reduced, the response speed of the DFS system is improved, and the software work efficiency is improved.

[0143] The following describes the hardware automatic frequency modulation device based on clock division and multiplexing provided by the present invention. The hardware automatic frequency modulation device based on clock division and multiplexing described below and the hardware automatic frequency modulation method based on clock division and multiplexing described above can be referenced to each other.

[0144] An embodiment of the present invention further provides a hardware automatic frequency modulation system based on clock frequency division and multiplexing, comprising:

[0145] Receiving module 701, used for receiving hardware frequency modulation request;

[0146] A selection module 702, configured to generate a clock selection signal according to the hardware frequency modulation request;

[0147] The clock selection signal is used to select a set clock signal from at least two clock signals as an output; the at least two clock signals include a first clock signal corresponding to a low-frequency band hardware frequency modulation request; the low-frequency band hardware frequency modulation request is a hardware frequency modulation request in which the target frequency is not higher than a set threshold;

[0148] The first clock signal is an output signal of a clock frequency dividing circuit; the clock frequency dividing circuit is a logic circuit that takes a clock source signal as input and obtains a first clock signal with a frequency lower than that of the clock source signal.

[0149] Furthermore, the at least two clock signals further include a second clock signal; the second clock signal is a clock source signal output by a clock source; the selection module 702 includes:

[0150] The low-frequency sub-module is used to determine that the hardware frequency modulation request is a low-frequency band hardware frequency modulation request, generate a clock selection signal and a clock frequency division signal corresponding to the first clock signal, and send the clock frequency division signal to the clock frequency division circuit so that the clock frequency division circuit is connected to perform hardware frequency division on the clock source signal to obtain the first clock signal.

[0151] The first high-frequency submodule is used to determine that the hardware frequency modulation request is a high-frequency band hardware frequency modulation request and the target frequency is the same as the second clock signal, and then generate a clock selection signal corresponding to the second clock signal; the high-frequency band hardware frequency modulation request refers to a hardware frequency modulation request with a target frequency higher than a set threshold.

[0152] The second high-frequency sub-module is used to determine that the hardware frequency modulation request is a high-frequency band hardware frequency modulation request, and the target frequency is different from the second clock signal, and then generate a clock source frequency modulation signal and send it for the clock source frequency modulation unit to adjust the clock source signal output by the clock source; the clock source frequency modulation signal includes the target frequency of the hardware frequency modulation request.

[0153] The system further comprises:

[0154] a first adjustment selection submodule, configured to determine that the frequency of the adjusted clock source signal is the same as the target frequency, and then generate a clock selection signal corresponding to the second clock signal;

[0155] The second adjustment selection submodule is used to determine that the adjusted clock source signal frequency is different from the target frequency, and the ratio of the target frequency to the adjusted clock source signal frequency is less than the set low frequency band threshold ratio, and then generate a clock selection signal corresponding to the first clock signal.

[0156] Figure 8 An example of a physical structure diagram of an electronic device is shown below. Figure 8As shown, the electronic device may include: a processor 810, a communication interface 820, a memory 830 and a communication bus 840, wherein the processor 810, the communication interface 820 and the memory 830 communicate with each other via the communication bus 840. The processor 810 may call the logic instructions in the memory 830 to execute a hardware automatic frequency modulation method based on clock division and multiplexing, the method comprising: receiving a hardware frequency modulation request; generating a clock selection signal according to the hardware frequency modulation request; the clock selection signal is used to select a set clock signal from at least two clock signals as a clock output signal; the at least two clock signals include a first clock signal corresponding to a low-frequency hardware frequency modulation request; the low-frequency hardware frequency modulation request refers to a hardware frequency modulation request with a target frequency not higher than a set threshold; the first clock signal is the output signal of a clock frequency division circuit; the clock frequency division circuit is a logic circuit that takes a clock source signal as input and obtains a first clock signal with a frequency lower than the clock source signal.

[0157] In addition, the logic instructions in the above-mentioned memory 830 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0158] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the hardware automatic frequency modulation method based on clock division and multiplexing provided by the above methods, the method including: receiving a hardware frequency modulation request; generating a clock selection signal according to the hardware frequency modulation request; the clock selection signal is used to select a set clock signal from at least two clock signals as a clock output signal; the at least two clock signals include a first clock signal corresponding to a low-frequency band hardware frequency modulation request; the low-frequency band hardware frequency modulation request refers to a hardware frequency modulation request in which the target frequency is not higher than a set threshold; the first clock signal is the output signal of a clock division circuit; the clock division circuit is a logic circuit that takes a clock source signal as input and obtains a first clock signal with a frequency lower than the clock source signal.

[0159] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the hardware automatic frequency modulation method based on clock division and multiplexing provided by the above-mentioned methods, the method comprising: receiving a hardware frequency modulation request; generating a clock selection signal according to the hardware frequency modulation request; the clock selection signal is used to select a set clock signal from at least two clock signals as a clock output signal; the at least two clock signals include a first clock signal corresponding to a low-frequency band hardware frequency modulation request; the low-frequency band hardware frequency modulation request refers to a hardware frequency modulation request in which the target frequency is not higher than a set threshold; the first clock signal is the output signal of a clock division circuit; the clock division circuit is a logic circuit that takes a clock source signal as input and obtains a first clock signal with a frequency lower than that of the clock source signal.

[0160] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0161] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0162] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A hardware automatic frequency modulation method based on clock division and multiplexing, characterized in that: include: The frequency modulation control unit receives a hardware frequency modulation request; The frequency modulation control unit generates a clock selection signal according to the hardware frequency modulation request; The clock selection signal is used to select a set clock signal from at least two clock signals as a clock output signal; the at least two clock signals include a first clock signal corresponding to a low-frequency band hardware frequency modulation request; the low-frequency band hardware frequency modulation request is a hardware frequency modulation request in which the target frequency is not higher than a set threshold; The first clock signal is an output signal of a clock frequency dividing circuit; the clock frequency dividing circuit is a logic circuit that takes a clock source signal as input and generates a first clock signal with a frequency lower than that of the clock source signal; The at least two clock signals further include a second clock signal; The second clock signal is a clock source signal output by a clock source; The step of generating a clock selection signal according to the hardware frequency modulation request comprises: determining that the hardware frequency modulation request is a high-band hardware frequency modulation request and that the target frequency is different from the second clock signal, generating and sending a clock source frequency modulation signal for the clock source frequency modulation unit to adjust the clock source signal output by the clock source; the clock source frequency modulation signal includes the target frequency of the hardware frequency modulation request; After the step of determining that the hardware frequency modulation request is a high-band hardware frequency modulation request and the target frequency is different from the second clock signal, generating a clock source frequency modulation signal and sending it for the clock source frequency modulation unit to adjust the clock source signal output by the clock source, the method further includes: determining that the adjusted clock source signal frequency is the same as the target frequency, and generating a clock selection signal corresponding to the second clock signal; If it is determined that the adjusted clock source signal frequency is different from the target frequency, and the ratio of the target frequency to the adjusted clock source signal frequency is less than a set low-frequency band threshold ratio, a clock selection signal corresponding to the first clock signal is generated; the low-frequency band threshold ratio is set based on the physical properties of the clock frequency dividing circuit, and the low-frequency band threshold ratio is the ratio of the highest frequency that the clock frequency dividing circuit can output to the clock source frequency.

2. The hardware automatic frequency modulation method based on clock division and multiplexing according to claim 1, characterized in that: The at least two clock signals further include a second clock signal; The second clock signal is a clock source signal output by a clock source; The step of generating a clock selection signal according to the hardware frequency modulation request comprises: If it is determined that the hardware frequency modulation request is a high-band hardware frequency modulation request and the target frequency is the same as the second clock signal, a clock selection signal corresponding to the second clock signal is generated; the high-band hardware frequency modulation request refers to a hardware frequency modulation request with a target frequency higher than a set threshold.

3. The hardware automatic frequency modulation method based on clock division and multiplexing according to claim 1, characterized in that: The step of generating a clock selection signal according to the hardware frequency modulation request comprises: If it is determined that the hardware frequency modulation request is a low-frequency band hardware frequency modulation request, a clock selection signal and a clock division signal corresponding to the first clock signal are generated, and the clock division signal is sent to the clock division circuit so that the clock division circuit is connected to perform hardware division on the clock source signal to obtain the first clock signal.

4. The hardware automatic frequency modulation method based on clock division and multiplexing according to claim 3, characterized in that: The hardware frequency modulation request refers to a signal generated when the operating parameters of the chip meet a preset frequency modulation range; the chip operating parameters include any one or any combination of operating temperature, operating voltage, and operating power consumption.

5. Application of a clock output signal obtained by the hardware automatic frequency modulation method based on clock division and multiplexing according to any one of claims 1 to 4 in chip power consumption control.

6. A hardware automatic frequency modulation device based on clock division and multiplexing, characterized in that: The device is used to execute the hardware automatic frequency modulation method based on clock division and multiplexing according to any one of claims 1 to 4, comprising: A clock source, the clock source comprising a clock source output terminal for outputting a clock source signal; A frequency modulation control unit, the frequency modulation control unit comprising a frequency modulation control unit input terminal for receiving a hardware frequency modulation request and a first frequency modulation control unit output terminal for outputting a clock selection signal; a clock frequency dividing circuit, the clock frequency dividing circuit comprising a first clock frequency dividing circuit input terminal electrically connected to the clock source output terminal and a clock frequency dividing circuit output terminal for outputting a first clock signal; the first clock signal having a frequency lower than that of the clock source signal; A selection output device, wherein a first input terminal of the selection output device is electrically connected to the output terminal of the clock source, a second input terminal of the selection output device is electrically connected to the output terminal of the clock frequency division circuit, and a control terminal of the selection output device is electrically connected to the first output terminal of the frequency modulation control unit; The selection outputter can output the clock source signal received at the first input terminal of the selection outputter or the first clock signal received at the second input terminal of the selection outputter according to the clock selection signal received at the control terminal.

7. The hardware automatic frequency modulation device based on clock division and multiplexing according to claim 6, characterized in that: The frequency modulation control unit further includes a second output terminal of the frequency modulation control unit for outputting a preset frequency division parameter; the clock frequency division circuit further includes a second input terminal of the clock frequency division circuit electrically connected to the second output terminal of the frequency modulation control unit; The frequency division parameters include a frequency division period, a high-level duration, a frequency increase step, and a frequency decrease step; wherein the frequency division period refers to the period of the first clock signal; the high-level duration refers to the duration of the first clock signal at a high level in a single period; the frequency decrease step refers to the step in the process of step-by-step frequency reduction of the clock source signal to the first clock signal; the frequency increase step refers to the step in the process of step-by-step frequency increase of the first clock signal to the clock source signal when the clock frequency division circuit stops working.

8. The hardware automatic frequency modulation device based on clock frequency division and multiplexing according to claim 7, characterized in that: The frequency division parameters are loaded into the frequency modulation control unit during the initialization process.

9. The hardware automatic frequency modulation device based on clock frequency division and multiplexing according to claim 7, characterized in that: The duty cycle of the first clock signal can be adjusted by the frequency division period and the high level duration in the frequency division parameters.

10. The hardware automatic frequency modulation device based on clock division and multiplexing according to any one of claims 6 to 9, characterized in that: The hardware automatic frequency regulation device is used to control power consumption in a chip.

11. A hardware automatic frequency modulation system based on clock division and multiplexing, characterized in that: include: A receiving module, used for receiving hardware frequency modulation requests; A selection module, configured to generate a clock selection signal according to the hardware frequency modulation request; The clock selection signal is used to select a set clock signal from at least two clock signals as an output; the at least two clock signals include a first clock signal corresponding to a low-frequency band hardware frequency modulation request; the low-frequency band hardware frequency modulation request is a hardware frequency modulation request in which the target frequency is not higher than a set threshold; The first clock signal is an output signal of a clock frequency dividing circuit; the clock frequency dividing circuit is a logic circuit that takes a clock source signal as input and generates a first clock signal with a frequency lower than that of the clock source signal; The at least two clock signals further include a second clock signal; The second clock signal is a clock source signal output by a clock source; The step of generating a clock selection signal according to the hardware frequency modulation request comprises: determining that the hardware frequency modulation request is a high-band hardware frequency modulation request and that the target frequency is different from the second clock signal, generating and sending a clock source frequency modulation signal for the clock source frequency modulation unit to adjust the clock source signal output by the clock source; the clock source frequency modulation signal includes the target frequency of the hardware frequency modulation request; After the step of determining that the hardware frequency modulation request is a high-band hardware frequency modulation request and the target frequency is different from the second clock signal, generating a clock source frequency modulation signal and sending it for the clock source frequency modulation unit to adjust the clock source signal output by the clock source, the method further includes: determining that the adjusted clock source signal frequency is the same as the target frequency, and generating a clock selection signal corresponding to the second clock signal; If it is determined that the adjusted clock source signal frequency is different from the target frequency, and the ratio of the target frequency to the adjusted clock source signal frequency is less than a set low-frequency band threshold ratio, a clock selection signal corresponding to the first clock signal is generated; the low-frequency band threshold ratio is set based on the physical properties of the clock frequency dividing circuit, and the low-frequency band threshold ratio is the ratio of the highest frequency that the clock frequency dividing circuit can output to the clock source frequency.

12. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the steps of the hardware automatic frequency modulation method based on clock division and multiplexing as claimed in any one of claims 1 to 4 are implemented.

13. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the hardware automatic frequency modulation method based on clock division and multiplexing as claimed in any one of claims 1 to 4 are implemented.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the hardware automatic frequency modulation method based on clock division and multiplexing as claimed in any one of claims 1 to 4 are implemented.

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