Network-on-chip architecture and related equipment, data transmission system

Abstract

The embodiment of the present invention provides a network-on-chip architecture and related equipment, and a data transmission system, wherein the network-on-chip architecture includes a storage configuration layer, which is used to configure a storage device for the network-on-chip so that the data to be transmitted is temporarily stored in the storage device during the transmission process; an arbitration control layer, which is used to arbitrate and control the transmission path of the data to be transmitted, and determine the transmission path connected to the output interface so that the transmission path connected to the output interface is the data transmission path; and a data link layer, which is used to control the transmission of the data to be transmitted based on the corresponding transmission path. The embodiment of the present invention improves the configuration efficiency of the network architecture.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of chip technology, and in particular to an on-chip network architecture and related equipment and a data transmission system. Background Art

[0002] The network on chip (NOC, network on chip, also known as the on-chip bus network) is used to realize the interconnection of various devices in the system-on-chip (SOC, system on chip) and is a major component of multi-core technology.

[0003] When data is transmitted in the on-chip network, it is usually necessary to adjust the configuration of the network architecture of the on-chip network to adapt to the transmission rules of network data. However, when the network architecture is reconfigured, the configuration efficiency is low.

[0004] Therefore, how to achieve efficient configuration of the network architecture has become an urgent problem to be solved by those skilled in the art. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a network-on-chip architecture and related devices, and a data transmission system to achieve efficient configuration of the network architecture.

[0006] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0007] In a first aspect, an embodiment of the present invention provides a network on chip architecture, including:

[0008] A storage configuration layer, used to configure a storage device for the on-chip network so that the data to be transmitted is temporarily stored in the storage device during the transmission process;

[0009] The arbitration control layer is used to perform arbitration control on the transmission path of the data to be transmitted, and determine the transmission path connected to the output interface so that the transmission path connected to the output interface is the data transmission path;

[0010] The data link layer is used to control the transmission of the data to be transmitted based on the corresponding transmission path.

[0011] In a second aspect, an embodiment of the present invention further provides a network on chip, including:

[0012] An input interface, an output interface, a node located in the network, an arbitrator located between the node and the output interface, and a storage device connected between the input interface and the output interface; wherein the on-chip network is used to construct the on-chip network architecture provided by an embodiment of the present invention.

[0013] In a third aspect, an embodiment of the present invention further provides a data transmission system, characterized in that the data transmission system performs data transmission based on the on-chip network architecture provided by an embodiment of the present invention.

[0014] In a fourth aspect, an embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more executable instructions, and the one or more executable instructions are used to perform data transmission based on the on-chip network architecture described above.

[0015] An embodiment of the present invention provides an on-chip network architecture and related equipment, and a data transmission system. The on-chip network architecture includes a storage configuration layer, which is used to configure a storage device for the on-chip network so that the data to be transmitted is temporarily stored in the storage device during the transmission process; an arbitration control layer, which is used to arbitrate and control the transmission path of the data to be transmitted, and determine the transmission path connected to the output interface so that the transmission path connected to the output interface is the data transmission path; and a data link layer, which is used to control the transmission of the data to be transmitted based on the corresponding transmission path.

[0016] It can be seen that by managing the on-chip network architecture in layers and controlling different aspects based on different layer structures, each layer structure is independent of each other, thereby reducing the correlation between various configurations in the network structure. In the process of configuring the network architecture, based on the independence of each layer structure, the configuration of each layer structure does not affect other layer structures, thereby reducing the impact on the configurations in other layer structures, reducing the correlation factors that need to be considered in the reconfiguration process of the network architecture, and improving the configuration efficiency of the network architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0018] Figure 1 An optional structural diagram of a network on chip provided by an embodiment of the present invention;

[0019] Figure 2 A schematic diagram of an optional structure of a cache in a network on chip provided by an embodiment of the present invention;

[0020] Figure 3 An optional schematic diagram of an arbitrator provided in an embodiment of the present invention performing arbitration based on a transmission path;

[0021] Figure 4 An optional layer structure diagram of the on-chip network architecture provided by an embodiment of the present invention;

[0022] Figure 5 An example diagram of allocation of a physical channel provided by an embodiment of the present invention;

[0023] Figure 6 A schematic diagram of an optional flow chart of data transmission in a network on chip provided by an embodiment of the present invention;

[0024] Figure 7 An optional schematic diagram of a network on chip provided by an embodiment of the present invention;

[0025] Figure 8 An example diagram of a sub-network connection structure provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] As described in the background art, when reconfiguring a network architecture, the configuration efficiency is low.

[0028] The inventor believes that this is because, when reconfiguring the network architecture, the associations between different configurations usually affect other configurations, causing the network architecture reconfiguration process to consider more associated factors, which in turn leads to low configuration efficiency of the network architecture and even the need to redesign the network architecture.

[0029] Based on this, an embodiment of the present invention provides an on-chip network architecture and related equipment, and a data transmission system. The on-chip network architecture includes a storage configuration layer, which is used to configure a storage device for the on-chip network so that the data to be transmitted is temporarily stored in the storage device during the transmission process; an arbitration control layer, which is used to arbitrate and control the transmission path of the data to be transmitted, and determine the transmission path connected to the output interface so that the transmission path connected to the output interface is the data transmission path; a data link layer, which is used to control the transmission of the data to be transmitted based on the corresponding transmission path.

[0030] It can be seen that by managing the on-chip network architecture in layers and controlling different aspects based on different layer structures, each layer structure is independent of each other, thereby reducing the correlation between various configurations in the network structure. In the process of configuring the network architecture, based on the independence of each layer structure, the configuration of each layer structure does not affect other layer structures, thereby reducing the impact on the configurations in other layer structures, reducing the correlation factors that need to be considered in the reconfiguration process of the network architecture, and improving the configuration efficiency of the network architecture.

[0031] The network on chip provided by the embodiment of the present invention is described in detail below.

[0032] In an optional implementation, the embodiment of the present invention provides a crossbar type bus topology structure on-chip network architecture, referring to Figure 1 An optional structural diagram of an on-chip network is shown, wherein the on-chip network includes an input interface, an output interface, nodes located in the network, an arbitrator located between the nodes and the output interface, and a storage device connected between the input interface and the output interface, wherein a node is used to control a transmission path from an input interface to an output interface.

[0033] The input interface is used to connect to the input end. For multiple input interfaces, the figure takes input interface 0, input interface 1... input interface N as an example for display. The input end can be an IP (Intellectual Property) module or a computing core, etc. The figure takes the IP module as an input end as an example for illustration. For multiple IP modules, the figure takes IP_0, IP_1... IP_N as an example for illustration. The output interface is used to connect to the output end. For multiple output interfaces, the figure takes output interface 0, output interface 1... output interface N as an example for illustration. The output end can be an IP module or a computing core, etc. Similarly, the figure takes the IP module as an output end as an example for illustration. For multiple IP modules, the figure takes IP_0, IP_1... IP_N as an example for illustration. The node can be, for example, a switch node, which is used to provide a corresponding data transmission path.

[0034] It is understandable that, in order to achieve data interaction, the IP module or computing core is usually both an input end and an output end, and only needs to be connected to the on-chip network based on different interfaces.

[0035] During the data transmission process, the input end is configured with a cache queue (not shown in the figure), which is stored in a storage device. One transmission path corresponds to one cache queue, and the input end can allocate the data to be transmitted to the corresponding cache queue according to the target output interface of the data to be transmitted, and correspondingly, the output interface receives the data to be transmitted of the corresponding transmission path.

[0036] Specifically, the storage device may include a cache, which may be set in one or more components of the input interface, output interface, and node (hereinafter referred to as node) of the on-chip network, for caching the data to be transmitted to the corresponding node, and enabling the output interface to read the data to be transmitted when the transmission path competition is successful. Figure 2 A schematic diagram of the optional structure of the cache in the on-chip network is shown, in which the input interface, the output interface, and the node are all configured with a cache as an example. Correspondingly, the cache corresponding to the input interface is identified by cfg_in_buff in the figure, the cache corresponding to the node is identified by cfg_pt_buff in the figure, and the cache corresponding to the input interface is identified by cfg_ot_buff in the figure, wherein one transmission path corresponds to one cache (refer to the dotted arrow in the figure). In an optional example, a row of nodes can correspond to a row of caches, and the cache corresponding to each node can be allocated from the row of caches, and the caches allocated to each node can be the same or different. Correspondingly, in other examples, a column of nodes can also correspond to a column of caches, and the caches corresponding to each node can be allocated from the column of caches, and the caches allocated to each node can be the same or different. In the example of having both a row cache and a column cache, the cache allocated to each node can be the sum of the cache allocated to the row cache and the cache allocated to the column cache.

[0037] For further reference, Figure 1 The storage device may further include a shared storage device connected between the input interface and the output interface, for storing the data to be transmitted that failed to compete for the transmission path, and when the data to be transmitted to the output interface is idle, the data to be transmitted is transmitted using the transmission path. The shared storage device may be directly or indirectly connected between the input interface and the output interface. For example, when the shared storage device is indirectly connected between the input interface and the output interface, the shared storage device may be connected between the node and the arbitrator.

[0038] by Figure 1For example, when input interface 0 based on node B and input interface 1 based on node A compete for the transmission path corresponding to output interface 1 at the same time, the transmission path that fails in the competition will transfer the data to be transmitted to the shared storage device. Taking the failure of the transmission path competition of node A as an example, the data to be transmitted of the corresponding node A is transmitted to the shared storage device (refer to the dotted line transmission path), and when the subsequent transmission path of node A is idle, the data to be transmitted is transmitted to the arbitrator corresponding to output interface 1 based on FIFO (first in first out mechanism) to transfer the data to be transmitted to output interface 1. In other optional examples, a FIFO memory can be further set between the shared storage device and the arbitrator to improve data processing performance. It can be understood that by realizing strict sequential transmission in the network, the embodiment of the present invention will not cause disorder even if the capacity of the storage device is increased.

[0039] It should be noted that the transmission path of the data to be transmitted is a data transmission path, which means that the route for transmitting the data to be transmitted is in a smooth state, and can also be understood as that the physical line of the corresponding transmission path is in an idle state. Figure 1 In the process of data transmission from input interface 0 to node B, if the shared storage device stores data to be transmitted from node C or node D to output interface N and no other data needs to be transmitted, that is, the transmission path is a data transmission path, that is, the route is in an idle state, then the transmission path can be transmitted to output interface N based on the transmission path from the shared storage device to output port N.

[0040] The arbitrator is used to arbitrate based on preset rules to determine the data to be transmitted to the output interface. Specifically, when multiple transmission paths simultaneously transmit the data to be transmitted to the same output interface (i.e., transmission path competition occurs, i.e., transmission congestion occurs), the arbitration selects a transmission path to be connected to the output structure, so that the transmission path connected to the output interface is the data transmission path, and then the output interface receives the data to be transmitted of the transmission path. Among them, the transmission path selected by the arbitration can be understood as a successful competition transmission path, and the transmission path not selected by the arbitration can be understood as a failed competition transmission path. When a transmission path transmits the data to be transmitted to an output interface, the arbitration output interface receives the data to be transmitted of the transmission path, and accordingly, the transmission path can be understood as a successful competition transmission path.

[0041] refer to Figure 3An optional schematic diagram of an arbitrator performing arbitration based on a transmission path is shown, wherein the input end still takes multiple IP modules as an example, and IP_0, IP_1...IP_N are used as examples in the figure; the output end still takes multiple IP modules as an example, and similarly, IP_0, IP_1...IP_N are used as examples in the figure, P is a node in the network, and the on-chip network further includes a selector for indicating the node to be selected by the input data to be transmitted, and accordingly, the arbitrator indicates the node from which the output data to be transmitted comes from among the arbitrated nodes.

[0042] It should be noted that the hardware architecture of the on-chip network architecture may also be of other types, and the present invention does not make any specific limitation here.

[0043] In an optional implementation, based on Figure 1 The optional structure diagram of the on-chip network architecture is shown, and the embodiment of the present invention further provides an optional layer structure diagram of the on-chip network architecture, Figure 4 The optional layer structure diagram of the on-chip network architecture provided by an embodiment of the present invention is exemplarily shown. The on-chip network architecture includes:

[0044] The storage configuration layer 110 is used to configure a storage device for the on-chip network so that the data to be transmitted is temporarily stored in the storage device during the transmission process; the arbitration control layer 120 is used to arbitrate and control the transmission path of the data to be transmitted, and determine the transmission path connected to the output interface so that the transmission path connected to the output interface is the data transmission path; the data link layer 130 is used to control the transmission of the data to be transmitted based on the corresponding transmission path.

[0045] The storage configuration layer 110 may be a storage device for configuring the on-chip network. The storage device may be a cache corresponding to each node, or a shared storage device corresponding to the on-chip network. Alternatively, the storage device may include both a cache corresponding to each node and a shared storage device corresponding to the on-chip network.

[0046] When the storage device configured for the on-chip network is a cache corresponding to each node, the data to be transmitted can be temporarily stored in the cache of the corresponding node during data transmission, and when the transmission path competition is successful, the output interface reads the data to be transmitted.

[0047] Among them, when the storage device configured for the on-chip network is a shared storage device corresponding to the on-chip network, the data to be transmitted that failed to compete for the transmission path can be stored during the data transmission process, and when the transmission path of the data to be transmitted is a data transmission path, the data to be transmitted can be transmitted using the transmission path.

[0048] Accordingly, when the storage device configured for the on-chip network includes both a cache corresponding to each node and a shared storage device corresponding to the on-chip network, the data to be transmitted can be temporarily stored in the cache of the node corresponding to the transmission path during the data transmission process, and when the transmission path competition is successful, the output interface reads the data to be transmitted, and when the transmission path competition fails, the data to be transmitted is stored, and when the data transmission path from the transmission path of the data to be transmitted to the output interface is idle, the data to be transmitted is transmitted using the transmission path.

[0049] It is understandable that in the actual operation of the on-chip network, not all output interfaces are used every beat (i.e., one clock cycle of the chip), and the configuration of the shared storage device allows the data to be transmitted that has failed in the competition to be output when the data transmission path is idle, thereby coordinating the data transmission process and avoiding the blocking of the output port by the data to be transmitted that has failed in the competition when the data transmission path is insufficient. At the same time, the data transmission efficiency is improved when the data transmission path is idle, so that the data transmission of the on-chip network is always in an efficient operating state, or in a full-bandwidth operating state most of the time.

[0050] It should be noted that the configuration of the storage configuration layer may include the size of the cache capacity of each node in the on-chip network, wherein the cache capacity of a node may be as small as 0. Specifically, the storage configuration layer may allocate a row cache corresponding to each row node to each row node, and / or the storage configuration layer may allocate a column cache corresponding to each column node to each column node, thereby realizing the configuration of the cache of each node. In an optional example, the storage form of the cache corresponding to each node in the on-chip network may also be included, such as a register, RAM (Random Access Memory) or FIFO memory (First Input First Output). Among them, factors such as network load capacity, delay requirements, and cost control may be considered for the configuration of the storage configuration layer. At the same time, in some examples, the data transmission characteristics of the input / output terminals corresponding to each input / output interface may be further considered.

[0051] The arbitration control layer 120 is used to perform arbitration control on the transmission path of the data to be transmitted, and determine the transmission path connected to the output interface so that the transmission path connected to the output interface serves as a data transmission path.

[0052] The arbitration control layer 120 is used to control the arbitrator to arbitrate based on a preset mechanism, wherein the arbitration mode of the arbitration control layer 120 can be random arbitration, weight arbitration, etc., and the present invention does not make specific limitations here. It can be understood that when multiple transmission paths simultaneously transmit data to be transmitted to the same output interface (i.e., transmission path competition occurs, i.e., congestion occurs), the arbitration control layer 120 arbitrates and selects a transmission path to be connected to the output interface, so that the transmission path connected to the output interface is a data transmission path, and then the output interface receives the data to be transmitted of the transmission path. When a transmission path transmits data to be transmitted to an output interface, the transmission path is arbitrated to be connected to the output interface, so that the transmission path connected to the output interface is a data transmission path, and then the output interface receives the data to be transmitted of the transmission path.

[0053] The arbitration control layer 120 can also adjust the bandwidth of the physical channel corresponding to the virtual channel based on the congestion data of each virtual channel. Specifically, in the on-chip network, a virtual channel (virtualchannelVC) is also provided relative to the physical channel, wherein there is a corresponding relationship between the virtual channel and the physical channel. When data is transmitted, the data to be transmitted is usually allocated based on the virtual channel, and correspondingly, at the physical level, the data to be transmitted is transmitted based on the physical channel corresponding to the allocated virtual channel.

[0054] In the initial stage, the virtual channels can evenly share the bandwidth of the physical channels. However, as the on-chip network operates, some virtual channels may often be in a congested state (for example, the transmission path corresponding to the data is often in a state of contention), while some virtual channels may often be in an idle state. In an embodiment of the present invention, the bandwidth of the corresponding physical channel can be adjusted for the virtual channel based on the congestion data of each virtual channel (for example, the number of congestion times in the previous cycle), so that the virtual channel can transmit data based on the adjusted bandwidth in the next cycle. In an optional example, the virtual channel can complete the bandwidth allocation adjustment based on QoS (Quality of Service) identification. Accordingly, in the arbitration control layer, the arbitrator can provide QoS support.

[0055] Obviously, by adaptively adjusting the hardware resources of the on-chip network architecture, the utilization of hardware resources can be improved, thereby improving the data transmission efficiency of the on-chip network and improving the QoS of the network.

[0056] Among them, in the embodiment of the present invention, the adjustment of the virtual channel and the physical channel can be adapted between the input end and the input interface, between the input interface and the node, and between the node and the output interface. The embodiment of the present invention does not make specific limitations here.

[0057] refer to Figure 5 An example diagram of physical channel allocation is shown, in which an input / output terminal (usually one terminal is both an input terminal and an output terminal) and an input / output interface are used as an example for explanation. It can be seen that after the virtual channel and the physical channel are adjusted, the sub-channels sub-phy110 to sub-phy11N of the input / output terminal IP_0 are no longer limited to the sub-channels sub-phy120 to sub-phy12N after the initial equal division, but further utilize the sub-channel sub-phy220. Correspondingly, the sub-channels sub-phy210 to sub-phy21N of the input / output terminal IP_1 no longer utilize the sub-channel sub-phy220, but are adjusted to sub-phy22N, while the other input / output terminals maintain the original channel configuration, that is, the sub-channels sub-phy310 to sub-phy31N are configured to the sub-channels sub-phy320 to sub-phy32N, and the sub-channels sub-phy410 to sub-phy41N are configured to the sub-channels sub-phy420 to sub-phy42N. The arbitration control layer may utilize a fabric control unit to receive software or hardware information to control network connections.

[0058] The data link layer 130 is used to control the transmission of the data to be transmitted based on the corresponding transmission path. Specifically, after the transmission path of the data to be transmitted is selected by arbitration, the transmission path can be understood as a data transmission path, and then the data can be migrated according to the specific result data. Among them, the result data is at least used to indicate that the transmission path is a data transmission path, and then the latter device in the transmission path can be controlled to read the data to be transmitted stored in the previous device, so as to realize the transmission of the data to be transmitted. Of course, the data migration method in the present invention can be a valid-ready handshake method, a req-gnt handshake method or an enable-credit handshake method, and the present invention does not make specific limitations here.

[0059] refer to Figure 6 The optional flow diagram of data transmission in the on-chip network shown in the figure, in the process of data transmission, based on the transmission path determined by the arbitrator, the cache in the node and the corresponding handshake method can be used to implement data handshake transmission, so as to transmit the data to be transmitted to each input / output terminal,

[0060] In the embodiment of the present invention, the data link layer may be further used to provide a data compression strategy so that the data is compressed before transmission.

[0061] Specifically, an optional data compression strategy can be as follows:

[0062] When data is transmitted, the data to be transmitted can be divided into data segments with a preset length, and accordingly, the data to be transmitted includes at least one data segment. At the same time, the data segments can be divided into valid data and invalid data, and an identification bit corresponding to the data segment is provided to indicate that the corresponding data segment is valid data or invalid data. All identification bits corresponding to the data to be transmitted can constitute an identification data segment, and the arrangement order of the identification bits in the identification data segment is consistent with the arrangement order of the data segments of the data to be transmitted.

[0063] For example, the data segment can be set to 8 bits, and each 8 bits of data corresponds to an identification bit bitbyte_en. In other examples of the present invention, the preset length of the data segment can also be set to other values, such as 16 bits, 32 bits, 64 bits, etc., and the present invention does not make specific limitations here.

[0064] When data is transmitted, only valid data in the data to be transmitted and the identification data segment corresponding to the data to be transmitted can be transmitted based on the indication of the identification data segment, thereby compressing the data volume of the data to be transmitted and improving data transmission efficiency.

[0065] In a specific example, invalid data of the data to be transmitted may be deleted, and the remaining data may be compactly arranged to form compressed data, and the compressed data may be further transmitted.

[0066] It is understandable that, based on the compression strategy, the data link layer further provides a data decompression strategy to restore the data to be transmitted. The corresponding decompression strategy may be as follows:

[0067] Based on the identification bit in the identification data segment and the position of the identification bit in the identification data segment, the position of the received data in the data to be transmitted is determined, and the invalid data is further supplemented to restore the data to be transmitted.

[0068] In a further example, when all data segments of the data to be transmitted are valid data, the identification data segment may be removed and only the data to be transmitted is transmitted, thereby compressing the data volume of the data to be transmitted and improving data transmission efficiency.

[0069] Specifically, data that is all "0" can be set as invalid data, and at the same time, the identification bit of valid data can be set to "1". When the data in the identification data segment are all "1", the data in the identification data segment can be reversed to make it all "0", and the identification data segment is no longer transmitted.

[0070] The corresponding decompression strategy may be set to determine that the received data is the data to be transmitted when the length of the received data is equal to the length of the data to be transmitted.

[0071] It is understandable that the network-on-chip architecture provided by the embodiment of the present invention is easy to configure and also facilitates flexible changes in network topology, thereby simplifying the development process. In addition, the network-on-chip architecture provided by the embodiment of the present invention, the corresponding physical hardware such as input / output interfaces, nodes, arbitrators, etc. are all repetitive components, and interfaces and nodes can be added or deleted at any time based on corresponding needs, and the corresponding architecture only needs to be configured and adjusted layer by layer, further improving the flexibility of the network topology.

[0072] It is understandable that the interfaces and carrying capacity of the on-chip network are limited. As the number of interfaces of the on-chip network increases, the chip design timing becomes tighter. At the same time, the more interfaces the on-chip network has, the larger the scale, the longer the maximum transmission distance between the corresponding interfaces, and the heavier the burden on the on-chip network. Based on this, an embodiment of the present invention further provides an on-chip network, which may include sub-networks, wherein the sub-networks may be networked based on the principle of proximity, and the sub-networks are interconnected.

[0073] In an optional example, the on-chip network may include multiple sub-networks. For details, refer to Figure 7 An optional schematic diagram of an on-chip network is shown, taking the networking of the first sub-network and the second sub-network as an example for explanation. The first sub-network and the second sub-network can both be understood as independent on-chip networks, and the first sub-network and the second sub-network can be interconnected and networked through an input / output interface. Specifically, an output interface of the first sub-network is connected to an input interface of the second sub-network, and an input interface of the first sub-network is connected to an output interface of the second sub-network.

[0074] It is understandable that, compared with the interconnection channels between modules / cores, the channels connecting sub-networks have a greater bandwidth requirement. In the embodiment of the present invention, multiple interfaces can be interconnected to meet the bandwidth requirement. Specifically, multiple input / output interfaces can be allocated to the sub-network to meet the bandwidth requirement of the sub-network. In a specific example, refer to Figure 7 An optional schematic diagram of a network on a chip is shown, from which it can be seen that, compared with one input / output interface connecting one IP, there can be multiple input interfaces connecting the first subnetwork to the second subnetwork, and there can be multiple output interfaces connecting the first subnetwork to the second subnetwork.

[0075] It should be noted that in some optional examples, multiple input / output interfaces are simultaneously allocated to an input / output end, and the input / output end is not limited to a sub-network, but can also be a module or a computing core, etc. The present invention does not make specific limitations here.

[0076] It can be seen that compared to increasing the bus width of an input / output port to accommodate a larger bandwidth requirement, the embodiment of the present invention can unify network components by simultaneously allocating multiple input / output interfaces to an input / output port, thereby avoiding the problem of complex network structure and corresponding complex configuration caused by too many types of components.

[0077] Specifically, in a network with multiple input / output interfaces allocated at the same time, the corresponding data transmission changes from serial transmission to parallel transmission. Based on this, a sequence configuration function can be added to the corresponding data transmission process at the arbitration control layer.

[0078] Specifically, when an input / output port is assigned multiple input / output interfaces at the same time, the data to be transmitted of the multiple input / output interfaces are transmitted simultaneously, and the arbitration control layer can configure priorities for different mounting paths (for example, the physical bus mounted to the input interface or the physical bus mounted to the output interface), thereby determining the transmission order of different data to be transmitted based on the corresponding priorities. The mounting path is used to indicate the mounting relationship between the input interface and the physical bus, and the mounting relationship between the output interface and the physical bus.

[0079] Among them, the priority order can be determined based on the priority and / or data type of the data to be transmitted in the physical bus. For example, when data transmission requires the transmission of control information first and then the transmission of data matching the control information, the control information and the matching data can be transmitted to the input / output interface in the same clock cycle based on different mounting paths, and the arbitration control layer can configure the order configuration function for different mounting paths, so that the signal that needs to be transmitted first is configured on a mounting path with a high priority (such as a physical bus with a priority order), and the signal that is transmitted later is configured on a mounting path with a low priority (such as a physical bus with a normal order), so that even if the data to be transmitted is transmitted concurrently, there will be no confusion in the order of data transmission.

[0080] refer to Figure 7 As shown, the control information is the head data (shown as Head in the figure), and the matching data is the tail data (shown as Tail in the figure). In the data input path, the mount path used to transmit the Head can be configured as a high priority, and the mount path used to transmit the Tail can be configured as a low priority for data transmission.

[0081] Even data with different priorities can be sent in parallel under the premise that the mounting path is unobstructed, and high-priority data can be loaded to the high-priority mounting path, while low-priority data can be loaded to the low-priority mounting path. In this way, the priority of the data can be distinguished from the mounting path, and the corresponding priority information can be retained to the next layer of network transmission, thereby maintaining the priority determination.

[0082] Furthermore, when the input ends of multiple input interfaces are simultaneously assigned to transmit data to the output end of a single output interface, the arbitration control layer can configure the arbitrator to output the data to be transmitted based on the priority order of the mounting path, thereby avoiding the phenomenon of data transmission order confusion in the data to be transmitted.

[0083] Still Figure 7 For example, based on the mount path used to transmit the Head being configured as a high priority and the mount path used to transmit the Tail being configured as a low priority for data transmission, data can be transmitted, so that no matter what the delay corresponding to the Head (shown as delay1 in the figure) and the delay corresponding to the Tail (shown as delay2 in the figure) are, the output data can still be output in priority order, thereby ensuring the original order of the data.

[0084] In a further optional example, in the on-chip network, different sub-networks may be connected using a synchronizer, wherein the connection mode of the connection may be an asynchronous connection. For example, the on-chip network includes a first sub-network and a second sub-network, and the first sub-network and the second sub-network may be asynchronously connected. Figure 8 The example diagram of the sub-network connection structure is shown, and the asynchronous connection can be, for example, afifo (Asynchronous First In First Out), so that each sub-network dynamically sets its own voltage frequency according to its specific circumstances (including but not limited to the operating frequency of the IP module, sub-network delay requirements, etc.).

[0085] In a further optional example, an embodiment of the present invention further configures at least one layer among the storage configuration layer, the arbitration control layer and the data link layer with independent clock gating management for controlling the clock switching based on the operating status of the corresponding layer to reduce the power consumption of the on-chip network.

[0086] In a specific example, each layer is configured with independent clock gating management for clock on / off control based on the operating status of each layer. For example, after the arbitration control layer completes an arbitration, the clock of the arbitration control layer can be turned off, and after the data to be transmitted in this arbitration is completed, the clock of the arbitration control layer can be turned on to perform the next arbitration process.

[0087] Alternatively, in another example, when transmission congestion occurs in the data to be transmitted, the storage configuration layer needs to store the data to be transmitted that failed to compete for the transmission path, and when the transmission path of the data to be transmitted is a data transmission path, use the transmission path to transmit the data to be transmitted. Accordingly, the clock of the storage configuration layer can be turned on at this time, and at the same time, the clocks of the arbitration control layer and the data link layer can also be turned off, thereby saving network power consumption to the greatest extent.

[0088] An embodiment of the present invention further provides a data transmission system, which can perform data transmission based on the network-on-chip architecture provided by an embodiment of the present invention.

[0089] An embodiment of the present invention provides a storage medium, wherein the storage medium stores one or more executable instructions, and the one or more executable instructions are used to perform data transmission based on the on-chip network architecture provided by the embodiment of the present invention.

[0090] The above describes multiple implementation schemes provided by the embodiments of the present invention. The various optional methods introduced in the implementation schemes can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present invention.

[0091] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A network-on-chip architecture, characterized in that: include: A storage configuration layer, used to configure a storage device for the on-chip network so that the data to be transmitted is temporarily stored in the storage device during the transmission process, wherein the storage device is a cache corresponding to each node and a shared storage device corresponding to the on-chip network, wherein the data to be transmitted is temporarily stored in the cache of the corresponding node, and the shared storage device stores the data to be transmitted that fails in the competition transmission path, and when the transmission path of the data to be transmitted is a data transmission path, the data to be transmitted is transmitted using the transmission path; The arbitration control layer is used to perform arbitration control on the transmission path of the data to be transmitted, and determine the transmission path connected to the output interface so that the transmission path connected to the output interface is the data transmission path; wherein one node is used to control the transmission path from an input interface to an output interface; The data link layer is used to control the transmission of the data to be transmitted based on the corresponding transmission path; The arbitration control layer is also used to configure priorities for different mount paths to determine the transmission order of different data to be transmitted based on the corresponding priorities of the mount paths, wherein the data to be transmitted of multiple input / output interfaces are transmitted simultaneously; the mount path is used to indicate the mounting relationship between the input interface and the physical bus, and the mounting relationship between the output interface and the physical bus; the priority is determined based on the priority and / or data type of the data to be transmitted in the physical bus, and the priority is used to determine the transmission order of the data to be transmitted.

2. The network-on-chip architecture according to claim 1, characterized in that: The storage configuration layer is further configured to transmit the data to be transmitted based on a first-in-first-out mechanism when the transmission path of the data to be transmitted is a data transmission path.

3. The network-on-chip architecture according to claim 1, characterized in that: The storage configuration layer is also used to configure the cache capacity of each node in the on-chip network, wherein the minimum cache capacity of a node is 0.

4. The network-on-chip architecture according to claim 3, characterized in that: The storage configuration layer is also used to configure the cache capacity of each node in the on-chip network, specifically: the storage configuration layer allocates a row cache corresponding to each row node, and / or the storage configuration layer allocates a column cache corresponding to each column node.

5. The network-on-chip architecture according to claim 1, characterized in that: The arbitration control layer is further used to adjust the bandwidth of the physical channel corresponding to the virtual channel based on the congestion data of each virtual channel.

6. The network-on-chip architecture according to claim 5, characterized in that: The step of adjusting the bandwidth of the physical channel corresponding to the virtual channel based on the congestion data of each virtual channel includes: adjusting the bandwidth of the physical channel corresponding to the virtual channel based on the number of congestion times of each virtual channel in the previous cycle; wherein the virtual channel transmits data based on the adjusted bandwidth in the next cycle.

7. The network-on-chip architecture according to claim 1, characterized in that: The data link layer is also used to provide a data compression strategy so that data is compressed before transmission.

8. The network-on-chip architecture according to claim 7, characterized in that: The data compression strategy includes: Dividing the data to be transmitted into data segments with a preset length, wherein the data to be transmitted includes at least one data segment; Divide the data segments into valid data and invalid data, and provide identification bits corresponding to the data segments; wherein the identification bits corresponding to the data to be transmitted constitute identification data segments, and the arrangement order of the identification bits in the identification data segments is consistent with the arrangement order of the data segments of the data to be transmitted; Based on the indication of the identification data segment, only valid data in the data to be transmitted and the identification data segment corresponding to the data to be transmitted are transmitted.

9. The network-on-chip architecture according to claim 8, characterized in that: The data compression strategy also includes: When all data segments of the data to be transmitted are valid data, the identification data segment is removed and only the data to be transmitted is transmitted.

10. The network-on-chip architecture according to claim 7, characterized in that: The data link layer is also used to provide a data decompression strategy to restore the data to be transmitted.

11. The network-on-chip architecture according to claim 1, characterized in that: An input end is simultaneously allocated with multiple input interfaces, and / or an output end is simultaneously allocated with multiple output interfaces.

12. The network-on-chip architecture according to claim 11, characterized in that: When the input ends of the multiple input interfaces are simultaneously assigned to transmit the data to be transmitted to the output end of the single output interface, the arbitration control layer configures the arbitrator to output the data to be transmitted based on the priority order of the mounting paths.

13. The network-on-chip architecture according to claim 1, characterized in that: At least one of the storage configuration layer, the arbitration control layer and the data link layer is configured with independent clock gating management to perform clock on / off control based on the operating status of the corresponding layer.

14. The network-on-chip architecture according to claim 13, characterized in that: The storage configuration layer, the arbitration control layer and the data link layer are all configured with independent clock gating management; The clock gating management at least includes: After the arbitration control layer completes one arbitration, the clock of the arbitration control layer is turned off, and after the data to be transmitted in this arbitration is completed, the clock of the arbitration control layer is turned on; and / or, When transmission congestion occurs in the data to be transmitted, the storage configuration layer turns on the clock, stores the data to be transmitted that failed in the competition transmission path, and when the transmission path of the data to be transmitted is a data transmission path, uses the transmission path to transmit the data to be transmitted, and at the same time, turns off the clocks of the arbitration control layer and the data link layer.

15. A network on chip, characterized in that: include: An input interface, an output interface, a node located in the network, an arbitrator located between the node and the output interface, and a storage device connected between the input interface and the output interface; wherein the on-chip network is used to construct the on-chip network architecture described in any one of claims 1-14.

16. The network on chip according to claim 15, characterized in that: The storage device comprises a shared storage device for storing data to be transmitted that fails in the competition transmission path.

17. The network on chip according to claim 16, characterized in that: The shared storage device is directly or indirectly connected between the input interface and the output interface, wherein when the shared storage device is indirectly connected between the input interface and the output interface, the shared storage device is connected between the node and the arbitrator.

18. The network on chip according to claim 15, characterized in that: The storage device includes a cache, which is arranged in one or more components of an input interface, an output interface, or a node of the on-chip network.

19. The network on chip according to claim 18, characterized in that: The cache includes a row cache and / or a column cache, wherein a row of nodes corresponds to a row of cache, and / or a column of nodes corresponds to a column of cache.

20. The network on chip according to claim 15, characterized in that: The network on chip comprises at least a first sub-network and a second sub-network, wherein an output interface of the first sub-network is connected to an input interface of the second sub-network, and an input interface of the first sub-network is connected to an output interface of the second sub-network.

21. The network on chip according to claim 20, characterized in that: The first sub-network has a plurality of input interfaces connected to the second sub-network, and the first sub-network has a plurality of output interfaces connected to the second sub-network.

22. The network on chip according to claim 20, characterized in that: The first sub-network and the second sub-network are asynchronously connected.

23. The network on chip according to claim 15, characterized in that: An input end may be assigned with multiple input interfaces at the same time, and an output end may be assigned with multiple output interfaces at the same time.

24. A data transmission system, characterized in that: The data transmission system performs data transmission based on the on-chip network architecture described in any one of claims 1-14.

25. A storage medium, characterized in that: The storage medium stores one or more executable instructions, and the one or more executable instructions are used to perform data transmission based on the on-chip network architecture described in any one of claims 1-14.

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