Pixel circuits, display panels, and display devices

Abstract

This invention provides a pixel circuit, a display panel, and a display device. The pixel circuit includes a first driving circuit, a second driving circuit, and a first capacitor. A first plate of the first capacitor is electrically connected to the output terminal of the first driving circuit, and a second plate of the first capacitor is electrically connected to the second driving circuit. The first driving circuit is configured to generate a control current based on a first data signal, and the second driving circuit is configured to generate a driving current based on a second data signal and control the flow period of the driving current based on the control current. A light-emitting element is electrically connected to the second driving circuit to receive the driving current. This invention can solve the problem of improving the performance stability of pixel circuits.

Description

[0001] This application is a divisional application of Chinese Patent No. 202410372041.7, filed on March 29, 2024, entitled "Pixel Circuit, Display Panel and Display Device". Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a pixel circuit, a display panel, and a display device. Background Technology

[0003] Pixel circuits are incorporated into the display panel to drive light-emitting elements. To achieve more precise adjustment of the grayscale of the light-emitting elements, existing technologies have proposed a pixel circuit that includes pulse width modulation (PWM) and pulse amplitude modulation (PA) circuits. However, the pixel circuits provided by existing technologies still have certain performance issues, which may affect the display effect during application. Summary of the Invention

[0004] This invention provides a pixel circuit, a display panel, and a display device to solve the technical problem of improving the performance of pixel circuits.

[0005] In a first aspect, embodiments of the present invention provide a pixel circuit, the pixel circuit including a first driving circuit, a second driving circuit, and a first capacitor; a first plate of the first capacitor is electrically connected to the output terminal of the first driving circuit, and a second plate of the first capacitor is electrically connected to the second driving circuit; the first driving circuit is configured to generate a control current based on a first data signal, and the second driving circuit is configured to generate a driving current based on a second data signal and control the flow period of the driving current based on the control current; a light-emitting element is electrically connected to the second driving circuit to receive the driving current.

[0006] Secondly, based on the same inventive concept, embodiments of the present invention also provide a display panel, which includes the pixel circuit provided in any embodiment of the present invention.

[0007] Thirdly, based on the same inventive concept, embodiments of the present invention also provide a display device, which includes the display panel provided in any embodiment of the present invention.

[0008] The pixel circuit, display panel, and display device provided in this invention have the following beneficial effects: The output terminal of the first driving circuit and the second driving circuit in the pixel circuit are connected via a first capacitor. The control current provided by the output terminal of the first driving circuit causes a change in the voltage of the first plate of the first capacitor by ΔV, which in turn causes a corresponding change in the voltage of the second plate of the first capacitor by ΔV. Through the coupling effect of the first capacitor, the gate voltage of the controlled transistor in the second driving circuit changes by ΔV, causing the controlled transistor to turn off. The second driving circuit then stops providing driving current to the light-emitting element, thereby achieving control over the flow period of the driving current. There is no direct correlation between the gate voltage of the controlled transistor in the second driving circuit and the control current provided by the first driving circuit, allowing for more precise control over the turning off of the controlled transistor, which is beneficial for improving the performance stability of the pixel circuit. Furthermore, there is no necessary magnitude relationship between the voltage value of the output signal of the first driving circuit and the source voltage of the controlled transistor, reducing the correlation between the signals required for the operation of the first and second driving circuits. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of a pixel circuit in related technologies; Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another pixel circuit in an embodiment of the present invention; Figure 4 A signal timing diagram provided in an embodiment of the present invention; Figure 5 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 6 Another signal timing diagram provided in an embodiment of the present invention; Figure 7 Another signal timing diagram provided in an embodiment of the present invention; Figure 8 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 9 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 10 Another signal timing diagram provided in an embodiment of the present invention; Figure 11 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 12 A schematic diagram of a display panel provided in an embodiment of the present invention; Figure 13 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 14 Another signal timing diagram provided in an embodiment of the present invention; Figure 15 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 16 Another signal timing diagram provided in an embodiment of the present invention; Figure 17 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 18 Another signal timing diagram provided in an embodiment of the present invention; Figure 19 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 20 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 21 Another signal timing diagram provided in an embodiment of the present invention; Figure 22 Another signal timing diagram provided in an embodiment of the present invention; Figure 23 Another signal timing diagram provided in an embodiment of the present invention; Figure 24 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 25 Another signal timing diagram provided in an embodiment of the present invention; Figure 26 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 27 Another signal timing diagram provided in an embodiment of the present invention; Figure 28 Another signal timing diagram provided in an embodiment of the present invention; Figure 29 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 30 Another signal timing diagram provided in an embodiment of the present invention; Figure 31 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 32Another signal timing diagram provided in an embodiment of the present invention; Figure 33 Another signal timing diagram provided in an embodiment of the present invention; Figure 34 Another signal timing diagram provided in an embodiment of the present invention; Figure 35 Another signal timing diagram provided in an embodiment of the present invention; Figure 36 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 37 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 38 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 39 Another signal timing diagram provided in an embodiment of the present invention; Figure 40 A schematic diagram of a display panel circuit is provided for an embodiment of the present invention; Figure 41 Another signal timing diagram provided in an embodiment of the present invention; Figure 42 Another pixel circuit schematic diagram provided for implementation of the present invention; Figure 43 Another pixel circuit schematic diagram provided in an embodiment of the present invention; Figure 44 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0011] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0013] Figure 1 This is a schematic diagram of a pixel circuit in related technologies, such as... Figure 1As shown, the pixel circuit includes a pulse width modulation (PWM) circuit 01 and a pulse amplitude modulation (PAM) circuit 02. The PWM circuit 01 is configured to control the pulse width of the driving current supplied to the light-emitting element (LD) based on the PWM data voltage. The PAM circuit 02 is configured to control the amplitude of the driving current supplied to the LD based on the PAM data voltage. Here, the pulse width of the driving current is understood as the duration of the driving current, and the amplitude of the driving current is understood as the magnitude of the driving current. In related technologies, the output terminal of the PWM circuit 01 is connected to the gate of a transistor 021 in the PAM circuit 02. The output signal of the PWM circuit 01 is directly written to the gate of the transistor 021 to control the change in the gate potential of the transistor 021, thereby turning off the transistor 021 to achieve modulation of the pulse width of the driving current. In this method, the voltage value of the gate of the transistor 021 is directly related to the voltage value of the output signal of the PWM circuit 01, resulting in certain performance issues in the pixel circuit, which may affect the display effect in applications. Furthermore, the voltage value of the output signal of the pulse width modulation circuit 01 needs to have a certain magnitude relationship with the source voltage of transistor 021 in order to control the transistor 021 to turn off.

[0014] Figure 2 A pixel circuit schematic diagram provided for an embodiment of the present invention, such as... Figure 2As shown, the pixel circuit includes a first driving circuit 10, a second driving circuit 20, and a first capacitor C1. The first driving circuit 10 is a PWM (Pulse Width Modulation) circuit, and the second driving circuit 20 is a PAM (Pulse Amplitude Modulation) circuit. The pixel circuit generates a driving current under the control of the pulse amplitude modulation circuit 20 and the pulse width modulation circuit 10. The pulse amplitude modulation circuit 20 can be used to control the amplitude of the driving current, and the pulse width modulation circuit 10 can be used to adjust the pulse width of the voltage applied to the first electrode of the light-emitting element LD. The pulse width modulation circuit 10 adjusts the actual emission period of the driving current applied to the light-emitting element LD by adjusting the pulse width of the voltage applied to the first electrode of the light-emitting element LD; at the same time, it can maintain the driving current applied to the light-emitting element LD at a constant level to adjust the grayscale or brightness of the light-emitting element LD, rather than adjusting the grayscale or brightness of the light-emitting element by adjusting the magnitude of the driving current applied to the light-emitting element LD. Therefore, the pulse amplitude modulation circuit 20 can provide driving current to the light-emitting element so that the light-emitting element is driven with optimal luminous efficiency, and adjust the luminous duty cycle (i.e., the emission period of the light-emitting element) of the light-emitting element through the pulse width modulation circuit 10 to adjust the grayscale or brightness of the light-emitting element. The first plate of the first capacitor C1 is electrically connected to the output terminal of the first driving circuit 10, and the second plate of the first capacitor C1 is electrically connected to the second driving circuit 20. Figure 2 The diagram illustrates a controlled transistor 201 in the second driving circuit 20, with the second plate of the first capacitor C1 connected to the gate of the controlled transistor 201. The controlled transistor 201 can be a driving transistor in the second driving circuit 20 that generates driving current, or it can be a transistor in the second driving circuit 20 connected in series with the driving transistor.

[0015] In this circuit, the first driving circuit 10 is configured to generate a control current based on a first data signal PWM-Data, and the second driving circuit 20 is configured to generate a driving current based on a second data signal PAM-Data and control the flow period of the driving current based on the control current. The flow period is also known as the pulse width of the driving current, or the duration of providing the driving current. The light-emitting element LD is electrically connected to the second driving circuit 20 to receive the driving current. The light-emitting element LD can be a light-emitting diode (LED), such as a mini LED or micro LED.

[0016] In this embodiment of the invention, the output terminal of the first driving circuit 10 and the second driving circuit 20 are connected via a first capacitor C1. The control current provided by the output terminal of the first driving circuit 10 causes a change of ΔV in the voltage of the first plate of the first capacitor C1, and the voltage of the second plate of the first capacitor C1 also changes by ΔV accordingly. Through the coupling effect of the first capacitor C1, the gate voltage of the controlled transistor 201 in the second driving circuit 20 changes by ΔV, causing the controlled transistor 201 to turn off. The second driving circuit 20 then stops providing driving current to the light-emitting element LD, thereby achieving control over the flow period of the driving current. There is no direct correlation between the gate voltage of the controlled transistor 201 in the second driving circuit 20 and the control current provided by the first driving circuit 10, allowing for more precise control over the turning off of the controlled transistor 201, which is beneficial for improving the performance stability of the pixel circuit. Moreover, there is no necessary magnitude relationship between the voltage value of the output signal of the first driving circuit 10 and the source voltage of the controlled transistor 201, which reduces the correlation between the signals required for the operation of the first driving circuit 10 and the second driving circuit 20.

[0017] In addition, when Figure 1 When transistor 021 is the driving transistor in pulse amplitude modulation circuit 02, the output signal of pulse width modulation circuit 01 is directly given to the gate of the driving transistor in pulse amplitude modulation circuit 02 to control the driving transistor to turn off. Writing the output signal of pulse width modulation circuit 01 to the gate of the driving transistor causes partial damage to the gate's threshold compensation information. In applications, this can lead to differences in the driving characteristics of pixel circuits at different locations on the display panel, thus affecting the display effect. Especially in low grayscale displays, the threshold difference of the first driving transistor M7 at different locations on the display panel will be displayed, causing problems with display uniformity.

[0018] In the scheme of this embodiment of the invention, when the first driving circuit 10 controls the driving transistor in the second driving circuit 20 through the first capacitor C1, the output signal of the first driving circuit 10 causes the potential of the first plate of the first capacitor C1 to change by ΔV. Due to the coupling effect of the first capacitor C1, the potential of the gate of the driving transistor in the second driving circuit 20 changes from V... PAM - Data -|Vth| changes to V PAM - Data -|Vth|+△V. V PAM - DataVth is the data voltage written into the second driving circuit 20, and Vth is the threshold voltage of the driving transistor. When the output signal of the first driving circuit 10 controls the driving transistor in the second driving circuit 20 to be turned off, the threshold compensation information in the gate of the driving transistor is protected. In applications, this can improve the display effect of low grayscale and eliminate the display unevenness caused by the difference in threshold voltage of the driving transistors in different second driving circuits 20.

[0019] In some implementations... Figure 3 This is a schematic diagram of another pixel circuit in an embodiment of the present invention. Figure 4 A signal timing diagram provided in an embodiment of the present invention. Figure 4 The provided signal timing can be used for driving Figure 3 The pixel circuit in the embodiment.

[0020] like Figure 3 As shown, the first driving circuit 10 includes a second driving transistor M1, a first gate reset transistor M2, a first data write transistor M3, a first compensation transistor M4, a first control transistor M6, a third control transistor M5, and a third capacitor C3. The third capacitor C3 is the storage capacitor in the first driving circuit 10, and can also be referred to as the first storage capacitor in the pixel circuit. The third control transistor M5 is connected between the second power supply voltage line PWM-Vdd and the first terminal of the second driving transistor M1. The first control transistor M6 is connected between the second terminal of the second driving transistor M1 and the output terminal OUT of the first driving circuit 10. The first data write transistor M3 is connected to the first terminal of the second driving transistor M1. The first compensation transistor M4 is connected to the second terminal and the gate of the second driving transistor M1. The first gate reset transistor M2 is connected to the gate of the second driving transistor M1. The first plate of the third capacitor C3 is connected to the gate of the second driving transistor M1, and the second plate of the third capacitor C3 is connected to the sweep frequency signal terminal SWEEP. The gate of the first gate reset transistor M2 receives the third scan signal PWM-S1, and the gates of the first data write transistor M3 and the first compensation transistor M4 receive the fourth scan signal PWM-S2. The gates of the first control transistor M6 and the third control transistor M5 receive the first light-emitting control signal PWM-EM. The first control transistor M6 and the third control transistor M5 constitute the first light-emitting control module 101 in the first driving circuit 10.

[0021] In some embodiments, the first driving circuit 10 includes a second driving transistor M1, a first gate reset transistor M2, a first data write transistor M3, a first control transistor M6, a third control transistor M5, and a third capacitor C3. The third control transistor M5 is connected between the second power supply voltage line PWM-vdd and the first terminal of the second driving transistor M1. The first control transistor M6 is connected between the second terminal of the second driving transistor M1 and the output terminal OUT of the first driving circuit 10. The first data write transistor M3 is connected to the first terminal of the second driving transistor M1, and the first gate reset transistor M2 is connected to the gate of the second driving transistor M1. The first plate of the third capacitor C3 is connected to the gate of the second driving transistor M1, and the second plate of the third capacitor C3 is connected to the sweep frequency signal terminal SWEEP. The gate of the first gate reset transistor M2 receives the third scan signal PWM-S1, and the gates of the first data write transistor M3 and the first compensation transistor M4 receive the fourth scan signal PWM-S2. The gates of the first control transistor M6 and the third control transistor M5 receive the first light emission control signal PWM-EM. Compared to the aforementioned embodiments, the first driving circuit 10 may also omit the first compensation transistor M6.

[0022] The second driving circuit 20 includes a first driving transistor M7, a second gate reset transistor M8, a second data write transistor M9, a second compensation transistor M10, a second control transistor M11, a fourth control transistor M12, and an electrode reset transistor M13. The second control transistor M11 is connected between the first power supply voltage line PAM-vdd and the first electrode of the first driving transistor M7, and the fourth control transistor M12 is connected between the second electrode of the first driving transistor M7 and the light-emitting element LD. The first driving transistor M7 is configured to generate a driving current under the control of its gate voltage. The second data write transistor M9 is connected to the first electrode of the first driving transistor M7, the second compensation transistor M10 is connected to the second electrode and gate of the first driving transistor M7, the second gate reset transistor M8 is connected to the gate of the first driving transistor M7, the electrode reset transistor M13 is connected to the first electrode of the light-emitting element LD, the fourth control transistor M12 is also connected to the first electrode of the light-emitting element LD, and the second electrode of the light-emitting element LD is connected to the third power supply voltage line PVEE. In this circuit, the gate of the second gate reset transistor M8 receives the first scan signal PAM-S1; the gates of the second data write transistor M9, the second compensation transistor M10, and the electrode reset transistor M13 receive the second scan signal PAM-S2. The gates of the second control transistor M11 and the fourth control transistor M12 receive the second light emission control signal PAM-EM. The second control transistor M11 and the fourth control transistor M12 constitute the second light emission control module 201 in the second driving circuit 20.

[0023] In other embodiments, the second driving circuit 20 includes a first driving transistor M7, a second gate reset transistor M8, a second data write transistor M9, a second control transistor M11, a fourth control transistor M12, and an electrode reset transistor M13. Compared to the aforementioned embodiments, the second driving circuit 20 may also omit the second compensation transistor M6.

[0024] Figure 3 The diagram illustrates that the first terminal of the electrode reset transistor M13 is connected to the third power supply voltage line PVEE. In other embodiments, the first terminal of the electrode reset transistor M13 receives a second reset signal PAM-REF, meaning the first terminal of the electrode reset transistor M13 and the first terminal of the second gate reset transistor M8 receive the same signal. In still other embodiments, the first terminal of the electrode reset transistor M13 is not connected to the third power supply voltage line PVEE, and the first terminal of the electrode reset transistor M13 and the first terminal of the second gate reset transistor M8 receive different signals; these are not illustrated in the diagrams below.

[0025] Figure 3 The diagram shows that the first plate of the first capacitor C1 is connected to the first control transistor M6 in the first driving circuit 10, and the second plate of the first capacitor C1 is connected to the gate of the first driving transistor M7 in the second driving circuit 20.

[0026] Figure 3 The diagram illustrates that each transistor in the pixel circuit is a p-type transistor. The transistor's gate receives a low-level signal as an enable signal, which controls the transistor to be in the on state. Combined with... Figure 4 The operation of the pixel circuit includes a first input stage t1, a second input stage t2, and a light emission stage t3.

[0027] In the first input stage t1, the second driving circuit 20 sequentially executes the gate reset stage t11 and the data writing stage t12. In the gate reset stage t11, the first scan signal PAM-S1, at an enable level, controls the second gate reset transistor M8 to turn on, writing the second reset signal PAM-REF to the gate of the first driving transistor M7, thus resetting the gate of the first driving transistor M7. In the data writing stage t12, the second scan signal PAM-S2, at an enable level, controls the second data writing transistor M9 and the second compensation transistor M10 to turn on, writing the second data signal PAM-Data to the gate of the first driving transistor M7 and performing threshold compensation; during this stage, the electrode reset transistor M13 turns on to reset the electrodes of the light-emitting element LD.

[0028] In the second input stage t2, the first driving circuit 10 sequentially executes the gate reset stage t21 and the data writing stage t22. In the gate reset stage t21, the third scan signal PWM-S1, at its enable level, controls the first gate reset transistor M2 to turn on, and writes the third reset signal PWM-REF to the gate of the second driving transistor M1, thus resetting the gate of the second driving transistor M1. In the data writing stage t22, the fourth scan signal PWM-S2, at its enable level, controls the first data writing transistor M3 and the first compensation transistor M4 to turn on, writing the first data signal PWM-Data to the gate of the second driving transistor M1 and performing threshold compensation.

[0029] The light-emitting stage t3 is not the effective light-emitting stage of the light-emitting element LD. The light-emitting stage includes the effective light-emitting period of the light-emitting element LD and a portion of the non-light-emitting period of the light-emitting element LD. The light-emitting stage t3 can be understood as the stage in which the second light-emitting control signal PAM-EM and the first light-emitting control signal PWM-EM are at the enable level. In the light-emitting stage t3, the second light-emitting control signal PAM-EM controls the second control transistor M11 and the fourth control transistor M12 to turn on. The first driving transistor M7 generates a driving current under the control of its gate voltage, and the second driving circuit 20 provides a driving current to the light-emitting element LD. The first light-emitting control signal PWM-EM controls the first control transistor M6 and the third control transistor M5 to turn on. At the same time, the voltage value of the sweep frequency signal SWEEP (which uses the same marking as the sweep frequency signal terminal SWEEP) gradually changes, and the voltage of the gate of the second driving transistor M1 changes due to the coupling effect of the third capacitor C3. When the gate voltage of the second driving transistor M1 is equal to (or less than) the absolute difference between its source voltage and threshold voltage, the second driving transistor M1 turns on. The potential of the first plate of the first capacitor C1 is gradually raised. Finally, the second driving transistor M1 turns on and supplies the second power supply voltage PWM-Vdd (marked the same as the second power supply voltage line) to the first plate of the first capacitor C1 via the first control transistor M6, causing a change in the voltage of the first plate of the first capacitor C1. This voltage change on the first plate involves charge accumulation, which is equivalent to providing a control current to the first plate of the first capacitor C1. This, in turn, causes a change in the gate voltage of the first driving transistor M7 through the coupling effect of the first capacitor C1, causing the first driving transistor M7 to turn off, thus stopping the supply of driving current to the light-emitting element LD. During the light-emitting stage t3, a control current is generated based on the first data voltage PWM-Vdata and the sweep frequency signal SWEEP in the first driving circuit 10 to control the duration of the driving current provided by the second driving circuit 20, thereby adjusting the effective light-emitting duration of the light-emitting element LD and thus controlling the brightness and grayscale of the light-emitting element LD.

[0030] It should be noted that, to simplify the labeling method, in this embodiment of the invention, the signal line and the signal provided by the signal line are labeled with the same label, and the signal terminal and the signal provided by the signal terminal are also labeled with the same label. For example, the sweep frequency signal and the sweep frequency signal terminal are both labeled SWEEP, and the second power supply voltage line and the second power supply voltage are both labeled PWM-vdd. In this embodiment of the invention, the third control transistor M5 of the pixel circuit is connected to the second power supply voltage line PWM-vdd, which can also be understood as the first terminal of the third control transistor M5 receiving the second power supply voltage signal PWM-vdd. The labeling issues involved in the following embodiments will not be listed and explained one by one, and can all be understood by referring to the description here.

[0031] In one related technology, the output terminal of the first driving circuit 10 is directly connected to the gate of the first driving transistor M7 in the second driving circuit 20, so the signal output from the first driving circuit 10 is directly written to the gate of the first driving transistor M7. For example, after data writing and threshold compensation, the gate voltage of the first driving transistor M7 is V. PAM-Data -|Vth|,V PAM-Data Vth represents the voltage value of the second data signal PAM-Data, and Vth represents the threshold voltage of the first driving transistor M7. When the second driving transistor M1 in the first driving circuit 10 is turned on, the potential of the first plate of the first capacitor C1 is gradually raised. Finally, the first driving circuit 10 writes the second power supply voltage PWM-vdd to the gate of the first driving transistor M7, causing a change in the gate voltage. At this time, the threshold compensation information |Vth| in the gate voltage of the first driving transistor M7 is overwritten by the second power supply voltage PWM-vdd. When applied to a display panel, due to process limitations during manufacturing, the characteristics of the first driving transistor M7 at different locations will vary. When the threshold compensation information of the first driving transistor M7 is overwritten, it leads to differences in the driving characteristics of the pixel circuits at different locations on the display panel, which will affect the display effect. Especially in low grayscale display, the threshold difference of the first driving transistor M7 at different locations on the display panel will be displayed, causing problems with display uniformity.

[0032] In this embodiment of the invention, the first driving circuit 10 is connected to the first driving transistor M7 in the second driving circuit 20 via a first capacitor C1. The control current provided by the first driving circuit 10, through the coupling effect of the first capacitor C1, causes a change in the gate voltage of the first driving transistor M7, thereby controlling the first driving transistor M7 to turn off, thus achieving control over the flow period of the driving current. When the voltage on the first plate of the first capacitor C1 changes by ΔV, the gate voltage of the first driving transistor M7 also changes by ΔV. For the first driving transistor M7, after experiencing the first input stage t1, the gate voltage of the first driving transistor M7 is V. PAM-Data-|Vth|. During the light-emitting stage t3, due to the coupling effect of the first capacitor C1, the gate voltage of the first driving transistor M7 changes to V. PAM-Data -|Vth|+△V, threshold compensation information is retained in the gate voltage of the first driving transistor M7. When applied to display panels, this can improve display quality, especially enhancing the display effect of low grayscale displays.

[0033] Furthermore, in this embodiment, the voltage value of the output signal of the first driving circuit 10 and the source voltage of the first driving transistor M7 are not necessarily related in magnitude. Therefore, there may be no magnitude relationship between the second power supply voltage PWM-vdd and the first power supply voltage PAM-vdd. Consequently, the original voltage supplying power to the first power supply voltage line PAM-vdd and the second power supply voltage line PWM-vdd can be the same. This reduces the number of pins in the display panel and also helps improve the uniformity of the power supply voltage signal in the display panel. Of course, in some embodiments, when the number of pins is not considered, the original voltage supplying power to the first power supply voltage line PAM-vdd and the second power supply voltage line PWM-vdd can also be different.

[0034] Figure 5 Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 5 As shown, the first driving circuit 10 is in Figure 3 The schematic structure also includes a fifth transistor T5, where the first terminal of the fifth transistor T5 is grounded (connected to GND), and the second terminal of the fifth transistor T5 is connected to the second plate of the third capacitor C3. The gate of the fifth transistor T5 receives the fourth scan signal PWM-S2. Combined with... Figure 4 During the data writing phase of the first driving circuit 10, the fourth scan signal PWM-S2 provides an enable signal to control the fifth transistor T5 to turn on.

[0035] in addition, Figure 3 and Figure 5 In this embodiment, each transistor is illustrated as a p-type transistor. In other embodiments, each transistor in the pixel circuit is an n-type transistor, which will not be illustrated in the accompanying drawings.

[0036] In some embodiments, at least one of the first gate reset transistor M2 and the first compensation transistor M4 is an n-type transistor, at least one of the second gate reset transistor M8 and the second compensation transistor M10 is an n-type transistor, and the remaining transistors are p-type transistors, which are not illustrated in the accompanying drawings. It can be understood that when the first compensation transistor M4 is an n-type transistor and the first data write transistor M3 is a p-type transistor, they are controlled by different control signals. Similarly, when the second compensation transistor M10 is an n-type transistor and the second data write transistor M9 is a p-type transistor, they are controlled by different control signals.

[0037] In some embodiments, the active layer of the transistor in the pixel circuit can be formed of any of polycrystalline silicon, amorphous silicon, and oxide semiconductor. When the active layer of the transistor is formed of polycrystalline silicon, it can be formed using a low-temperature polycrystalline silicon (LTPS) process. A transistor with an active layer of oxide semiconductor is an oxide transistor, which exhibits relatively lower leakage current compared to silicon transistors. Using oxide semiconductor for part of the transistor's active layer can effectively reduce flicker in the display panel. Optionally, at least one of the first gate reset transistor M2 and the first compensation transistor M4 is an oxide transistor, and at least one of the second gate reset transistor M8 and the second compensation transistor M10 is an oxide transistor.

[0038] In some implementations, the first light emission control signal PWM-EM and the second light emission control signal PAM-EM can be set to the same signal. In the operation of the pixel circuit, the first light emission control module 101 in the first driving circuit 10 and the second light emission control module 201 in the second driving circuit 20 are simultaneously turned on.

[0039] In some implementations, the first light emission control signal PWM-EM and the second light emission control signal PAM-EM are different signals, and their enable levels can be set to have different start and / or end times. For example... Figure 4 As shown, the start time of the first light-emitting control signal PWM-EM as the enable signal is earlier than the start time of the second light-emitting control signal PAM-EM as the enable signal. The end time of the first light-emitting control signal PWM-EM as the enable signal is later than the end time of the second light-emitting control signal PAM-EM as the enable signal. Setting the start time of the first light-emitting control signal PWM-EM as earlier than the start time of the second light-emitting control signal PAM-EM as the enable signal reduces the possibility of the first driving circuit 10 delaying the supply of control current to the second driving circuit 20, thereby preventing the phenomenon of the light-emitting element LD lighting up unexpectedly when the display is in a dark state.

[0040] This invention also provides another timing diagram that can be used to drive Figure 3 The pixel circuit provided in the embodiment, Figure 6 Another signal timing diagram provided for an embodiment of the present invention, such as Figure 6 As shown, the operation of the pixel circuit includes a first input stage t1, a second input stage t2, and a light-emitting stage t3. The first input stage t1 corresponding to the second driving circuit 20 and the second input stage t2 corresponding to the first driving circuit 10 at least partially overlap.

[0041] In some implementations, such as Figure 4 As shown, at least during the second input phase t2, when the fourth scan signal PWM-S2 provides the enable signal, the sweep signal SWEEP is at a low level. After the enable signal period of the fourth scan signal PWM-S2 ends, the sweep signal SWEEP changes from low to high, with a voltage change of ΔV. SWEEP Then, during the light-emitting stage t3, the sweep signal SWEEP gradually changes from high to low. Since the sweep signal line SWEEP is connected to the gate of the second driving transistor M1 through the third capacitor C3, when the sweep signal SWEEP jumps from low to high, it will raise the gate potential of the second driving transistor M1. After the first data signal PWM-Data is written and threshold compensation is performed, the voltage of the gate of the second driving transistor M1 increases by ΔV. SWEEP With the target gate voltage of the second driving transistor M1 fixed, the sweep frequency signal SWEEP uses... Figure 4 The illustrated timing can reduce the voltage value of the first data signal PWM-Data. Correspondingly, the voltage value of the first data signal PWM-Data can be set to a relatively large range. When the voltage value of the first data signal PWM-Data is fixed, after data writing, the signal transition of the sweep signal SWEEP will raise the gate voltage of the second driving transistor M1. When the rate of change of the sweep signal SWEEP level is fixed, it takes longer for the gate of the second driving transistor M1 to fall to the turn-on condition. That is, the off time of the second driving transistor M1 in the light-emitting stage t3 becomes longer, and correspondingly, the duration for which the second driving circuit 20 provides driving current becomes longer. In this embodiment, the waveform design of the sweep signal SWEEP can improve the degree of freedom in controlling the flow period of the driving current.

[0042] In other implementations, Figure 7 Another signal timing diagram provided for an embodiment of the present invention, such as Figure 7 As shown, during the initial period of the second input stage t2 and the light emission stage t3, the sweep frequency signal SWEEP is at a high level. During the light emission stage t3, the sweep frequency signal SWEEP gradually changes from a high level to a low level, and the voltage change is ΔV. SWEEP .

[0043] In some implementations... Figure 8Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 8 As shown, the second driving circuit 20 also includes a second storage capacitor Cst, which is the second storage capacitor in the pixel circuit. One plate of the second storage capacitor Cst is connected to the first power supply voltage line PAM-vdd, and the other plate is connected to the gate of the first driving transistor M7.

[0044] In some implementations, the output of the first driving circuit 10 is connected to the light emission duration control transistor in the second driving circuit 20 via a first capacitor C1. Figure 9 This is another pixel circuit schematic diagram provided in an embodiment of the present invention. Figure 9 The transistors in the first driving circuit 10 and the second driving circuit 20 can be referred to Figure 3 The examples are used for understanding. Figure 9 As shown, the second driving circuit 20 includes a storage capacitor Cst, one plate of which is connected to the first power supply voltage line PAM-vdd, and the other plate is connected to the gate of the first driving transistor M7. The second driving circuit 20 also includes a light-emitting duration control transistor M14, which is connected in series between the first power supply voltage terminal (i.e., the signal terminal in the second driving circuit 20 connected to the first power supply voltage line PAM-vdd) and the third power supply voltage line PVEE. The light-emitting duration control transistor M14 is electrically connected between the first driving transistor M7 and the light-emitting element LD. The second plate of the first capacitor C1 is electrically connected to the gate of the light-emitting duration control transistor M14. In this embodiment, the driving current generated by the first driving transistor M7 can only be provided to the light-emitting element LD when the light-emitting duration control transistor M14 is in the on state.

[0045] Figure 10 This is another signal timing diagram provided in an embodiment of the present invention. Figure 9 The pixel circuit provided in the embodiment can also be used Figure 10 The signal timing is used for driving. For example... Figure 10As shown, during the light-emitting stage t3, the second light-emitting control signal PAM-EM controls the second control transistor M11 and the fourth control transistor M12 to turn on. The first driving transistor M7 generates a driving current under the control of its gate voltage. At the same time, the light-emitting duration control transistor M14 is turned on, so the second driving circuit 20 provides a driving current to the light-emitting element LD. The first light-emitting control signal PWM-EM controls the first control transistor M6 and the third control transistor M5 to turn on. At the same time, the voltage value of the sweep frequency signal SWEEP gradually changes. Due to the coupling effect of the third capacitor C3, the voltage of the gate of the second driving transistor M1 changes. When the gate voltage of the second driving transistor M1 is equal to (or less than) the difference between the absolute value of the source voltage and the threshold voltage of the second driving transistor M1, the second driving transistor M1 turns on. The potential of the first plate of the first capacitor C1 is gradually raised. Finally, the second power supply voltage PWM-vdd is supplied to the first plate of the first capacitor C1 through the first control transistor M6, causing the voltage of the first plate of the first capacitor C1 to change. The voltage change on the first plate will result in a charge accumulation process, which is equivalent to providing a control current to the first plate of the first capacitor C1. Then, through the coupling effect of the first capacitor C1, the gate voltage of the light emission duration control transistor M14 changes, causing the light emission duration control transistor M14 to turn off, thereby stopping the supply of driving current to the light-emitting element LD. During the light emission stage t3, a control current is generated based on the control of the first data voltage PWM-Vdata and the sweep frequency signal SWEEP in the first driving circuit 10 to control the time when the second driving circuit 20 provides driving current, thereby adjusting the effective light emission duration of the light-emitting element LD, and thus controlling the light emission brightness and grayscale of the light-emitting element LD.

[0046] In this embodiment of the invention, the first driving circuit 10 is connected to the light-emitting duration control transistor M14 in the second driving circuit 20 via a first capacitor C1. When the output signal of the first driving circuit 10 controls the voltage change ΔV on the first plate of the first capacitor C1 (i.e., the difference between the voltage value on the first plate after the output signal of the first driving circuit 10 is written onto the first plate and the original voltage value on the first plate), the gate voltage of the light-emitting duration control transistor M14 also changes ΔV due to the coupling effect of the first capacitor C1. When the voltage difference between the gate voltage and the source voltage of the light-emitting duration control transistor M14 is equal to (or less than) the absolute value of its threshold voltage, the light-emitting duration control transistor M14 is turned off. The path between the first driving transistor M7 and the light-emitting element LD is then cut off, and the second driving circuit 20 stops providing driving current to the light-emitting element LD, thereby achieving control over the duration of driving current flow. Since there is no direct correlation between the gate voltage of the light-emitting duration control transistor M14 and the control current provided by the first driving circuit 10, the turning off of the light-emitting duration control transistor M14 can be controlled more precisely, which is beneficial to improving the performance stability of the pixel circuit. Furthermore, there is no necessary relationship between the voltage value of the output signal of the first driving circuit 10 and the source voltage of the light emission duration control transistor M14, which can reduce the correlation between the signals required for the operation of the first driving circuit 10 and the second driving circuit 20.

[0047] like Figure 9 As shown, the second driving circuit 20 also includes a light-emitting reset circuit 21. The light-emitting reset circuit 21 is connected between the first reset signal line Vset and the gate of the light-emitting duration control transistor M14. The light-emitting reset circuit 21 is configured to reset the gate of the light-emitting duration control transistor M14 using the first reset signal Vset provided by the first reset signal line Vset. The control terminal of the light-emitting reset circuit 21 is connected to the reset control line SET, which provides the reset control signal SET. Figure 10 As shown, before the light-emitting stage t3, the reset control line SET provides an enable signal to control the light-emitting reset circuit 21 to turn on, so that the first reset signal Vset resets the gate of the light-emitting duration control transistor M14.

[0048] like Figure 9As shown, the light-emitting reset circuit 21 includes a light-emitting reset transistor M15. The gate of the light-emitting reset transistor M15 is connected to the reset control line SET. The first terminal of the light-emitting reset transistor M15 is connected to the first reset signal line Vset. The second terminal of the light-emitting reset transistor M15 is connected to the gate of the light-emitting duration control transistor M14. The light-emitting reset circuit 21 also includes a stabilizing capacitor C0. The stabilizing capacitor C0 is used to stabilize the potential of the gate of the light-emitting duration control transistor M14. One plate of the stabilizing capacitor C0 is connected to the first reset signal line Vset, and the other plate is connected to the gate of the light-emitting duration control transistor M14.

[0049] In some implementations... Figure 11 Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 11 As shown, the first plate of the first capacitor C1 and the output terminal of the first driving circuit 10 are electrically connected to the first node N1. The pixel circuit also includes a second capacitor C2 electrically connected to the first node N1, with the first plate of the first capacitor C1 and the first plate of the second capacitor C2 electrically connected. The second capacitor C2 is used at least to stabilize the potential of the first node N1 during the floating potential period. The floating potential period refers to the period when no active signal is written at that node. During the floating potential period, the potential of the first node N1 is easily affected by other signals and fluctuates. The second capacitor C2 can stabilize the potential of the first node N1, ensuring stable operation of the pixel circuit. Optionally, the first capacitor C1 and the second capacitor C2 share a single plate.

[0050] Combination Figure 4 As shown in the schematic timing diagram, during the light-emitting stage t3, as the voltage value of the sweep frequency signal SWEEP gradually changes, the gate voltage of the second driving transistor M1 is pulled low. When the voltage difference between the gate and source of the second driving transistor M1 is equal to (or less than) the absolute value of its threshold voltage, the second driving transistor M1 is turned on, and the potential of the first node N1 is gradually raised. Finally, the first driving circuit 10 writes the second power supply voltage PWM-Vdd to the first node N1. Figure 4 The time marked t3′ is the critical moment and the moment when the first driving circuit 10 switches from off to on. From this moment, the first driving circuit 10 begins to provide control current. At this time, the potential of the first plate of the first capacitor (i.e., the output terminal of the first driving circuit 20) is gradually raised until the gate potential of the first driving transistor M7 is coupled up to a certain value, causing the first driving transistor M7 to turn off. That is to say, before time t3′, the first node N1 is in a floating potential state. The time when the first node N1 is in a floating potential state includes at least the gate reset stage t11 of the second driving circuit 20, the data writing stage t12, and the stage when the second driving circuit 20 generates driving current.

[0051] It should be noted that the process of the gate potential of the first driving transistor M7 being coupled up until it reaches a certain value and completely turns off requires a certain amount of time and cannot be completed instantaneously. Before the first driving transistor M7 is completely turned off, the second driving circuit 20 provides driving current to the light-emitting element LD to control its light emission. The time from the initial coupling up of the gate potential of the first driving transistor M7 to its complete turn-off accounts for a very small proportion of the light-emitting stage t3, and this time is also very short compared to the actual light-emitting period of the light-emitting element LD. Figure 4 The diagram only simplifies the illustration to show time t3′, which is the moment when the second driving transistor M1 is turned on, the moment when the first driving circuit 10 starts to provide control current to the first capacitor C1, and the moment when the first driving transistor M7 is completely turned off (that is, the moment when the second driving circuit 20 stops providing driving current to the light-emitting element LD). Time t3′′ is the moment when the second driving circuit 20 switches from providing driving current to not providing driving current.

[0052] During the gate reset stage t11 of the second driving circuit 20, the second gate reset transistor M8 turns on to reset the gate of the first driving transistor M7. During this stage, the second capacitor C2 stabilizes the potential of the first node N1, preventing potential fluctuations in the first node N1 from affecting the gate reset of the first driving transistor M7.

[0053] During the data writing stage t12 of the second driving circuit 20, the second data writing transistor M9 and the second compensation transistor M10 are turned on, writing the second data signal PAM-Data to the gate of the first driving transistor M7 and performing threshold compensation. During this stage, the second capacitor C2 is used to stabilize the potential of the first node N1, while the first capacitor C1 acts as a storage capacitor, ensuring that the second data signal PAM-Data is accurately written to the gate of the first driving transistor M7.

[0054] During the light-emitting stage t3: The period t31, between the initial moment when the second light-emitting control signal PAM-EM provides the enable signal and the moment t3′′, is the period during which the second driving circuit 20 provides the driving current, which is also the actual light-emitting period of the light-emitting element LD. The moment t3′ is when the first driving circuit 10 begins to provide the control current. The moment t3′ is before the moment t3′′, and before the moment t3′, the first node N1 is in a floating potential state. The grayscale displayed by the light-emitting element LD when it emits light is related to the length of the t31 period and the voltage magnitude of the second data signal PAM-Data. The t31 period covers the moment t3′, and the time interval between the moments t3′ and t3′′ is relatively short. This means that the actual light-emitting time before the moment t3′ occupies most of the actual light-emitting period t31. In this embodiment of the invention, before the moment t3′, the second capacitor C2 is used to stabilize the potential of the first node N1, thereby stabilizing the gate voltage of the first driving transistor M7. This allows the second driving circuit 20 to stably provide the driving current, ensuring the accuracy of the grayscale display by the light-emitting element LD.

[0055] In some embodiments, the second capacitor C2 is used at least to stabilize the potential of the first node N1 when the first control transistor M6 is on (i.e., in the open state) and the second drive transistor M1 is off (i.e., in the closed state). Combined with... Figure 11 As shown, the first control transistor M6 is connected to the first node N1. During the period when the first control transistor M6 is on and the second driving transistor M1 is off, since the second driving transistor M1 is off, even if the first control transistor M6 is on, no signal is written to the first node N1. Therefore, during this period, the first node N1 is in a floating potential state. Combined with... Figure 4 In the light-emitting phase t3: time t3′ is the moment when the first driving circuit 10 switches from cutoff to on. During the period when the second light-emitting control signal PAM-EM provides the enable signal, the first control transistor M6 is in the on state. Therefore, time period t32 is the period when the first control transistor M6 is on and the second driving transistor M1 is off. Since the start time of the first light-emitting control signal PWM-EM as the enable signal is no later than the start time of the enable signal in the second light-emitting control signal PAM-EM, time period t32 covers the actual light-emitting period t31 of the light-emitting element LD. At least during time period t32, the potential of the first node N1 is stabilized by the second capacitor C2, thereby stabilizing the gate voltage of the first driving transistor M7, so that the second driving circuit 20 can stably provide the driving current, ensuring the accuracy of the grayscale display of the light-emitting element LD.

[0056] In some implementations, such as Figure 11As shown, the first plate of the second capacitor C2 is electrically connected to the first node N1, and the second plate of the second capacitor C2 is connected to the first constant voltage signal line VH1. The first constant voltage signal line VH1 provides a constant voltage signal, thereby enabling the second capacitor C2 to stabilize the potential of the first node N1.

[0057] The constant voltage signal can be, for example, one of the following: the second power supply voltage PWM-vdd, the first power supply voltage PAM-vdd, the third reset signal PWM-REF, the second reset signal PAM-REF, or the third power supply voltage PVEE (provided by the third power supply voltage line PVEE).

[0058] In some embodiments, the first plate of the second capacitor C2 is electrically connected to the first node N1, and the second plate of the second capacitor C2 is electrically connected to the first power supply voltage line PAM-vdd. The first power supply voltage line PAM-vdd is multiplexed as the first constant voltage signal line VH1. That is, the second plate of the second capacitor C2 is connected to the same signal line as the second control transistor M11. This arrangement can reduce the wiring in the display panel, and the first capacitor C1 and the second capacitor C2 can be used together as storage capacitors in the second driving circuit 20 during the gate reset phase t11 and the data writing phase t12 of the second driving circuit 20.

[0059] There are two wiring methods used in display panels. The first wiring method involves a first power supply voltage line PAM-vdd extending in a fixed direction, connected to both the second control transistor M11 and the second capacitor C2. The second wiring method involves two first power supply voltage lines PAM-vdd extending in intersecting directions and electrically connected, one connected to the second control transistor M11 and the other to the second capacitor C2.

[0060] In some implementations... Figure 12 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Figure 12 Medium pixel circuit Figure 11 The structure is illustrated below. Figure 12 The diagram illustrates two pixel circuits in row n and two pixel circuits in row (n+1), for a total of four pixel circuits, where n is a positive integer. It also shows the light-emitting elements (LDs) connected to the pixel circuits. (Example:) Figure 12 As shown, the display panel contains signal lines extending along a first direction x and a second direction y, which intersect each other. For example, the sweep frequency signal line SWEEP(n) provides the sweep frequency signal SWEEP to the pixel circuit in the nth row, and the first light emission control line PWM-EM(n) is the first light emission control line PWM-EM connected to the pixel circuit in the nth row. Other signal lines can be understood similarly and will not be elaborated upon here. Figure 12As can be seen, the display panel has a first power supply voltage line PAM-vdd and a second power supply voltage line PWM-vdd. The first driving circuit 10 is connected to the second power supply voltage line PWM-vdd, and the second driving circuit 20 is connected to the first power supply voltage line PAM-vdd.

[0061] Figure 12 The diagram illustrates that both the first power supply voltage line PAM-vdd and the second power supply voltage line PWM-vdd extend along the second direction y. In other embodiments, one of the first power supply voltage line PAM-vdd and the second power supply voltage line PWM-vdd may extend along the second direction y, while the other may extend along the first direction x. In still other embodiments, the display panel may contain both a first power supply voltage line PAM-vdd extending along the second direction y and a second power supply voltage line PWM-vdd extending along the first direction x.

[0062] by Figure 11 Taking the illustrated pixel circuit as an example, when the second plate of the second capacitor C2 is connected to the first power supply voltage line PAM-vdd, the first capacitor C1 and the second capacitor C2 can be used together as storage capacitors in the second driving circuit 20 during the gate reset phase t11 and the data writing phase t12. During the actual light emission period in the light emission phase t3, the second driving circuit 20 provides a driving current to the light-emitting element LD, where the driving current Id = K. (V) PAM-Data -V PAM-vdd ) 2 V PAM-Data This represents the voltage value of the second data signal, PAM-Data, in V. PAM-vddThe voltage value of the first power supply voltage PAM-vdd is represented by K, which is a constant related to the characteristics of the first driving transistor M7. When multiple pixel circuits are arranged in the display panel, the magnitude of the first power supply voltage PAM-vdd received by the second driving circuit 20 in the pixel circuits at different positions in the panel will vary. This is because the first power supply voltage line PAM-vdd arranged in the panel has impedance, and when there is current in the first power supply voltage line PAM-vdd, there is a voltage drop in the signal line. Due to the existence of the voltage drop, there is a deviation in the first power supply voltage PAM-vdd received by each second driving circuit 20 at different positions. The larger the sum of the driving currents generated by each second driving circuit 20 connected to the first power supply voltage line PAM-vdd, the larger the deviation of the first power supply voltage PAM-vdd. The deviation of the first power supply voltage PAM-vdd means that there is a difference between the voltage value actually received by the second driving circuit 20 and the voltage value provided by the driving chip. This difference affects the magnitude of the driving current Id, which in turn affects the brightness of the light-emitting element LD, causing display unevenness problems.

[0063] To further address the issue of uneven display, embodiments of the present invention also provide a pixel circuit, in which a compensation module is incorporated. In some implementations, Figure 13 Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 13 As shown, the pixel circuit includes a first capacitor C1, a second capacitor C2, and a compensation module 30. The first plate of the first capacitor C1 and the output terminal of the first driving circuit 10 are electrically connected to the first node N1. The first plate of the second capacitor C2 is electrically connected to the first node N1, and the second plate of the second capacitor C2 is electrically connected to the compensation module 30. The compensation module 30 is configured to write a reference voltage Vp to the second plate of the second capacitor C2 during the first period of operation of the second driving circuit 20, and to write a first power supply voltage PAM-vdd to the second plate of the second capacitor C2 during the second period of operation of the second driving circuit 20; the first period and the second period do not overlap in the working cycle of the pixel circuit.

[0064] The compensation module 30 can write different voltages to the second plate of the second capacitor C2 at different times during which the second driving circuit 20 operates. For example, the second time period includes at least the period during which the second driving circuit 20 operates and generates driving current (e.g., Figure 4 The timing diagram indicates the t31 period, while the first period precedes the period during which the second drive circuit 20 generates drive current. Optionally, the first period includes the gate reset phase t11 and / or the data write phase t12 during which the second drive circuit 20 operates.

[0065] Taking the first time period, including the data writing phase t12, as an example.

[0066] During the gate reset phase t11 of the second driving circuit 20, the second gate reset transistor M8 turns on to reset the gate of the first driving transistor M7. During the data writing phase t12 of the second driving circuit 20, the second data writing transistor M9 and the second compensation transistor M10 turn on to write the second data signal PAM-Data to the gate of the first driving transistor M7 and perform threshold compensation. The voltage at the gate of the first driving transistor M7 is V. PAM-vdd -|Vth|, at this time, the compensation module 30 writes the reference voltage Vp to the second plate of the second capacitor C2.

[0067] During the actual light-emitting period t31 in the light-emitting stage t3, the compensation module 30 writes the first power supply voltage PAM-vdd to the second plate of the second capacitor C2. When the voltage of the second plate of the second capacitor C2 jumps from the reference voltage Vp to the first power supply voltage PAM-vdd, the voltage change is V. PAM-vdd -Vp. Due to the coupling effect of the first capacitor C1 and the second capacitor C2, the voltage at the gate of the first driving transistor M7 jumps to V. PAM-Data -|Vth|+ V PAM-vdd -Vp. During the actual light-emitting period t31, the second control transistor M11 and the fourth control transistor M12 are turned on, and the first driving transistor M7 generates a driving current under the control of its gate voltage. The formula for calculating the driving current is: Driving current Id = K (Vgs-| Vth |) 2 Vgs is the voltage difference between the gate and source of the driving transistor. In the first driving transistor M7, its gate voltage is V... PAM-Data -|Vth|+V PAM-vdd -Vp, whose source voltage is V PAM-vdd Then Vsg = V PAM-vdd - (V) PAM-Data -|Vth|+ V PAM-vdd -Vp) = V PAM-Data -|Vth|-Vp. Id=K (V) PAM-Data -Vp) 2 At this point, the drive current is related to the second data signal PAM-Data and the reference voltage Vp, but is independent of the threshold voltage and the first power supply voltage PAM-vdd. This allows the compensation module 30 to compensate for the deviation of the first power supply voltage PAM-vdd that affects the drive current, ensuring that the drive current is no longer affected by the deviation of the first power supply voltage PAM-vdd. This avoids display unevenness caused by the deviation of the first power supply voltage PAM-vdd and improves display uniformity.

[0068] It should be noted that, since the time interval between t3′ and t3′′ is very short, the compensation module 30 can play a role for most of the actual light emission period t31 to improve display uniformity.

[0069] In some implementations, the reference voltage Vp is greater than or equal to the first power supply voltage PAM-vdd. The reference voltage Vp is an ideal voltage, i.e., a voltage without any current loss. The reference voltage Vp can be considered as the power supply voltage provided by the driver chip without voltage drop loss. Applied to a display panel, the compensation module 30 in the pixel circuits at different locations on the display panel receives the same reference voltage Vp value, thereby ensuring that the driving current generated by the pixel circuit is not affected by voltage drop and improving the display unevenness problem caused by voltage drop. A dedicated line can be used in the display panel to provide the reference voltage Vp, ensuring that there is no voltage drop during the transmission of the reference voltage Vp, and that the reference voltage Vp received by the pixel circuits at all locations on the display panel is the same.

[0070] In some implementations, such as Figure 13 As shown, in the first driving circuit 10, the third control transistor M5 is connected between the second power supply voltage line PWM-vdd and the second driving transistor M1. Optionally, the second power supply voltage PWM-vdd provided by the second power supply voltage line PWM-vdd is multiplexed as the reference voltage Vp, that is, the driving chip provides the same voltage to the reference voltage line (used to transmit the reference voltage Vp) and the second power supply voltage line PWM-vdd. This setting can reduce the number of signals output by the driving chip, which helps to simplify the design of the driving chip.

[0071] In some implementations, the compensation module 30 is connected to the second power supply voltage line PWM-vdd, that is, the reference voltage Vp is provided by the second power supply voltage line PWM-vdd. Compared with the first power supply voltage line PAM-vdd, the second power supply voltage line PWM-vdd has no load and large current, and the load on the second power supply voltage line PWM-vdd is small. The second power supply voltage PWM-vdd provided by it has no current loss. It can also be understood that the second power supply voltage PWM-vdd is a power supply voltage without voltage drop loss. This ensures that the driving current generated by the pixel circuit is not affected by voltage drop, and improves the display unevenness problem caused by voltage drop.

[0072] In some implementations, such as Figure 13As shown, the compensation module 30 includes a first transistor T1 and a second transistor T2. The gate of the first transistor is connected to a first control signal line K1, which provides a first control signal K1. The first terminal of the first transistor T1 receives a reference voltage Vp, and the second terminal is connected to the second plate of the second capacitor C2. The gate of the second transistor T2 is connected to a second control signal line K2, which provides a second control signal K2. The first terminal of the second transistor T2 is connected to a first power supply voltage line PAM-vdd, and the second terminal is connected to the second plate of the second capacitor C2. Specifically, during the first time period, the first control signal K1 acts as an enable signal, controlling the first transistor T1 to turn on and write the reference voltage Vp into the second plate of the second capacitor C2. During the second time period, the second control signal K2 acts as an enable signal, controlling the second transistor T2 to turn on and write the first power supply voltage PAM-vdd into the second plate of the second capacitor C2.

[0073] Figure 14 This is another signal timing diagram provided in an embodiment of the present invention. Figure 14 The signal timing provided in the embodiment can be used for driving. Figure 13 The pixel circuit provided in the embodiment. (For example...) Figure 14 As shown, the first control signal K1 and the second control signal K2 are inverse signals. When the first transistor T1 and the second transistor T2 are of the same type, it can be ensured that the turn-on periods of the first transistor T1 and the second transistor T2 do not overlap. Therefore, the periods during which the compensation module 30 writes the reference voltage Vp and the first power supply voltage PAM-vdd to the second plate of the second capacitor C2 do not overlap.

[0074] like Figure 13 As shown, the first driving circuit 10 includes a first light-emitting control module 101, which is connected in series with the second driving transistor M1. The control terminal of the first light-emitting control module 101 receives a first light-emitting control signal PWM-EM. The second driving circuit 20 includes a second light-emitting control module 201, which is connected in series with the first driving transistor M7. The control terminal of the second light-emitting control module 201 receives a second light-emitting control signal PAM-EM. Figure 13 The diagram illustrates that the first light-emitting control module 101 includes a first control transistor M6 and a third control transistor M5, and the second light-emitting control module 201 includes a second control transistor M11 and a fourth control transistor M12.

[0075] In other embodiments, the first light-emitting control module 101 includes at least a first control transistor M6, which is connected between the second driving transistor M1 and the first capacitor C1. The gate of the first control transistor M6 receives a first light-emitting control signal PWM-EM. The gate of the first control transistor M6 and the gate of the third control transistor M5 may receive different signals. The second light-emitting control module 201 includes a second control transistor M11, which is connected between the second driving transistor M7 and the light-emitting element LD. The gate of the second control transistor M11 receives a second light-emitting control signal PAM-EM. The gate of the second control transistor M11 and the gate of the fourth control transistor M12 may receive different signals, as will be described in the following related embodiments.

[0076] Combination Figure 14 From the timing diagram, the second control signal K2 has the same timing as the first light-emitting control signal PWM-EM, meaning the second control signal K2 reuses the first light-emitting control signal PWM-EM. When the first light-emitting control module 101 includes a first control transistor M6 and a third control transistor M5, that is, the gate of the first control transistor M6 receives the second control signal K2, and the gate of the third control transistor M5 also receives the second control signal K2. The reuse of the original control signal by the second control signal K2 reduces wiring in the display panel, saving wiring space.

[0077] In this process, the second control signal K2 provides an enable signal during the light-emitting stage t3 to control the second transistor T2 to turn on and write the first power supply voltage PAM-vdd into the second plate of the second capacitor C2. The light-emitting stage t3 occurs after the first input stage t1 of the second driving circuit 20. At least during the first input stage t1 of the second driving circuit 20, the first control signal K1 provides an enable signal to control the first transistor T1 to turn on and write the reference voltage Vp into the second plate of the second capacitor C2. This configuration allows the voltage of the second plate of the second capacitor C2 to have a voltage jump at the initial moment of the light-emitting stage t3. Due to capacitive coupling, the gate voltage of the first driving transistor M7 also jumps accordingly, and the amount of voltage change is related to the first power supply voltage PAM-vdd. Therefore, during the period when the second control transistor M11 and the fourth control transistor M12 are turned on, the driving current generated by the first driving transistor M7 is unrelated to the first power supply voltage PAM-vdd. The compensation module 30 is used to compensate for the deviation of the first power supply voltage PAM-vdd that affects the drive current, so that the drive current is no longer affected by the deviation of the first power supply voltage PAM-vdd, thus improving the uniformity of the display.

[0078] In other embodiments, the timing of the second control signal K2 is the same as that of the second light-emitting control signal PAM-EM, and the second control signal K2 multiplexes the second light-emitting control signal PAM-EM. Since the transistor controlled by the second light-emitting control signal PAM-EM is connected in series with the first driving transistor M7, the enable signal of the second light-emitting control signal PAM-EM affects the period during which the first driving transistor M7 generates the driving current. By setting the second control signal K2 to multiplex the second light-emitting control signal PAM-EM, at the initial moment when the gate of the first driving transistor M7 generates the driving current, the second control signal K2 controls the second transistor T2 to write the first power supply voltage PAM-vdd to the second plate of the second capacitor C2, thereby causing a change in the gate voltage of the first driving transistor M7, and making the gate voltage change value related to the first power supply voltage PAM-vdd. Thus, the driving current can be made unrelated to the first power supply voltage PAM-vdd during the period when the first driving transistor M7 generates the driving current, realizing the compensation module 30 to compensate for the deviation of the first power supply voltage PAM-vdd that affects the driving current, thereby improving the display uniformity.

[0079] In other implementations, Figure 15 This is another pixel circuit schematic diagram provided in an embodiment of the present invention. Figure 16 Another signal timing diagram provided for an embodiment of the present invention. For example... Figure 15 As shown, the gate of the second data writing transistor M9 in the second driving circuit 20 receives the first control signal K1. That is, the second data writing transistor M9 and the first transistor T1 share the same control signal. Figure 15 The diagram illustrates the gate of the second compensation transistor M10 and the gate of the reset transistor M13, both of which receive the first control signal K1. (Combined with...) Figure 3 and Figure 4 In this embodiment, the second scan signal PAM-S2 can be described as being multiplexed into the first control signal K1. In application, the signal line connected to the gate of the second data write transistor M9 and the signal line connected to the gate of the first transistor T1 can be the same signal line or different signal lines. When different signal lines are connected, these different signal lines transmit the same first control signal K1; here, "different signal lines" refers to the different wiring positions of the signal lines in the display panel.

[0080] In this embodiment, the first period of operation of the compensation module 30 includes the data writing phase of the second drive circuit 20.

[0081] Figure 16The diagram illustrates that the second control signal K2 and the first light-emitting control signal PWM-EM are the same signal. During the data writing phase t12 of the second driving circuit 20: the first control signal K1, at an enable level, controls the first transistor T1 to write the reference voltage Vp to the second plate of the second capacitor C2. The first capacitor C1 and the second capacitor C2 together function as storage capacitors during this phase. The first control signal K1 also controls the second data writing transistor M9 and the second compensation transistor M10 to turn on, writing the second data signal PAM-Data to the gate of the first driving transistor M7 and performing threshold compensation. During the light-emitting stage t3: the second control signal K2 controls the second transistor T2 to turn on, writing the first power supply voltage PAM-vdd into the second plate of the second capacitor C2, causing a voltage jump at the second plate of the second capacitor C2, which in turn causes a voltage jump at the gate voltage of the first driving transistor M7, and the amount of gate voltage change is related to the first power supply voltage PAM-vdd; when the second light-emitting control signal PAM-EM controls the second control transistor M11 and the fourth control transistor M12, the first driving transistor M7 generates a driving current under the control of its gate voltage. At this time, the magnitude of the driving current is independent of the first power supply voltage PAM-vdd, realizing the compensation module 30 to compensate for the deviation of the first power supply voltage PAM-vdd that affects the driving current, thereby improving the display uniformity. In addition, in this embodiment, the first transistor T1 and the transistors in the second driving circuit 20 share the same control signal, which can reduce the wiring in the display panel and save wiring space.

[0082] In other implementations, Figure 17 Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 17 As shown, in the second driving circuit 20, the gate of the second gate reset transistor M8 receives the first control signal K1. That is, the second gate reset transistor M8 and the first transistor T1 share the same control signal. Combined with... Figure 3 and Figure 4 In this embodiment, the first scan signal PAM-S1 can be multiplexed as the first control signal K1. In application, the signal line connected to the gate of the second gate reset transistor M8 and the signal line connected to the gate of the first transistor T1 can be the same signal line or different signal lines. When different signal lines are connected, these different signal lines transmit the same first control signal K1; here, "different signal lines" refers to the different wiring positions of the signal lines in the display panel.

[0083] In this embodiment, the first period of operation of the compensation module 30 includes the gate reset phase of the second drive circuit 20.

[0084] Figure 18 Another signal timing diagram provided for an embodiment of the present invention. Figure 17The pixel circuit provided in the embodiment can employ Figure 18 The implementation example uses the signal timing provided for driving. Figure 18 The second control signal K2 and the first light-emitting control signal PWM-EM are illustrated as the same signal. In this embodiment, during the gate reset stage t11 of the second driving circuit 20: the first control signal K1, at an enable level, controls the first transistor T1 to turn on, writing the reference voltage Vp to the second plate of the second capacitor C2. Simultaneously, the first control signal K1 controls the second gate reset transistor M8 to turn on, resetting the gate of the first driving transistor M7. During this stage, the first capacitor C1 and the second capacitor C2 together act as storage capacitors. During the light-emitting stage t3: the second control signal K2 controls the second transistor T2 to turn on, writing the first power supply voltage PAM-vdd to the second plate of the second capacitor C2, causing a voltage jump at the second plate of the second capacitor C2, which in turn causes a voltage jump at the gate voltage of the first driving transistor M7. The amount of change in the gate voltage is related to the first power supply voltage PAM-vdd. This makes the magnitude of the driving current independent of the first power supply voltage PAM-vdd, enabling the compensation module 30 to compensate for deviations in the first power supply voltage PAM-vdd that affect the driving current, thus improving display uniformity. In addition, in this embodiment, the first transistor T1 and the transistors in the second driving circuit 20 share the same control signal, which can reduce the wiring in the display panel and save wiring space.

[0085] In other implementations, Figure 19 Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 19 As shown, the compensation module 30 includes a first transistor T1, a second transistor T2, and a sixth transistor T6. The first transistor T1 and the sixth transistor T6 are connected in parallel. The first terminal of the first transistor T1 receives a reference voltage Vp, and its second terminal is connected to the second plate of the second capacitor C2. The first terminal of the sixth transistor T6 also receives a reference voltage Vp and its second terminal is connected to the second plate of the second capacitor C2. The first terminal of the second transistor T2 is connected to the first power supply voltage line PAM-vdd, and its second terminal is connected to the second plate of the second capacitor C2. The gate of the first transistor T1 receives a first control signal K1, and the second gate reset transistor M8 shares the control signal with the first transistor T1. The gate of the second transistor T2 receives a second control signal K2, and the gate of the sixth transistor T6 shares the control signal with the second data write transistor M9.

[0086] In other implementations, Figure 20 Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 20As shown, the gate of the electrode reset transistor M13 in the second driving circuit 20 receives the first control signal K1. That is, the electrode reset transistor M13 and the first transistor T1 share the same control signal. Figure 21 This is another signal timing diagram provided in an embodiment of the present invention. Figure 20 The pixel circuit provided in the embodiment can employ Figure 21 The provided signal timing is used for driving. Figure 21 The second control signal K2 and the first light-emitting control signal PWM-EM are illustrated as the same signal.

[0087] like Figure 21 As shown, the period during which the first control signal K1 is continuously at the enable level covers at least the gate reset phase t11 and the data writing phase t12 of the second driving circuit 20. That is, the first period of operation of the compensation module 30 includes the gate reset phase t11 and the data writing phase t12 of the second driving circuit 20. In this embodiment, during the gate reset phase t11 and the data writing phase t12 of the second driving circuit 20, the first control signal K1 continuously controls the first transistor T1 to be in the on state. Then, the first capacitor C1 and the second capacitor C2 can be used together as storage capacitors, so that the gate of the first driving transistor M7 is accurately reset and then the accurate second data signal is written.

[0088] In some embodiments, the period during which the first control signal K1 is continuously at the enable level covers at least the gate reset phase t11 and the data write phase t12 of the second drive circuit 20. Specifically, the falling edge of the first control signal K1 is no later than the falling edge of the first scan signal PAM-S1, and the rising edge of the first control signal K1 is no earlier than the rising edge of the second scan signal PAM-S2; that is, the pulse width of the enable signal of the first control signal K1 is greater than the sum of the pulse widths of the enable signals of the first scan signal PAM-S1 and the second scan signal PAM-S2. Alternatively, the falling edge of the first control signal K1 coincides with the falling edge of the first scan signal PAM-S1 (i.e., both are falling edges), and the rising edge of the first control signal K1 coincides with the rising edge of the second scan signal PAM-S2 (i.e., both are rising edges).

[0089] In other implementations, Figure 22 This is another signal timing diagram provided in an embodiment of the present invention. Figure 22 The provided signal timing can be used for driving Figure 13 or Figure 20 The pixel circuit provided in the embodiment. (For example...) Figure 22As shown, the first input phase t1 of the second driving circuit 20 and the second input phase t2 of the first driving circuit 10 do not overlap. The first time period of the compensation module 30 includes both the first input phase t1 and the second input phase t2 of the second driving circuit 20. The period during which the first control signal K1 is continuously at the enable level covers both the first input phase t1 and the second input phase t2. In this embodiment, the compensation module 30 continuously writes the reference voltage Vp to the second plate of the second capacitor C2 during the first input phase t1 and the second input phase t2. Then, for at least a portion of the time period after the second input phase t2, such as at least during the period when the first light emission control signal PWM-EM (or the second light emission control signal PAM-EM) is at the enable level, it writes the first power supply voltage PAM-vdd to the second plate of the second capacitor C2. This achieves compensation for the deviation of the first power supply voltage PAM-vdd that affects the driving current using the compensation module 30, thereby improving display uniformity.

[0090] In other embodiments, the first period of operation of the compensation module 30 includes a first input phase t1 of the second drive circuit 20 and a partial second input phase t2 of the first drive circuit 10. That is, the period during which the first control signal K1 is continuously at the enable level covers both the first input phase t1 and a portion of the second input phase t2. This is not illustrated in the accompanying drawings.

[0091] In other implementations, Figure 23 This is another signal timing diagram provided in an embodiment of the present invention. Figure 23 The provided signal timing can be used for driving Figure 13 or Figure 20 The pixel circuit provided in the embodiment. (For example...) Figure 23 As shown, the first input phase t1 of the second driving circuit 20 and the second input phase t2 of the first driving circuit 10 do not overlap. The first time period of the compensation module 30 includes both the first input phase t1 and the second input phase t2 of the second driving circuit 20. Specifically, the first enable level of the first control signal K1 covers the first input phase t1, and the second enable level of the first control signal K1 covers the second input phase t2.

[0092] In some embodiments, the pixel circuit includes a first pixel circuit and a second pixel circuit. The first pixel circuit is coupled to a first light-emitting element, and the second pixel circuit is coupled to a second light-emitting element. The first and second light-emitting elements emit different colors. Both the first and second pixel circuits include a first capacitor C1 and a second capacitor C2. The capacitance value of the second capacitor C2 in the first pixel circuit is different from the capacitance value of the second capacitor C2 in the second pixel circuit.

[0093] During certain periods of pixel circuit operation, the second capacitor C2 and the first capacitor C1 need to work together as storage capacitors in the second driving circuit 20. The larger the capacitance value of the second capacitor C2, the more charge it can store, and the longer it can maintain the gate potential of the first driving transistor M7 during the light-emitting phase. Furthermore, generally, the larger the capacitance value of the second capacitor C2, the larger the area it occupies in the display panel. Differentiating the second capacitor C2 according to the color differences of the light-emitting elements can meet the brightness requirements of different color light-emitting elements and make reasonable use of the space on the display panel.

[0094] In some implementations, the first light-emitting element emits red light, and the second light-emitting element emits blue or green light. The capacitance value of the second capacitor C2 in the first pixel circuit is greater than the capacitance value of the second capacitor C2 in the second pixel circuit. This arrangement can meet the brightness requirements of light-emitting elements of different colors and allows for efficient use of space on the display panel.

[0095] In other embodiments, the capacitance values ​​of the second capacitor C2 in the pixel circuits connected to different color light-emitting elements in the display panel are all equal.

[0096] In some implementations... Figure 24 Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 24 As shown, the first plate of the first capacitor C1 and the output terminal of the first driving circuit 10 are electrically connected to the first node N1. The pixel circuit also includes a third transistor T3. The gate of the third transistor T3 receives a third control signal K3. The first terminal of the third transistor T3 is connected to the second constant voltage signal line VH2, and the second terminal of the third transistor T3 is connected to the first node N1. The second constant voltage signal line VH2 can transmit the same signal as the second reset signal line PAM-REF. In this embodiment, when the third transistor T3 is in the on state, it can connect the first plate of the first capacitor C1 to the second constant voltage signal line VH2, resetting the first node N1. It also stabilizes the potential of the first node N1, at which point the first capacitor C1 can be used as a storage capacitor in the second driving circuit 20.

[0097] When the third control signal K3 is at the enable level, the third transistor T3 turns on and writes the constant voltage signal transmitted to the second constant voltage signal line VH2 to the first node N1. The first control transistor M6 in the first drive circuit 10 is connected to the first node N1, and is connected in series with the second drive transistor M1. After the second drive transistor M1 is turned on, it gradually raises the potential of the first node N1, eventually transmitting the second power supply voltage PWM-Vdd to the first node N1 via the first control transistor M6, thereby regulating the flow period of the drive current provided by the second drive circuit 20. In this embodiment of the invention, the period when the third control signal K3 is at the enable level does not overlap with the period when the first control transistor M6 receives the enable level. This ensures that the third transistor T3 resets the first node N1 during a certain period, allowing the potential of the first node N1 to change after the second drive transistor M1 turns on, thus changing the potential of the first plate of the first capacitor C1. This, in turn, controls the gate potential of the first drive transistor M7 through coupling, thereby regulating the flow period of the drive current provided by the second drive circuit 20.

[0098] In some implementations, the second constant voltage signal line VH2 provides a voltage value of V1 for the second constant voltage signal, and the second power supply voltage line PWM-vdd provides a voltage value of V2 for the second power supply voltage; wherein V2 > V1; optionally, V2 - V1 ≥ 3V. After the third transistor T3 is turned on, it writes the second constant voltage signal to the first node N1, which is also written to the first plate of the first capacitor C1; after the second driving transistor M1 is turned on, it writes the second power supply voltage to the first plate of the first capacitor C1 through the first control transistor M6, thereby causing a change in the potential of the first plate of the first capacitor C1. The voltage difference between V2 and V1 is the amount of potential change of the first plate of the first capacitor C1, and the amount of potential change affects the coupling effect on the gate potential of the first driving transistor M7. Setting V2 - V1 ≥ 3V can ensure that the first capacitor C1 has a better coupling effect to control the gate potential change of the first driving transistor M7.

[0099] In some embodiments, the second gate reset transistor M8 in the second driving circuit 20 is used to transmit the second reset signal PAM-REF to the gate of the first driving transistor M7 for reset. The second constant voltage signal line VH2 provides the second reset signal PAM-REF; alternatively, the light-emitting element LD is connected to the third power supply voltage line PVEE, and the third power supply voltage line PVEE and the second constant voltage signal line VH2 transmit the same signal. This arrangement allows the second constant voltage signal line VH2 to transmit a signal with a lower voltage value, satisfying the coupling requirement of the first capacitor C1, and allowing it to share the signal originally needed by the pixel circuit without increasing the number of signals required to drive the pixel circuit, thus simplifying the design of the driving chip.

[0100] In some implementations... Figure 25 This is another signal timing diagram provided in an embodiment of the present invention. Figure 25 The provided signal timing can be used for driving Figure 24 The pixel circuit provided in the embodiment. (For example...) Figure 25 As shown, the third control signal K3 and the first light-emitting control signal PWM-EM received by the gate of the first control transistor M6 are inverted signals. This configuration facilitates the generation of the third control signal K3 and simplifies the design of the driver chip.

[0101] In other implementations, Figure 26 Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 26 As shown, one of the first control transistor M6 and the third transistor T3 is a p-type transistor and the other is an n-type transistor. The gate of the first control transistor M6 receives the third control signal K3. That is, the gates of the first control transistor M6 and the third transistor T3 receive the same signal. When the third control signal K3 is at an enable level, controlling the first control transistor M6 to be in the on state, it controls the third transistor T3 to be in the off state; when the third control signal K3 is at an enable level, controlling the third transistor T3 to be in the on state, it controls the first control transistor M6 to be in the off state.

[0102] Figure 26 The diagram illustrates the first control transistor M6 as a p-type transistor and the third transistor T3 as an n-type transistor. Figure 26 The diagram also illustrates that the first gate reset transistor M2 and the first compensation transistor M4 are n-type transistors, as are the second gate reset transistor M8 and the second compensation transistor M10. Specifically, the gate of the first gate reset transistor M2 receives the fifth scan signal PWM-S1-n, the gate of the first compensation transistor M4 receives the sixth scan signal PWM-S2-n, the gate of the second gate reset transistor M8 receives the seventh scan signal PAM-S1-n, and the gate of the second compensation transistor M10 receives the eighth scan signal PAM-S2-n. This implementation reduces the leakage current from the first gate reset transistor M2 and the first compensation transistor M4 to the gate of the second driving transistor M1 when they are off, and also reduces the leakage current from the second gate reset transistor M8 and the second compensation transistor M10 to the gate of the first driving transistor M7 when they are off. Furthermore, by setting one of the first control transistor M6 and the third transistor T3 to an n-type transistor, no new process technology is required.

[0103] In some implementations, the gate of the second gate reset transistor M8 and the gate of the third transistor T3 receive the same signal. Alternatively, the gate of the second gate reset transistor M8 receives the third control signal K3. Figure 27This is another signal timing diagram provided in an embodiment of the present invention. Figure 27 The provided signal timing can be used to drive, for example Figure 24 The provided pixel circuitry. For example... Figure 27 As shown, during the gate reset stage t11 of the second driving circuit 20, the third control signal K3, at an enable level, controls the third transistor T3 to turn on, connecting the first node N1 to the second constant voltage signal line VH2. This stabilizes the potential of the first node N1 and resets it. When the third control signal K3 controls the second gate reset transistor M8 to turn on and reset the gate of the second driving transistor M7, the first capacitor C1 functions as a storage capacitor.

[0104] In some implementations, the gates of the second data write transistor M9 and the third transistor T3 receive the same signal. Alternatively, the gate of the second data write transistor M9 receives the third control signal K3. Figure 28 This is another signal timing diagram provided in an embodiment of the present invention. Figure 28 The provided signal timing can be used to drive, for example Figure 24 The provided pixel circuitry. For example... Figure 28 As shown, during the data writing stage t12 of the second driving circuit 20, the third control signal K3, at an enable level, controls the third transistor T3 to turn on, connecting the first node N1 to the second constant voltage signal line VH2. This stabilizes the potential of the first node N1 and resets it. When the third control signal K3 controls the second data writing transistor M9 to turn on and write the second data signal PAM-Data to the gate of the second driving transistor M7, the first capacitor C1 functions as a storage capacitor.

[0105] In other implementations, Figure 29 This is another pixel circuit schematic diagram provided in an embodiment of the present invention. Figure 30 This is another signal timing diagram provided in an embodiment of the present invention. Figure 30 The provided signal timing can be used to drive, for example Figure 29 The provided pixel circuitry. For example... Figure 29 As shown, the gate of electrode reset transistor M13 receives the third control signal K3, meaning that the gate of electrode reset transistor M13 and the gate of the third transistor T3 receive the same signal. Figure 30As shown, in the first input stage t1 of the second driving circuit 20, the third control signal K3 enables the electrode reset transistor M13 to reset the electrodes of the light-emitting element LD. Simultaneously, the third control signal K3 enables the third transistor T3 to connect the first node N1 to the second constant voltage signal line VH2, thereby stabilizing the potential of the first node N1 and resetting it. This allows the first capacitor C1 to function as a storage capacitor during both the gate reset stage t11 and the data writing stage t12 of the second driving circuit 20.

[0106] In some embodiments, the second driving circuit 20 includes a data writing circuit configured to write a second data signal PAM-Data to the second driving circuit 20 under the control of its control terminal signal; the data writing circuit includes, for example, Figure 24 The diagram illustrates a second data writing transistor M9 and a second compensation transistor M10. The second driving circuit 20 also includes a second gate reset transistor M8 and an electrode reset transistor M13. The second gate reset transistor M8 is connected to the gate of the first driving transistor M7, and the electrode reset transistor M13 is connected to the light-emitting element LD. The width and length of the channel of the third transistor T3 are the same as the width and length of the channel of at least one of the second data writing transistor M9, the second compensation transistor M10, the second gate reset transistor M8, and the electrode reset transistor M13. This arrangement ensures that the characteristics of the third transistor T3 are substantially the same as the switching characteristics of at least one of the aforementioned transistors. Since two transistors with the same channel width and length can be turned off or on under the same voltage control, the same signal can be used to control transistors with the same switching characteristics. For example, if the width and length of the channel of the third transistor T3 are the same as the width and length of the channel of the second gate reset transistor M8, then both the gate of the third transistor T3 and the gate of the second gate reset transistor M8 can be configured to receive the third control signal K3. In this case, both the third transistor T3 and the second gate reset transistor M8 can be p-type transistors or both can be n-type transistors. As another example, if the width and length of the channel of the third transistor T3 are the same as the width and length of the channel of the second data write transistor M9, then both the gate of the third transistor T3 and the gate of the second data write transistor M9 can be configured to receive the third control signal K3.

[0107] In other implementations, Figure 31 Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 31As shown, the second driving circuit 20 includes a first driving transistor M7, a second data writing transistor M9, a second gate reset transistor M8, and an electrode reset transistor M13. The second data writing transistor M9 is configured to write a second data signal PAM-Data to the second driving circuit 20 under the control of its gate signal. The second data writing transistor M9 and the second gate reset transistor M8 are respectively connected to the gate of the first driving transistor M7, and the electrode reset transistor M13 is connected to the light-emitting element. The width and length of the channel of the third transistor T3 are the same as the width and length of the channel of at least one of the second data writing transistor M9, the second gate reset transistor M8, and the electrode reset transistor M13. This configuration ensures that the characteristics of the third transistor T3 are substantially the same as those of at least one of the aforementioned transistors, allowing the same signal to control transistors with the same characteristics.

[0108] It should be noted that in some embodiments of the present invention, the circuit structures of the first driving circuit 10 and the second driving circuit 20 are similar. Both circuits include a driving transistor, a data writing transistor, a gate reset transistor, a compensation transistor, and a light-emitting control transistor. Specifically, in some embodiments, the first driving circuit 10 includes a second driving transistor M1, a first gate reset transistor M2, a first data writing transistor M3, a first compensation transistor M4, a first control transistor M6, and a third control transistor M5. The second driving circuit 20 includes a first driving transistor M7, a second gate reset transistor M8, a second data writing transistor M9, a second compensation transistor M10, a second control transistor M11, and a fourth control transistor M12.

[0109] In other implementations, Figure 32 Another signal timing diagram provided in this embodiment of the invention can be used to drive, such as Figure 24 The pixel circuit shown. Combined with... Figure 24The first driving circuit 10 includes a second driving transistor M1 and a first control transistor M6, with the first control transistor M6 connected between the first node N1 and the second driving transistor M1. The gate of the first control transistor M6 receives a first light-emitting control signal PWM-EM. The second driving circuit 20 includes a first driving transistor M7 and a fourth control transistor M12, with the fourth control transistor M12 connected between the light-emitting element LD and the first driving transistor M7. The gate of the fourth control transistor M12 receives a second light-emitting control signal PAM-EM. The high-level voltage value VGH1 of the first light-emitting control signal PWM-EM is different from the high-level voltage value VGH2 of the second light-emitting control signal PAM-EM, and / or the low-level voltage value VGL1 of the first light-emitting control signal PWM-EM is different from the low-level voltage value VGL2 of the second light-emitting control signal PAM-EM. The high-level voltage value VGH3 of the third control signal K3 is the same as the high-level voltage value VGH1 of the first light-emitting control signal PWM-EM, and the low-level voltage value VGL3 of the third control signal is the same as the low-level voltage value VGL1 of the first light-emitting control signal PWM-EM. Figure 32 The diagram only illustrates one possible timing sequence for the third control signal K3.

[0110] This implementation differentiates the high and low level voltage values ​​of the light-emitting control signals required by the first driving circuit 10 and the second driving circuit 20, enabling precise control of the control transistors in the two driving circuits. This improves the stability of the pixel circuit operation and reduces the risk of display failure. Furthermore, setting the high and low level voltage values ​​of the third control signal K3 to be equal to those of the first light-emitting control signal PWM-EM can be combined with a scheme where the length and width of the channel of the third transistor T3 are the same as the length and width of the channel of the first control transistor M6. This ensures that the characteristics of the third transistor T3 and the first control transistor M6 are essentially identical. Further setting the third control signal K3 and the first light-emitting control signal PWM-EM to be inverse signals ensures that the third transistor T3 stabilizes the potential of the first node N1 during certain periods without affecting the output signal at the output terminal of the first driving circuit 10. It also facilitates the generation of the third control signal K3 and simplifies the design of the driving chip.

[0111] In some embodiments, the first driving circuit 10 includes a first type of transistor, and the second driving circuit 20 includes a second type of transistor. (Combined with...) Figure 24In the first driving circuit 10, the first type of transistors includes at least one of a first data writing transistor M3 and a first gate reset transistor M2. The first data writing transistor M3 is connected to the first terminal of the second driving transistor M1, and the first gate reset transistor M2 is connected to the gate of the second driving transistor M1. In the second driving circuit 20, the second type of transistors includes at least one of a second data writing transistor M9, a second gate reset transistor M8, and an electrode reset transistor M13. The second data writing transistor M9 is connected to the first terminal of the first driving transistor M7, the second gate reset transistor M8 is connected to the gate of the first driving transistor M7, and the electrode reset transistor M13 is connected to the light-emitting element LD.

[0112] The gate of the first type of transistor receives a first type of control signal, and the gate of the second type of transistor receives a second type of control signal. Combined Figure 32 Let's take an example where the gates of the first data write transistor M3 and the first gate reset transistor M2 both receive a first type of control signal, and the gates of the second data write transistor M9, the second gate reset transistor M8, and the electrode reset transistor M13 all receive a second type of control signal. Then, the first type of control signal includes the third scan signal PWM-S1 and the fourth scan signal PWM-S2, and the second type of control signal includes the first scan signal PAM-S1 and the second scan signal PAM-S2.

[0113] Specifically, the high-level voltage value VGH4 of the first type of control signal is different from the high-level voltage value VGH5 of the second type of control signal, and / or, the low-level voltage value VGL4 of the first type of control signal is different from the low-level voltage value VGL5 of the second type of control signal. The high-level voltage value VGH3 of the third control signal K3 is the same as the high-level voltage value VGH5 of the second type of control signal, and the low-level voltage value VGL3 of the third control signal K3 is the same as the low-level voltage value VGL5 of the second type of control signal.

[0114] This implementation differentiates the high and low level voltage values ​​of the scanning signals required by the first driving circuit 10 and the second driving circuit 20, enabling precise control of the transistors in the two driving circuits using the scanning signals. This improves the stability of the pixel circuit operation and reduces the risk of display failure. Furthermore, setting the high and low level voltage values ​​of the third control signal K3 to be equal to those of the second type of control signal can be achieved by designing the length and width of the channel of the third transistor T3 to be the same as that of the second type of transistor. This ensures that the characteristics of the third transistor T3 are essentially the same as those of the second type of transistor. Furthermore, setting the third control signal K3 to be the same as the second type of control signal ensures that the third transistor T3 stabilizes the potential of the first node N1 during certain periods without affecting the output signal at the output terminal of the first driving circuit 10. For example, when the second type of transistor includes the second data writing transistor M9, if the length and width of the channel of the third transistor T3 are set to be the same as the length and width of the channel of the second data writing transistor M9, then the gate of the second data writing transistor M9 and the gate of the third transistor T3 can both receive the third control signal K3.

[0115] In some implementations... Figure 33 Another signal timing diagram provided in this embodiment of the invention can be used to drive, such as Figure 29 The pixel circuit shown. (As shown in the image.) Figure 33 As shown, the working cycle of the pixel circuit includes a light-emitting stage t3 and a reset stage t4. The reset stage t4 includes N sub-reset stages t4z arranged in sequence. The light-emitting stage t3 includes M sub-light-emitting stages t3z arranged in sequence. The first sub-reset stage t4z is located before the first sub-light-emitting stage t3z. There is a sub-reset stage t4z between two adjacent sub-light-emitting stages t3z. N and M are both positive integers; optionally, N and M are the same. Figure 33 The diagram uses N=M=3 for illustration.

[0116] Combination Figure 29 and Figure 33 As can be seen, during the sub-reset phase t4z, the third control signal K3 provides an enable level to control the third transistor T3 to turn on, connecting the first node N1 to the second constant voltage signal line VH2, thus resetting the first node N1.

[0117] During the sub-light emission stage t3z: the first light emission control signal PWM-EM provides an enable level, and the second light emission control signal PAM-EM also provides an enable level. Specifically, the second light emission control signal PAM-EM, providing an enable level, controls the second control transistor M11 and the fourth control transistor M12 to turn on. The first driving transistor M7 generates a driving current under the control of its gate voltage, thus the second driving circuit 20 provides driving current to the light-emitting element LD. The first light emission control signal PWM-EM, providing an enable level, controls the first control transistor M6 and the third control transistor M5 to turn on. Simultaneously, the voltage value of the sweep frequency signal SWEEP gradually changes, causing a change in the gate voltage of the second driving transistor M1 through coupling. When the second driving transistor M1 turns on, the first driving circuit 10 provides a control current to the first plate of the first capacitor C1, causing a change in the voltage of the first plate of the first capacitor C1. This, in turn, causes a change in the gate voltage of the first driving transistor M7 through the coupling effect of the first capacitor C1, causing the first driving transistor M7 to turn off. Therefore, the second driving circuit 20 stops providing driving current to the light-emitting element LD.

[0118] By setting a sub-reset stage t4z between two adjacent sub-light-emitting stages t3z, and ensuring that the light-emitting element LD has a non-light-emitting period between two actual light-emitting stages, the pixel circuit can control the light-emitting element LD to emit light multiple times after writing the second data signal PAM-Data once. This reduces display screen flicker and allows for adaptation to more driving methods. Specifically, the second input stage t2 of the first driving circuit 10 and the first input stage t1 of the second driving circuit 20 are completed before the first sub-light-emitting stage t3z. Setting the first sub-reset stage t4z before the first sub-light-emitting stage t3z allows the first node N1 to be reset and its potential stabilized, enabling the first capacitor C1 to be used as the storage capacitor for the second driving circuit 20.

[0119] In some implementations, combined Figure 29 and Figure 33 As can be seen, the gate of electrode reset transistor M13 receives the third control signal K3. During the sub-reset phase t4z, the gate of electrode reset transistor M13 receives the enable level of the third control signal K3, and electrode reset transistor M1 turns on to reset the electrodes of the light-emitting element LD. In this embodiment, resetting the first node N1 during the sub-reset phase t4z also resets the electrodes of the light-emitting element LD, which can work together to control the light-emitting element LD to emit light multiple times.

[0120] Figure 29In this illustration, the gates of electrode reset transistor M13 and the third transistor T3 receive the same signal. In other embodiments, the gates of electrode reset transistor M13 and the third transistor T3 receive different signals, which also allows the electrode reset transistor M13 to reset the electrodes of the light-emitting element LD during the sub-reset phase t4z. This embodiment will be described below.

[0121] In some embodiments, the second driving circuit 20 includes a second data writing module configured to write a second data signal PAM-Data to the second driving circuit 20 under the control of the second scan signal PAM-S2. The second data writing module may include... Figure 29 The second data writing module, illustrated in the diagram, may also include a second data writing transistor M9 and a second compensation transistor M10. Figure 31 The second data, as shown in the diagram, is written into crystal M9.

[0122] The pixel circuit's operating cycle also includes a first gate reset stage and a first data write stage, sequentially set. The first gate reset stage is the gate reset stage t11 of the second driving circuit 20, and the first data write stage is the data write stage t12 of the second driving circuit 20. Combined with... Figure 33 In the gate reset phase t11 of the second driving circuit 20, the first scan signal PAM-S1 enables the second gate reset transistor M8 to reset the gate of the first driving transistor M7. In the data writing phase t12 of the second driving circuit 20, the second scan signal PAM-S2 enables the second data writing module to open and write the second data signal PAM-Data into the second driving circuit 20. The first sub-reset phase t4z covers the data writing phase t12 of the second driving circuit 20. In this phase, the third transistor T3 turns on, connecting the second constant voltage signal line VH2 to the first node N1, resetting and stabilizing the potential of the first node N1. This allows the first capacitor C1 to be used as the storage capacitor of the second driving circuit 20, ensuring the accuracy of writing the second data signal PAM-Data.

[0123] In some embodiments, the first sub-reset stage t4z covers the gate reset stage t11 of the second driving circuit 20, that is, it covers the first gate reset stage. Then, in the gate reset stage t11, the third transistor T3 turns on, connecting the second constant voltage signal line VH2 to the first node N1, which can reset the first node N1 and stabilize its potential. This allows the first capacitor C1 to be used as the storage capacitor of the second driving circuit 20, ensuring a complete reset of the second driving transistor M7.

[0124] In other implementations, Figure 34 Another signal timing diagram provided in this embodiment of the invention can be used to drive, such as Figure 29 The pixel circuit shown. (As shown in the image.) Figure 34 As shown, the first sub-reset phase t4z covers the gate reset phase t11 and the data write phase t12 of the second driving circuit 20, meaning the first sub-reset phase t4z covers both the first gate reset phase and the first data write phase. Alternatively, the first sub-reset phase t4z can be said to cover the first input phase t1 of the second driving circuit 10. Figure 34 The diagram illustrates that the pulse width of the enable level of the third control signal K3 in the first sub-reset stage t4z is greater than the pulse width of the enable level of the third control signal K3 in the other sub-reset stages t4z. The pulse width of the enable level is also the duration of the enable level. In other embodiments, the pulse width of the enable level of the third control signal K3 is equal in each sub-reset stage t4z.

[0125] In some embodiments, the pulse width of the enable level of the sub-reset phase t4z is equal to the pulse width of the enable level of the second scan signal PAM-S2, or the pulse width of the enable level of the sub-reset phase t4z is greater than the pulse width of the enable level of the second scan signal PAM-S2. In some embodiments, the pulse width of the enable level of the sub-reset phase t4z is greater than the sum of the pulse widths of the enable level of the second scan signal PAM-S2 and the pulse widths of the enable level of the first scan signal PAM-S1.

[0126] In some implementations, the pulse width of the enable level of the sub-reset phase t4z is equal to the pulse width of the enable level of the fourth scan signal PWM-S2, or the pulse width of the enable level of the sub-reset phase t4z is greater than the pulse width of the enable level of the fourth scan signal PWM-S2. In some implementations, the pulse width of the enable level of the sub-reset phase t4z is greater than the sum of the pulse widths of the enable levels of the fourth scan signal PWM-S2 and the third scan signal PWM-S1.

[0127] In some embodiments, the pulse width of the enable level of the sub-reset phase t4z is less than half the pulse width of the enable level of the first light emission control signal PWM-EM; and / or, the pulse width of the enable level of the sub-reset phase t4z is less than half the pulse width of the enable level of the first light emission control signal PWM-EM.

[0128] In some embodiments, the first driving circuit includes a first data writing module, the control terminal of which receives a fourth scan signal PWM-S2, and the first data writing module is configured to write a first data signal to the first driving circuit under the control of the voltage at its control terminal; the first data writing module includes, for example, Figure 29The first data writing transistor M3 is illustrated in the diagram. The gate of the first gate reset transistor M2 is connected to the gate of the second drive transistor M1, and the gate of the first gate reset transistor M2 receives the third scan signal PWM-S1.

[0129] The working cycle of the pixel circuit also includes a second gate reset stage and a second data writing stage set in sequence. The second gate reset stage is the gate reset stage t21 of the first driving circuit 10, and the second data writing stage is the data writing stage t22 of the first driving circuit 10.

[0130] Figure 35 Another signal timing diagram provided for an embodiment of the present invention, such as Figure 35 As shown, during the gate reset phase t21 of the first driving circuit 10, the third scan signal PWM-S1, at an enable level, controls the first gate reset transistor M2 to turn on and reset the gate of the second driving transistor M1. During the data writing phase t22 of the first driving circuit 10, the fourth scan signal PWM-S2, at an enable level, writes the first data signal PWM-Data to the gate of the second driving transistor M1. The first sub-reset phase t4z covers both the gate reset phase t21 and the data writing phase t22 of the first driving circuit 10. That is, the first sub-reset phase t4z covers both the second gate reset phase and the second data writing phase. Alternatively, the first sub-reset phase t4z can be said to cover the second input phase t2 of the first driving circuit 10.

[0131] In some embodiments, the first sub-reset stage t4z only covers the gate reset stage t21 during which the first driving circuit 10 operates. In some embodiments, the first sub-reset stage t4z only covers the data write stage t22 during which the first driving circuit 10 operates. In some embodiments, the first sub-reset stage t4z covers both the gate reset stage t21 and part of the data write stage t22 during which the first driving circuit 10 operates. No illustrations are provided in these embodiments.

[0132] In some embodiments, the gate of the first gate reset transistor M2 in the first driving circuit 10 receives the third scan signal PWM-S1, and the control terminal of the first data writing module (see the description of its structure in the above-mentioned related embodiments) receives the fourth scan signal PWM-S2. In the second driving circuit 20, the gate of the second gate reset transistor M8 receives the first scan signal PAM-S1; the control terminal of the second data writing module (see the description of its structure in the above-mentioned related embodiments) receives the second scan signal PAM-S2. The pulse width of the enable level of the third control signal K3 is greater than the pulse width of the enable level of at least one of the first scan signal PAM-S1, the second scan signal PAM-S2, the third scan signal PWM-S1, and the fourth scan signal PWM-S4. The enable level of the third control signal K3 controls the third transistor T3 to turn on, connecting the second constant voltage signal line VH2 to the first node N1. Therefore, the pulse width of the enable level of the third control signal K3 affects the maintenance time of the stable potential of the first node N1. The pulse width of the enable level of the third control signal K3 is set to be related to the pulse width of at least one of the aforementioned scan signals, which facilitates the combination of the enable level period of the third control signal K3 with the enable level period of the aforementioned scan signals. For example, if the pulse width of the enable level of the third control signal K3 is set to be greater than the pulse width of the enable level of the second scan signal PAM-S2, and the enable level period of the third control signal K3 at least covers the data writing phase t22 of the second driving circuit 20, then the conduction of the third transistor T3 during the data writing phase t22 can stabilize the potential of the first node N1, allowing the first capacitor C1 to be used as the storage capacitor of the second driving circuit 20, ensuring the accurate writing of the second data signal PAM-Data.

[0133] In some implementations... Figure 36 Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 36 As shown, the pixel circuit includes a first driving circuit 10, a second driving circuit 20, a first capacitor C1, a second capacitor C2, and a third transistor T3. In this embodiment, during at least a portion of the time when the first node N1 is in a floating potential state, the second capacitor C2 and the third transistor T3 can jointly stabilize the potential of the first node N1, ensuring the stable operation of the pixel circuit.

[0134] Figure 36 The diagram illustrates that the gate of the third transistor T3 receives the third control signal K3, and the gate of the electrode reset transistor M13 receives the second scan signal PAM-S2. In other embodiments, the gate of the electrode reset transistor M13 may receive the third control signal K3. Based on the description of the sub-reset stage in the above embodiments, it can be understood that the pixel circuit can then emit light multiple times after receiving the second data signal only once, thus improving the display flicker problem.

[0135] In other implementations, Figure 37 Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 37 As shown, the pixel circuit includes a first driving circuit 10, a second driving circuit 20, a first capacitor C1, a second capacitor C2, a third transistor T3, and a compensation module 30. The second capacitor C2 is used at least to stabilize the potential of the first node N1 during the period when the first node N1 is floating. The first plate of the second capacitor C2 is electrically connected to the first node N1, and the second plate of the second capacitor C2 is electrically connected to the compensation module 30. In the compensation module 30, the gate of the first transistor T1 receives a third control signal K3, and the gate of the second transistor T2 receives a second control signal K2. Based on the above description of the embodiment involving the compensation module 30, it can be seen that the compensation module 30 can compensate for the deviation of the first power supply voltage PAM-vdd that affects the driving current, so that the driving current is no longer affected by the deviation of the first power supply voltage PAM-vdd, thereby improving display uniformity. The pixel circuit provided by this embodiment has better stability.

[0136] Figure 37 The diagram also illustrates that the gate of the electrode reset transistor M13 receives the third control signal K3. Considering the aforementioned scheme involving multiple sub-reset stages and multiple sub-light emission stages, Figure 37 The embodiment also enables applications that emit light multiple times after a second data signal is input once.

[0137] In some implementations... Figure 38 Another pixel circuit schematic diagram provided in an embodiment of the present invention, such as... Figure 38 As shown, the pixel circuit includes a third transistor T3 and a fourth transistor T4. The gate of the third transistor T3 receives a third control signal K3, and the gate of the fourth transistor T4 receives a fourth control signal K4. The first terminal of the fourth transistor T4 is connected to the second constant voltage signal line VH2, and the second terminal of the fourth transistor T4 is connected to the first node N1. The third transistor T3 and the fourth transistor T4 are connected in parallel. In the second driving circuit 20, the gate of the second gate reset transistor M8 receives a first scan signal PAM-S1, and the gate of the second data writing transistor M9 receives a second scan signal PAM-S2. The fourth control signal K4 is the same as the first scan signal PAM-S1, and the second scan signal PAM-S2 is the same as the third control signal K3.

[0138] Figure 38 Implementation examples can be adopted Figure 4 Driven by the provided signal timing, combined with Figure 4In the gate reset phase t11 of the first driving circuit 10, the first scan signal PAM-S1, at an enable level, controls the second gate reset transistor M8 to reset the gate of the first driving transistor M7. Simultaneously, the fourth control signal K4, at an enable level, controls the fourth transistor T4 to turn on, connecting the second constant voltage signal line VH2 to the first node N1. This not only resets the first node N1 but also allows the first capacitor C1 to function as a storage capacitor during this phase. In the data writing phase t12 of the first driving circuit 10, the second scan signal PAM-S2, at an enable level, controls the writing of the second data signal to the gate of the first driving transistor M7. Simultaneously, the third control signal K3, at an enable level, controls the third transistor T3 to turn on, connecting the second constant voltage signal line VH2 to the first node N1. This not only resets the first node N1 but also allows the first capacitor C1 to function as a storage capacitor during this phase, ensuring the accuracy of the data writing.

[0139] In some implementations... Figure 39 Another signal timing diagram provided in this embodiment of the invention can be used to drive, such as Figure 24 The pixel circuit shown. (As shown in the image.) Figure 24 As illustrated, the gate of the second gate reset transistor M8 receives the first scan signal PAM-S1, and the gate of the second data write transistor M9 receives the second scan signal PAM-S2.

[0140] Combination Figure 39 As can be seen, the third control signal K3 is the same as the second scan signal PAM-S2; that is, the gate of the third transistor T3 and the gate of the second data write transistor M9 receive the same signal. Optionally, the gate of the third transistor T3 and the gate of the second data write transistor M9 can be connected to the same signal line.

[0141] In the gate reset stage t11 of the second driving circuit 20, the first scan signal PAM-S1 is at the enable level, controlling the second gate reset transistor M8 to turn on. In the data writing stage t12 of the second driving circuit 20, the second scan signal PAM-S2 controls the second data writing transistor M9 to turn on. Since the third control signal K3 is the same as the second scan signal PAM-S2, the data writing stage t12 of the second driving circuit 20 is the first sub-reset stage t4z. In this stage, the third control signal K3 controls the third transistor T3 to turn on to reset the first node N1 and maintain the potential of the first node N1 stable. In the sub-reset stage t4z after the first sub-reset stage t4z, the second scan signal PAM-S2 controls the second data writing transistor M9 to turn on. By controlling the data line not to transmit the second data signal, no new second data signal is written to the second driving circuit 20. Moreover, in this stage, the third control signal K3 controls the third transistor T3 to turn on to reset the first node N1. In this way, the light-emitting element LD can be controlled to emit light multiple times after one input of the second data signal.

[0142] In a display panel, the gate of the second gate reset transistor M8 is connected to the first scan signal line, which provides the first scan signal PAM-S1. The gate of the second data write transistor M9 is connected to the second scan signal line, which provides the second scan signal PAM-S2. Figure 40 This is a schematic diagram of a display panel circuit provided in an embodiment of the present invention. Figure 40 The pixel circuitry in the display panel is shown in a simplified diagram only, such as... Figure 40As shown, a first scan driving circuit 41 and a second scan driving circuit 42 are set in the display panel. Each scan driving circuit includes multiple cascaded shift registers (VSRs). The figure illustrates the nth-stage shift register VSR(n) and the (n+1)th-stage shift register VSR(n+1) in the first scan driving circuit 41, and also illustrates the nth-stage shift register VSR(n) and the (n+1)th-stage shift register VSR(n+1) in the second scan driving circuit 42, where n is a positive integer. The nth-stage shift register VSR(n) in the first scan driving circuit 41 is connected to the nth first scan signal line PAM-S1(n), and the (n+1)th-stage shift register VSR(n+1) is connected to the (n+1)th first scan signal line PAM-S1(n+1). In the second scan drive circuit 42, the nth stage shift register VSR(n) is connected to the nth second scan signal line PAM-S2(n), and the (n+1)th stage shift register VSR(n+1) is connected to the (n+1)th second scan signal line PAM-S2(n+1). That is, the first scan signal line is connected to the output of the shift register in the first scan drive circuit 41, and the second scan signal line is connected to the output of the shift register in the second scan drive circuit 42. This arrangement satisfies the design requirement that the gate of the third transistor T3 and the gate of the second data write transistor M9 receive the same signal. Furthermore, using different scan drive circuits to provide the scan signals reduces the load on the scan signal lines, which is beneficial for improving display uniformity.

[0143] In some implementations... Figure 41 Another signal timing diagram provided in this embodiment of the invention can be used to drive, such as Figure 38 The pixel circuit shown. Combined with... Figure 38 In this configuration, the fourth transistor T4 and the third transistor T3 are connected in parallel. The gate of the fourth transistor T4 receives the fourth control signal K4, and the gate of the third transistor T3 receives the third control signal K3. The third control signal K3 is the same as the second scan signal PAM-S2, and the fourth control signal K4 is the same as the first scan signal PAM-S1. Combined with... Figure 38 and Figure 41 The sub-reset stage t4z includes a gate reset stage t11 and a data writing stage t12, which are sequentially configured to operate the second driving circuit 20. In the gate reset stage t11, the first scan signal PAM-S1 is enabled, controlling the second gate reset transistor M8 and the fourth transistor T4 to turn on respectively. In the data writing stage t12, the second scan signal PAM-S2 is enabled, controlling the second data writing transistor M9 and the third transistor T3 to turn on respectively. This configuration allows the fourth transistor T4 and the third transistor T3 to share the original scan signal, simplifying the wiring in the display panel.

[0144] When applied in a display panel, a first scan signal line and a second scan signal line are arranged in the display panel. The first scan signal line provides the first scan signal PAM-S1, and the second scan signal line provides the second scan signal PAM-S2. The first scan signal line and the second scan signal line are respectively connected to two cascaded shift registers in a third scan drive circuit.

[0145] In other implementations, Figure 42 Another pixel circuit schematic diagram provided for the implementation of the present invention, such as Figure 42 As shown, in the first driving circuit 10, the first control transistor M6 is connected between the second driving transistor M1 and the first capacitor C1; the gate of the first control transistor M6 receives the first light-emitting control signal PWM-EM. In the second driving circuit, the second control transistor M11 is connected between the first power supply voltage line PAM-vdd and the first driving transistor M7, and the fourth control transistor M12 is connected between the first driving transistor M7 and the light-emitting element LD. The gate of the second control transistor M11 receives the first light-emitting control signal PWM-EM, and the gate of the fourth control transistor M12 receives the second light-emitting control signal PAM-EM.

[0146] In the pixel circuit, since the fourth control transistor M12 is connected to the light-emitting element LD, the load on the light-emitting control signal line connected to the gate of the fourth control transistor M12 is relatively large. In the embodiment of the present invention, the first light-emitting control signal PWM-EM that drives the first driving circuit 10 is introduced into the second driving circuit 20, and the gate of the second control transistor M11 is configured to receive the first light-emitting control signal PWM-EM. This can reduce the load on the light-emitting control signal line connected to the gate of the fourth control transistor M12, which is beneficial to improving display uniformity.

[0147] In some embodiments, the pixel circuit includes a first pixel circuit and a second pixel circuit, and the light-emitting elements include a first light-emitting element and a second light-emitting element with different emitting colors. The first pixel circuit is coupled to the first light-emitting element, and the second pixel circuit is coupled to the second light-emitting element. The voltage value of the second data signal received by the first pixel circuit is different from the voltage value of the second data signal received by the second pixel circuit. This embodiment can differentiate the voltage value of the second data signal based on the luminous efficiency differences of the light-emitting elements of different colors, which can help improve the color shift problem in the display.

[0148] In some embodiments, when the same color light-emitting element displays different gray levels, the voltage value of the second data signal written to the pixel circuit is equal. This embodiment controls the gray level displayed by the light-emitting element by controlling the flow period of the driving current.

[0149] In other embodiments, the voltage values ​​of the second data signals received by the pixel circuits coupled to different color light-emitting elements are equal during operation. This embodiment controls the grayscale displayed by the light-emitting elements by controlling the flow period of the driving current and compensates for the differences in luminous efficiency between different light-emitting elements.

[0150] In some implementations... Figure 43 This is another pixel circuit schematic diagram provided in an embodiment of the present invention, for comparison. Figure 9 From the examples, Figure 43 Implementation examples in Figure 9 The pixel circuit provided in this embodiment is further supplemented with a second capacitor C2 and a third transistor T3. The functions and operating periods of the second capacitor C2 and the third transistor T3 can be found in the descriptions of the relevant embodiments above, and will not be repeated here.

[0151] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the enable level is high and the disable level is low. That is, when the gate potential of an N-type transistor is high, its first and second terminals are connected; when the gate potential of an N-type transistor is low, its first and second terminals are turned off. For P-type transistors, the enable level is low and the disable level is high. That is, when the gate potential of a P-type transistor is low, its first and second terminals are connected; when the gate potential of a P-type transistor is high, its first and second terminals are turned off. In specific implementations, the gate of each transistor is used as its control electrode. Furthermore, depending on the signal and type of the gate of each transistor, its first terminal can be used as the source and its second terminal as the drain, or vice versa. No distinction is made here. The source and drain of a transistor can sometimes be used interchangeably, and sometimes the source and drain of a transistor can be collectively referred to as source-drain. In addition, the enable level in this embodiment is a general term, which refers to any level that enables a transistor to conduct.

[0152] Based on the same inventive concept, embodiments of the present invention also provide a display panel. Figure 44 This is a schematic diagram of a display panel provided in an embodiment of the present invention. The display panel includes multiple pixel circuits, which are the pixel circuits illustrated in any of the above embodiments. The structure of the pixel circuits has been described in the above embodiments and will not be repeated here.

[0153] Based on the same inventive concept, embodiments of the present invention also provide a display device, which includes the display panel provided in any embodiment of the present invention. The display device may be, for example, an electronic device with display functionality such as a mobile phone, tablet, computer, television, in-vehicle display, or smartwatch.

[0154] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0155] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A pixel circuit, characterized in that, include: First driving circuit, second driving circuit, first capacitor, and second capacitor; The first plate of the first capacitor is connected to the output terminal of the first driving circuit. The second plate of the first capacitor is connected to the second driving circuit; The first driving circuit is a pulse width modulation circuit; The second driving circuit is a pulse amplitude modulation circuit; The first plate of the first capacitor is connected to the output terminal of the first driving circuit at the first node; The first plate of the second capacitor is connected to the first node; The pixel circuit includes a first pixel circuit and a second pixel circuit, and the light-emitting element includes a first light-emitting element and a second light-emitting element with different light-emitting colors. The first pixel circuit is coupled to the first light-emitting element, and the second pixel circuit is coupled to the second light-emitting element. The capacitance value of the second capacitor in the first pixel circuit is different from the capacitance value of the second capacitor in the second pixel circuit.

2. The pixel circuit according to claim 1, characterized in that, The capacitance value of the second capacitor in the first pixel circuit is greater than the capacitance value of the second capacitor in the second pixel circuit. The first light-emitting element emits red light, and the second light-emitting element emits blue or green light.

3. The pixel circuit according to claim 1, characterized in that, The second plate of the second capacitor is connected to the first constant voltage signal line, which provides a constant voltage signal.

4. The pixel circuit according to claim 3, characterized in that, The second driving circuit includes a first driving transistor, a second control transistor, and a second gate reset transistor; The second control transistor is connected between the first power supply voltage line and the first terminal of the first driving transistor, and the first power supply voltage line provides the first power supply voltage; The second gate reset transistor is connected to the gate of the first driving transistor and provides a second reset signal to the gate of the first driving transistor; The first driving circuit includes a second driving transistor, a third control transistor, and a first gate reset transistor; The third control transistor is connected between the second power supply voltage line and the first terminal of the second driving transistor, and the second power supply voltage line provides the second power supply voltage. The first gate reset transistor is connected to the gate of the second driving transistor and provides a third reset signal to the gate of the second driving transistor; The pixel circuit is connected to the light-emitting element, the light-emitting element is connected to the third power supply voltage line, and the third power supply voltage line provides the third power supply voltage. The constant voltage is any one of the first power supply voltage, the second power supply voltage, the third power supply voltage, the second reset signal, and the third reset signal.

5. The pixel circuit according to claim 1, characterized in that, The second driving circuit includes a first driving transistor, and the second plate of the first capacitor is connected to the gate of the first driving transistor.

6. The pixel circuit according to claim 1, characterized in that, The second driving circuit includes a first driving transistor and a light emission duration control transistor, wherein the light emission duration control transistor is connected between the first driving transistor and the light emission element; The second plate of the first capacitor is connected to the gate of the light emission duration control transistor.

7. The pixel circuit according to claim 6, characterized in that, The second driving circuit further includes a light-emitting reset circuit, which is connected between the first reset signal line and the gate of the light-emitting duration control transistor; The light-emitting reset circuit is connected to the first reset signal line, receives the first reset signal, and is used to reset the gate of the light-emitting duration control transistor.

8. The pixel circuit according to claim 1, characterized in that, The pixel circuit includes a first pixel circuit and a second pixel circuit, and the light-emitting element includes a first light-emitting element and a second light-emitting element with different light-emitting colors. The first pixel circuit is coupled to the first light-emitting element, and the second pixel circuit is coupled to the second light-emitting element. The voltage value of the second data signal received by the first pixel circuit is different from the voltage value of the second data signal received by the second pixel circuit.

9. The pixel circuit according to claim 1, characterized in that, The pixel circuit must satisfy at least one of the following: The first driving circuit includes a second driving transistor, a first control transistor, a third control transistor, a first data writing transistor, a first compensation transistor, a first gate reset transistor, a fifth transistor, and a third capacitor; The third control transistor is connected between the second power supply voltage line and the first terminal of the second driving transistor. The first control transistor is connected between the second terminal of the second driving transistor and the output terminal of the first driving circuit. The first data write transistor is connected to the first terminal of the second driving transistor. The first compensation transistor is connected to the second terminal and the gate of the second driving transistor. The first gate reset transistor is connected to the gate of the second driving transistor. The first plate of the third capacitor is connected to the gate of the second driving transistor. The second plate of the third capacitor is connected to the sweep frequency signal terminal. The first terminal of the fifth transistor is grounded. The second terminal of the fifth transistor is connected to the second plate of the third capacitor. or, The second driving circuit includes a first driving transistor, a second control transistor, a fourth control transistor, a second data writing transistor, a second compensation transistor, a second gate reset transistor, and an electrode reset transistor. The second control transistor is connected between the first power supply voltage line and the first terminal of the first driving transistor. The fourth control transistor is connected between the second terminal of the first driving transistor and the light-emitting element. The second data write transistor is connected to the first terminal of the first driving transistor. The second compensation transistor is connected to the second terminal and the gate of the first driving transistor. The second gate reset transistor is connected to the gate of the first driving transistor. The electrode reset transistor is connected to the light-emitting element.

10. The pixel circuit according to claim 1, characterized in that, The first capacitor and the second capacitor share a common electrode.

11. A display panel, characterized in that, Includes the pixel circuit described in any one of claims 1-10.

12. A display device, characterized in that, Includes the display panel as described in claim 11.

Images