Ultra-high density low-profile edge card connector

Abstract

The present disclosure relates to ultra-high density, low profile edge card connectors. The present disclosure increases interconnect density by using a different technology approach than currently used in the industry (stamping and molding). By using a microelectromechanical system (MEMS) technology approach, better geometry and impedance control is achieved to reduce impedance discontinuities and feature sizes. In addition, the present disclosure also includes low connector insertion force, no contact wiping, and precise alignment mechanisms between the connector contacts and the connector contacts on the mating substrate.

Description

[0001] This application is a divisional application of the application patent application with the application date of September 4, 2019, the application number of 201910832300.9, and the invention name of "Ultra-high density low profile edge card connector".

[0002] Cross Reference to Related Applications

[0003] This application claims priority to U.S. Patent Application Serial No. 62 / 726,833 filed September 4, 2018, U.S. Patent Application Serial No. 62 / 727,227 filed September 5, 2018, and U.S. Patent Application Serial No. 62 / 812,492 filed March 1, 2019, the disclosures of each of which are incorporated by reference as if set forth in their entirety herein. TECHNICAL FIELD

[0004] The present application relates to connectors, and in particular to ultra-high density low profile edge card connectors. BACKGROUND

[0005] In the never-ending demand for network traffic growth, ASIC (application specific integrated circuit) switches, FPGAs (field programmable gate arrays) or microprocessors are increasing their IO (input / output) bandwidth capabilities and lane counts. At the same time, transistor sizes are getting smaller and smaller, with current process nodes having dropped from 12 nanometers to 7 nanometers. As a result, ASIC die sizes have remained almost constant, but their IO densities have increased dramatically. The challenge then becomes creating an electrical interface (i.e., twinaxial cable) or optical interface that is dense enough (less than 0.5 millimeter contact pitch, less than 2 millimeter lane density) to carry all of these lanes (512 lanes) at ultra-high speeds such as 112 gigabits per second per lane.

[0006] There is a need for connectors that can mate and unmate, that can support high bandwidth electrical signals and have high density, i.e., small pitch, between lanes. The connectors need to be compact so that they take up minimal space, making them easy to integrate with other electronic components and ancillary elements such as heat sinks that can need to be cooled during system operation. SUMMARY

[0007] In one aspect of the disclosure, a high density edge card electrical connector can include a flexible circuit having conductive traces formed on a surface of a flexible substrate. The electrical connector can further include a pressure plate configured to cause the flexible circuit to be pressed against electrical contact pads on a substrate to form electrical connections between the electrical contacts and the flexible circuit, thereby defining a separable interface between the electrical connector and the substrate.

[0008] In another aspect of the disclosure, an interconnect system can be configured to place an expansion card in electrical communication with an ASIC package substrate, the interconnect system including a separable interface between an expansion card substrate of the expansion card and the ASIC package substrate.

[0009] In another aspect of the disclosure, an electrical connector can include a flexible circuit having contact pads spaced apart from one another along a row direction at a contact pitch, the contact pitch being less than about 0.5 millimeters.

[0010] In another aspect of the disclosure, a locking mechanism for an interconnect system, the locking mechanism can include an electrical connector mounted on an edge of a printed circuit board. The interconnect system can further include a host printed circuit board supporting a substrate, wherein the substrate can be mated and unmated with the connector. The locking mechanism can be mounted on the host printed circuit board and can allow free movement in an insertion direction of the connector to the substrate, but prevents movement in a withdrawal direction, wherein the locking mechanism does not constrain the position of the printed circuit board in at least one direction.

[0011] In another aspect of the disclosure, an interconnect system includes an expansion card substrate defining a top surface and a bottom surface opposite the top surface along a lateral direction; and electrical contact pads disposed along an edge of the expansion card substrate on the top surface and the bottom surface, and the electrical contact pads are arranged along a row direction. The interconnect system can further include a top alignment block mounted to the top surface, wherein the top alignment block is mounted along the edge of the expansion card substrate on the top surface; wherein the top alignment block is in mechanical alignment with the contact pads on the top surface of the expansion card substrate. The interconnect system can further include a bottom alignment block, wherein the bottom alignment block is mounted along the edge of the expansion card substrate on the bottom surface, wherein the bottom alignment block is in mechanical alignment with the contact pads on the bottom surface of the expansion card substrate.

[0012] In another aspect of the disclosure, an interconnect system can include an electrical connector mounted to a first printed circuit board having a thickness. The interconnect system can further include a top flexible circuit and a bottom flexible circuit mounted to the printed circuit board and disposed on a top of the first printed circuit board and a bottom of the first printed circuit board, respectively, wherein an opening between leading edges of the two flexible circuits is sized greater than or equal to the thickness of the first printed circuit board.

[0013] In another aspect of the disclosure, an electrical interconnect system can include an IC package having an IC substrate and an IC die mounted to the IC substrate, wherein the IC substrate defines a top surface and a bottom surface opposite one another, and the IC package is mounted to a host substrate. The interconnect system can further include an electrical connector having electrical conductors in electrical communication with the opposite top surface and bottom surface of the IC substrate to establish electrical pathways between the electrical connector and the IC package that do not route first through the host substrate.

[0014] In another aspect of the disclosure, an optical transceiver can include an interposer defining a top surface and a bottom surface, and an optical fiber supported by one of the top surface and the bottom surface. The optical transceiver can also include an optical engine supported by the other of the top surface and the bottom surface, the optical engine including at least one light source, at least one light source driver, at least one photodetector, and at least one current-to-voltage converter.

[0015] In another aspect of the disclosure, an IC package can include an IC die, an IC package substrate having a top surface, a bottom surface opposite the top surface, and four edges defining a perimeter of the IC package, the IC die mounted on the top surface. The IC package can also include a row of electrical contacts of the IC package substrate at least one edge of the four edges, the electrical contacts of the row of electrical contacts distributed proximate the at least one edge on at least one of the top surface and the bottom surface of the IC package substrate.

[0016] In another aspect of the disclosure, an IC package can include an IC die, a rectangular IC package substrate having a top surface, a bottom surface opposite the top surface, and four edges defining a perimeter of the IC package, the IC die mounted on the top surface. The IC package can also include an electrical connector mounted proximate an edge of the IC package substrate. BRIEF DESCRIPTION OF DRAWINGS

[0017] The following detailed description will be better understood in conjunction with the appended drawings, of which the example embodiments are illustrated. It should be understood, however, that the application is not limited to the precise arrangements and instrumentalities shown herein. In the drawings:

[0018] Figure 1 An ASIC package mounted in a socket is shown with an edge card interface and three different interconnect interfaces on each side of the packaged die: a cable, a multimode optical engine, and a single mode optical engine;

[0019] Figure 2 A partial cutaway exploded perspective view of an ASIC die mounted on a socket is shown with contact pads on all four sides of the ASIC package adapted to mate with an ultra-high density edge card connector;

[0020] Figure 3 A simplified implementation of an ultra-high density edge card connector is shown;

[0021] Figure 4 An exploded view of a portion of an edge card connector is shown;

[0022] Figure 5A flexible circuit is shown with solder attached at one end (right end) and conductive malleable bumps for enhanced contactability at the other end (left end);

[0023] Figure 6 An exploded view of a pre-assembled expansion card with four flexible circuits and alignment blocks is shown;

[0024] Figure 7 A partial cutaway perspective view of an ultra-high density edge card connector is shown;

[0025] Figure 8A A schematic cross-sectional view of an electrical connector in an open or unclamped position is shown;

[0026] Figure 8B A schematic cross-sectional view of the electrical connector of Figure 8A in a closed or clamped position is shown;

[0027] Figure 9A A first step in docking an ultra-high density electrical connector to an ASIC package substrate is shown;

[0028] Figure 9B A second step in docking an ultra-high density electrical connector to an ASIC package substrate is shown;

[0029] Figure 9C A third step in docking an ultra-high density electrical connector to an ASIC package substrate is shown;

[0030] Figure 9D Details of various components of the electrical connector shown in Figures 9A-9C are shown in an open position;

[0031] Figure 9E Details of various components of the electrical connector shown in Figure 9D are shown in a closed position;

[0032] Figure 10A A partial top view of an ASIC package substrate and expansion card alignment principle is shown;

[0033] Figure 10B is a graphical illustration of an alignment principle to compensate for top-to-bottom metallization registration offset for an ASIC package substrate and expansion card;

[0034] Figure 10C is a schematic cross-sectional view of an expansion card showing top and bottom contact pads misaligned in a first direction and having an average position between the top and bottom contact pads;

[0035] Figure 10Dis a schematic cross-sectional view of an ASIC package substrate showing the top and bottom contact pads misaligned along a first direction and having an average position between the top and bottom contact pads;

[0036] Figure 10E is a schematic cross-sectional view of an ASIC package substrate showing the top and bottom contact pads misaligned along a second direction opposite the first direction and having an average position between the top and bottom contact pads;

[0037] Figure 11A is a side view of a core body having a flexible alignment feature;

[0038] Figure 11B is an enlarged perspective view of a portion of the core body showing the flexible alignment feature;

[0039] Figure 12 shows a locking mechanism that prevents withdrawal / disengagement of the expansion card;

[0040] Figure 13 is a side cross-sectional view of an interconnect system showing high speed electrical routing from an ASIC package to an expansion card;

[0041] Figure 14 shows a schematic perspective view of an electrically conductive pathway between an ASIC package substrate and an expansion card through a flexible circuit of ultra-high density electrical connectors;

[0042] Figure 15 is a cross-sectional view of an optical transceiver in one example;

[0043] Figure 16 is an exploded perspective view of an optical transceiver of another example;

[0044] Figure 17A is an exploded perspective view of an optical transceiver, a mid-layer, a plurality of light sources configured to align with the mid-layer, and a plurality of photodetectors configured to align with the mid-layer;

[0045] Figure 17B is a plan view of the mid-layer of Figure 17A showing light sources aligned with the mid-layer;

[0046] Figure 17C is a plan view of the mid-layer of Figure 17B and a light collection device configured to align with the mid-layer;

[0047] Figure 17D is a perspective view of a frame of the light collection device supporting Figure 17D at a location aligned with the mid-layer;

[0048] Figure 18 is a side cross-sectional view of an optical transceiver having an alternative heat dissipation system;

[0049] Figure 19A is a schematic front view of a heat dissipation system for an optical transceiver in one example;

[0050] Figure 19B is a schematic front view of a heat dissipation system for an optical transceiver in another example;

[0051] Figure 19C is a schematic front view of a heat dissipation system for an optical transceiver in yet another example;

[0052] Figure 19D is a schematic front view of a heat dissipation system for an optical transceiver in yet another example;

[0053] Figure 19E is a schematic front view of a heat dissipation system for an optical transceiver in yet another example;

[0054] Figure 20A is a perspective view of an ASIC package in one example having a flexible circuit directly connected to the ASIC package;

[0055] Figure 20B is a perspective view of a data communication system including Figure 20A the ASIC package shown;

[0056] Figure 21A is a perspective view of an ASIC package in one example having an electrical connector mounted therewith; and

[0057] Figure 21B is a perspective view of a data communication system including Figure 21A the ASIC package shown. DETAILED DESCRIPTION

[0058] The present disclosure relates to a low profile high bandwidth edge card connector of ultra-high density (less than 0.3 mm pitch). In addition, this interconnect approach allows the connection of the edge card connector to have low insertion force, low or no wiping effect between the contact pads and the contacts, and very low stub effect, which minimizes discontinuity and attenuation of signal integrity. A representative, but non-limiting, electrical contact pitch can have electrical contact patches of less than or equal to about 0.5 mm electrical contact pitch, resulting in a channel density of less than 2 mm. There can be 512 channels into and out of the ASIC package, each running at ultra-high speed, such as 112 gigabits per second per channel and having an asynchronous multi-source crosstalk worst case of no more than 6%.

[0059] Referring first to Figure 1 and 2Data communication system 20 can include an integrated circuit (IC) package 22, at least one data communication device 24 in electrical communication with IC package 22, and a host substrate 25. Host substrate 25 can be configured as a host printed circuit board (PCB). At least one data communication device 24 can be configured as at least one expansion card 27. As will be described in greater detail below, at least one expansion card 27 can directly interface with IC package 22. That is, when expansion card 27 is interfaced with IC package 22, an electrical pathway is established between expansion card 27 and IC package 22 without first routing through host substrate 25. IC package 22 can be mounted to host substrate 25 so as to place IC package in electrical communication with host substrate 25. In particular, data communication system 20 can include a socket 30 mounted to underlying host substrate 25. Socket 30 can be configured as a land grid array (LGA) socket. IC package 22 can be mounted to socket 30, thereby mounting IC package 22 to host substrate 25.

[0060] IC package 22 can include an IC package substrate 32 and an IC die 34 mounted on IC package substrate 32. IC package 22 can also include a plurality of serializer / deserializer (SerDes) dies 23. IC package 22 can also include an IC package lid 21 that is in thermal contact with IC die 34 and facilitates the transfer of heat from IC die 34 during operation. When IC package 22 is mounted to socket 30, IC die 34 is in electrical communication with host substrate 25. In some examples, (IC) package 22 can be configured as an application specific integrated circuit (ASIC) package 22. Accordingly, IC die 34 can be configured as an ASIC die 34, and IC package substrate 32 can be referred to as an ASIC package substrate 32. While ASIC package 22 referenced below includes ASIC die 34 and ASIC package substrate 32, it should be recognized that ASIC package 22 and its ASIC components can otherwise be referred to as IC package and its IC components. ASIC package substrate 32 can define a plurality of edges 28. Edges 28 can include a first longitudinal edge 29a and a second longitudinal edge 29b that oppose one another along a longitudinal direction L. Edges 28 can also include a first lateral edge 31a and a second lateral edge 31b that oppose one another along a lateral direction A that is perpendicular to longitudinal direction L. Lateral edges 31a and 31b can extend from first longitudinal edge 29a to second longitudinal edge 29b. Lateral edges 31a and 31b can be oriented perpendicular to longitudinal edges 29a and 29b such that ASIC package substrate 32 can define a rectangular shape.

[0061] The ASIC package substrate 32 can define a first surface 33a and a second surface 33b opposite one another along a transverse direction T perpendicular to both the longitudinal direction L and the lateral direction A. The first surface 33a can be disposed above the second surface 33b and can therefore be referred to as a top surface. The second surface 33b can be configured as a bottom surface 33b. All of the substrates disclosed herein can similarly define a top surface and a bottom surface opposite the top surface along the transverse direction T. The top surface of the main substrate 25 can face the bottom surface 33b of the ASIC package substrate 32. The top surface of the main substrate 25 can face the bottom surface of the expansion card 27. Further, all of the substrates disclosed herein can include longitudinal edges opposite one another along the longitudinal direction L and lateral edges opposite one another along the lateral direction A.

[0062] Accordingly, the ASIC die 34 can be in electrical communication with the main substrate 25 through the LGA socket 30. The ASIC package 22 can include a plurality of electrical conductors configured to mate with complementary electrical conductors of a complementary electrical assembly. In one example, the electrical conductors 36 are configured as electrical contact pads 38 carried by one or both of the first surface 33a and the second surface 33b. For example, the contact pads 38 can be disposed on one or more of up to all of the edges 29a-29b and 31a-31b of the ASIC package substrate 32. The complementary electrical assembly can be configured as the at least one electrical connector 26. The at least one electrical connector 26 can be mounted to the expansion card 27. The electrical connector 26 can be configured as an edge card connector.

[0063] The electrical connector 26 includes an electrically insulative connector housing 40 and a plurality of electrical contacts supported by the connector housing 40. As described below, the electrical contacts of the electrical connector 26 can be defined by at least one compliant electrical circuit 68 (see Figure 5 ). The connector housing 40 can define a socket 42 (see Figure 3 ) configured to receive one of the edges 29a-29b and 31a-31b to mate the electrical contacts with a respective one of the electrical contact pads 38 at one of the edges of the ASIC package substrate 32, and thereby also mate the respective expansion card 27 to the ASIC package. It can therefore be appreciated that the electrical connector 26 can be directly mated to the IC package 22. That is, when the electrical connector 26 is mated to the IC package 22, and in particular to the IC package substrate 32, an electrical pathway is established between the electrical connector and the IC package 22 without first routing through the main substrate 25.

[0064] The electrical connectors 26 mounted to the plurality of different expansion cards 27 can be mated to different edges 28 of the ASIC package substrate 32. For example, electrical connectors 26 mounted to three different expansion cards 27 can be mated to three edges of the ASIC package substrate 32, respectively. One or more electrical connectors 26 can be mounted to each expansion card 27 and mated to a respective one of the edges of the ASIC package substrate 32. The fourth edge of the ASIC package substrate 32 can be left unconnected, as desired. The LGA socket 30 can carry power and low speed control signals to the ASIC package 22. The electrical connectors 26 can support high speed signals. As noted above, the electrical connectors can be mounted to respective expansion cards 27 that support different high speed electronic components, such as memory, microprocessors, field programmable gate arrays (FPGAs), graphics processing units (GPUs), and support different types of transmission media.

[0065] The expansion cards 27 can take a variety of forms, including but not limited to: 1) electrical expansion cards 27a that are mounted with electrical cables 44 (e.g., twinaxial cables), 2) optical multi-mode (MM) expansion cards 27b that have one or more optical transceivers 116 mounted with multi-mode optical engines 46, and 3) optical single-mode (SM) expansion cards 27c that have one or more optical transceivers 117 mounted with single-mode optical engines 48. These can be silicon photonics based optical engines. The electrical cables 44 and the optical transceivers 116 and 117 can be referred to as examples of data communication devices. However, the data communication devices supported by the expansion cards 27 are not limited to the electrical cables 44 and the optical transceivers 116 and 117 shown.

[0066] The electrical expansion cards 27a can be considered passive expansion cards, while the optical multi-mode expansion cards 27b and the single-mode expansion cards 27c can be considered active expansion cards. The distinction between passive and active expansion cards is that active expansion cards typically include additional electrical contacts for power and control signals, and can also include electronic chips that boost or clean up high speed signals. These connections can be provided by secondary low speed connectors mounted on PCBs. Active expansion cards can also include opto-electronic or electro-optical conversion elements.

[0067] The expansion card 27 can be low-speed electrically connected through a secondary low-speed connector 50 on the host substrate 25 that mates with an electrical connector on a bottom surface of the expansion card 27. The low-speed connector can be removable from the host substrate 25, depending on the configuration of the expansion card 27. The expansion card 27a can include an electrical cable that extends along one or both of the top and bottom surfaces of the expansion card. When the electrical cable extends along the bottom of the expansion card 27a, the electrical cable can interfere with the secondary low-speed connector if present on the host substrate 25. Accordingly, in some examples, the electrical expansion card 27a can be configured as an active expansion card if an electrical driver is mounted to the expansion card 27a to extend its reach.

[0068] Referring now to Figure 3 As noted above, the ASIC package substrate 32 can include a plurality of contact pads 38 supported on one or both of the first and second surfaces 33a, 33b along one or more edges 28. The contact pads 38 can be dense. For example, the contact pads 38 can be arranged along a respective row direction 37 with a contact pitch ranging from about 0.2 millimeters to about 0.3 millimeters. The expansion card 27 supports the electrical connector 26 that is oriented such that the electrical contacts of the electrical connector 26 are arranged along a row direction that is parallel to an edge of the expansion card 27. The edges of the expansion card 27 can be disposed proximate to the respective edges 28 of the ASIC package substrate 32. It is to be understood that references herein to a size, dimension, shape, direction, or other parameter using the terms "approximately," "substantially," and "nearly" and derivatives thereof can include the recited size, dimension, shape, direction, or other parameter itself as well as a size, dimension, shape, direction, or other parameter within plus or minus 20% of the recited size, dimension, shape, direction, or other parameter, including plus or minus 10%, plus or minus 5%, and plus or minus 2% of the recited size, dimension, shape, direction, or other parameter.

[0069] According to one aspect of the disclosure, the electrical connector 26 can be kept low in a lateral (also referred to as a height) direction T. In one example, the height of the electrical connector 26 can be about 4 millimeters. The height of the electrical connector 26 that extends above the ASIC package substrate 32 when mated with the ASIC package substrate can be less than or equal to about 1.5 millimeters. Accordingly, in one example, the height of the electrical connector 26 that extends above the ASIC package substrate 32 when mated with the ASIC package substrate can be less than or equal to about one-half of the height of the electrical connector 26. Thus, the electrical connector 26 does not impede access to the top of the ASIC package 22. The data communication system 20 can include a heat dissipation component 52 (see Figure 20B), the heat dissipation component 52 can include one or both of an air-cooled heat sink or a liquid-cooled heat spreader to be disposed on top of the ASIC package 22 to facilitate cooling of the ASIC package 22. The data communication system 20 can further minimize any technical disruption on the ASIC package and maintain current production methods of the silicon die vendor.

[0070] With continued reference to Figures 1-3 , the data communication system 20 can further include at least one locking mechanism 54 that can be attached to the expansion card 27. The locking mechanism 54 can also be mounted to the main substrate 25 to secure the expansion card 27 once it is mated with the ASIC package substrate 32, preventing it from moving in a direction away from the ASIC package substrate 32 a distance sufficient to cause the expansion card 27 to become unmated from the ASIC package substrate 32. In one example, the locking mechanism 54 can substantially prevent movement of the expansion card 27 relative to the main substrate 25, and thus relative to the ASIC package substrate 32, as described in greater detail below. In one example, the locking mechanism 54 does not mechanically bind the expansion card 27 such that positioning of the expansion card 27 is controlled by alignment blocks 56 (see Figure 4 ) on the expansion card 27 that mate with alignment features of the electrical connectors 26, as described in greater detail below.

[0071] Referring now to Figures 3-4 , the expansion card 27 can be configured as an expansion card substrate 58 having a front edge 60. The expansion card substrate 58 can be configured as an expansion card PCB. The expansion card 27 can include a plurality of electrical contact pads 57 extending along the front edge 60 of the expansion card substrate 58. The substrate 58 can be an organic material, glass, ceramic, or other insulating material. The electrical contact pads 57 can be arranged in one or more rows extending in a row direction, and can be located on both a top surface and a bottom surface of the expansion card 27. The expansion card 27 can further include an alignment component 62 along the front edge 60. The alignment component 62 can be configured as an alignment notch 63 in the expansion card substrate 58. The alignment component 62 can be substantially centered about the front edge 60 of the expansion card substrate 58. Further, the alignment notch 63 can be larger than the slot in the alignment block 56. The alignment block 56 can be mounted near the front edge 60 of the expansion card substrate 58. On the top surface of the expansion card substrate 58 and on the bottom surface of the expansion card substrate 58, the expansion card 27 can include at least one alignment block 56. Similarly, the ASIC package substrate 32 can include at least one alignment block 56. The ASIC package can include at least one alignment block 56 on the top surface 33a of the ASIC package substrate 32 and at least one alignment block on the lower surface 33b of the ASIC package substrate 32.

[0072] The alignment pads 64 for aligning the block 56 can be disposed between adjacent sets of contact pads 57 on both the top and bottom of the expansion card substrate 58. The alignment pads 64 and the contact pads 57 can be fabricated on the expansion card substrate 58 during the same processing step, such that they are precisely positioned relative to one another. The processing step can be a photolithographic processing step. Size tolerances of less than about 10 microns can be achieved during the photolithographic processing step. The contact pads 57 can be configured as solder reflow pads suitable for soldering, or can be configured for ultrasonic, thermal ultrasonic, or any suitable other type of bonding, which results in a low impedance electrical pathway and mechanical bonding between the contact pads 57 and the conductive traces 66 on the flexible circuit 68 (see Figure 5 ).

[0073] Accordingly, the at least one flexible circuit 68 can be mechanically and electrically attached to the expansion card substrate 58. For example, the at least one flexible circuit 68 can be mechanically and electrically attached to a top surface of the expansion card substrate 58. In one example, a pair of flexible circuits 68 can be arranged in a side-by-side manner, mechanically and electrically attached to the top surface of the expansion card substrate 58. Further, the at least one flexible circuit 68 can be mechanically and electrically attached to a bottom surface of the expansion card substrate 58. In one example, a pair of flexible circuits 68 can be arranged in a side-by-side manner, mechanically and electrically attached to the bottom surface of the expansion card substrate 58.

[0074] The alignment block 56 can be secured to the alignment pads 64, thereby mounting the alignment block 56 to the expansion card substrate 58. For example, the alignment block 56 can be fixed to the alignment pads 64 using a surface mount technology (SMT) assembly process with a precision ranging from about 10 microns to about 50 microns, such as from about 30 microns to about 35 microns. Alternatively, the alignment block 56 can be secured to the alignment pads 64 using a die bonding process, which can have a precision ranging from about 1 micron to about 5 microns. It should be appreciated that any suitable alternative method can be used to secure the alignment block 56 to the expansion card substrate 58. The alignment block 56 can have an alignment tolerance with the contact pads 57 of the expansion card 27 that is within 5%, within 10%, or within 20% of the contact pad width. Such alignment tolerances can be on the order of a few microns to a few tens of microns. Thus, the alignment block can be precisely aligned with the contact pads 57, which along with other aspects of the present disclosure enables a small contact pitch of less than about 0.3 millimeters between the contact pads 57 in a plurality of contact pads 57 along a respective row, where the respective row is oriented along a row direction. The expansion card substrate 58 can also include at least one retainer component, which can be configured as a retainer notch 70 configured to receive a complementary retainer component of an electrical connector 26 mounted to the expansion card 27. For example, the expansion card substrate 58 can include a retainer notch 70 in each opposing edge of the expansion card substrate 58. A front edge of the expansion card substrate 58 having the contact pads 57 can extend between the opposing edges of the expansion card substrate 58.

[0075] Referring now to Figure 5 The flexible circuit 68 can be soldered or permanently attached to the expansion card substrate 58, thereby mounting the expansion card 27 to the electrical connector 26. The flexible circuit 68 can include a thin dielectric substrate 72, such as an organic or glass substrate. The substrate 72, and thus the flexible circuit 68, can be flexible and can be substantially planar in its un-flexed state. Alternatively, the substrate 72 can have some set curl or other non-planar shape. The flexible circuit 68 can be metalized, thereby defining conductive traces 74 on a first major surface 76a of the substrate 72. The conductive traces 74 can span almost the entire length of the flexible substrate 72. In one example, the length of the conductive traces 74 can be about 6 millimeters, although it should be appreciated that longer or shorter trace lengths can be used. A second major surface 76b opposite the first major surface 76a along the transverse direction T can be metalized to form a ground plane. The conductive traces 74 can include signal traces S, which can be arranged in pairs to form differential signal pairs 79 suitable for transmitting high-bandwidth electrical signals. The differential signal pairs 79 can be arranged as coplanar waveguide structures. The conductive traces can include at least one ground trace G disposed between adjacent signal traces.

[0076] When the ASIC package substrate 32 is inserted into the electrical connector 26 and the flexible circuit 68 is bent inward due to the structure of the electrical connector 26 described below, the flexibility of the flexible circuit 68 allows the flexible circuit 68 to contact the electrical contact pads 38 of the ASIC package substrate 32. In addition, as the electrical connection is made between the flexible circuit 68 and the ASIC package substrate 32, the individual conductive traces 74 along the edge of the flexible circuit 68 can vary in position along the transverse direction T to conform to variations in the height or flatness of the ASIC package substrate 32. This also enables substrates of different thicknesses to be in electrical communication with each other on opposite sides of the electrical connector 26.

[0077] The conductive traces 74 can terminate along one edge of the flexible circuit 68 at first electrical contact pads 75 adapted to be soldered to the reflow pads of the expansion card substrate 58 as described above. A solder mask can cover the flexible circuit 68 during the soldering process as desired. The mask can then be removed. Soldering is one of several methods available to provide a permanent electrical and mechanical connection between the flexible circuit 68 and the expansion card substrate 58. Gold-tin solder can be used to make such a connection, although other types of solder can also be used such as, but not limited to, tin-silver-copper (SnAgCu). The opposite ends of the conductive traces 74 can terminate at second electrical contact pads 77 adapted to form an electrical connection with the mating conductive contact pads 38 of the ASIC package substrate 32. The electrical contact pads 75 and 77 can be flexible or can be ductile conductive bumps having a height of 30 to 50 microns. This further enables any height variations in the ASIC package substrate contact pads 38 to be accommodated. In some embodiments, the contact pads 77 do not have a geometry distinguishable from the electrical traces and are defined by the respective ends of the electrical traces. It will thus be appreciated that the electrical connector 26 can include a plurality of electrical conductors. The electrical conductors can be defined by one or more of the conductive traces, the electrical contact pads 75, and the electrical contact pads 77. The electrical contact pads 75 can be referred to as first electrical contact pads and the electrical contact pads 77 can be referred to as second electrical contact pads. It will of course be appreciated that the electrical connector 26 can include any suitable alternative configuration of electrical conductors configured to place the ASIC substrate 32 in electrical communication with the expansion card substrate 58 as desired.

[0078] It will be appreciated that in one example, the individual contact pads 75 and 77 can be mechanically connected to each other by the flexible substrate 72. This eliminates the problem of a single flex finger that can otherwise cause the electrical connector 26 to be inoperable. Since the flexible circuit contact pads 75 and 77 are on a flexible circuit, the contact pads 75 and 77 do not need to be arranged in a straight line when the flexible circuit contact pads 75 and 77 are mated to another substrate. The flexible circuit 68 can be bent to accommodate bends or warpage in the mating substrate.

[0079] Referring now toFigure 6 The edge card connector 26 can include at least one flex circuit 68, at least one pressure plate 78, a core body 80, and a latch body 82. The flex circuit 68 can include conductive traces 74 (described above) in electrical communication with the conductive pads 57 of the expansion card 27. Figure 5 The at least one flex circuit 68 can be mounted to the expansion card substrate 58. For example, the at least one flex circuit 68 can be mounted to a top surface of the expansion card substrate 58, and the at least one flex circuit 68 can be mounted to a bottom surface of the expansion card substrate 58. In one example, a first pair of flex circuits 68 can be mounted to the top surface of the expansion card substrate 58, and a second pair of flex circuits 68 can be mounted to the bottom surface of the expansion card substrate 58. For the sake of clarity, other electrical components mounted to the expansion card substrate 58 are not shown, but various electrical components can in fact be mounted. That is, the expansion card 27 can be pre-assembled and can include a substrate with various electronic components already mounted to the card by soldering or suitable alternatives.

[0080] The core body 80 can be formed of a flexible, electrically insulating material, such as plastic. The core body 80 can fit over the flex circuits 68 and the expansion card substrate 58. The core body 80 can also include one or more retainer components configured to couple to retainer components of the expansion card substrate 58. For example, the core body 80 can include a retainer protrusion that is received in a retainer notch 70 of the expansion card substrate 58 (see Figure 4 The at least one pressure plate 78 can include at least one top pressure plate (e.g., a pair of top pressure plates) and at least one bottom pressure plate (e.g., a pair of bottom pressure plates). The pressure plates 78 can be formed of any suitable flexible material, such as metal. Each pressure plate 78 can bound a front end and a rear end opposite the front end. Each pressure plate 78 can include a plurality of springs 84 at the front end thereof. Each pressure plate 78 can also include an engagement flap 71 at the rear end thereof. A top notch 88 can be defined between the top pressure plates 78, and a bottom notch can be defined between the bottom pressure plates 78. The pressure plates 78 are configured to fit over the core body 80 and the flex circuits 68, such that each flex circuit 68 has its own pressure plate 78. The latch body 82 is configured to fit over the pressure plates 78. The engagement flaps 71 are configured to prevent the latch body 82 from disengaging from the rest of the connector 26 once the latch body 82 has been fitted over the pressure plates 78.

[0081] A method for mounting an electrical connector 26 to an expansion card 27 can include attaching a flex circuit 68 to the expansion card 27. For example, the flex circuit 68 can be soldered to a top surface and a bottom surface of the expansion card 27 near the front end, such that the flex circuit 68 (seeFigure 5 ) are mounted to corresponding contact pads 57 (see Figure 4 ) of the expansion card 27. The pressure plate 78 can be mounted to the core body 80. The expansion card 27 with the flex circuit 68 can be inserted into the core body 80, thereby defining an subassembly, with the flex circuit 68 being soldered to the expansion card 27. The latch body 82 can then be mounted to the subassembly, thereby completing the assembly of the expansion card 27. In particular, the latch body 82 is mounted on the pressure plate 78 and the core body 80.

[0082] Thus, as shown in Figure 7 , the latch body 82 forms an outer surface of a substantial portion of the electrical connector 26. The latch body 82 can define a receptacle 42 into which the ASIC package substrate 32 can be inserted. However, it should be appreciated that any desired substrate can be inserted into the receptacle 42. The latch body 82 can also include a disengagement hole 81 (see Figure 6 ) that extends through the top and bottom of the latch body 82, which enables the latch body 82 to be removed from the core body 80 as desired. The disengagement hole 81 can be aligned with a corresponding engagement stop 71 located inside the latch body 82.

[0083] The engagement stops 71 can be provided on corresponding outwardly facing surfaces of the pressure plate 78. The engagement stops 71 are accessible through the disengagement hole 81 in the latch body 82 (see Figure 6 ). When the ASIC package substrate 32 is inserted into the connector 26 and the connector 26 is in its closed or clamped position, the pressure plate 78 exerts pressure on the flex circuit 68 (see Figure 6 ), thereby pressing the flex circuit 68 against the ASIC package substrate 32. The pressure can be substantially uniform.

[0084] The notches 88 defined by the pressure plate 78 are configured to accommodate corresponding protrusions 92 of the core body 80 in order to selectively limit movement of the core body toward and away from the ASIC package substrate 32 (see Figure 3 ). In particular, the notches 88 can each define a track 91 along which the protrusions 92 translate when the core body is selectively translated toward and away from the ASIC package substrate 32. When the core body 80 has reached a limit of travel toward the ASIC package substrate 32, the protrusions 92 contact a surface of the pressure plate that defines a first end of the track 91. When the core body 80 has reached a limit of travel away from the ASIC package substrate 32, the protrusions 92 contact a surface of the pressure plate that defines an opposite second end of the track 91. Although in one example the pressure plate 78 defines the notches 88 and corresponding tracks 91, while the core body 80 defines the protrusions 92, in other examples the pressure plate 78 can define the protrusions 92, while the core body 80 can define the tracks 91.

[0085] Referring now to Figures 8A-8B , a cross-sectional view of the electrical connections between the expansion card substrate 58 and the ASIC package substrate 32 is shown. At least one top flexible circuit 68 is mechanically and electrically connected to the top surface of the expansion card substrate 58. For example, a pair of top flexible circuits are mechanically and electrically connected to the top surface of the expansion card substrate 58. At least one bottom flexible circuit 68 is electrically connected to the bottom surface of the expansion card substrate 58. For example, a pair of bottom flexible circuits are mechanically and electrically connected to the bottom surface of the expansion card substrate 58.

[0086] In Figure 8A the open position, the top and bottom flexible circuits 68 can be oriented substantially parallel to the top and bottom surfaces of the expansion card substrate 58, respectively. Alternatively, the top and bottom flexible circuits 68 can be slightly curled away from the top and bottom surfaces of the ASIC package substrate 32, respectively. Thus, the gap between the leading edges of the flexible circuits 68 in the lateral direction is greater than the thickness of the ASIC package substrate 32. In Figure 8B the closed position, each flexible circuit 68 is bent inwardly along the lateral direction toward the ASIC package substrate 32. In the closed position, the electrical traces 74 of the flexible circuits 68 (see Figure 5 ) are in electrical communication such that the electrical traces 74 are in electrical contact with the contact pads 38 of the ASIC package substrate 32, thereby mating the electrical connectors 26 with the ASIC package substrate 32. In particular, the electrical contact pads of the electrical traces 74 (see Figure 5 ) are in electrical communication with the contact pads 38 of the ASIC package substrate 32. Thus, in the closed or clamped position, the flexible circuits 68 form a continuous electrical pathway between the contact pads 38 of the ASIC package substrate 32 and the contact pads 57 of the expansion card substrate 58.

[0087] Various components of the electrical connector 26, such as the pressure plate 78 and the latch body 82, can facilitate the opening and clamping of the flexible circuits 68 relative to the ASIC package substrate 32. In particular, the spring tabs 84 of the pressure plate 78 (see Figure 6 ) are configured to bias the flexible circuits 68 against the ASIC package substrate 32. The spring tabs 84 can be shaped to cause the flexible circuits 68 to bend at a location between the expansion card substrate 58 and the ASIC package substrate 32, and can cause the flexible circuits 68 to be biased against the ASIC package substrate 32. In one example, the electrical connections of the expansion card 27 and ASIC package substrate system can be configured to have no conductive stubs, thereby improving signal integrity, which is particularly useful at high bandwidth data transfer speeds.

[0088] Furthermore, the contact pads 38 of the ASIC package substrate 32 and the contact pads 57 of the expansion card substrate 58 do not experience wiping as they are in electrical communication with the flex circuit 68. When the flex circuit 68 is mounted to the expansion card substrate 58, the contact pads 57 of the expansion card substrate 58 do not wipe the flex circuit 68. Furthermore, when the flex circuit 68 is mated to the ASIC package substrate 32, the contact pads 38 of the ASIC package substrate 32 do not wipe the flex circuit 68. In some examples, this reduces wear on the contacts during mating and unmating operations. Also, in some examples, the contact pads 38 and 57 do not experience mechanical loading in the mating / unmating direction. This enables the contact pads 38 and 57 to be sized smaller and placed closer together than traditional contacts, as they do not need to withstand the mechanical loading associated with wiping. The flex circuit 68 mounted to the expansion card substrate 58 and mated to the ASIC package substrate 32 can define a resulting connection system, which can be referred to as a "zero insertion force" connection system.

[0089] Referring now to Figures 9A-9C , the electrical connector is configured to place the expansion card substrate 58 in electrical communication with the ASIC package substrate 32. In particular, the expansion card substrate 58 is inserted into the electrical connector 26 along a respective insertion direction. The front edge 60 of the expansion card substrate 58 defines a front edge with respect to the insertion direction.

[0090] As noted above, the electrical connector 26 can include the latch body 82, the core body 80, which can define a connector housing having the receptacle 42, the pressure plate 78, and the flex circuit 68. The receptacle 42 is configured to receive the ASIC package substrate 32 when the ASIC package substrate 32 is mated with the electrical connector 26. In this regard, the receptacle 42 can be referred to as a mating receptacle. While in one example the mating receptacle 42 receives the ASIC package substrate 32 and the expansion card substrate 58 is mounted to the electrical connector 26, in another example, the mating receptacle 42 can receive the expansion card substrate 58 and the ASIC package substrate 32 can be mounted to the electrical connector 26. Thus, the electrical connector 26 can be mounted to one of the ASIC package substrate 32 and the expansion card substrate 58, and the electrical connector can be mated with the other of the ASIC package substrate 32 and the expansion card substrate 58.

[0091] As shown in Figures 9A-9B , the latch body 82 is shown in its "open" position, which allows the ASIC package substrate 58 to translate into the connector 26 (see Figure 7 ). In the open position of the latch body 82, the flex circuit 68 can extend substantially straight out from the expansion card 27, such that the ASIC package substrate 32 can be inserted into the electrical connector 26 without contacting the flex circuit 68 (seeFigure 9D Alternatively, the flexible circuit 68 can be manufactured with a slight bend, such that the opening between the top and bottom flexible circuits 68 is greater than the thickness of the expansion card substrate 58. Therefore, the ASIC package substrate 58 can be inserted into the electrical connector 26 without abutting the front edge of the flexible circuit 68, which would otherwise prevent insertion of the ASIC package substrate 58.

[0092] Next, the electrical connector 26 can be moved to its closed or clamped position. Specifically, the latch body 82 can be translated toward the expansion card substrate 58 to simultaneously latch the ASIC package substrate 32 and the electrical connector 26 together, and clamp the contact pads 38 of the ASIC package substrate 32 between the flexible circuits 68, thereby mating the flexible circuits 68 with the ASIC package substrate 32. In this regard, the electrical connector 26 can be inserted into the socket 42 and supported near the front edge 60 of the expansion card substrate 32. The ASIC package substrate 32 has electrical contact pads extending along one or more edges 28 of the ASIC package substrate 32 on one or both of its top and bottom surfaces. As will be described in more detail below, the expansion card substrate 58 can be prevented from moving away from the electrical connector 26.

[0093] During the clamping process, the latch body 82 can push the pressure plate 78 backward toward the expansion card base plate 58, thereby causing the pressure plates 78 to spring toward each other in the lateral direction, such as... Figure 9C and 9E As shown. The spring 84 along the leading edge of the pressure plate 78 can be configured to conform to the contours of the top and bottom surfaces of the ASIC package substrate 32. In some examples, the spring 84 can be configured to accommodate planarization variations in the ASIC package. Therefore, the spring 84 presses into the flexible circuitry 68, forcing it to face inward toward each other along the lateral direction T toward the ASIC package substrate 32. Thus, the flexible circuitry 68 is clamped to the ASIC package substrate 32, as shown in Figures 8 and 9E. The flexible circuitry 68 and the ASIC package substrate 32 define a separable interface that electrically connects the expansion card 27 to the ASIC package substrate 32, thereby electrically connecting the expansion card 27 to the ASIC die.

[0094] The ASIC package 22, the expansion card 27, and the electrical connector 26 can define an interconnect system that allows substrates of different thicknesses along the transverse direction T to be in electrical communication with each other through the electrical connector 26. For example, when the ASIC package substrate 32 has a range of thicknesses along the transverse direction T that can range from about 10% thicker than the thickness of the expansion card substrate along the transverse direction T to about 50% thinner than the thickness of the expansion card substrate along the transverse direction T, the flexible circuit 68 can be connected to the ASIC package substrate 32 and the expansion card substrate 58. In one particular non-limiting example, the thickness of the expansion card substrate 58 can be about 1.6 millimeters, and the thickness of the ASIC package substrate 32 can be about 1.2 millimeters. Thus, in some examples, the thickness of the ASIC package substrate 32 can be about 75% of the thickness of the expansion card substrate 58.

[0095] As described above, the contact pads 38 of the package substrate 32, the contact pads 57 of the expansion card 27, and the contact pads 75 and 77 of the electrical connector 26 can have a contact pitch along the row direction that is less than about 0.5 millimeters. For example, the contact pitch can range from about 0.2 millimeters to about 0.5 millimeters. In one example, the contact pitch can range from about 0.2 millimeters to about 0.3 millimeters. It will be appreciated that when the contact pitch is less than about 0.5 millimeters, new challenges are presented with respect to contact pad alignment at the interface between the contact pads. Such an interface can be defined between the contact pads 38 of the package substrate and the contact pads 77 of the flexible circuit 68, and thus between the contact pads 38 of the package substrate and the contact pads of the electrical connector 26. Such an interface can also be defined between the contact pads 57 of the expansion card 27 and the contact pads 75 of the flexible circuit 68, and thus between the contact pads 57 of the expansion card 27 and the contact pads of the electrical connector 26.

[0096] Contact pad alignment is generally dependent on the footprint of the substrate, the substrate top-to-bottom metallization registration, and the attachment mechanism of the expansion card. The alignment tolerance must be less than the contact width or the contact-to-contact pitch to ensure a secure electrical connection between the contacts on both sides of the interconnect system. Referring now to FIG. 4, a cross-sectional view of the interconnect system of FIG. 1 is shown, according to one non-limiting example. Figures 10A-10BThe interconnect system, and thus the data communication system 20, includes alignment blocks 56 precisely placed on the ASIC package substrate 32 and the expansion card substrate 58. The alignment blocks 56 can be precisely die-bonded or reflow soldered to the ASIC package substrate 32 and the expansion card substrate 58 by standard SMT production tools. Each of the substrates 32 and 58 can include at least one alignment block 56. For example, each of the substrates 32 and 58 can include at least one alignment block 56 on a bottom surface thereof, and at least one alignment block 56 on a top surface thereof. In one example, each of the substrates 32 and 58 can include a respective single alignment block 56 on a top surface thereof, and a respective single alignment block 56 on a bottom surface thereof. As will be appreciated from the following description, the alignment blocks 56 on both the top and bottom surfaces can help compensate for possible misalignment between the metallization layers on the top and bottom surfaces of the substrates 32 and 58.

[0097] Referring also to Figure 10A and 10B The electrical connector 26 is configured to align the contact pads 38 of the ASIC package substrate 32 with the contact pads 57 of the expansion card substrate 58 having the flexible circuits 68. Specifically, for each interface between a contact pad 38 at the top surface of the ASIC package substrate 32 and a contact pad 77 of at least one top flexible circuit 68, and further for each interface between a contact pad 38 of the bottom surface of the ASIC package substrate 32 and a contact pad 77 of at least one bottom flexible circuit 68, at least one flexible alignment structure of the core body 80 is configured to average the position of the top and bottom metallization along the row direction on both the ASIC package substrate and the expansion card substrate, thereby reducing the misalignment amplitude.

[0098] As described above, the alignment block 56 can be mounted to the top surface as well as the bottom surface of one or both of the ASIC package substrate 32 and the expansion card substrate 58. The alignment block 56 can include alignment features 93, such as slots 94, that are configured to receive flexible alignment features 95, such as flexible walls 96 of the core body 80. For example, the flexible walls 96 can extend from a surface of the core body 80. The distal ends of the flexible walls 96 can be received in the aligned slots 94 of the alignment block 56. If the alignment block 56 is not perfectly aligned with the flexible walls 96, the flexible walls can elastically deform or flex in order to be received in the slots 94, accommodating the misalignment. The ASIC package substrate 32 and the expansion card substrate 58 will thus be urged into a respective position along the row direction under the flexing force applied by the flexible walls 96 to the alignment block 56 and thus to the expansion card 27 as well as under the counter force applied by the alignment block 56 to the flexible walls 96. Thus, the flexing force of the flexible walls 96 and the associated flexing is averaged. As a result, the movement of the ASIC package substrate 32 and the expansion card substrate 58 along the row direction relative to each other is also averaged to minimize the misalignment between the contact pads 57 of the expansion card substrate 58 and the contact pads 75 of the flexible circuit 68. This also minimizes the overall misalignment between the contact pads 38 of the ASIC package substrate 32 and the contact pads 57 of the expansion card substrate 58.

[0099] It will of course be appreciated that the alignment features of the core body 80 can alternatively be configured as slots and the alignment features of the alignment block 56 can be configured as flexible walls configured to be received in the recesses.

[0100] In Figure 10B one example shown, there is a first misalignment distance R h along the row direction between the top contact pads and the bottom contact pads 38 of the ASIC package substrate 32. That is, the contact pads 38 on the bottom surface and the contact pads 38 on the top surface are not perfectly aligned and the misalignment distance is R h . Similarly, there is a second misalignment distance R p along the row direction between the top contact pads 57 on the top surface of the expansion card substrate 58 and the bottom contact pads 57 on the bottom surface of the expansion card substrate 58. The alignment features on the first side of the separable interface including the ASIC package substrate 32 and the alignment features on the second side of the separable interface including the expansion card 27 cause the core body 80 to be intermediate the two misalignment distances R h and R p along the row direction. Thus, the overall misalignment between the respective contact pads of the ASIC package substrate 32 and the expansion card substrate 58 is the average of the misalignments or R 总体 = (R h + R p2. The typical maximum misalignment between the top and bottom contact pads on both the ASIC package substrate 58 and the expansion card substrate 32 can be approximately 37.5 micrometers. As a non-limiting assumption, a worst-case misalignment occurs if the misalignment has opposite orientations. That is, the bottom contact pad on the ASIC package substrate 58 is displaced to the right or left, and the contact pads on the expansion card substrate 58 are displaced to the left or right (opposite to the direction on the ASIC package substrate 58). In this case, because both the ASIC package substrate and the expansion card substrate have this amount of misalignment, the misalignment along the row direction between the contact pads 38 of the ASIC package substrate 32 and the contact pads 57 of the expansion card substrate 58 will also be approximately 37.5 micrometers. For contact pitches in the range of approximately 200 to 300 micrometers, misalignment caused by the interconnect system will not significantly affect the electrical performance of the electrical connector 26.

[0101] Now refer to Figure 10C The top contact pad 57 and the bottom contact pad 57 of the expansion card substrate 58 are not aligned in the first relative direction. Figure 10C The average position 97 between the left edges of the top and bottom contact pads 57 is also shown. Figure 10D The top contact pad 38 and bottom contact pad 38 of the ASIC package substrate 32 are shown. The misalignment between the top contact pad 38 and the bottom contact pad 38 of the ASIC package substrate 32 in a first relative direction is a first distance, which is the same as the misalignment distance between the contact pad 57 of the expansion card substrate 58. Therefore, Figure 10D The average position 98 between the top contact pad and the bottom contact pad 38 Figure 10C The average position 97 between the top and bottom contact pads 57 is the same. Therefore, when misaligned with the same orientation and distance on the ASIC package substrate 32 and the expansion card substrate 58, both the top and bottom contact pads 38 of the ASIC package substrate 32 will be perfectly aligned with the corresponding top and bottom contact pads 57 of the expansion card 27. The corresponding top and bottom contact pads 57 of the expansion card 27 are electrically connected to the top and bottom contact pads 38 respectively via the electrical connector 26. (Refer to...) Figure 10E The misalignment distance between the top contact pad and the bottom contact pad 38 of the ASIC package substrate 32 is the same as the misalignment distance between the top contact pad and the bottom contact pad 57, but the misalignment between the top contact pad and the bottom contact pad 38 of the ASIC package substrate 32 is in a second relative direction opposite to the first relative direction. In this case, the average position will be in the middle (midway) between the first distance of the first relative orientation and the first distance of the second relative orientation.

[0102] Now for reference Figures 11A-11BThe core body 80 can include a top portion 81, a middle portion 83, and a bottom portion 85. The middle portion 83 is disposed between the top portion 81 and the bottom portion 85 along the transverse direction T. The core body 80 can define an upper slot 87 between the top portion 81 and the middle portion 83. The core body 80 can define a lower slot 89 between the bottom portion 85 and the middle portion 83. As noted above, the core body 80 can include the flexible alignment features 95. For example, the middle portion 83 can include the flexible alignment features 95. However, it should be appreciated that the flexible alignment features 95 can be disposed at any suitable alternative location of the core body 80 as desired. When the core body 80 receives the expansion card substrate 58 as described above, the top flexible circuit 68 extends through the upper slot 87, and the bottom flexible circuit 68 extends through the lower slot 89. The slots 87 and 89 can extend along the entire width of the expansion card substrate 58 along the row direction, and can further extend along the entire width of the ASIC package substrate 32 along the row direction.

[0103] Reference is now made to Figure 11B In particular, the flexible alignment features 95 of the core body 80 can include at least one flexible wall 96 that extends above and below the middle portion 83 along the transverse direction T. The at least one flexible wall 96 can extend to the top portion 81 and the bottom portion 85. The at least one flexible wall 96 can further protrude from the middle portion 83 in directions toward and away from the expansion card substrate 58. The at least one flexible wall 96 can have a first wall portion adjacent to the expansion card substrate 58 that is received in the engagement blocks 56 on the top and bottom surfaces of the expansion card substrate 58 in the manner described above. The first wall portion can be disposed at a first end of the at least one wall 96. The at least one wall 96 can define a second wall portion opposite the expansion card substrate that engages the alignment blocks 56 on the top and bottom surfaces of the ASIC package substrate 32 when the electrical connector 26 is mated with the ASIC package 22 as described above. As previously noted, the at least one wall can flex and twist so as to average out misalignments between the contact pads 57 on the expansion card substrate 58 and the contact pads 38 on the ASIC package substrate 32. In one example, the at least one flexible wall 96 can include a first flexible wall and a second flexible wall 96 spaced apart from one another along the row direction. The row direction can be perpendicular to the mating direction of the electrical connector 26 with the ASIC package substrate 32, and thus perpendicular to the direction from the ASIC package substrate 32 to the expansion card 27.

[0104] Reference is now made to Figure 12 And as described above, the expansion card 27 can be locked in place relative to the ASIC package substrate 32 when the electrical connector 26 is mated with the ASIC package substrate 32. For example, as described above with respect to the described Figures 1-3As shown, the locking mechanism 54 can be attached to the expansion card 27 and mounted to the host substrate 25, thereby securing the expansion card 27 once mated with the ASIC package substrate 32, preventing it from moving in a direction away from the ASIC package substrate 32 a distance sufficient to cause the expansion card 27 to be unmated from the electrical connectors 26, which would cause the electrical connections between the expansion card 27 and the ASIC package substrate 32 to be removed. The locking mechanism 54 can allow the expansion card 27 to move toward the electrical connectors 26, and thus toward the ASIC package substrate 32, to cause the expansion card 27 to be mated to the electrical connectors 26. The locking mechanism 54 can allow one-way movement of the expansion card 27, such that the locking mechanism 54 prevents retraction / unmating of the expansion card 27. Thus, the locking mechanism 54 can allow the expansion card substrate 58 to move freely into the electrical connectors 26, but prevent retraction of the expansion card 27.

[0105] The expansion card 27 can be disconnected from the electrical connector 26 by actuating the release member 99. The release member 99 can be configured as a release button that can be pressed to allow the expansion card 27 to be retracted a distance sufficient to allow the expansion card 27 to be removed from the electrical connector 26. The locking mechanism 54 can include a locking body 102 having an opening 104 that is sized to receive the expansion card substrate 58 such that the expansion card substrate 58 can be moved relative to the locking body 102 in the transverse direction T. The locking mechanism 54 can also include at least one engagement member above and below the expansion card substrate 58 that is configured to prevent movement of the expansion card substrate 58 away from the electrical connector 26. The engagement member can be configured as a cylinder 106 disposed above and below the expansion card substrate 58 that is configured to be free to rotate between the release member 99 and the locking body 102. The cylinder 106 can be driven into the expansion card substrate 58 by a wedge surface 108 of a corresponding wedge 109 of the locking body 102, effectively clamping the expansion card substrate 58 in place. For example, when a rearward force is applied to the expansion card 27 to remove the expansion card 27 from the electrical connector 26, the expansion card 27 causes the cylinder 106 to rotate along the wedge surface 108, causing the cylinder to travel toward the expansion card 27 until the cylinder effectively clamps the expansion card 27 and prevents movement of the expansion card 27 away from the electrical connector 26. In addition, the locking mechanism 54 can include a spring tab member 105 that will urge the wedge 109 toward the cylinder 106, causing the wedge surface 108 to push the cylinder 106 against the expansion card substrate 58, biasing the expansion card substrate 58. When the release member 99 is actuated, the spring tab member 105 disengages from the wedge member 99. Advantageously, relative to some examples of locking mechanisms 54, the above-described locking mechanism 54 does not require any precise height or position along the direction of travel of the expansion card 27. Thus, the expansion card 27 can be positioned in the connector 26 in the above-described manner defined by the alignment block 56, rather than defined by the locking mechanism 54. Accordingly, electrical connections can be maintained through all of the contact pads of the electrical connector 26. In addition, the locking mechanism 54 can not require precise positioning of the expansion card substrate 58 relative to the main substrate 25 along the transverse direction T. The locking system can function as described above with any positioning of the expansion card substrate 58 that fits through the opening 104.

[0106] Referring now to Figure 13 The interconnect system 101 can define an electrical transmission line 110 that is configured to support high bandwidth signals between the ASIC package substrate 32 and the expansion card substrate 58 of the type described above. For example, a high bandwidth signal can travel from the ASIC package substrate 32 to the expansion card substrate 58. Alternatively or additionally, a high bandwidth signal can travel from the expansion card substrate 58 to the ASIC package substrate 32. As previously described with respect to the interconnect system 101, the electrical transmission line 110 can be configured to support high bandwidth signals between the ASIC package substrate 32 and the expansion card substrate 58 in either direction. Figure 2As described, the LGA socket 30 can be mounted to the host substrate 25. The ASIC package 22 having the ASIC die 34 can be mounted on the ASIC package substrate 32. Further, if desired, a serializer / deserializer (SerDes) die 23 can be mounted on the ASIC package substrate 32. The ASIC package substrate 32 can at least partially define a plurality of differential pair transmission lines 110 that can route high bandwidth signals from the SerDes die 23 to contact pads 38 disposed along respective edges 28 of the ASIC package substrate 32. The ASIC package substrate 32 can include conductive vias 114 extending from a top surface to a bottom surface of the ASIC package substrate 32, and thus can route electrical signals to both the top and bottom surfaces of the ASIC package substrate 32.

[0107] As described above, the electrical connector 26 can be adapted to a respective one of the edges 28 of the ASIC package substrate 32 to place the ASIC package substrate 32 in electrical communication with the expansion card 27, and thus the ASIC die 34 in electrical communication with the expansion card 27. The flexible circuit 68 of the electrical connector 26 can establish a separable interface with the electrical contact pads to which the electrical connector 26 is mated. In one example, the electrical connector 26 can be mated with the ASIC package substrate 32. Thus, the flexible circuit 68 can be in removable electrical communication with the contact pads 38 of the ASIC package substrate 32. The electrical communication between the contact pads 38 of the ASIC package substrate 32 and the flexible circuit 68 can define a separable interface, and can be mated and unmated as desired. That is, the interconnect assembly does not prevent the ASIC package substrate 32 from being removed from the electrical connector in order to unmate the ASIC package substrate 32 from the flexible circuit 68. The flexible circuit 68 is configured to make permanent electrical contact with the contact pads to which the electrical connector 26 is mounted. In one example, the electrical connector 26 can be mounted to the expansion card 27. Thus, the flexible circuit 68 can be configured to make permanent electrical connections with the contact pads 57 of the expansion card substrate 58. That is, the expansion card 27 is prevented from being removed from the electrical connector without actuating the release member 99 described above. The plurality of differential pair transmission lines 110 can route high speed electrical signals to and from the contact pads 57 of the expansion card substrate 28 to other areas of the expansion card 27. Figure 12 The plurality of differential pair transmission lines 110 can route high speed electrical signals to and from the contact pads 57 of the expansion card substrate 28 to other areas of the expansion card 27.

[0108] Referring now to Figure 14 , the interconnect system is shown schematically showing the expansion card substrate 58 in electrical communication with the ASIC package substrate 32 through the at least one flexible circuit 68. In particular, the transmission lines 110 (see Figure 13 ) are configured to define continuous transmission lines 110 through and between the ASIC package substrate 32 and the expansion card substrate 58.

[0109] While this disclosure has generally described in context the establishment of a separable interface (i.e., an electrical connection capable of mating and disassembling) between expansion card substrate 58 and ASIC package substrate 32, it is understood that the electrical connector 26 and associated electrical connection methods described herein can be used in any situation where high-bandwidth electrical signals are transmitted between two generally planar substrates having contact pads along their respective edges. In some examples, the respective edges may face each other. Aspects of this disclosure can be particularly advantageous when a high overall data transfer rate across the electrical connection is desired. A high overall data transfer rate is provided when adjacent contact pads have a high density, which is defined by the small contact pitch between adjacent contact pads along the row direction and the continuity of the electrical transmission path with minimal impedance discontinuity.

[0110] like Figure 15 As shown, optical engine 118 may be included in optical transceiver 116. Optical engine 118 of optical transceiver 116 is configured to receive an electrically transmitted signal from ASIC package 22, convert the electrically transmitted signal into an optical transmitted signal, and output the converted optical transmitted signal to a second component. Optical engine 118 may be further configured to receive an optically received signal from a third component, convert the optically received signal into an electrically received signal, and output the converted electrically received signal for transmission to ASIC package 22. Optical transceiver 116 may include a plurality of optical fibers 120, including one or both of optical transmitting fiber 122 and optical receiving fiber 124. The optically transmitted signal may be transmitted along optical transmitting fiber 122 to the second component. The optically received signal may be received from the third component along optical receiving fiber 124.

[0111] Optical transceiver 116 includes an optical transmitter 126 and an optical receiver 128. When expansion card 27 is electrically connected to ASIC package substrate 32, optical transmitter 126 and optical receiver 128 can be coupled between ASIC package 22 and a second component, respectively. Optical transmitter 126 can be configured to receive an electrical transmission signal from ASIC package 22, convert the electrical transmission signal into an optical transmission signal, and output the converted optical transmission signal for transmission to the second component. Optical receiver 128 can be configured to receive an optical reception signal from a third component, convert the optical reception signal into an electrical reception signal, and output the converted electrical reception signal for transmission to ASIC package 22. Electrical signals can be transmitted along expansion card substrate 58 to and from ASIC package substrate 32 and optical transceiver 116. Figure 16 As shown, transmitter 126 is illustrated, which can be understood as follows: Figure 16 The device can be alternatively configured as receiver 128.

[0112] The optical transceiver 116 can include an optical engine 118 of one or both of an optical transmitter 126 and an optical receiver 128. The optical engine 118 can be supported by an optical interposer 130, which is provided for the light to travel through. The interposer 130, in turn, can be supported by the expansion card 27. Further, the interposer 130 can be mounted to the expansion card 27, such as to a top surface of the expansion card 27. In one example, solder balls 133 can mount the interposer 130 to the expansion card 27. However, it should be appreciated that the interposer 130 can be mounted to the expansion card 27 in any suitable alternative manner.

[0113] In one example, the interposer 130 can be a glass interposer 130. The optical transceiver 116 can include an optical coupler 132 configured to support the optical fiber 120. The optical transceiver 116 can further include a frame 134 that supports the optical coupler 132. The frame 134 can be mounted to the interposer 130. For example, the frame 134 can be mounted to a top surface of the interposer 130. Thus, in one example, the frame 134, and thus the optical coupler 132 and the optical fiber 120, can be supported on a top surface of the interposer 130. The optical engine 118 can be supported on a bottom surface of the interposer 130 opposite the top surface. Thus, the optical fiber 120 can be supported on a first surface of the interposer 130, and the optical engine 118 can be supported on a second surface of the interposer 130 opposite the first surface along the transverse direction T.

[0114] The optical engine 118 of the optical transmitter 126 can further include at least one light source 136, such as a plurality of light sources 136 that emit light that is directed to the optical transmit fiber 122. In one example, the light sources 136 can be configured as any suitable diode laser. For example, the light sources 136 can be configured as lasers, preferably emitting wavelengths ranging from about 760 nanometers (nm) to about 1600 nm. The lasers can be configured as vertical cavity surface emitting lasers (VCSELs) 138, distributed feedback (DFB) lasers, or Fabry-Perot (FP) lasers. The optical transmitter 126 can include at least one driver 131 that converts voltage modulation to current modulation in order to modulate light from the light sources 136 based on electrical signals received from the ASIC package 22.

[0115] The optical transmitter 126 can include a plurality of optical transmit fibers 122 that are optically aligned with the optical engine 118 of the optical transmitter 126, and in particular, with the light source 136. Thus, the optical transmit fibers 122 are configured to receive respective optical transmit signals output by the optical engine 118 of the transmitter 126 and transmit the optical transmit signals to the second component. The fiber coupler 132 is configured to support the optical transmit fibers 122 such that the input ends of the optical transmit fibers 122 are optically aligned with the light output by the optical engine (and in particular, from the light source 136) of the transmitter 126. Thus, the input ends of the optical transmit fibers 122 are configured to receive optical transmit signals from the optical engine 118 of the transmitter 126. In some embodiments, the optical coupler 132 can include a transmit reflector 141. The optical transmit signals output from the light source 136 can be directed along a first transmit direction to the transmit reflector 141 and along a second transmit direction that is offset by an angle relative to the first transmit direction to the input ends of the optical transmit fibers 122. The first transmit direction can be oriented substantially along the transverse direction T. The transmit reflector 141 can be metallic, a multi-layer dielectric coating, an uncoated total internal reflection surface, or made of any suitable alternative reflective material or interface as desired.

[0116] It can be desirable to converge the beam of the optical transmit signals near the input ends of the optical transmit fibers 122 such that the optical transmit signals are mode matched with the optical transmit fibers 122. In one example, one or more optical transmit elements can be disposed between the light source 136 and the optical transmit fibers 122. These intervening optical transmit elements can include one or more of a mirror, a lens, a transparent substrate, and an optically transparent coupler that collectively provide an optical path between the light source 136 and the optical transmit fibers 122.

[0117] By way of example, the transmitter 126 can include one or more lenses through which the optical transmit signals are transmitted in order to control the beam size of the optical transmit signals. For example, a first optical transmit lens 140 can be supported on the top surface of the interposer 130 in alignment with the light source 136. Thus, the optical transmit signals pass through the first optical transmit lens 140. A second optical transmit lens 142 can be supported by the frame 134 in alignment with the first optical transmit lens 140. Alternatively, the optical transceiver 116 can include one of the first optical transmit lens 140 and the second optical transmit lens 142 without including the other of the first optical transmit lens 140 and the second optical transmit lens 142.

[0118] In one example, the first transmit lens 140 can be configured as a collimating lens. Thus, the light emission signal can be collimated from the first light emission lens 140 to the second light emission lens. This can accommodate alignment tolerances between the light emission fiber 122 and the light source 136. The second transmit lens 142 can be configured as a focusing lens. Thus, the light emission signal can be converging in a direction from the at least one light emission lens 140 to the input end of the light emission fiber 122. In one example, the second light emission lens 142 can be supported on a bottom surface of the frame 134 that faces a top surface of the interposer 130. The collimating lens and the converging lens can be placed in any location as desired. In other examples, the light emitter 126 can include the transmit lens 142 supported by the frame 134 but not the transmit lens 140 supported by the interposer 130. In this example, the transmit lens 142 supported by the frame 134 can be configured as a focusing lens. It should be appreciated that the light emitter 126 can include any number of lenses as desired.

[0119] The second light emission lens 142 supported by the frame 134 can be configured as a transmit optical lens array 144 that includes an optical block 143 and a plurality of transmit lenses 142 supported by the optical block 143. In this regard, it should be appreciated that the lenses 142 (see Figure 17C ) of the lens array 144 can be configured to shape the light emission signal emitted from the plurality of light sources 136. The light emitter 126 can also include one or more monitoring photodiodes (MPD) 129 that can receive a portion of the light generated by the light sources 136 to monitor the light output. As will be described in greater detail below, the interposer 130 can include an alignment component configured to align the emission optical block with the light sources 136 along a direction that is perpendicular to the lateral direction T.

[0120] With continued reference to Figure 15The optical receiver 128 is configured to receive optical receive signals from the third component, convert the optical receive signals to electrical receive signals, and output the electrical receive signals to the ASIC package substrate 32 when the expansion card 27 is in electrical communication with the ASIC package 22. The optical engine 118 of the receiver 128 can include at least one photodetector 146 optically aligned with a corresponding at least one optical receive fiber 124 and a current-to-voltage converter 148 in electrical communication with the at least one photodetector 146. For example, the optical engine 118 of the receiver 128 can include a plurality of photodetectors 146, each optically aligned with a respective one of the plurality of optical receive fibers 124. The photodetectors 146 can thus be said to place the optical receive fibers 124 in data communication with the current-to-voltage converter 148.

[0121] The optical receiver 128, and in particular the optical coupler 132, can include at least one optical receive reflector 150 aligned with the output end of the optical receive fiber 124. The optical receive signals are thus launched from the output end of the optical receive fiber 124 in a first receive direction, reflected off the optical receive reflector 150, and travel to the photodetector 146 in a second receive direction offset by an angle from the first receive direction. The second receive direction can be oriented substantially along the transverse direction T. The optical receive reflector 150 can be metallic, a multi-layer dielectric coating, an uncoated total internal reflection surface, or made of any suitable alternative reflective material or interface as desired.

[0122] In one example, one or more optical elements can be disposed between the optical receive fiber and the photodetector 146. These intervening optical elements can include one or more mirrors, lenses, transparent substrates, and optically transparent couplers that collectively provide an optical path between the optical receive fiber 124 and the photodetector 146. The optical elements can match the size of the optical receive signal beam to the size of the photosensitive region of the photodetector 146 and can accommodate alignment tolerances between the optical receive fiber 124 and the photodetector 146. High coupling efficiency can be advantageously maintained over a large operating temperature range.

[0123] In some embodiments, the optical receiver 128 can include a first receiving lens 152, which can be supported by the frame 134. For example, the first receiving lens 152 can be supported on a bottom surface of the frame 134 facing the interposer 130. The optical receiver 128 can include a second receiving lens 154, which can be supported on a top surface of the interposer 130 facing the frame 134. The first receiving lens 152 can be a collimating lens. Thus, the optical receiving signal can be collimated from the first receiving lens 152 to the second receiving lens 154. It can be appreciated that the beam of collimated optical receiver 128 signal can include an alignment tolerance between the wide-limited optical receiver 128 signal and the active photosensitive area of the photodetector 146. The second receiving lens 154 can be a focusing lens. Thus, the optical receiving signal can be focused from the second receiving lens 154 to the photodetector 146. Alternatively, the optical receiver 128 can include one of the first receiving lens 152 and the second receiving lens 154 without including the other of the first receiving lens 152 and the second receiving lens 154. For example, the optical receiver 128 can include the first receiving lens 152 without including the second receiving lens 154. In this example, the first receiving lens 152 can be configured as a focusing lens. The collimating lens and the focusing lens can be positioned at any location as desired. The interposer 130 can include an alignment component configured to align the photodetector 146 with the first receiving lens.

[0124] The photodetector 146 is configured to convert the optical receiving signal to a corresponding electrical receiving signal. The electrical receiving signal can have a current level that is proportional to the amount of optical photons of the received optical receiving signal. Typically, the photo-generated current increases with an increase in the intensity of the input optical receiving signal and decreases with a decrease in the intensity of the input optical receiving signal. It should be appreciated that the current level of the electrical receiving signal does not have to be linearly proportional to the amount of optical photons of the received optical receiving signal, and typically the proportionality is non-linear. Thus, a higher intensity or number of incident optical photons per unit time of an optical receiving signal will be converted to an electrical signal having a higher current level than an optical receiving signal having a lower number of optical photons. Data can be transmitted through this modulated optical signal and electrical signal.

[0125] The current-to-voltage converter 148 can be configured to receive an electrically received signal from the photodetector 146, regulate the electrically received signal, and output the regulated electrically received signal. In one example, the current-to-voltage converter 148 is a transimpedance amplifier (TIA) that amplifies the electrically received signal to a voltage level suitable for communication with the first electrical component. The photodetector 146 can be a PIN photodiode (named for its P-doped, intrinsic, and N-doped junction structure), which is then coupled to an ultra-low noise, extremely high-gain transimpedance amplifier that modulates the received photodiode current to an electrically compatible output voltage. In one example, the voltage output can be a differential voltage output. The TIA output typically includes a limiting amplifier (LA) stage and an equalization circuit. Advanced functions such as optical signal loss detection (LOS), received optical power, and squelch can also be implemented.

[0126] Therefore, the electrical receiving signal output by the current-to-voltage converter 148 is the electronic equivalent of the optical signal received by the photodetector 146. Thus, the electrical receiving signal output by the current-to-voltage converter 148 can mimic the digital pattern of the received optical pattern within the electrical signal. The current-to-voltage converter 148 outputs the regulated electrical transmitting signal from each channel to the corresponding electrical contact pad 57 of the expansion card substrate 58.

[0127] like Figure 15 As shown, the optical engine of the optical transmitter 126 can be disposed on a first side of the interposer layer 130, while the optical engine of the optical receiver 128 can be disposed on an opposite second side of the interposer layer 130. The first and second sides of the interposer layer 130 can be defined by the same surface of the interposer layer 130. In one example, the surface can be defined by the bottom surface of the interposer layer 130, which is opposite to the top surface of the interposer layer 130 along the lateral direction T. Alternatively, the surface can be defined by the top surface of the interposer layer 130. The first and second sides can be opposite each other in a direction substantially perpendicular to the lateral direction T.

[0128] Each of the photodetector 146, the light source 136, the driver 131, and the current-to-voltage converter 148 can be supported on the bottom surface of the interlayer 130.

[0129] As stated above, and now referring to Figure 17AThe interposer layer 130 may include an alignment member 156 configured to align the photodetector 146 with a first light-receiving lens 152 supported by the frame 134. Specifically, the interposer layer 130 may include a plurality of markings 158 on its outer surface. The markings 158 may be oriented as corresponding circles in a plane perpendicular to the lateral direction T. The circles may be arranged in a plurality of corresponding arrays, in which the circles are aligned with each other such that their central axes are linearly aligned. The central axes may be linearly aligned with each other along a straight line oriented perpendicular to the lateral direction. Therefore, when the circle markings 158 are viewed along the lateral direction T, the entire diameter of the circle is visible.

[0130] The first plurality of alignment components 156 can be aligned with complementary alignment components 137 of VCSEL 138 (or a light source replacing VCSEL 138) to ensure that VCSEL 138 or the light source is positioned relative to the interposer layer 130 as such Figure 17B The predetermined positions in a plane perpendicular to the lateral direction T are shown, wherein the first plurality of alignment members 156 may have a circular profile or any other suitable geometry. The complementary alignment members of the VCSEL 138 or alternative light source may be defined by the emission aperture 139 of the VCSEL 138 or alternative light source. Furthermore, the second plurality of alignment members 156 may be aligned with the complementary alignment members 145 of the photodetector 146 to ensure that the photodetector 146 is positioned relative to the interposer 130 in a plane perpendicular to the lateral direction T, wherein the second plurality of alignment members 156 may be configured as circular or any suitable alternative geometry.

[0131] Now for reference Figures 17C-17DThe interposer layer 130 may include a focusing alignment member 157 configured to align the lens 142 and the light source 136 of the emitting focusing device 143 substantially along the lateral direction T. Therefore, a corresponding straight line traveling substantially along the lateral direction T may intersect both the lens 142 and the corresponding light source 136 of the lens array 143. The emitting focusing device 143 may include at least one complementary alignment member 147. The at least one complementary alignment member 147 is configured to align with the focusing device alignment member 157 to align the focusing device 143 with the VCSEL or other light source 136. Therefore, the second light-emitting lens 142 supported by the frame 134 can be optically aligned with the emission aperture 139 of the VCSEL or other light source along the lateral direction T. As described above, the focusing device 143 faces the top surface of the interposer layer 130. Since the focusing device 143 is supported by the frame 134, the alignment of the focusing device 143 with the first plurality of alignment members 156 also positions the frame 134 relative to the interposer layer 130 along a plane perpendicular to the lateral direction T. In this regard, the focusing device 143 may provide an alignment component 147 for the frame 134. However, it is understood that the frame 134 may have any suitable alternative alignment component as needed. Thus, the first light-receiving lens 152 supported by the frame 134 can be positioned to align with the photodetector 146 along the lateral direction T.

[0132] Now for reference Figure 15 and 18 Up to 19E, the optical transceiver 116 may include a heat dissipation system 160, which can be configured to dissipate heat from the current-to-voltage converter 148, the light source 136, and the driver 131. For example... Figures 19A-19E As shown, heat from each of the current-to-voltage converter 148, the light source, and the driver 131 can be directed upwards and away from the top surface of the interposer 130, or downwards and away from the bottom surface of the interposer 130. For example, as Figures 19A-19B As shown, a heat sink 135 can be mounted to the top surface of the interposer 130 to guide heat generated by the current-to-voltage converter 148, the light source 136, and the driver 131 upwards and away from the top surface of the interposer 130. The interposer 130 may include thermal vias that establish a heat conduction path from the current-to-voltage converter 148, the light source 136, and the driver 131 to the heat sink.

[0133] Heatsink 162 can be as follows Figure 19A The single, integral structure shown. Or, as... Figure 19BAs shown, the heat sink 162 can be segmented (i.e., divided into sections) such that the first section 135a of the heat sink 135 is in thermal communication with the current-to-voltage converter 148. The second section 135b of the heat sink 135 is in thermal communication with the light source 136, and the third section 135c of the heat sink 135 is in thermal communication with the driver 131. One or more, up to all, of the first section 135a, the second section 135b, and the third section 135c are spaced apart from each other and thus isolated from each other with respect to thermal conduction. As a result, the heat generated by the driver 131 is isolated from the light source 134 and the current-to-voltage converter 148 with respect to thermal conduction through the heat sink 135. It can be understood that the heat sink 135 can be configured to conduct heat to the top heat sink (see...). Figure 18 (Heat sink 170 in the middle). Alternatively, one or both of the heat sink and the heat sink can be disposed laterally on opposite surfaces of the interposer 130 relative to the light engine 118. The heat sink or heat sink can be supported on the top surface of the interposer 130, while the light engine 138 can be supported on the bottom surface of the interposer. It should be understood that the heat sink or heat sink can alternatively be supported on the bottom surface of the interposer 130, and the light engine 138 can be supported on the top surface of the interposer.

[0134] like Figure 19C As shown, the heat generated by the current-to-voltage converter 148 and the driver 131 can be directed upwards and away from the top surface of the interposer 130. The heat generated by the light source 136 can be directed downwards and away from the lower surface of the interposer 130. Therefore, the heat generated by the current-to-voltage converter 148 and the driver 131 can be directed in a first direction, and the heat generated by the light source 136 can be directed in a second direction opposite to the first direction. Alternatively, as... Figure 19D As shown, the heat generated by the current-to-voltage converter 148 and the driver 131 can be guided downwards and away from the bottom surface of the interposer 130. The heat generated by the light source 136 can be guided downwards and away from the top surface of the interposer 130. Therefore, the heat generated by the current-to-voltage converter 148 and the driver 131 can be guided in a first direction, and the heat generated by the light source 136 can be guided in a second direction opposite to the first direction. Furthermore, the light source 136 can be disposed between the current-to-voltage converter 148 and the driver 131 along the bottom surface of the interposer 130. Finally, as will now be referred to... Figure 15 and Figure 19E As described, heat from each of the current-to-voltage converter 148, the light source 136, and the driver 131 can be directed downwards and away from the bottom surface of the interlayer 130.

[0135] In this respect, and as will now be described, it should be understood that the heat dissipation system 160 may be designed such that heat from any one or more, up to all, of the current-to-voltage converter 148, the light source 136, and the driver 131 may be selectively directed upwards and away from the top surface of the interposer 130. Alternatively or additionally, the heat dissipation system 160 may be designed such that heat from any one or more, up to all, of the current-to-voltage converter 148, the light source 136, and the driver 131 may be selectively directed downwards and away from the bottom surface of the interposer 130.

[0136] Now for reference Figure 15 The transceiver 116 may include a bottom heat sink 164 supported against the current-to-voltage converter 148, the light source 136, and the driver 131. For example, the bottom heat sink 164 may be supported against the respective bottom surfaces of the current-to-voltage converter 148, the light source 136, and the driver 131. In one example, the bottom heat sink 164 may extend along the lateral direction T past the expansion card 27. The bottom heat sink 164 may be configured to receive heat generated by the current-to-voltage converter 148, the light source 136, and the driver 131, and to direct the received heat downwards and away from the bottom surface of the interposer 130. The transceiver 116 may also include a heat sink 166 extending along the bottom surface of the heat sink 164, capable of receiving heat from the heat sink 164, and directing heat away from the optical engine along a plane perpendicular to the lateral direction T. The heat sink 166 may extend outwards from the heat sink in at least one direction perpendicular to the lateral direction T.

[0137] In one example, the heat sink 164 can be a single, monolithic structure. Or, as... Figure 15As shown, heat sink 164 can be segmented such that the first segment 164a of the top heat sink 164 is thermally connected to the current-to-voltage converter 148. The second segment 164b of the top heat sink 164 is thermally connected to the light source 136, and the third segment 164c of the heat sink 164 is thermally connected to the driver 131. One or more, up to all, of the first segment 162a, the second segment 162b, and the third segment 162c can be separated from each other by air gaps and thus isolated from each other relative to thermal conduction. As a result, the heat generated by the drivers 131 is isolated from the light source 134 and the current-to-voltage converter 148 relative to thermal conduction through the heat sink 162. Heat sink 166 can be in thermal contact with each segment 162a to 162c. Heat sink 166 can define a single integral structure. Alternatively, heat sink 166 can define separate segments in contact with the corresponding segments of segments 164a-164c and isolated from each other by air gaps. Heat emitted by the current-to-voltage converter 148 and at least one driver 131 can be dissipated in a first direction and a second direction, which are opposite to each other and both are substantially perpendicular to the transverse direction T. Heat emitted by the light source 136 can be dissipated in a third direction, which is substantially perpendicular to the first and second directions, which are opposite to each other, and substantially perpendicular to the transverse direction T.

[0138] like Figure 15 As shown, any one or more up to all of the heat from the current-voltage converter 148, at least one driver 131, and light source 136 can be directed downwards by placing a heat sink or a segment of the heat sink below any one or more up to all of the current-voltage converter 148, at least one driver 131, and light source 136, such that the heat sink is in thermal conduction with one or more up to all of the current-voltage converter 148, at least one driver 131, and light source 136.

[0139] Now for reference Figure 18 By placing a heat sink or a section thereof below any one or more of the current-voltage converter 148, at least one driver 131, and light source 136, heat from any one or more of the current-voltage converter 148, at least one driver 131, and light source 136 can be directed downwards, such that the heat sink is in thermal conduction with the current-voltage converter 148, at least one driver 131, and light source 136.

[0140] like Figure 18As shown, a first heat sink 168 may be at least partially embedded in an expansion card substrate 58. Therefore, the first heat sink 168 may be defined by one or more metallization layers of the expansion card substrate 58. The top surface of the first heat sink 168 may be in thermal contact with one or more, or even entirely, the bottom surfaces of the current-to-voltage converter 148, at least one driver 131, and the light source 136. For example, the top surface of the first heat sink 168 may be in direct contact with one or more, or even entirely, the bottom surfaces of the current-to-voltage converter 148, at least one driver 131, and the light source 136. Alternatively, the expansion card substrate 58 may define one or more thermal vias extending upward from the top surface of the first heat sink 168 toward a corresponding one of the current-to-voltage converter 148, at least one driver 131, and the light source 136. The thermal vias may contact the corresponding current-to-voltage converter 148, at least one driver 131, and light source 136. Alternatively, the thermal hole may contact the bottom surface of the heat sink, which in turn contacts at least one or more, and at most all, of the current-to-voltage converter 148, at least one driver 131, and the light source 136.

[0141] The heat dissipation system 160 may further include an external heat sink 170 extending upward from the top surface of the interposer layer 130. The first heat sink 168 may be positioned in thermal communication with the external heat sink 170. For example, the heat dissipation system 160 may include a thermal interface 172, which may be configured as a thermally conductive slug extending from the top surface of the first heat sink 168 to the bottom surface of the interposer layer 130. The interposer layer 130 may include a plurality of thermally conductive vias 173 extending from the external heat sink 170 to the thermal interface 172. Thus, the thermal interface 172 is in thermal communication with the external heat sink 170.

[0142] The first heat sink 168 can be segmented such that a first segment 168a of the first heat sink 168 is in thermal communication with the current-to-voltage converter 148. A second segment 168b of the first heat sink 168 is in thermal communication with the light source 136. A third segment 168c of the first heat sink 168 is in thermal communication with the driver 131. One or more of the first segment 168a, the second segment 168b, and the third segment 168c, up to all of them, can be spaced apart from each other by gaps and thus isolated from each other in terms of thermal conduction. Therefore, the heat generated by the driver 131 is isolated from the light source 136 and the current-to-voltage converter 148 by thermal conduction through the heat sink 162. The heat generated by the current-to-voltage converter 148 and at least one driver 131 can be dissipated in opposing first and second directions, each substantially perpendicular to the lateral direction T. The heat generated by the light source 136 can be dissipated along a third third direction, which is substantially perpendicular to the opposing first and second directions and substantially perpendicular to the lateral direction T. In another example, the first heat sink 168 can be a single integral structure.

[0143] In this regard, although various heat sinks have been described as being segmented into three segments, it should be understood that heat sinks can be segmented into a desired number of segments. For example, a heat sink can be segmented into two segments, with the first segment thermally connected to at least one driver 131 and the second segment thermally connected to the current-to-voltage converter 148 and the light source 136.

[0144] Therefore, the heat dissipation system 160 may include a first heat sink 168, which is in thermal communication with at least one or more, and at most all, of the current-to-voltage converter 148, at least one driver 131, and light source 136. The heat dissipation system 160 may also include a second heat sink 135, which is also in thermal communication with at least one or more, and at most all, of the current-to-voltage converter 148, at least one driver 131, and light source 136. The first heat sink 168 may be in thermal communication with at least one or more, and at most all, of a first surface (such as a bottom surface) of the current-to-voltage converter 148, at least one driver 131, and light source 136. The second heat sink 168 may be in thermal communication with at least one or more, and at most all, of an opposing second surface (such as a top surface) of the current-to-voltage converter 148, at least one driver 131, and light source 136. Therefore, the opposing first and second surfaces may be opposite to each other in the lateral direction T.

[0145] In one example, a second heat sink 135 may be disposed on the top surface of an interposer 130. The interposer 130 may include a second plurality of thermal vias as described above with respect to thermal via 173. Thermal via 173 extends from the second heat sink 135 to a corresponding one of the current-to-voltage converter 148, at least one driver 131, and the light source 136. For example, the second thermal via may extend to the bottom surface of the second heat sink 135. In this respect, thermal via 173 may be referred to as a first plurality of thermal vias. A heat sink 170 may be mounted to the top surface of the second heat sink 135. Therefore, heat can be dissipated from at least one or more, and at most all, of the current-to-voltage converter 148, at least one driver 131, and the light source 136 through the second plurality of thermal vias of the interposer 130, the second heat sink 135, and the heat sink 170 to the heat sink 170. In this respect, heat can dissipate upwards from the top surface of the interposer 130.

[0146] Figure 15 and Figure 18 The heat generated by the current-to-voltage converter 148, at least one driver 131, and the light source 136 is shown to be selectively directed upwards to the external heat sink 170 or downwards to the heat sink 166. Therefore, it can be understood that... Figures 19A-19E The heat dissipation system shown can be determined by configuring the heat dissipation system 160 to selectively direct one of the heat sources, namely the current-to-voltage converter 148, at least one driver 131, and the light source 136, upward and downward. For example, with Figure 18 The first heat sink 168 shown can conduct heat upwards, while... Figure 15 The thermally conductive connection of the bottom heat sink 164 shown can guide heat downwards.

[0147] Now for reference Figures 20A-20BAs described above, an optical transceiver 116 or other data communication device can be mounted on the expansion card 27. The expansion card 27 can be electrically connected to the ASIC package substrate 32 via a detachable interface. The detachable interface can be defined between the flexible circuit 60 and the expansion card substrate 58. For example, an electrical connector 26 can be mounted to the expansion card substrate 58, and a flexible circuit 69 can be mated to the expansion card substrate 58 to electrically connect the flexible circuit 69 to each of the ASIC package substrate 32 and the expansion card substrate 58. The flexible circuit 69 can extend directly from the ASIC package substrate 32 and can be mechanically and electrically connected to the electrical traces of the ASIC package substrate 32. Each flexible circuit 69 defines a free end that carries an electrical contact pad 103 configured to abut against the expansion card substrate 58. The electrical connector 26 can be supported by the expansion card substrate 58. The electrical connector 26 can press the electrical contact pad 103 of the flexible circuit 69 against the corresponding contact pad of the expansion card substrate 58 in the manner described above. Alternatively, the electrical connector 26 may include a connector housing and electrical contacts supported by the connector housing, and be configured to mate with the electrical contact pad 103 of the flexible circuit 69, which is received in a socket of the electrical connector 26. In this respect, it should be understood that the electrical connector 26 can be configured in any suitable manner as needed to mount to the expansion card substrate 58 and mate with the flexible circuit 69 so that the flexible circuit 69 is in electrical communication with the expansion card substrate. Therefore, a detachable interface can be defined by the flexible circuit 69 and the electrical connector 26.

[0148] In another example, instead of extending directly from the ASIC package substrate 32, it can be described above regarding... Figures 1-3 The flexible circuit 69 is mounted to the ASIC package substrate 32 in the manner described above, as indicated by the expansion card substrate 58. The electrical connector 26 can be referenced above. Figures 1-3 The described arrangement relates the ASIC package substrate 32 to the expansion card substrate 58. Therefore, the electrical traces of the flexible circuit 69 can be positioned to be electrically connected to each of the ASIC package substrate 32 and the expansion card substrate 58 via a separable interface. It should be understood that the flexible circuit 69 can adapt to changes in height between the ASIC package substrate 32 and the expansion card substrate 58 in the lateral direction while maintaining electrical connection between the expansion card substrate 58 and the ASIC package substrate 32.

[0149] Or, refer to Figures 21A-21BAn optical transceiver 116 or other data communication device can be mounted on the expansion card 27. The expansion card 27 can be electrically connected to the ASIC package substrate 32 via a detachable interface as described above. The detachable interface can be defined between the flexible circuit 69 and the expansion card substrate 58. For example, an electrical connector 26 can be mounted on the ASIC package substrate 32 and mate with the flexible circuit 69 extending from the expansion card substrate 58. Thus, the electrical connector 26 can mate the flexible circuit 69 to the ASIC package substrate 32, so that the flexible circuit 69 is electrically connected to each of the ASIC package substrate 32 and the expansion card substrate 58. The flexible circuit 69 can extend directly from the expansion card substrate 58 to a corresponding free end, which carries an electrical contact pad configured to mate with the electrical connector 26 mounted to the ASIC package substrate 32. In this respect, it can be said that the electrical contact pad mates with the ASIC package substrate 32. The electrical connector 26 can also be supported by the ASIC package substrate 32 and can be an electrical trace electrically connected to the ASIC package substrate 32. For example, the electrical connector 26 can be used in conjunction with the above. Figures 1-3 The described method for the expansion card substrate involves pressing the electrical contact pads of the flexible circuit 68 against the corresponding contact pads of the ASIC package substrate 32. Alternatively, the electrical connector 26 may include a connector housing and electrical contacts supported by the connector housing, the connector housing being mounted to the contact pads of the ASIC substrate 32 to mount the electrical connector to the ASIC substrate 32. The electrical connector 26 may receive a free end of the flexible circuit 69 to mate the contact pads with the corresponding mating ends of the electrical contacts of the electrical connector. Therefore, it is understood that the electrical connector can be configured as any suitable electrical connector to be mounted to the ASIC substrate 32 and mated with the flexible circuit 69, thereby placing the ASIC substrate in electrical communication with the flexible circuit 69, and thus in electrical communication with the expansion card substrate. Therefore, a separable interface between the expansion card 27 and the ASIC package 22 can be defined between the flexible circuit 68 and the ASIC package substrate 32.

[0150] In another example, instead of directly extending from the expansion card substrate 58, the flexible circuit 68 can be referenced above. Figures 1-3 The circuit is mounted to the expansion package substrate 58 in the manner described. Therefore, the electrical traces of the flexible circuit 68 can be electrically connected to each of the ASIC package substrate 32 and the expansion card substrate 58 via a separable interface.

[0151] Figures 20A-21BThe detachable interface is shown to be defined by a first end of flexible circuitry 68 and expansion card 27. A second end of flexible circuitry 68, opposite to the first end, can extend directly from ASIC package substrate 32. Alternatively, the second end of flexible circuitry can be mounted to ASIC package substrate 32. Alternatively, the detachable interface can be defined by a first end of flexible circuitry 68 and ASIC package substrate 32. A second end of flexible circuitry 68, opposite to the first end, can extend directly from expansion card substrate 58. Alternatively, the second end of flexible circuitry 68 can be mounted to expansion card substrate 58. Therefore, electrical connector 26 can interface at least one flexible circuitry 68 to either ASIC package substrate 32 or expansion card substrate 58.

[0152] Still refer to Figures 20A-21B The optical fiber 120 can extend from the optical coupler 132 in a direction that limits mechanical interference between the optical fiber 120 and the main substrate 25. For example, in a view of the data communication system 20 along the lateral direction T, the optical fiber 120 can extend along a direction that is not perpendicular to the corresponding outer edge of the main substrate 25, with the corresponding optical transceiver 116 including the optical fiber 120 arranged along the corresponding outer edge. Unless otherwise stated, the selected optical transceiver 116 can be positioned along a selected outer edge of the main substrate 25. Furthermore, the selected optical transceiver 116 can be positioned closest to a selected outer edge of the main substrate rather than any other edge. In a view of the main substrate 25 along the lateral direction, the optical fiber 120 of the selected optical transceiver 116 can extend from the optical coupler 132 in a direction not perpendicular to the selected outer edge. In one example, the optical fiber 120 of the selected optical transceiver 116 can extend from the optical coupler 132 in a direction substantially parallel to the selected outer edge. Furthermore, the plurality of optical transceivers 116 can be positioned along a selected outer edge such that the corresponding optical fiber 120 of the plurality of optical transceivers extends from the optical coupler 132 along that direction. Thus, the optical fiber 120 of at least one optical transceiver 116 positioned along a selected outer edge can extend on the optical fiber 120 of an adjacent optical transceiver 116 as they extend along that direction.

[0153] Furthermore, in a view of the data communication system 20 along the lateral direction T, the optical fiber 120 may extend along a direction not perpendicular to the corresponding outer edge of the expansion card substrate 58, and the corresponding optical transceiver 116 of the optical fiber 120 may be arranged along the outer edge. Unless otherwise stated, a selected optical transceiver 116 may be positioned along a selected outer edge of the expansion card substrate 58. The outer edge of the expansion card substrate may be positioned in electrical communication with the IC package 22. For example, the expansion card substrate 58 may define a contact pad arranged along its outer edge, which is in electrical communication with the IC package 22. In one example, the outer edge may be mounted to the electrical connector 26 in the manner described above.

[0154] In a view of the ASIC package substrate 32 along the lateral direction T, the optical fiber 120 of the selected optical transceiver 116 can extend from the optical coupler 132 along a direction not perpendicular to a selected outer edge 28 of the ASIC package substrate 32. In one example, the optical fiber 120 of the selected optical transceiver 116 can extend from the optical coupler 132 along a direction substantially parallel to the selected outer edge 28. Multiple optical transceivers 116 can be positioned along the selected outer edge 28 such that the corresponding optical fiber 120 of the multiple optical transceivers extends from the optical coupler 132 along this direction. Therefore, the optical fiber 120 of at least one optical transceiver 116 positioned along the selected outer edge can extend along the optical fiber 120 of an adjacent optical transceiver 116 as they extend along this direction.

[0155] Still referencing Figures 20A-21B The expansion card 27 can be supported on the main substrate 25. Furthermore, the data communication system 20 may also include a bottom heat sink 164 disposed between the main substrate 25 and at least one interposer, such as a first interposer and a second interposer supporting at least one corresponding optical transceiver 116. For example, each of the first and second interposers 30 may support multiple optical transceivers. The bottom heat sink may be in thermal communication with at least one or more, and at most all, of the current-to-voltage converter, light source, and light source driver as described above.

[0156] It should be noted that the description and discussion of the embodiments shown in the accompanying drawings are for illustrative purposes only and should not be construed as limiting this disclosure. Those skilled in the art will understand that this disclosure covers a wide range of embodiments. Furthermore, it should be understood that the concepts described above with respect to the above embodiments can be used alone or in combination with any other embodiments described above. It should also be understood that, unless otherwise stated, the various alternative embodiments described above with respect to one illustrated embodiment are applicable to all embodiments as described herein.

Claims

1. An interconnection system, comprising: An IC package, wherein the IC package has an IC packaging substrate and an IC die mounted on the IC packaging substrate, An adapter circuit extends from the IC package substrate and is in electrical communication with the IC package substrate; An expansion card extends from the adapter circuit, and the expansion card is electrically connected to the adapter circuit and the IC package; An electrical path is established between the expansion card and the IC die, and the electrical path does not first pass through the main substrate when the IC package is mounted on the main substrate, wherein the electrical path is a continuous electrical path; Electrical connectors mounted on the expansion card.

2. The interconnection system as described in claim 1, characterized in that, The IC package is configured to be mounted on the main substrate, such that the IC package is electrically connected to the main substrate.

3. The interconnection system as described in claim 2, characterized in that, An electrical path is established between the expansion card and the IC package, and the electrical path does not first pass through the main substrate.

4. The interconnection system as described in claim 3, characterized in that, It also includes the main substrate.

5. The interconnection system as claimed in claim 1, characterized in that, The IC packaging substrate is an ASIC packaging substrate.

6. The interconnection system as described in any one of claims 1 to 5, characterized in that, It also includes a cable installed on the expansion card.

7. The interconnection system as described in any one of claims 1 to 5, characterized in that, It also includes an optical transceiver installed on the expansion card.

8. The interconnection system as claimed in claim 1, characterized in that, The IC die mentioned therein is an ASIC die.

9. The interconnection system as claimed in claim 1, characterized in that, The electrical connector mentioned therein is a card edge connector.

10. The interconnection system as claimed in claim 1, characterized in that, It also includes electrical connectors, which are respectively mated to different sides of the IC packaging substrate.

11. The interconnection system as claimed in claim 10, characterized in that, The electrical connector is mated to all four sides of the IC packaging substrate.

12. The interconnection system as claimed in claim 1, characterized in that, The adapter circuit is mounted on the IC packaging substrate.

13. An interconnection system, comprising: An ASIC package, wherein the ASIC includes an ASIC package substrate and an ASIC die mounted on the ASIC package substrate; An expansion card electrically connected to the ASIC packaging substrate; An adapter circuit is disposed between the expansion card and the ASIC packaging substrate. The adapter circuit extends from the ASIC packaging substrate and is in electrical communication with the ASIC packaging substrate. The adapter circuit is planar in a non-flexible state, and the expansion card extends from the adapter circuit and is in electrical communication with the adapter circuit. Electrical connectors mounted on the expansion card; and When the ASIC package is mounted on the main substrate, an electrical path is established between the expansion card and the ASIC package. The electrical path does not first pass through the main substrate, and the electrical path is a continuous transmission path through the adapter circuit.

14. The interconnection system as claimed in claim 13, characterized in that, The expansion card and the ASIC packaging substrate define a detachable interface.

15. The interconnection system as claimed in claim 13, characterized in that, The electrical connector enables the adapter circuit to communicate electrically with the expansion card.

16. The interconnection system as claimed in claim 13, characterized in that, The adapter circuit extends directly outward from the expansion card.

17. The interconnection system as claimed in claim 13, characterized in that, The electrical connector connects the adapter circuit to the ASIC package substrate.

18. The interconnection system as claimed in claim 13, characterized in that, It also includes a cable installed on the expansion card.

19. The interconnection system as claimed in any one of claims 13 to 18, characterized in that, It also includes the main substrate.

20. The interconnection system as claimed in claim 13, characterized in that, The adapter circuit is mounted on the ASIC package substrate.

21. The interconnection system as claimed in claim 1, characterized in that, It also includes an intermediary layer installed on the expansion card, an optical transceiver installed on the intermediary layer, and an optical fiber installed on the optical transceiver.

22. The interconnection system as claimed in claim 21, characterized in that, The optical transceiver is disposed along the outer edge of the expansion card.

23. The interconnection system as claimed in claim 22, characterized in that, The optical fiber extends in a direction that is not perpendicular to the outer edge of the expansion card.

24. The interconnection system as claimed in claim 1, characterized in that, The adapter circuit is received by the socket of the electrical connector so that the electrical connector mates with the adapter circuit.

25. The interconnection system as claimed in claim 1, characterized in that, The adapter circuit is mounted on the top surface of the expansion card, and the interconnection system further includes a second adapter circuit mounted on the bottom surface of the expansion card.

26. The interconnection system as claimed in claim 1, characterized in that, The IC packaging substrate has opposing top and bottom surfaces, and the IC package further includes multiple contact pads on the top surface.

27. The interconnection system as claimed in claim 26, characterized in that, The IC packaging substrate defines multiple edges, and the contact pads are arranged along all edges of the IC packaging substrate.

28. The interconnection system as claimed in any one of claims 26 to 27, characterized in that, The expansion card defines contact pads, which are arranged along the outer edge of the expansion card, and the expansion card is electrically connected to the IC package.

29. The interconnection system as claimed in claim 28, characterized in that, The contact pads of the IC packaging substrate and the contact pads of the expansion card have a contact pitch ranging from approximately 0.2 mm to approximately 0.5 mm.

30. The interconnection system as claimed in claim 1, characterized in that, It also includes multiple cables that communicate electrically with the expansion card.

31. The interconnection system as claimed in claim 1, characterized in that, One edge of the expansion card is adjacent to a corresponding edge of the IC packaging substrate.

32. The interconnection system as claimed in claim 1, characterized in that, The electrical connection between the expansion card and the IC packaging substrate has no conductive residue.

33. The interconnection system as claimed in claim 1, characterized in that, The electrical connector is electrically connected to the electrical traces on the IC packaging substrate.

34. The interconnection system as claimed in claim 1, characterized in that, It also includes an electrical transmission line that supports 112 gigabits per second of signaling between the IC package substrate and the expansion card, and has a worst-case asynchronous multi-source crosstalk of no more than 6%.

35. The interconnection system as claimed in claim 1, characterized in that, The expansion card also includes an expansion card substrate having a top surface and a bottom surface opposite the top surface in a lateral direction, wherein the electrical connector is mounted to the expansion card substrate to enable the expansion card substrate to be electrically connected to the IC package.

36. The interconnection system as claimed in claim 35, characterized in that, The expansion card substrate is supported on the main substrate, wherein the expansion card substrate supports at least one optical transceiver, the at least one optical transceiver having an optical coupler and a plurality of optical fibers supported by the optical coupler.

37. The interconnection system as claimed in claim 36, characterized in that, The optical fiber is substantially parallel to the edge orientation of the expansion card substrate in a lateral view relative to the interconnect system, wherein the expansion card substrate defines an electrical contact pad that is electrically connected to the IC package.

38. The interconnection system as claimed in claim 37, characterized in that, The edge of the expansion card substrate is mounted to the electrical connector.

39. The interconnection system as described in any one of claims 37 to 38, characterized in that, At least one optical transceiver is supported by the top surface of the expansion card substrate.

40. The interconnection system as described in any one of claims 37 to 38, characterized in that, The at least one optical transceiver includes a plurality of optical transceivers arranged along the edge of the main substrate, wherein the optical fiber is substantially parallel to the edge orientation of the main substrate in a lateral view relative to the interconnect system.

41. The interconnection system as claimed in claim 40, characterized in that, The optical fiber, viewed in a lateral direction relative to the interconnect system, is substantially parallel to the edge orientation of the IC package substrate, the expansion card substrate having an upper surface and a lower surface opposite each other in the lateral direction.

42. The interconnection system as claimed in claim 36, characterized in that, The at least one optical transceiver includes a plurality of optical transceivers arranged along the edge of the IC package substrate, wherein the optical fibers of the plurality of optical transceivers are substantially parallel to the edge orientation of the IC package substrate in a lateral view relative to the interconnect system.

43. The interconnection system as claimed in claim 36, characterized in that, The at least one optical transceiver includes an interposer supported by the expansion card substrate, an optical fiber supported on a first surface of the interposer, and an optical engine supported on a second surface of the interposer, the second surface being opposite to the first surface in a lateral direction.

44. The interconnection system as claimed in claim 43, characterized in that, The optical transceiver includes an optical transmitter and an optical receiver, wherein the optical engine of the optical transmitter is disposed on a first side of the interposer layer, and the optical engine of the optical receiver is disposed on a second side of the interposer layer, the second side being opposite to the first side in a direction perpendicular to the lateral direction.

45. The interconnection system as claimed in claim 43, characterized in that, The optical engine includes a light source, at least one light source driver, and a current-to-voltage converter, and the optical transceiver also includes at least one heat sink configured to dissipate heat from at least one or more of the light source, at least one light source driver, and current-to-voltage converter, up to the entirety of them.

46. ​​The interconnection system as claimed in claim 45, characterized in that, The at least one heat sink is configured to dissipate heat from the current-to-voltage converter, the light source, and at least one light source driver in one of the corresponding directions, the upward and the downward directions.

47. The interconnection system as claimed in claim 45, characterized in that, It includes a heat dissipation path from at least one of the current-voltage converter, the light source, and at least one light source driver through the interposer to the top surface of the interposer.

48. The interconnection system as claimed in claim 45, characterized in that, It also includes a heat sink on the opposite surface of the expansion card substrate in the lateral direction relative to the interposer layer.

49. The interconnection system of claim 45, further comprising: A heat sink, which is at least partially embedded in the expansion card substrate and is in thermal communication with at least one of a current-to-voltage converter, a light source, and at least one light source driver; as well as A thermal interface extending from the top surface of the heat sink to the bottom surface of the interlayer.

50. The interconnection system as claimed in claim 49, characterized in that, It also includes at least one thermally conductive hole that extends from the thermal interface through the intermediary layer to an external heat sink supported on the top surface of the intermediary layer.

51. The interconnection system as claimed in claim 36, characterized in that, The IC package includes an ASIC package, the IC package substrate includes an ASIC package substrate, and the IC die includes an ASIC die.

52. The interconnection system as claimed in claim 1, characterized in that, The IC packaging substrate has rows of electrical contacts, and the electrical contacts of the rows are distributed adjacent to at least one edge on both the top and bottom surfaces of the IC packaging substrate.

53. The interconnection system as claimed in claim 1, characterized in that, The IC packaging substrate has rows of electrical contacts, and the electrical contacts of the rows are distributed on at least one of the top and bottom surfaces of the IC packaging substrate adjacent to the four edges of the IC packaging substrate.

54. The interconnection system as claimed in claim 1, characterized in that, The IC packaging substrate has rows of electrical contacts, and the electrical contacts of the rows are distributed on both the top and bottom surfaces of the IC packaging substrate adjacent to the four edges of the IC packaging substrate.

55. The interconnection system as claimed in claim 1, characterized in that, The IC packaging substrate has opposing top and bottom surfaces, and the IC package further includes a plurality of contact pads on the top surface.

56. The interconnection system as claimed in claim 55, characterized in that, The IC packaging substrate defines multiple edges, and the contact pads are arranged along all edges of the IC packaging substrate.

57. The interconnection system as described in claim 55 or 56, characterized in that, The expansion card defines contact pads, which are arranged along the outer edge of the expansion card, and the expansion card is electrically connected to the IC package.

58. The interconnection system as claimed in claim 57, characterized in that, The contact pads of the IC packaging substrate and the contact pads of the expansion card have a contact pitch ranging from approximately 0.2 mm to approximately 0.5 mm.

59. The interconnection system as claimed in claim 56, characterized in that, The top surface of the main substrate faces the bottom surface of the expansion card.

60. The interconnection system as claimed in claim 55, characterized in that, It also includes multiple cables installed on the expansion card.

61. The interconnection system as claimed in claim 55, characterized in that, One edge of the expansion card is adjacent to a corresponding edge of the IC packaging substrate.

62. The interconnection system as claimed in claim 55, characterized in that, The electrical connection between the expansion card and the IC packaging substrate has no conductive residue.

63. The interconnection system as claimed in claim 55, characterized in that, The electrical connector is electrically connected to the electrical traces on the IC packaging substrate.

64. The interconnection system as claimed in claim 55, characterized in that, It also includes an electrical transmission line that supports 112 gigabits per second of signaling between the IC package substrate and the expansion card, and has a worst-case asynchronous multi-source crosstalk of no more than 6%.

65. The interconnection system as claimed in claim 55, characterized in that, The expansion card is supported on the main baseboard.

66. The interconnection system as claimed in claim 55, characterized in that, The main substrate is configured as a printed circuit board.

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