Method and apparatus for subtractive self-alignment

Abstract

A method of forming an interconnect structure for a semiconductor device is described. The method includes depositing an etch stop layer on a substrate by physical vapor deposition, followed by in-situ deposition of a metal layer on the etch stop layer. The in-situ deposition step includes flowing a plasma treatment gas into a chamber, and exciting the plasma treatment gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate remains under vacuum during the deposition process and is not exposed to ambient air.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of interconnect structures and interconnect structure fabrication. More particularly, embodiments of the present disclosure provide methods for creating interconnect structures with aligned vias and / or contacts using subtractive processes. Background Art

[0002] Interconnect structures, such as personal computers, workstations, computer servers, mainframes, and other computer-related devices, such as printers, scanners, and hard disk drives, use logic and memory devices that provide large amounts of data storage capabilities and capacity, while offering low power consumption. The scaling of features has been the driving force behind the ever-growing semiconductor industry. Scaling to smaller and smaller features enables the density of functional units to be increased on the limited real estate of a semiconductor chip. For example, shrinking transistor size allows a greater number of memory or logic devices to be incorporated on a chip, resulting in the fabrication of products with increased capacity. However, the drive for more and more capacity is not without problems. The necessity to optimize the performance of each device becomes increasingly important.

[0003] On-chip electrical interconnects have previously been produced using "dual damascene" fabrication techniques in which holes are created through the various layers of the device structure and filled with conductive material to form interconnects between layers and between device features located on the individual layers. Dual damascene can allow the formation of vias (Vx) that are self-aligned to the overlying metal lines (Mx). However, for chips based on 50nm pitch (25nm half pitch size) and smaller feature sizes, there are gap fill and resistivity limitations that make the use of the previously relied upon "dual damascene" fabrication techniques impractical.

[0004] Accordingly, there is a need to improve the processing method of line resistance and via resistance. Summary of the invention

[0005] One or more embodiments of the present disclosure are directed to a method of forming an interconnect structure. In one or more embodiments, the method includes: depositing an etch stop layer on a substrate, wherein the step of depositing includes physical vapor deposition; and in-situ depositing a metal layer on the etch stop layer, wherein the step of in-situ depositing includes flowing a plasma treatment gas into a chamber and exciting the plasma treatment gas into a plasma to deposit the metal layer on the etch stop layer on the substrate, wherein the substrate is continuously under vacuum and is not exposed to ambient air.

[0006] Additional embodiments of the present disclosure are directed to a processing tool. In one or more embodiments, the processing tool includes: a central transfer station including a robot configured to move a wafer; and a plurality of processing stations, each processing station connected to the central transfer station and providing a processing area separate from a processing area of ​​an adjacent process station, the plurality of processing stations including a first physical vapor deposition chamber and a second physical vapor deposition chamber.

[0007] Further embodiments of the present disclosure are directed to a non-transitory computer-readable medium comprising instructions. In one or more embodiments, the non-transitory computer-readable medium comprises instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform the following operations: deposit an etch stop layer on a substrate; deposit a metal layer in situ on the etch stop layer; and maintain the substrate under vacuum. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In this way, the above-mentioned features of the present disclosure can be understood in detail, and a more particular description of the present disclosure, briefly summarized above, can be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be understood, however, that the drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered limiting of the scope of the present disclosure, as the present disclosure may admit to other equally effective embodiments.

[0009] Figure 1 According to one or more embodiments of the present disclosure, a schematic cross-sectional view of a physical vapor deposition chamber is illustrated;

[0010] Figure 2 According to one or more embodiments of the present disclosure, a cross-sectional view of a substrate is shown;

[0011] Figure 3 According to one or more embodiments of the present disclosure, a cross-sectional view of a substrate is shown;

[0012] Figure 4 According to one or more embodiments of the present disclosure, a cross-sectional view of a substrate is shown;

[0013] Figure 5 An isometric view of an interconnect structure is illustrated according to one or more embodiments of the present disclosure;

[0014] Figure 5A According to one or more embodiments, the diagram Figure 5 A cross-sectional view of an interconnect structure;

[0015] Figure 5B According to one or more embodiments, the diagram Figure 5 A top view of an interconnection structure;

[0016] Figure 6 An isometric view of an interconnect structure is illustrated according to one or more embodiments of the present disclosure;

[0017] Fig. 6A According to one or more embodiments, the diagram Figure 6 A cross-sectional view of an interconnect structure;

[0018] Figure 6B According to one or more embodiments, the diagram Figure 6 A top view of an interconnection structure;

[0019] Figure 7 An isometric view of an interconnect structure is illustrated according to one or more embodiments of the present disclosure;

[0020] Fig. 7A According to one or more embodiments, the diagram Figure 7 A cross-sectional view of an interconnect structure;

[0021] Figure 7B According to one or more embodiments, the diagram Figure 7 A top view of an interconnection structure;

[0022] Figure 8 According to one or more embodiments of the present disclosure, a cross-sectional view of an interconnect structure is illustrated;

[0023] Fig. 9 According to one or more embodiments of the present disclosure, a cross-sectional view of an interconnect structure is illustrated;

[0024] Fig.10 An isometric view of an interconnect structure is illustrated according to one or more embodiments of the present disclosure;

[0025] Fig. 10A According to one or more embodiments, the diagram Fig.10 A cross-sectional view of an interconnect structure;

[0026] Fig. 10B According to one or more embodiments, the diagram Fig.10 A top view of an interconnection structure;

[0027] Fig.11 An isometric view of an interconnect structure is illustrated according to one or more embodiments of the present disclosure;

[0028] Fig.11A According to one or more embodiments, the diagram Fig.11 A cross-sectional view of an interconnect structure;

[0029] Fig. 11B According to one or more embodiments, the diagram Figure 7 A top view of an interconnection structure;

[0030] Fig.12 An isometric view of an interconnect structure is illustrated according to one or more embodiments of the present disclosure;

[0031] Fig. 12A According to one or more embodiments, the diagram Fig.12 A cross-sectional view of an interconnect structure;

[0032] Fig. 12B According to one or more embodiments, the diagram Fig.12 A top view of an interconnection structure;

[0033] Fig.13 An isometric view of an interconnect structure is illustrated according to one or more embodiments of the present disclosure;

[0034] Fig.13A According to one or more embodiments, the diagram Fig.13 A cross-sectional view of an interconnect structure;

[0035] Fig. 13B According to one or more embodiments, the diagram Fig.13 A top view of an interconnection structure;

[0036] Fig.14 An isometric view of an interconnect structure is illustrated according to one or more embodiments of the present disclosure;

[0037] Fig.14A According to one or more embodiments, the diagram Fig.14 A cross-sectional view of an interconnect structure;

[0038] Fig. 14B According to one or more embodiments, the diagram Fig.14 A top view of an interconnection structure;

[0039] Fig.15 According to one or more embodiments of the present disclosure, a flowchart of a method is depicted; and

[0040] Fig.16 In accordance with one or more implementations, a cluster tool is illustrated. DETAILED DESCRIPTION

[0041] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is susceptible of other embodiments and can be practiced or carried out in various ways.

[0042] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactant gas," and the like are used interchangeably to refer to any gas species that can react with a substrate surface.

[0043] As used herein, "substrate" refers to any substrate or a material surface formed on a substrate on which a film treatment is performed during a manufacturing process. For example, substrate surfaces (on which treatment may be performed) include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to a pre-processing process to polish, etch, reduce, oxidize, hydroxylate, anneal and / or bake the substrate surface. In addition to the film treatment directly on the surface of the substrate itself, in the present disclosure, any film treatment step disclosed may also be performed on an underlying layer formed on the substrate as disclosed in more detail below, and the term "substrate surface" is intended to include such an underlying layer as indicated by the context. Thus, for example, in the case where a film / layer or a portion of a film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0044] One or more embodiments advantageously provide an integrated process for forming interconnects. In one or more embodiments, both core metal deposition and metal etch stop deposition are optimized to low resistivity films with their own process capabilities. The deposition chamber is integrated on the same processing platform with high vacuum levels to avoid undesirable metal oxidation.

[0045] One or more embodiments of the present disclosure advantageously provide methods that enable alignment of vias (relative to bottom lines) based on a subtractive scheme. Embodiments of self-aligned subtractive schemes allow for the formation of interconnect structures with etch stop layers / liners. Some embodiments advantageously provide self-alignment of vias.

[0046] One or more embodiments of the present disclosure advantageously improve chip interconnect resistance scaling. Resistance scaling includes two parts: line resistance and via resistance. In one or more embodiments, line resistance is improved by implementing low resistivity metal deposition. In one or more embodiments, via resistance is improved by integrating (without vacuum break) an ultra-thin and low resistivity metal etch stop layer.

[0047] In one or more embodiments, the process of one or more embodiments advantageously achieves a 15-50% or more reduction in line resistance, and a 20-30% or more reduction in via resistance, compared to conventional dual damascene interconnect fabrication. When compared to conventional dual damascene methods of depositing metal, the process of one or more embodiments achieves 50% or more film resistivity for both the core metal and the metal etch stop film. In addition, in one or more embodiments, the integrated platform further reduces the effective resistivity by about 20%.

[0048] An example of a physical vapor deposition chamber 50 useful for depositing the etch stop layer and metal layer of one or more embodiments is shown in Figure 1 Schematically illustrated in FIG. PVD chamber 50 includes a vacuum chamber 52 arranged about a central axis 54 on which a target 56 is supported by an insulator 58 that vacuum-seals the target 56 to the vacuum chamber 52 and electrically insulates the target 56 from the electrically grounded vacuum chamber 52. A vacuum pump system (not shown) evacuates the interior of the vacuum chamber 52 to a pressure in the low millitorr range.

[0049] In one or more embodiments, the shape of the front surface of the target 56 can be planar or generally concave with an outer peripheral edge that is thicker than the inner diameter portion. The target 56 includes a layer of metal that faces the interior of the vacuum chamber 52 and typically contains no more than 5 atomic % of elements other than the metal to be deposited to provide a source of sputtered metal.

[0050] The DC power source 60 biases the target negatively relative to the grounded vacuum chamber 52 or grounded sidewall shields (not shown) to ignite the plasma processing gas into a plasma.

[0051] In one or more embodiments, the plasma treatment gas comprises one or more of the following: neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe), and is supplied from a gas source to the vacuum chamber 52 through a mass flow controller. In a specific embodiment, the plasma treatment gas comprises krypton (Kr). Without intending to be bound by theory, it is believed that using a gas source 62 comprising krypton (Kr) as a plasma treatment gas does not result in the embedding of krypton atoms. Therefore, in one or more embodiments, the plasma treatment gas comprises krypton (Kr), consists essentially of krypton (Kr), or consists of krypton (Kr). In some embodiments, the plasma treatment gas comprises substantially only krypton atoms. In one or more embodiments, the gas source 62 is connected to the vacuum chamber 52 through a mass flow controller 64.

[0052] In one or more embodiments, the target power excites the plasma treatment gas into a plasma, and the positively charged ions of the plasma are accelerated toward the target 54 and sputter metal atoms from the target 54. The density of the plasma is increased by placing a magnetron 66 on the back side of the target 56, the magnetron 66 having an inner pole 68 of one magnetic polarity, the inner pole 68 being surrounded by an outer pole 70 of opposite magnetic polarity. The poles 68, 70 project a magnetic field parallel to the face of the target 56 into the vacuum chamber 52 to capture electrons and thereby increase the plasma density and the resulting sputtering rate. To improve sputtering uniformity and target utilization, the poles 68, 70 are not symmetrical about the central axis 54, but are supported on arms connected to a shaft 74 extending along the central axis 54. A motor 76 rotates the shaft 74 and thus the magnetron 66 about the central axis 54 to provide at least azimuthal uniformity.

[0053] A susceptor 80 within the vacuum chamber 52 supports a substrate 82 that is opposed to the target 56 to coat the substrate 82 with metal sputtered from the target 56. Optionally, an RF power source 84 biases the susceptor 80 through a capacitive coupling circuit 86. The susceptor 80 is conductive so that the susceptor 80 acts as an electrode. The RF bias in the presence of a plasma within the vacuum chamber 52 causes a negative DC self-bias to appear on the susceptor 80, causing the sputtered metal ions to accelerate toward the substrate 82 and the trajectories of these sputtered metal ions to enter deeply into any high aspect ratio holes formed in the substrate 82.

[0054] In one or more embodiments, the physical vapor deposition processing chamber for deposition of the etch stop layer differs from the physical vapor deposition processing chamber for metal layer deposition in terms of the sputtering plasma source. In one or more embodiments, the physical vapor deposition processing chamber for depositing bulk metal has either a DC or RF source, while the physical vapor deposition processing chamber for depositing the etch stop layer has an RF source. In addition, the physical vapor deposition processing chamber for depositing bulk metal has a susceptor / wafer temperature operating at a high temperature (above 250°C), while the etch stop layer deposition occurs at a low temperature (about 20°C to about 400°C). Furthermore, the physical vapor deposition processing chamber for bulk metal deposition uses krypton (Kr) as the sputtering gas, whereas the deposition of the etch stop layer uses N for a titanium (Ti) target. 2 (nitridation), or using argon (Ar) for a titanium nitride (TiN) target.

[0055] Embodiments of the present disclosure create interconnect structures that include deposition of multiple layers of material followed by subtractive techniques such as dry etching techniques or atomic layer etching (ALE). In one or more embodiments, the formed conductive interconnect structure is surrounded by a dielectric material as desired.

[0056] Reference Figure 2 In one or more embodiments, a first etch stop layer 110 is formed on a substrate 102. As described herein, the substrate 102 can be any suitable material. For descriptive purposes only, the substrate 102 will be discussed as a silicon substrate. In one or more embodiments, the substrate 102 represents a structure that contacts the underlying semiconductor structure to connect the interconnect structure to the underlying semiconductor device. For example, if connecting to a FEOL (front end of line) device such as a transistor, capacitor, or resistor, the substrate 102 can be a tungsten plug; or, if interconnection is required, the substrate 102 can be copper or other conductive plug material.

[0057] The illustrated embodiment includes an optional barrier layer 106. In one or more embodiments, the barrier layer 106 comprises a liner. In one or more embodiments, the barrier layer 106 may also be omitted from the stack. For example, if the first metal layer 108 has good adhesion to the substrate 102, the optional barrier layer 106 may be redundant. The optional barrier layer 106 may be any suitable material that can increase the adhesion of the first metal layer 108 to the substrate 102. In one or more embodiments, the barrier layer 106 comprises one or more of the following: tantalum (Ta), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), or tantalum / tantalum nitride (Ta / TaN). The optional barrier layer 106 may be deposited by any suitable technique known to a skilled person, including but not limited to atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), evaporation, or electroplating.

[0058] In one or more embodiments, the first metal (conductive) layer 108 is on the optional barrier layer 106; or on the substrate 102 if the optional barrier layer 106 is omitted. In one or more embodiments, the barrier layer 106 comprises a liner. The first metal layer 108 can be any suitable layer deposited by any suitable technique known to a skilled person. In one or more embodiments, the first metal layer 108 is deposited using physical vapor deposition.

[0059] In one or more embodiments, a first etch stop layer 110, which is also a conductor layer, overlies the first metal layer 108. In one or more embodiments, the first etch stop layer 110 comprises an etch stop material. The etch stop material may comprise any suitable material known to those skilled in the art. In one or more embodiments, the etch stop material comprises one or more of the following: titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), tungsten (W), or ruthenium (Ru). In a specific embodiment, the etch stop material comprises titanium nitride (TiN).

[0060] In one or more embodiments, the first etch stop layer 110 is formed using a Figure 1 The first etch stop layer 110 is formed by physical vapor deposition (PVD) in a processing chamber such as the processing chamber shown in FIG. In one or more embodiments, a high frequency RF source is used to generate a highly ionized plasma with a high concentration of metal ions. Without intending to be bound by theory, it is believed that the highly ionized plasma promotes modification of the crystal orientation of the first etch stop layer 110, resulting in tensile stress and high density positive combination, resulting in excellent etching selectivity.

[0061] In one or more embodiments, Figure 1 A target 54 comprising an etch stop material is provided in the processing chamber 50 illustrated in FIG. A pedestal 80 comprises a high current electrostatic chuck at a temperature in a range from about 20° C. to about 400° C., including a range from about 200° C. to about 300° C. In one or more embodiments, the pedestal 80 within the processing chamber 50 supports a substrate 102, the substrate 102 being opposite the target 54 to coat the substrate 102 with a first etch stop layer 110 sputtered from the target 54. In one or more embodiments, an RF power source biases the pedestal supporting the substrate 102 through a capacitive coupling circuit. The pedestal is conductive so that the pedestal acts as an electrode. The RF bias in the presence of a plasma within the processing chamber causes a negative DC self-bias to appear on the pedestal 80, causing the sputtered etch stop material ions to accelerate toward the substrate 102 and the trajectories of these sputtered etch stop material ions to enter deeply into any high aspect ratio holes formed in the substrate 102. In one or more embodiments, the RF power source is in a range from about 1 kW to about 10 kW, including a range from about 2 kW to about 3 kW.

[0062] In one or more implementations, the first etch stop layer 110 deposited on the substrate 102 has a thickness in a range from about 0.5 nm to 5.0 nm.

[0063] Reference Figure 3In one or more embodiments, after depositing the first etch stop layer 110, a metal layer 112 is deposited on the first etch stop layer 110. In one or more embodiments, the metal layer 112 comprises a low resistivity core metal. In one or more embodiments, the lower resistivity core metal is deposited with a high temperature biasable electrostatic chuck (ESC). In one or more embodiments, the metal layer 112 is deposited by a physical vapor deposition process. In one or more embodiments, the metal layer 112 may comprise one or more of the following: ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), iridium (Ir), metal silicide, metal alloy, and the like. In one or more embodiments, the metal layer 112 comprises one or more of the following: ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), and iridium (Ir). In a specific embodiment, the metal layer 112 comprises ruthenium (Ru). In other specific embodiments, the metal layer 112 comprises molybdenum (Mo). In other specific embodiments, the metal layer 112 comprises tungsten (W).

[0064] In one or more embodiments, a target 54 containing a metal to be sputtered to deposit the metal layer 112 is provided to a substrate such as Figure 1 1. The processing chamber 102 is provided in a processing chamber such as the chamber 50 illustrated in FIG. The processing chamber may also include a pedestal supporting the substrate 102. The pedestal 80 includes a high current electrostatic chuck at a temperature of less than about 500° C. In one or more embodiments, the temperature is in a range from about 200° C. to about 450° C. In one or more embodiments, a species selected from the following items flows into the chamber and is excited into a plasma to deposit a metal layer 112 on the first etch stop layer 110 on the substrate 102: neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and combinations thereof.

[0065] In one or more embodiments, the DC power source biases the target negatively from about 500 W to about 10 kW, including from about 900 W to about 8 kW, and from about 900 W to about 2 kW relative to the grounded processing chamber 50 or the grounded sidewall shield to excite the plasma processing gas into a plasma, such as neon (Ne), argon (Ar), krypton (Kr), xenon (Xe).

[0066] In one or more embodiments, the AC power source provides power in a range from about 0W to about 500W, including from about 200W to about 400W.

[0067] In one or more embodiments, the pressure of the processing chamber is in a range from about 5 mTorr to about 100 mTorr, including from about 5 mTorr to about 50 mTorr.

[0068] Reference Figure 4 In one or more embodiments, the seed metal 105 is first deposited, followed by the bulk metal layer 112 being deposited on the seed metal 105. Without intending to be bound by theory, it is believed that depositing the seed metal 105 first and then the bulk metal layer 112 improves the metal grain. Figure 4 In one or more embodiments, a target 54 of a metal comprising a metal layer 112 is provided in a processing chamber. The processing chamber may also include a pedestal 80 that supports a substrate. The pedestal 80 includes a high current electrostatic chuck at a temperature of less than about 500° C. In one or more embodiments, the temperature is in a range from about 200° C. to about 450° C. In one or more embodiments, a species selected from the following items flows into the chamber and is excited into a plasma to deposit a metal seed 102 on the first etch stop layer 110 on the substrate 102: neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and combinations of the foregoing items.

[0069] In one or more embodiments, the metal seed 105 comprises the same material as the metal layer 112. In one or more embodiments, the metal seed 105 comprises one or more of the following: ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), iridium (Ir), metal silicide, and metal alloy. In one or more embodiments, the metal seed 105 comprises one or more of the following: ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), and iridium (Ir). In one or more specific embodiments, the metal seed 105 comprises ruthenium (Ru). In other specific embodiments, the metal seed 105 comprises molybdenum (Mo).

[0070] In one or more embodiments, a DC power source biases the target 54 negatively from about 500 W to about 10 kW relative to a grounded processing chamber 50 or a grounded sidewall shield to excite a plasma processing gas, such as neon (Ne), argon (Ar), krypton (Kr), or xenon (Xe), into a plasma.

[0071] In one or more embodiments, the AC power source provides power in a range from about 0W to about 500W.

[0072] Subsequently, in one or more embodiments, a metal layer 112 is then deposited on the seed metal 105. In one or more embodiments, a target 54 of a metal comprising the metal layer 112 is provided in a processing chamber. The processing chamber may also include a pedestal 80 that supports the substrate. The pedestal 80 includes a high current electrostatic chuck at a temperature of less than about 500° C. In one or more embodiments, the temperature is in a range from about 200° C. to about 450° C. In one or more embodiments, a species selected from the following items flows into the chamber and is excited into a plasma to deposit a metal layer 112 on the metal seed 105 on the first etch stop layer 110 on the substrate 102: neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and combinations of the foregoing items.

[0073] In one or more embodiments, the DC power source biases the target 54 negatively from about 900 W to about 8 kW, and from about 900 W to about 2 kW relative to the grounded processing chamber 50 or the grounded sidewall shield to excite the plasma processing gas into a plasma, such as neon (Ne), argon (Ar), krypton (Kr), xenon (Xe).

[0074] In one or more embodiments, the AC power source provides power in a range from about 200W to about 400W.

[0075] Reference Figure 5 Depositing the first etch stop layer 110 and the metal layer 112 (and optional metal seed 105) in this manner provides an interconnect structure that does not have a failed etch stop layer.

[0076] Figure 5 An isometric three-dimensional view 100 showing an example starting "stack structure" 101 of layers to be used to form an interconnect structure. Figure 5A Graphics Figure 5 A cross-sectional view of the device shown in FIG. 100A . Figure 5B for Figure 5 A top view 100B of the interconnect structure illustrated in FIG. A skilled person will recognize that the exemplary "stacked structure" 101 is only one possible configuration and should not be considered as limiting the scope of the present disclosure.

[0077] In one or more embodiments, the first metal (conductive) layer 108 is on the optional barrier layer 106; or if the optional barrier layer 106 is omitted, it is on the substrate 102. In one or more embodiments, the barrier layer 106 includes a liner. The first metal layer 108 can be any suitable layer deposited by any suitable technique known to the skilled person. In one or more embodiments, as discussed above with respect to the metal layer 112, the first metal layer 108 is deposited using physical vapor deposition. In some embodiments, the first metal layer 108 is a conformal layer of a material selected from metals such as (by way of example and not limitation): tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), aluminum (Al), copper (Cu), silicide, graphene, or a combination of the foregoing. In one or more embodiments, the first metal layer includes ruthenium (Ru).

[0078] In one or more embodiments, a first etch stop layer 110, which is also a conductor layer, overlies the first metal layer 108. In one or more embodiments, a second metal layer 112 is formed on the first etch stop layer 110. The second metal layer 112 may (but need not) be the same as the first metal layer 108 described above. In one or more embodiments, the second metal layer 112 comprises a pillar-forming metal. In some embodiments, by way of example and not limitation, the pillar-forming metal is selected from one or more of the following: tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), aluminum (Al), copper (Cu), silicide, graphene, or a combination of the foregoing. In one or more embodiments, the second metal layer 112 comprises ruthenium (Ru).

[0079] In one or more embodiments, the first etch stop layer 110 is used to stop the etching of the second metal layer 112. In one or more embodiments, the second metal layer 112 includes ruthenium (Ru), and the first etch stop layer 110 includes one or more of the following items: titanium, tantalum, titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), or the like. In one or more embodiments, when the first metal layer 108 and the second metal layer 112 are different materials and have high etching selectivity to each other, the first etch stop layer 110 is omitted.

[0080] In one or more embodiments, the second etch stop layer 114 overlies the second metal layer 112. In one or more embodiments, the second etch stop layer 114 may (but need not) be the same composition as the first etch stop layer 110. In one or more embodiments, having the first etch stop layer 110 and the second etch stop layer 114 as the same material simplifies processing. In one or more embodiments, the second etch stop layer 114 may be a conformal layer of any suitable material (including but not limited to tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), W, Co, Ru, niobium (Nb), niobium nitride (NbN), and combinations thereof) deposited using a technique selected from the group consisting of CVD, PVD, ALD, deposition from an evaporated source of a metal, metal electroplating, or may be an oxide of titanium (Ti) doped with a dopant such as silicide.

[0081] In one or more embodiments, the second etch stop layer 114 is used for etching stop of the hard mask layer 116. In one or more embodiments, the hard mask layer 116 includes silicon oxide, and the second etch stop layer 114 includes one or more of the following: titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), or the like. In one or more embodiments, the second etch stop layer 114 is omitted and does not exist. In some embodiments, when the etching chemistry used for the hard mask layer 116 does not affect the second metal layer 112, such as, for example, when the hard mask layer 116 includes silicon oxide (SiO) and the second metal layer 112 includes ruthenium, the second etch stop layer 114 does not exist.

[0082] In one or more embodiments, a hard mask layer 116 overlies the second etch stop layer 114. In one or more embodiments, the hard mask layer is used in conjunction with an overlying "lithography stack" to transfer the device pattern through the underlying layers 114, 112, 110, and 108 described above. In one or more embodiments, the hard mask layer 116 is a single layer. In other embodiments, the hard mask layer 116 is a combination of layers. The hard mask layer 116 is not described herein, but in one or more embodiments, is made using materials and patterning techniques known in the art to provide patterns at the 10nm node (16nm HPCD) or lower. In some embodiments, the hard mask layer 116 comprises a metal or dielectric mask material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlO x), aluminum nitride (AlN), and combinations of the foregoing. The skilled artisan will recognize that using a chemical formula like SiO to represent silicon oxide does not imply any particular stoichiometric relationship between the elements. The chemical formula only identifies the major elements of the film.

[0083] In one or more embodiments, a bottom anti-reflective coating (BARC) 118 and a photoresist 120 are formed on the above layers. The illustrated photoresist 120 is patterned to have channels 122; however, the pattern may be any suitable shape or combination of shapes.

[0084] In one or more implementations, the combination of the hard mask layer 116, the bottom anti-reflective coating (BARC) 118, and the photoresist 120 is referred to herein as a first "lithographic patterned structure."

[0085] Figure 6 Illustration from Figure 5 An isometric view 200 of a partially patterned structure formed from a starting stacked structure 101 is shown in FIG. Fig. 6A Graphics Figure 6 A cross-sectional view of the structure shown in 200A. Figure 6B yes Figure 6 200B of the structure illustrated in FIG. 200B. In one or more embodiments, the second metal layer 112 is etched in a first direction to the top surface of the first etch stop layer 110 to establish a first conductive line 202 extending upwardly above the first etch stop layer 110. In one or more embodiments, forming the first conductive line 202 includes exposing the patterned interconnect stack structure 101 to an etching gas, and etching the patterned interconnect stack structure at a high etching rate. In one or more embodiments, the second metal layer 112 is etched at a high rate in a range of about 0.5 nm / s to about 5 nm / s, including about 1 nm / s, about 1.5 nm / s, about 2 nm / s, about 2.5 nm / s, about 3 nm / s, about 3.5 nm / s, about 4 nm / s, about 4.5 nm / s, or about 5 nm / s, for a time period in a range of about 10 seconds to about 100 seconds, including about 10 seconds to about 80 seconds, about 20 seconds to about 90 seconds, or about 10 seconds to about 60 seconds. Without intending to be bound by theory, it is believed that the combination of a high etch rate for a short period of time minimizes sputtering of the hard mask layer 116. In one or more embodiments, the second metal layer 112 comprises ruthenium (Ru) and is manufactured by Applied Materials, Inc., Santa Clara, California. In one or more embodiments, the source power is in a range of about 500 watts (W) to about 1800 W, the bias power is in a range of about 50 W to about 300 W, the bias power pulse duty cycle is in a range of about 15% to about 90%, the pressure is in a range of about 5 mTorr to about 50 mTorr, the electrostatic chuck temperature is in a range of about 30° C. to about 90° C., the oxygen gas flow rate is in a range of about 100 sccm to about 700 sccm, and the chlorine gas flow rate is in a range of about 20 sccm to 100 sccm.

[0086] In one or more embodiments, overlying the conductive lines 202 formed by the second metal layer 112 are lines 204 of the second etch stop layer 114, and lines 206 of the hard mask layer 116. In one or more embodiments, the conductive lines 202 are formed of a metal that provides an effective resistivity dictated by the node size of the semiconductor structure. In one or more embodiments, trenches 208 separate rows of the second metal layer 112 that will be further processed to become conductive interconnect contacts.

[0087] Figure 7 Image after removing the patterned stack structure Figure 6 An isometric three-dimensional view 300 of a portion of the patterned structure shown in FIG. Fig. 7A Graphics Figure 7 A cross-sectional view of the structure shown in 300A. Figure 7B for Figure 7 300B of the structure illustrated in FIG. In one or more embodiments, the first etch stop layer 110 is etched to the top surface of the first metal layer 108, and the first metal layer 108 is then etched to form the second conductive line 212 above the optional barrier layer 106 on the substrate 102. In one or more embodiments, the barrier layer 106 includes a liner. In one or more embodiments, the first etch stop layer 110 is titanium nitride (TiN) and is manufactured by Applied Materials, Inc. in Santa Clara, California. In one or more embodiments, the source power is in a range of about 300 W to about 1000 W, the bias power is in a range of about 50 W to about 300 W, the pressure is in a range of about 4 to about 15 mTorr, the electrostatic chuck temperature is in a range of about 30° C. to about 70° C., the gas flow rate of chlorine is in a range of about 30 sccm to about 250 sccm, the gas flow rate of methane is in a range of about 10 sccm to about 100 sccm, and the gas flow rate of nitrogen is in a range of about 30 to about 500 sccm. In one or more embodiments, the titanium nitride (TiN) etching process etches by pulsing the bias and source power in a frequency range of about 1000 Hz to about 10,000 Hz and a duty cycle range of about 15% to about 90%.

[0088] Figure 8 A cross-sectional view of a structure according to one or more embodiments is shown. Figure 8 In one or more embodiments, the second metal layer 112 of the first conductive line 202 is passivated during the etching process of the first metal layer 108. The etching with passivation reduces the erosion / necking of the sidewalls of the first conductive line 202 by preventing active species (e.g., free radicals or high-energy ions) from reacting with the first conductive line 202. In one or more embodiments, the sidewalls 203 of the first conductive line 202 are passivated by using a hard mask sputtering effect to sputter a hard mask material 214 to the sidewalls 203 of the first conductive line 202. In one or more embodiments, the sputtered hard mask material 214 is an oxide, such as silicon oxide, and the first metal layer 108 is ruthenium (Ru). In one or more embodiments, the hard mask sputtering effect is achieved by using a diluent gas (e.g., Ar, H 2 , He, N 2 ) is mixed with the etching gas. In one or more embodiments, the hard mask sputtering effect is achieved by mixing a diluent gas (e.g., Ar, H 2 , He, N 2 ) is mixed with an etching gas for ruthenium (Ru) etching. In one or more embodiments, the ruthenium (Ru) etching is performed at Applied Materials, Inc. in Santa Clara, California. The etching process is performed in an etching chamber. In one or more embodiments, the source power is in a range of about 300 W to about 1800 W, the bias power is in a range of about 50 W to about 300 W, the bias power pulse duty cycle is in a range of about 15% to about 90%, the pressure is in a range of about 4 mTorr to about 30 mTorr, the electrostatic chuck temperature is in a range of about 30° C. to about 90° C., the oxygen gas flow rate is in a range of about 100 to about 700 sccm, and the chlorine gas flow rate is in a range of about 20 to about 100 sccm. In one or more embodiments, the dilution gas is nitrogen (N 2), and is provided at a flow rate of 10 to 100 sccm.

[0089] Fig. 9 A cross-sectional view of a structure according to one or more embodiments is shown. Fig. 9 In one or more embodiments, the sputtered hard mask 214 on the sidewall 203 of the first conductive line 202 is then removed by a wet or dry etching process. In some embodiments, the sputtered hard mask 214 comprises a metal or a dielectric mask material. Suitable dielectric materials include, but are not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlO x ), aluminum nitride (AlN), and combinations thereof. In one or more embodiments, the sputtered hard mask 214 comprises silicon oxide and is removed by dilute hydrofluoric acid (DHF) cleaning. In one or more embodiments, the DHF cleaning is performed in a dilution range of about 100:1 to about 2000:1 for a time range of about 10 seconds to about 10 minutes. In one or more embodiments, the step of sputtering the sputtered hard mask 214 comprises adding a diluent gas to the etching gas. In one or more specific embodiments, the sputtered hard mask 214 comprises silicon oxide, the second conductive line 212 comprises ruthenium (Ru), and the diluent gas comprises nitrogen (N 2 ).

[0090] In one or more embodiments, overlying the second conductive lines 212 formed by the first metal layer 108 are lines 210 of the first etch stop layer 110, the first conductive lines 202, the lines 204 of the second etch stop layer 114, and the lines 206 of the hard mask layer 116. In one or more embodiments, the second conductive lines 212 are formed of a metal that provides an effective resistivity dictated by the node size of the semiconductor structure. In one or more embodiments, the trenches 208 separate the rows of conductive lines 202, 212 extending upward, and the rows of conductive lines 202, 212 extending upward will be further processed to become conductive interconnect contacts.

[0091] Fig.10 The diagram shows the previously etched trench 208 after filling it with a second BARC or spin-on dielectric material 124. Figure 74, a second BARC or spin-on dielectric material 124 is used to support a subsequently applied photoresist 126. In one or more embodiments, the BARC (bottom anti-reflective coating) or spin-on dielectric material 124 is formed from at least one of a polymer component, a cross-linking component, and an acid generator. In one or more embodiments, the BARC or spin-on dielectric material 124 is cured after being applied to the substrate surface, allowing the precursor material to penetrate into the space with the minimum critical dimension. Fig. 10A Graphics Fig.10 A cross-sectional view of the structure shown in 600A. Fig. 10B Graphics Fig.10 The top view 600B of the structure illustrated in FIG. 600B includes BARC or spin-on dielectric 124 filled trenches separating rows of material to be further processed to become conductive interconnects.

[0092] In one or more implementations, the combination of the bottom anti-reflective coating (BARC) or spin-on dielectric material 124 and the photoresist 126 is referred to herein as a second "lithographic patterned structure."

[0093] Fig.11 The diagram shows the structure of the substrate after etching a series of spaces (trench) 130 at an angle relative to previously etched trenches 128 (not shown because these previously etched trenches 130 are filled with BARC or spin-on dielectric 124). Fig.10 An isometric three-dimensional view of a portion of the patterned structure is shown in 700 . In one or more embodiments, the BARC or spin-on dielectric layer 124 and the hard mask layer 116 have been etched down to the upper surface of the first conductive line 202 . Fig.11A Graphics Fig.11 A cross-sectional view of the structure shown in 700A. Fig. 11B Graphics Figure 1 A top view of the structure shown in 700B.

[0094] Fig.12 The diagram shows the structure of the substrate after etching a series of spaces (trench) 130 at an angle relative to previously etched trenches 128 (not shown because these previously etched trenches 128 are filled with BARC or spin-on dielectric 124). Fig.11 An isometric three-dimensional view of a portion of the patterned structure is shown in 800. In one or more embodiments, the BARC or spin-on dielectric layer 124 and the conductive lines 202 have been etched to the upper surface of the lines of the first etch stop layer 210. Fig. 12A Graphics Fig.12 A cross-sectional view of the structure shown in 800A. Fig. 12B Graphics Fig.12 A top view of the structure shown in 800B.

[0095] Fig.13 After removing the BARC or spin-on dielectric layer 124, Fig.12 900, the removal of the BARC or spin-on dielectric layer 124 is typically performed by a dry etching process using an etchant plasma that does not affect layers 206, 202, 210, 212, 106, and 102. In one or more embodiments, the plasma etching process utilizes H 2 / N 2 or H 2 / O 2 mixture, with or without any diluent gas (e.g., Ar, He). Fig.13A Graphic display Fig.13 A cross-sectional view of the structure shown in 900A. Fig. 13B show Fig.13 A top view of the structure shown in 900B.

[0096] Fig.14 After removing the first etch stop layer 210 and the barrier layer 106, Fig.13 100, the removal of the first etch stop layer 210 and the barrier layer 106 is typically performed by a dry etching process using an etchant plasma that does not affect the layers 202, 210, 212, 106, and 102. In one or more embodiments, the plasma etching process utilizes H 2 / N 2 or H 2 / O 2 , with or without any diluent gas (e.g., Ar, He). Without intending to be bound by theory, it is believed that because the first etch stop layer 210 and the barrier layer 106 are conductive layers, the first etch stop layer 210 and the barrier layer 106 must be etched in the same pattern as the first metal layer 108 to avoid any line shorts. In one or more embodiments, the barrier layer 106 includes a liner that must be etched. Fig.14A The diagram is shown in Fig.14 A cross-sectional view of the structure shown in 1000A. Fig. 14B show Fig.14 A top view of the structure shown in 1000B.

[0097] Fig.15According to one or more embodiments of the present disclosure, a process flow diagram of method 1100 is illustrated. At operation 1106, an etch stop layer is formed on the substrate. As discussed above, the etch stop layer can be formed by physical vapor deposition (PVD) for depositing thin films. At operation 1108, a metal layer is deposited on the etch stop layer by physical vapor deposition. At operation 1110, an interconnect stack structure is formed. At operation 1120, a first conductive line is formed (e.g., by a subtractive etching process). At operation 1130, a second conductive line is formed (e.g., by a subtractive etching process). At operation 1140, a dielectric material (e.g., BARC or spin-on dielectric) is deposited. At operation 1150, the interconnect device is etched to form a self-aligned via. At operation 1160, the dielectric material is removed. At operation 1170, the first etch stop layer 210 and the barrier layer 106 are etched. In one or more embodiments, the barrier layer 106 includes a liner, and the liner is etched.

[0098] In some embodiments, the deposition of the first etch stop layer 110 and the second metal layer 112 is performed in an integrated system. In one or more embodiments, the integrated system avoids oxidation of the first etch stop layer 110, which may increase the resistivity of the first etch stop layer 110. In some embodiments, the deposition of the barrier layer 106 and the first metal layer 108 is performed in an integrated system. In one or more embodiments, the integrated system avoids oxidation of the barrier layer 106, which may increase the resistivity of the barrier layer 106. In one or more embodiments, the barrier layer 106 includes a liner, and the integrated system avoids oxidation of the liner, which may increase the resistivity of the liner.

[0099] By using a stacked structure of layers comprising variations of line metal; an etch stop material layer (in the form of a metal or doped ceramic or polymeric material) having a relatively high conductivity component; and a pattern transfer layer (typically comprising a hard mask material) constituting a lithographic stacked structure; and by applying subtractive techniques to form the desired structure within the stacked structure, it is possible to form interconnect conduits, for example, in the form of pillars, without the need to fill tiny capillaries with a fluid conductive material. The above described method of forming interconnect structures enables advancement to devices at 50 nm pitch sizes and smaller.

[0100] In one or more embodiments, the substrate is moved from a first physical vapor deposition chamber, where the first etch stop layer 110 is deposited, to a separate second physical vapor deposition chamber, where the metal layer 108 is deposited. In one or more embodiments, the movement of the substrate from the first chamber to the second chamber is an integrated process performed under vacuum without an air breach.

[0101] In one or more embodiments, the substrate is then moved to another processing chamber for further processing. The substrate may be moved directly from the physical vapor deposition chamber to a separate processing chamber, or the substrate may be moved from the physical vapor deposition chamber to one or more transfer chambers, and then to a separate processing chamber. Accordingly, the processing equipment may include multiple chambers in communication with a transfer station. Such equipment may be referred to as a "cluster tool" or "cluster system" and the like.

[0102] In general, a cluster tool is a modular system that includes multiple chambers that perform various functions, including substrate center-finding and orientation, degassing, annealing, deposition, and / or etching. According to one or more embodiments, a cluster tool includes at least a first chamber and a central transfer chamber. The central transfer chamber can accommodate a robot that can shuttle substrates between and among processing chambers and load lock chambers. The transfer chamber is typically maintained under vacuum conditions and provides an intermediate stage for transporting substrates from one chamber to another and / or to a load lock chamber positioned at the front end of the cluster tool. Two well-known cluster tools that may be suitable for use with the present invention are: and Both are available from Applied Materials, Inc., Santa Clara, California. However, the actual arrangement and combination of chambers may vary for the purpose of performing specific steps of the processes described herein. Other processing chambers that may be used include, but are not limited to, cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, thermal processing such as RTP, plasma nitridation, degassing, orientation, hydroxylation, and other substrate processes. By performing the processes in chambers on a cluster tool, surface contamination of the substrate with atmospheric impurities can be avoided without oxidation prior to deposition of subsequent films.

[0103] According to one or more embodiments, the substrate is maintained under vacuum or "load lock" conditions and is not exposed to ambient air when moving from one chamber to the next. The transfer chamber is therefore under vacuum and is "pumped" at vacuum pressure. An inert gas may be present in the processing chamber or the transfer chamber. In some embodiments, an inert gas is used as a purge gas to remove some or all of the reactants. According to one or more embodiments, a purge gas is injected at the outlet of the deposition chamber to prevent reactants from moving from the deposition chamber to the transfer chamber and / or additional processing chambers. Thus, the flow of inert gas forms a curtain at the outlet of the chamber.

[0104] Substrates may be processed in a single substrate deposition chamber, where a single substrate is loaded, processed, and unloaded before processing another substrate. Substrates may also be processed in a continuous manner, similar to a conveyor system, where multiple substrates are individually loaded into a first portion of the chamber, moved through the chamber, and unloaded from a second portion of the chamber. The shape of the chamber and associated conveyor system may form a straight path or a curved path. Additionally, the processing chamber may be a carousel, where multiple substrates move about a central axis and are exposed to processes such as deposition, etching, annealing, cleaning, etc. throughout the carousel path.

[0105] During processing, the substrate may be heated or cooled. Such heating or cooling may be accomplished by any suitable means, including but not limited to changing the temperature of the substrate support and flowing heated or cooled gas to the substrate surface. In some embodiments, the substrate support includes a heater / cooler that can be controlled to conductively change the substrate temperature. In one or more embodiments, the gas (either a reactive gas or an inert gas) employed is heated or cooled to locally change the substrate temperature. In some embodiments, the heater / cooler is positioned within the chamber adjacent to the substrate surface to convectively change the substrate temperature.

[0106] The substrate may also be static or rotated during processing. A rotating substrate may be rotated continuously or in discrete steps. For example, the substrate may be rotated throughout the entire process, or the substrate may be rotated in small amounts between exposures to different reactive or purge gases. Rotating the substrate during processing (whether continuously or stepwise) may help produce a more uniform deposition or etch by minimizing the effects of local variability, such as in gas flow geometry.

[0107] like Fig.16 As shown in , additional embodiments of the present disclosure are directed to a processing tool 900 for forming memory devices and methods. The cluster tool 900 includes at least one central transfer station 921, 931 having a plurality of sides. Robots 925, 935 are positioned within the central transfer station 921, 931 and are configured to move robot blades and wafers to each of the plurality of sides.

[0108] The cluster tool 900 includes a plurality of processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as process stations, connected to a central transfer station. The various processing chambers provide separate processing areas that are isolated from adjacent process stations. The processing chambers may be any suitable chamber, including but not limited to physical vapor deposition chambers, transfer spaces, wafer orienters / degas chambers, annealing chambers, etching chambers, and the like. The specific arrangement of process chambers and components may vary depending on the cluster tool and should not be considered to limit the scope of the present disclosure.

[0109] In some embodiments, cluster tool 900 includes at least one physical vapor deposition chamber. In some embodiments, cluster tool 900 includes two physical vapor deposition chambers connected to a central transfer station.

[0110] exist Fig.16 In the embodiment shown in FIG. 1 , the factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front 951 of the factory interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, those skilled in the art will understand that this is representative of only one possible configuration.

[0111] The size and shape of the loading chamber 954 and the unloading chamber 956 may vary depending on, for example, the substrates being processed in the cluster tool 900. In the embodiment shown, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette with a plurality of wafers positioned therein.

[0112] A robot 952 is within the factory interface 950 and can move between a loading chamber 954 and an unloading chamber 956. The robot 952 can transfer wafers from a cassette in the loading chamber 954 through the factory interface 950 to a load lock chamber 960. The robot 952 can also transfer wafers from a load lock chamber 962 through the factory interface 950 to a cassette in the unloading chamber 956. As will be appreciated by those skilled in the art, the factory interface 950 can have more than one robot 952. For example, the factory interface 950 can have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960 and a second robot that transfers wafers between the load lock 962 and the unloading chamber 956.

[0113] The cluster tool 900 shown has a first section 920 and a second section 930. The first section 920 is connected to the factory interface 950 through the load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921, and the first transfer chamber 921 has at least one robot 925 positioned in the first transfer chamber 921. The robot 925 is also called a robot wafer transfer mechanism. The first transfer chamber 921 is centrally located relative to the load lock chambers 960, 962, the process chambers 902, 904, 916, 918 and the buffer chambers 922, 924. The robot 925 of some embodiments is a multi-arm robot that can independently move more than one wafer at a time. In some embodiments, the first transfer chamber 921 contains more than one robot wafer transfer mechanism. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Individual wafers are carried on a wafer transfer blade located at the distal end of the first robot mechanism.

[0114] After processing the wafer in the first section 920, the wafer may be transferred to the second section 930 via a pass-through chamber. For example, the chambers 922, 924 may be single-directional or bi-directional pass-through chambers. The pass-through chambers 922, 924 may be used, for example, to cryogenically cool the wafer prior to processing in the second section 930, or to allow for cooling or post-processing of the wafer prior to moving back to the first section 920.

[0115] The system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of process chambers 902, 904, 916, 918, and the second plurality of process chambers 906, 908, 910, 912, 914. The system controller 990 may be any suitable component that can control the process chambers and the robot. For example, the system controller 990 may be a computer including a central processing unit (CPU) 992, a memory 994, an input / output (I / O) 996, and support circuits 998. The controller 990 may control the process tool 900 directly, or via a computer (or controller) associated with a particular process chamber and / or support system component.

[0116] In one or more embodiments, the controller 990 may be one of any form of general purpose computer processor that may be used in an industrial setting for controlling various chambers and subprocessors. The memory 994 or computer readable medium of the controller 990 may be one or more of readily accessible memories such as non-transitory memory (e.g., random access memory (RAM)), read-only memory (ROM), floppy disk, hard disk, optical storage media (e.g., compact disc or digital video disc), flash drive, or any other form of digital storage device, whether local or remote. The memory 994 may retain a set of instructions that can be operated by the processor (CPU 992) to control parameters and components of the processing tool 900.

[0117] Support circuits 998 are coupled to the CPU 992 for supporting the processor in a conventional manner. These circuits include caches, power supplies, clock circuits, input / output circuits and subsystems, and the like. One or more processes may be stored in the memory 994 as software routines that, when executed or called by the processor, cause the processor to control the operation of the processing tool 900 or individual processing units in the manner described herein. The software routines may also be stored and / or executed by a second CPU (not shown) that is remotely located from the hardware controlled by the CPU 992.

[0118] Some or all of the processes and methods of the present disclosure may also be performed in hardware. As such, the processes may be implemented in software and executed in hardware using a computer system as, for example, an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by a processor, the software routines convert a general purpose computer into a special purpose computer (controller) that controls the chamber operations so that the processes are performed.

[0119] In some embodiments, the controller 990 has one or more configurations to perform individual processes or sub-processes to perform the method. The controller 990 can be connected to the intermediate components and configured to operate the intermediate components to perform the functions of the method. For example, the controller 990 can be connected to the physical vapor deposition chamber and configured to control the physical vapor deposition chamber.

[0120] The process can be stored in the memory 994 of the system controller 990 as a software routine, which, when executed by the processor, causes the process chamber to perform the process of the present disclosure. The software routine can also be stored and / or executed by a second processor (not shown) remotely located from the hardware controlled by the processor. Some or all of the methods of the present disclosure can also be performed in hardware. As such, the process can be implemented in software and executed using a computer system, implemented in hardware, for example as an application specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by the processor, the software routine converts a general-purpose computer into a special-purpose computer (controller), which controls the chamber operation so that the process is performed.

[0121] In some embodiments, the system controller 990 is configured to control the physical vapor deposition chamber to deposit an etch stop layer on the wafer at a temperature in a range of about 20° C. to about 400° C., and to control the RF power source to have a power in a range from about 1 kW to about 10 kW.

[0122] In some embodiments, the system controller 990 has a configuration to control a physical vapor deposition chamber to deposit a metal layer on an etch stop layer on a wafer at a temperature in a range of about 200° C. to about 450° C., and to control a DC power source to have a power in a range of from about 500 W to about 10 kW at a pressure in a range of from about 5 mTorr to about 100 mTorr.

[0123] In one or more embodiments, a processing tool includes: a central transfer station including a robot configured to move a wafer; a plurality of process stations, each process station connected to the central transfer station and providing a processing area separate from a processing area of ​​an adjacent process station, the plurality of process stations including a first physical vapor deposition chamber and a second physical vapor deposition chamber; and a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move the wafer between the process stations and control processes occurring in each of the process stations.

[0124] The present disclosure is now described with reference to the following examples. Before describing several example implementations of the present disclosure, it should be understood that the present disclosure is not limited to the details of the construction or process steps set forth in the following description. The present disclosure allows for other implementations and can be practiced or implemented in various ways.

[0125] example

[0126] Example 1

[0127] A layer of titanium nitride (TiN) having a thickness of about 1.5 nm is formed on the substrate by physical vapor deposition. The TiN layer is formed at a temperature of 260° C. in a PVD chamber.

[0128] A layer of ruthenium (Ru) having a thickness of 10 to 100 nm is formed on the titanium nitride (TiN) layer by physical vapor deposition. The Ru layer is formed in a PVD chamber at a temperature in a range of about 250°C to about 450°C.

[0129] Two physical vapor deposition processing chambers are integrated and the deposition process is performed under vacuum without air breach.

[0130] The substrate with Ru on TiN etch stop layer was then etched by Applied Materials' SYM3 process with a combination of halogens (Cl, Br), oxygen, Ar, He, N2, pressurized at <100mTorr, in a direct plasma environment with source and bias.

[0131] Example 2 – Comparative Example

[0132] A layer of titanium nitride (TiN) having a thickness of about 1.5 nm was formed on the substrate by atomic layer deposition. The TiN layer was formed at a temperature of 340° C. in an atomic layer deposition chamber.

[0133] A layer of ruthenium (Ru) having a thickness of 10 to 100 nm is formed on the titanium nitride (TiN) layer by chemical vapor deposition (CVD). The Ru layer is formed in a chemical vapor deposition chamber at a temperature of about 150°C to about 250°C.

[0134] An atomic layer deposition process chamber and a chemical vapor deposition chamber are integrated in a process tool, and the deposition process is performed under vacuum without air breach.

[0135] The substrate with Ru on TiN etch stop layer was then etched by Applied Materials' SYM3, process with a combination of halogens (Cl, Br), oxygen, Ar, He, N2, pressurized at <100 mTorr, in a direct plasma environment of source and bias. There is no room for opening the TiN etch stop layer. Lines merge due to TiN impurities and TiN oxide (TiOx).

[0136] Example 3 – Comparative Example

[0137] A layer of titanium nitride (TiN) having a thickness of about 1.5 nm is formed on the substrate by physical vapor deposition. The TiN layer is formed in a physical vapor deposition chamber at a temperature ranging from room temperature to 300°C.

[0138] A layer of ruthenium (Ru) having a thickness of 10 to 100 nm is formed on the titanium nitride (TiN) layer by physical vapor deposition. The Ru layer is formed in a physical vapor deposition chamber at a temperature of 250-450°C.

[0139] The two PVD process chambers are not integrated into a single process tool and there is an air break between the deposition of the TiN and the deposition of the Ru layer.

[0140] The substrate with Ru on TiN etch stop layer was then etched by Applied Materials' SYM process with a combination of halogens (Cl, Br), oxygen, Ar, He, N2, pressurized at <100mTorr, in a direct plasma environment with source and bias.

[0141] result:

[0142]

[0143] The results show that the device formed in Example 1 has superior resistivity compared to the devices of Examples 2 and 3. The device (stacked structure) of Example 1 has a line resistance reduction of 15-50% more and a via resistance reduction of 20-30% more. In addition, the TiN etch stop layer of Example 1 can be successfully overetched without failure of the etch stop layer, while the etch stop layers of Examples 2 and 3 cannot be overetched.

[0144] The use of the terms "a" and "an" and "said" and similar referenced objects in the context of the description materials and methods discussed herein (especially in the context of the appended claims) is to be interpreted as covering both the singular and the plural, unless otherwise indicated herein or clearly contradictory to the context. The range of values ​​recorded herein is intended only to be used as a shorthand form for representing each separate value falling into the range individually, unless otherwise indicated herein, and each separate value is incorporated into the specification as if recorded individually herein. All methods described herein can be performed in any suitable order, unless otherwise indicated herein or clearly contradictory to the context. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate materials and methods, without limiting the scope, unless otherwise claimed. Any language in the specification should not be interpreted as indicating any unclaimed element as being necessary for practicing the disclosed materials and methods.

[0145] References throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in conjunction with an embodiment is included in at least one embodiment of the present disclosure. Thus, the presence of phrases such as "in one or more embodiments," "certain embodiments," "in an embodiment," or "in an embodiment" throughout this specification does not necessarily refer to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0146] Although the present disclosure is described herein with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. Those skilled in the art will appreciate that various modifications and variations may be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method for forming an interconnection, the method comprising the following steps: depositing an etch stop layer on the substrate, wherein the step of depositing comprises physical vapor deposition at a temperature in a range from 200° C. to 300° C., the etch stop layer comprising one or more of: titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), tungsten (W), and ruthenium (Ru); and in-situ depositing a metal layer on the etch stop layer, wherein the in-situ depositing step comprises the steps of flowing a plasma treatment gas into a processing chamber at a temperature in a range from 200° C. to 450° C., and exciting the plasma treatment gas into a plasma to deposit the metal layer on the etch stop layer on the substrate, the metal layer comprising one or more of the following: ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), iridium (Ir), metal silicide, and metal alloy, The substrate is continuously under vacuum and is not exposed to ambient air. 2 . The method of claim 1 , wherein the RF power source provides a power in a range from 1 kW to 10 kW to deposit the etch stop layer. 3 . The method of claim 2 , wherein the RF power source provides a power in a range from 2 kW to 3 kW to deposit the etch stop layer. The method of claim 1 , wherein the etch stop layer comprises titanium nitride (TiN).

5. The method of claim 1, wherein a power source from 500 W to 10 kW biases the metal target negatively to excite the plasma processing gas into plasma.

6. The method of claim 5, wherein the plasma processing gas comprises one or more of: neon (Ne), argon (Ar), krypton (Kr), xenon (Xe).

7. The method of claim 6, wherein the plasma processing gas comprises krypton (Kr).

8. The method as claimed in claim 1 further comprises the following steps: depositing a metal seed on the etch stop layer before depositing the metal layer, wherein the step of depositing the metal seed comprises the following steps: flowing a plasma treatment gas into the chamber, and exciting the plasma treatment gas into a plasma to deposit the metal seed on the etch stop layer.

9. The method of claim 8, wherein the metal seed comprises one or more of: ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), iridium (Ir), metal silicide, and metal alloy.

10. A processing tool comprising: a central transfer station including a robot configured to move wafers that remain under vacuum and are not exposed to ambient air; and a plurality of process stations, each process station connected to the central transfer station and providing a processing area separate from a processing area of ​​an adjacent process station, the plurality of process stations including a first physical vapor deposition chamber and a second physical vapor deposition chamber; a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move the wafer between the first physical vapor deposition chamber and the second physical vapor deposition chamber without breaking vacuum and configured to control the process occurring in each of the process stations, wherein the controller controls the deposition of an etch stop layer on the substrate by physical vapor deposition in the first physical vapor chamber at a temperature in the range of 200°C to 300°C, and wherein the controller controls the in-situ deposition of the metal layer on the etch stop layer by flowing a plasma treatment gas into the second physical vapor deposition chamber at a temperature in the range of 200°C to 450°C, and exciting the plasma treatment gas into plasma to deposit the metal layer on the etch stop layer on the substrate.

11. The processing tool of claim 10, wherein the first physical vapor deposition chamber comprises a first target comprising one or more of the following: titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), tungsten (W), or ruthenium (Ru), and the second physical vapor deposition chamber comprises a second target comprising one or more of the following: ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), iridium (Ir), metal silicide, and metal alloys.

12. A non-transitory computer readable medium comprising instructions which, when executed by a controller of a processing chamber, cause the processing chamber to: depositing an etch stop layer on the substrate by a physical vapor deposition process at a temperature in a range from 200° C. to 300° C., the etch stop layer comprising one or more of: titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), tungsten (W), and ruthenium (Ru); In-situ depositing a metal layer on the etch stop layer, wherein the in-situ depositing step is performed by the following steps: flowing a plasma treatment gas into a processing chamber at a temperature in a range from 200° C. to 450° C., and exciting the plasma treatment gas into a plasma to deposit the metal layer on the etch stop layer on the substrate, the metal layer comprising one or more of the following: ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), cobalt (Co), iridium (Ir), metal silicide, and metal alloy; and The substrate is maintained continuously under vacuum.

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