Semiconductor device and module

Abstract

The present application relates to a kind of semiconductor devices, with: semiconductor substrate, with in the thickness direction opposite first main surface and second main surface, in the length direction orthogonal to thickness direction opposite first end surface and second end surface;And circuit layer, set to the first main surface of semiconductor substrate, it is characterized in that, semiconductor substrate in the length direction second external electrode side end surface, i.e. first end surface side has in semiconductor substrate not set with the first end region of circuit layer, first exposed portion is set in the first end region, this first exposed portion is the part exposed between first main surface and first end surface except the first main surface of semiconductor substrate, in the direction parallel to the thickness direction and length direction of semiconductor substrate, the cut surface of cutting semiconductor substrate, by the part of first main surface with the circuit layer in the first main surface is divided into two by the dividing line of the central of thickness direction in two, when first end region is divided into two along thickness direction, the area of first area as the region of first main surface side is less than the area of second area as the region of second main surface side.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a module. BACKGROUND

[0002] As a representative capacitor element for a semiconductor integrated circuit, for example, a MIM (Metal Insulator Metal) capacitor is known. The MIM capacitor is a capacitor having a parallel-plate type configuration in which a lower electrode and an upper electrode sandwich a dielectric.

[0003] For example, in Patent Literature 1, a dielectric capacitor is disclosed in which one electrode, a dielectric layer, and another electrode are stacked in this order on a substrate, a first insulating layer covering the other electrode is formed with a first opening portion exposing a part of an upper surface of the other electrode, a second insulating layer covering the first insulating layer is formed with a second opening portion exposing a part of the upper surface of the other electrode, the opening size of the second opening portion is formed larger than the opening size of the first opening portion, and the surface of the recess portion is covered with a conductive hydrogen barrier layer.

[0004] In Patent Literature 2, a capacitor element is disclosed which is composed of a first metal film formed on one surface of a support substrate, a dielectric thin film having a high dielectric constant formed on the first metal film, and a second metal film formed on the dielectric thin film, and the end portion of the second metal film is located at a position where the dielectric thin film is away from the first metal film. In addition, in Patent Literature 2, it is disclosed that in order to avoid stress concentration at the time of heat treatment, a step portion is provided in the support substrate.

[0005] Patent Literature 1: Japanese Patent Application Laid-Open (kokai) No. 2008-252011;

[0006] Patent Literature 2: Japanese Patent Application Laid-Open (kokai) No. 06-140275.

[0007] However, in the case where the dielectric capacitor described in Patent Literature 1 is mounted on a substrate and a voltage is applied, if the substrate is a conductor, an electric field is generated between a pad provided on the substrate and a base electrode, and there is a problem that the substrate becomes a resistor of the above electric field and conductor loss occurs.

[0008] In addition, Patent Literature 2 discloses that in order to avoid stress concentration at the time of heat treatment, a step portion is provided in the support substrate. However, in the capacitor element described in Patent Literature 2, the back side of the support substrate and the second metal film are not present on the same plane, and thus there is a problem that surface mounting is not easy. SUMMARY

[0009] An object of the present application is to provide a semiconductor device and a module capable of reducing conductor loss caused by the resistance of a semiconductor substrate.

[0010] The semiconductor device of the present application includes: a semiconductor substrate having a first main surface and a second main surface opposed in a thickness direction, a first end surface and a second end surface opposed in a length direction orthogonal to the thickness direction, and a first side surface and a second side surface opposed in a width direction orthogonal to the thickness direction and the length direction; and a circuit layer provided on the first main surface of the semiconductor substrate, and is characterized in that the circuit layer includes: a first electrode layer provided on the semiconductor substrate side; a dielectric layer provided on the first electrode layer; a second electrode layer provided on the dielectric layer; a first external electrode electrically connected to the first electrode layer and led out to a surface of the circuit layer opposite to the semiconductor substrate; and a second external electrode electrically connected to the second electrode layer and led out to a surface of the circuit layer opposite to the semiconductor substrate, and the semiconductor substrate has a first end portion region on the second external electrode side in the length direction, that is, on the first end surface side, which is not provided with the circuit layer on the semiconductor substrate, and a first exposed portion is provided in the first end portion region, the first exposed portion being a portion exposed between the first main surface and the first end surface other than the first main surface of the semiconductor substrate, and in a cross section of the semiconductor substrate cut in a direction parallel to the thickness direction and the length direction of the semiconductor substrate, when the first end portion region is divided into two by a division line dividing the semiconductor substrate in the portion provided with the circuit layer on the first main surface into two with a center in the thickness direction as a boundary in the thickness direction, an area of a first region as a region on the first main surface side is smaller than an area of a second region as a region on the second main surface side.

[0011] Further, the module of the present application is characterized by including: the semiconductor device of the present application; a first pad electrically connected to the first external electrode; and a second pad electrically connected to the second external electrode and provided so as to protrude outwardly of the circuit layer.

[0012] According to the present application, it is possible to provide a semiconductor device and a module capable of reducing conductor loss caused by resistance of a semiconductor substrate. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a perspective view schematically showing one example of a semiconductor device of the present application.

[0014] Figure 2 is Figure 1 is a cross-sectional view taken along line A-A in

[0015] Figure 3 is a cross-sectional view schematically showing another example of a semiconductor device of the present application.

[0016] Figure 4 is a cross-sectional view schematically showing another example of the semiconductor device of the present application.

[0017] Figure 5 is a cross-sectional view schematically showing another example of the semiconductor device of the present application.

[0018] Figure 6 is a cross-sectional view schematically showing one example of a circuit layer constituting the semiconductor device of the present application.

[0019] Figure 7 is a perspective view schematically showing another example of the semiconductor device of the present application.

[0020] Figure 8 is a cross-sectional view of B-B line in Figure 7

[0021] Figure 9 A, Figure 9 B and Figure 9 C are process diagrams schematically showing one example of a manufacturing method of the semiconductor device of the present application.

[0022] Figure 10 A, Figure 10 B and Figure 10 C are process diagrams schematically showing another example of a manufacturing method of the semiconductor device of the present application.

[0023] Figure 11 A, Figure 11 B and Figure 11 C are process diagrams schematically showing another example of a manufacturing method of the semiconductor device of the present application.

[0024] Figure 12 A, Figure 12 B and Figure 12 C are process diagrams schematically showing another example of a manufacturing method of the semiconductor device of the present application.

[0025] Figure 13 is a cross-sectional view schematically showing one example of a module of the present application. DETAILED DESCRIPTION

[0026] Hereinafter, the semiconductor device and the module of the present application will be described.

[0027] However, the present application is not limited to the following structures, and can be appropriately changed and applied within the scope not changing the gist of the present application. Further, a structure in which two or more of the preferred structures of the present application described below are combined is also the present application.

[0028] [Semiconductor Device]​

[0029] The semiconductor device of the present application has: a semiconductor substrate having a first main surface and a second main surface opposed in a thickness direction, a first end surface and a second end surface opposed in a length direction orthogonal to the thickness direction, and a first side surface and a second side surface opposed in a width direction orthogonal to the thickness direction and the length direction; and a circuit layer provided on the first main surface of the semiconductor substrate, and is characterized in that the circuit layer has: a first electrode layer provided on the semiconductor substrate side; a dielectric layer provided on the first electrode layer; a second electrode layer provided on the dielectric layer; a first external electrode electrically connected to the first electrode layer and led out to a surface of the circuit layer on the side opposite to the semiconductor substrate; and a second external electrode electrically connected to the second electrode layer and led out to a surface of the circuit layer on the side opposite to the semiconductor substrate, the semiconductor substrate has, on the side of the second external electrode in the length direction, a first end surface, a first end region on the semiconductor substrate in which the circuit layer is not provided, and a first exposed portion provided in the first end region and exposed between the first main surface and the first end surface other than the first main surface, and in a cross section of the semiconductor substrate cut in a direction parallel to the thickness direction and the length direction, when the first end region is divided into two by a division line dividing the semiconductor substrate in the portion in which the circuit layer is provided on the first main surface with a center in the thickness direction, an area of a first region as a region on the first main surface side is smaller than an area of a second region as a region on the second main surface side.

[0030] Using Figure 1 and Figure 2 One example of the semiconductor device of the present application will be described.

[0031] Figure 1 is a perspective view schematically showing one example of the semiconductor device of the present application, Figure 2 is Figure 1 a cross-sectional view taken along the A-A line in

[0032] As shown in Figure 1 , the semiconductor device 1 has a semiconductor substrate 10 and a circuit layer 90.

[0033] The semiconductor substrate 10 has a first main surface 10a and a second main surface 10b that oppose each other in a thickness direction (T direction), a first end surface 10c and a second end surface 10d that oppose each other in a length direction (L direction) orthogonal to the thickness direction (T direction), and a first side surface 10e and a second side surface 10f that oppose each other in a width direction (W direction) orthogonal to the thickness direction (T direction) and the length direction (L direction).

[0034] The first main surface 10a, the second main surface 10b, the first end surface 10c, the second end surface 10d, the first side surface 10e, and the second side surface 10f of the semiconductor substrate 10 do not need to be smooth surfaces, and can be formed with unevenness.

[0035] The first main surface 10a and the second main surface 10b that oppose each other in the thickness direction (T direction) can be substantially parallel to each other. Therefore, the first main surface 10a and the second main surface 10b do not need to be strictly orthogonal to the thickness direction.

[0036] The first end surface 10c and the second end surface 10d that oppose each other in the length direction (L direction) can be substantially parallel to each other. Therefore, the first end surface 10c and the second end surface 10d do not need to be strictly orthogonal to the length direction.

[0037] The first side surface 10e and the second side surface 10f that oppose each other in the width direction (W direction) can be substantially parallel to each other. Therefore, the first side surface 10e and the second side surface 10f do not need to be strictly orthogonal to the width direction.

[0038] Therefore, for the semiconductor substrate that constitutes the semiconductor device of the present application, the first main surface 10a and the second main surface 10b, the first end surface 10c and the second end surface 10d, and the first side surface 10e and the second side surface 10f do not need to be strictly orthogonal, respectively.

[0039] In the present specification, a cross section of the semiconductor device 1 or the semiconductor substrate 10 that is parallel to the length direction (L direction) and the thickness direction (T direction) is referred to as an LT cross section. In addition, a cross section of the semiconductor device 1 or the semiconductor substrate 10 that is parallel to the width direction (W direction) and the thickness direction (T direction) is referred to as a WT cross section. In addition, a cross section of the semiconductor device 1 or the semiconductor substrate 10 that is parallel to the length direction (L direction) and the width direction (W direction) is referred to as an LW cross section.

[0040] The circuit layer 90 is provided on the first main surface 10a of the semiconductor substrate 10, and the first external electrode 70 and the second external electrode 80 are exposed on a surface on the side opposite to the semiconductor substrate 10 side.

[0041] The first external electrode 70 is provided on the second end surface 10d side of the semiconductor substrate 10, and the second external electrode 80 is provided on the first end surface 10c side of the semiconductor substrate 10.

[0042] As Figure 2 shown, an insulating layer 20 is provided on a first main surface 10a of a semiconductor substrate 10 that constitutes a semiconductor device 1, and a circuit layer 90 is provided on the insulating layer 20. The circuit layer 90 includes a first electrode layer 30 provided on the insulating layer 20, a dielectric layer 40 provided on the first electrode layer 30, a second electrode layer 50 provided on the dielectric layer 40, a first external electrode 70 electrically connected to the first electrode layer 30 and led out to a surface on the opposite side of the semiconductor substrate 10, and a second external electrode 80 electrically connected to the second electrode layer 50 and led out to a surface on the opposite side of the semiconductor substrate 10.

[0043] A protective layer 60 is provided on a surface of the dielectric layer 40 and a surface of a part of the second electrode layer 50.

[0044] The insulating layer 20 is provided between the first main surface 10a of the semiconductor substrate 10 and the first electrode layer 30.

[0045] Further, in Figure 2 the present embodiment, the circuit layer 90 is provided on the entire region of the first main surface 10a of the semiconductor substrate 10, but there can be a region on the first main surface 10a of the semiconductor substrate 10 on which the circuit layer 90 is not provided.

[0046] Further, the semiconductor substrate 10 has a first end region 11 and a second end region 12 on which the circuit layer 90 is not provided. The first end region 11 is disposed on a first end surface 10c side of the semiconductor substrate 10, and the second end region 12 is disposed on a second end surface 10d side of the semiconductor substrate 10.

[0047] The first end region 11 refers to a region from an end 90c of the circuit layer 90 on the first end surface 10c side to the first end surface 10c of the semiconductor substrate 10. Further, the second end region 12 refers to a region from an end 90d of the circuit layer 90 on the second end surface 10d side to the second end surface 10d.

[0048] The first end region 11 is provided with a first exposed portion 13.

[0049] The first exposed portion 13 is a portion exposed between the first main surface 10a and the first end surface 10c of the semiconductor substrate 10 other than the first main surface 10a.

[0050] In the first end portion region 11, when the first end portion region 11 is 2-divided in the thickness direction by a division line that 2-divides the semiconductor substrate 10 in the portion in which the circuit layer 90 is provided on the first main face 10a with the center in the thickness direction as a boundary, the area S1 of the first region 11a that is a region on the first main face 10a side is smaller than the area S2 of the second region 11b that is a region on the second main face 10b side.

[0051] That is, the semiconductor substrate 10 becomes a shape like a first main face 10a and a ridge line portion of a first end face 10c of a rectangular parallelepiped when the semiconductor substrate 10 is assumed to be a rectangular parallelepiped are chamfered.

[0052] In a case in which the semiconductor device is mounted on the pad and a voltage is applied, a power line that is generated due to a potential difference between the pad that is electrically connected to the second electrode layer and the first electrode layer that constitutes the circuit layer passes through the semiconductor substrate, and thus conductor loss caused by the resistance of the semiconductor substrate is generated. However, if the semiconductor substrate 10 is the shape described above, the volume of the semiconductor substrate 10 through which the power line passes is reduced, and it is possible to reduce the conductor loss caused by the resistance of the semiconductor substrate.

[0053] The second exposed portion 14 is provided in the second end portion region 12.

[0054] The second exposed portion 14 is a portion that is exposed between the first main face 10a and the second end face 10d other than the first main face 10a of the semiconductor substrate 10.

[0055] In the second end portion region 12, when the second end portion region 12 is 2-divided in the thickness direction by a division line that 2-divides the semiconductor substrate 10 in the portion in which the circuit layer 90 is provided on the first main face 10a with the center in the thickness direction as a boundary, the area S3 of the third region 12a that is a region on the first main face 10a side is smaller than the area S4 of the fourth region 12b that is a region on the second main face 10b side.

[0056] Further, when the semiconductor device is mounted on the substrate, a potential difference is not generated between the first electrode layer and the pad that is electrically connected to the first electrode layer. Therefore, Figure 2 the second exposed portion 14 in the first end portion region 11 does not have an effect of reducing conductor loss. Therefore, the second exposed portion can not be provided in the second end portion region. However, from the viewpoint of adjusting the weight balance of the semiconductor device and the viewpoint of reducing manufacturing costs, it is preferable that the second exposed portion be provided in the second end portion region. Furthermore, it is preferable that the shape of the first exposed portion and the shape of the second exposed portion be approximately linearly symmetrical.

[0057] In Figure 2In the middle, the first exposed portion 13 is an inclined shape in which the distance from the imaginary line 10c' obtained by extending the first end face 10c to the first exposed portion 13 in the length direction changes linearly from the first main face 10a toward the second main face 10b.

[0058] The second exposed portion 14 is roughly symmetrical in shape to the first exposed portion 13.

[0059] exist Figure 2 In the middle, the angle θ1 formed by the imaginary line 10c' obtained by extending the first end face 10c and the first exposed part 13 is 35.3°.

[0060] The angle θ1 formed by the imaginary line 10c' obtained by extending the first end face 10c and the first exposed portion 13 is not particularly limited, but is preferably 4° or more and 36° or less.

[0061] The ratio of the maximum thickness of the first exposed portion 13 to the thickness of the semiconductor substrate 10 is preferably 30% or more and 70% or less.

[0062] When the maximum thickness of the first exposed portion is less than 30% of the thickness of the semiconductor substrate, conductor losses cannot always be sufficiently reduced. On the other hand, when the maximum thickness of the first exposed portion is more than 70% of the thickness of the semiconductor substrate, debris that could damage the semiconductor device due to impacts can sometimes be generated.

[0063] Furthermore, the first exposed portion refers to the portion of the semiconductor substrate other than the first main surface that is exposed between the first main surface and the first end surface. Additionally, the maximum thickness of the first exposed portion is the maximum height of the first exposed portion when viewed from the first end surface; it is the height of the semiconductor substrate when viewed from the first end surface side minus the height of the first end surface (length in the height direction).

[0064] In the LT cross-section of the semiconductor substrate, the maximum length of the distance in the length direction from the imaginary line obtained by extending the first end face to the first exposed portion is preferably 5 μm or more and 20 μm or less.

[0065] In the semiconductor device of the present invention, the shape of the first exposed portion is not limited to the shape described above. Another example of the shape of the first exposed portion is... Figure 3 , Figure 4 as well as Figure 5 Please provide an explanation.

[0066] Figure 3 This is a cross-sectional view schematically illustrating another example of the semiconductor device of the present invention.

[0067] The semiconductor device 2 has a first end portion region 11 in which no circuit layer 90 is formed on the first main surface 10a of the semiconductor substrate 10. The first exposed portion 13a is formed in the first end portion region 11.

[0068] In the semiconductor device 2, a distance in a length direction from an imaginary line 10c' obtained by extending the first end surface 10c to the first exposed portion 13a in a region 13a1 on the first main surface 10a side when the first exposed portion 13a is divided in two in a thickness direction at a portion where the thickness of the first exposed portion 13a is the greatest changes by Δd1, which is smaller than a distance in a length direction from the imaginary line 10c' obtained by extending the first end surface 10c to the first exposed portion 13a in a region 13a2 on the second main surface 10b side changes by Δd2.

[0069] Figure 4 is a cross-sectional view schematically showing still another example of the semiconductor device of the present application.

[0070] The semiconductor device 3 has a first end portion region 11 in which no circuit layer 90 is formed on the semiconductor substrate 10. The first exposed portion 13b is formed in the first end portion region 11.

[0071] The semiconductor device 3 has a region 13b1 provided on the first main surface 10a side in which a distance in a length direction from an imaginary line 10c' obtained by extending the first end surface 10c to the first exposed portion 13b does not change, and a region 13b2 provided on the second main surface 10b side in which a distance in a length direction from the imaginary line 10c' obtained by extending the first end surface 10c to the first exposed portion 13b changes.

[0072] Figure 5 is a cross-sectional view schematically showing still another example of the semiconductor device of the present application.

[0073] The semiconductor device 4 has a first end portion region 11 in which no circuit layer 90 is formed on the semiconductor substrate 10. The first exposed portion 13c is formed in the first end portion region 11.

[0074] The semiconductor device 4 has a region 13c1 provided on the first main surface 10a side in which a distance in a length direction from an imaginary line 10c' obtained by extending the first end surface 10c to the first exposed portion 13c changes linearly, and a region 13c2 provided on the second main surface 10b side in which a distance in a length direction from the imaginary line 10c' obtained by extending the first end surface 10c to the first exposed portion 13c changes non-linearly from the first main surface 10a toward the second main surface 10b.

[0075] Further, in Figure 1 , Figure 2 , Figure 3 ,Figure 4 and Figure 5 Although an example in which no region in which the first exposed portion is not formed exists in the first end portion region is described in the first aspect, in the semiconductor device of the present application, a region in which the first exposed portion is not formed can exist in a part of the first end portion region.

[0076] In one embodiment of the semiconductor device of the present application, it is preferable that, in the LT cross section, the distance in the length direction from the imaginary line that extends the first end surface of the semiconductor substrate to the first electrode layer is longer than the distance in the length direction from the imaginary line to the second electrode layer.

[0077] Figure 6 is a cross-sectional view schematically showing one example of a circuit layer that configures the semiconductor device of the present application.

[0078] In Figure 6 In the semiconductor device 5 shown in FIG. 1, the distance Ll in the length direction from the imaginary line 10c' that extends the first end surface 10c of the semiconductor substrate 10 to the first electrode layer 30 is longer than the distance L2 in the length direction from the imaginary line 10c' that extends the first end surface 10c to the second electrode layer 50.

[0079] If Ll is longer than L2, when the semiconductor device 5 is mounted on a substrate and a voltage is applied, the electric field lines generated between the conductor such as a pad connected to the second external electrode 80 and the first electrode layer 30 can be shielded by the second electrode layer 50, and thus conductor loss can be suppressed.

[0080] The difference between the distance Ll and the distance L2 (distance L3) is not particularly limited, but is preferably 5 μm or more and 200 μm or less.

[0081] If the above distance L3 is less than 5 μm, sometimes the second electrode layer cannot sufficiently shield the electric field lines generated from the first electrode layer to the conductor such as a pad connected to the second external electrode. Conversely, if the above distance L3 exceeds 200 μm, the region in which the first electrode layer and the second electrode layer face each other becomes narrow, and sometimes the semiconductor device cannot exhibit a desired electrostatic capacity.

[0082] In one embodiment of the semiconductor device of the present application, it is preferable that the semiconductor substrate has a first side portion region on the first side surface side, the first side portion region is not provided with a circuit layer on the semiconductor substrate, and a third exposed portion is provided in the above first side portion region, the third exposed portion being a portion exposed between the first main surface and the first side surface other than the first main surface of the semiconductor substrate.

[0083] In the WT profile, when the first side portion region is 2-divided in the thickness direction by a division line that 2-divides the semiconductor substrate in the portion provided with the circuit layer on the first main face with the central portion in the thickness direction as a boundary, the area of a fifth region that is a region on the first main face side is smaller than the area of a sixth region that is a region on the second main face side.

[0084] In one embodiment of the semiconductor device of the present application, it is preferable that the semiconductor substrate have a second side portion region on the second side face side, that the second side portion region be a region on the semiconductor substrate where no circuit layer is provided, and that a fourth exposed portion be provided in the above-described second side portion region, the fourth exposed portion being a portion exposed between the first main face and the second side face other than the first main face of the semiconductor substrate.

[0085] In the WT profile, when the second side portion region is 2-divided in the thickness direction by a division line that 2-divides the semiconductor substrate in the portion provided with the circuit layer on the first main face with the central portion in the thickness direction as a boundary, the area of a seventh region that is a region on the first main face side is smaller than the area of an eighth region that is a region on the second main face side.

[0086] Further, it is preferable that the shape of the third exposed portion be approximately line-symmetrical to the shape of the fourth exposed portion.

[0087] Figure 7 is a perspective view schematically showing another example of the semiconductor device of the present application, Figure 8 is Figure 7 a B-B line cross-sectional view in

[0088] As shown in Figure 7 and Figure 8 , the semiconductor substrate 10 that constitutes the semiconductor device 6 has a first side portion region 15 and a second side portion region 16 where no circuit layer 90 is provided on the semiconductor substrate 10. The first side portion region 15 is disposed on the first side face 10e side of the semiconductor substrate 10, and the second side portion region 16 is disposed on the second side face 10f side.

[0089] The first side portion region 15 refers to a region from an end portion 90e of the first side face 10e side of the circuit layer 90 to the first side face 10e of the semiconductor substrate 10. Further, the second side portion region 16 refers to a region from an end portion 90f of the second side face 10f side of the circuit layer 90 to the second side face 10f.

[0090] The third exposed portion 17 is provided in the first side portion region 15.

[0091] The third exposed portion 17 is a portion exposed between the first main face 10a and the first side face 10e other than the first main face 10a of the semiconductor substrate 10.

[0092] In the first side portion region 15, when the first side portion region 15 is divided into two in the thickness direction by a division line that divides the semiconductor substrate 10 in the portion in which the circuit layer 90 is provided on the first main face 10a into two at the center in the thickness direction, the area S5 of the fifth region 15a, which is a region on the first main face 10a side, is smaller than the area S6 of the sixth region 15b, which is a region on the second main face 10b side.

[0093] That is, the semiconductor substrate 10 becomes a shape in which, for example, a corner portion of the first main face 10a and the first side face 10e when the semiconductor substrate 10 is assumed to be a rectangular parallelepiped is chamfered.

[0094] The fourth exposed portion 18 is provided in the second side portion region 16.

[0095] The fourth exposed portion 18 is a portion exposed between the first main face 10a and the second side face 10f other than the first main face 10a of the semiconductor substrate 10.

[0096] The fourth exposed portion 18 is a shape that is approximately line-symmetrical to the third exposed portion 17.

[0097] In the second side portion region 16, when the second side portion region 16 is divided into two in the thickness direction by a division line that divides the semiconductor substrate 10 in the portion in which the circuit layer 90 is provided on the first main face 10a into two at the center in the thickness direction, the area S7 of the seventh region 16a, which is a region on the first main face 10a side, is smaller than the area S8 of the eighth region 16b, which is a region on the second main face 10b side.

[0098] That is, the semiconductor substrate 10 becomes a shape in which, for example, a corner portion of the first main face 10a and the second side face 10f when the semiconductor substrate 10 is assumed to be a rectangular parallelepiped is chamfered.

[0099] In a case in which the semiconductor device 6 is mounted on a pad and a voltage is applied, a power line generated due to a potential difference between the pad on the side electrically connected to the second electrode layer 50 and the first electrode layer 30 that constitutes the circuit layer 90 passes through the semiconductor substrate 10, and thus conductor loss caused by the resistance of the semiconductor substrate occurs. However, if the semiconductor substrate 10 is the above-described shape, the volume of the semiconductor substrate 10 through which the power line passes decreases, and it is possible to reduce the conductor loss caused by the resistance of the semiconductor substrate 10.

[0100] Further, in Figure 7In the case where the semiconductor substrate 10 is assumed to be a rectangular parallelepiped, the entire region of the first side surface 10e of the semiconductor substrate 10 and the ridge line portion of the first main surface 10a and the entire region of the second side surface 10f and the ridge line portion of the first main surface 10a are provided with the third exposed portion 17 and the fourth exposed portion 18, respectively. Here, the power line that becomes a cause of conductor loss is generated between the pad connected to the second external electrode 80 and the first electrode layer 30, and thus the third exposed portion 17 and the fourth exposed portion 18 can not be provided at a position away from the pad connected to the second external electrode 80, for example, around the first external electrode 70.

[0101] The angle θ2 formed by the imaginary line 10e' obtained by extending the first side surface 10e and the third exposed portion 17 is not particularly limited, but is preferably 4° or more and 36° or less.

[0102] Hereinafter, each structure of the semiconductor device constituting the present application will be described.

[0103] As a material constituting the semiconductor substrate, silicon or the like is exemplified.

[0104] The specific resistance of the semiconductor substrate is preferably 10 －5 Ωcm or more and 10 5 Ωcm or less.

[0105] The outer dimensions of the semiconductor substrate are not particularly limited, but the length is preferably 200 μm or more and 600 μm or less, the thickness is preferably 50 μm or more and 100 μm or less, and the width is preferably 100 μm or more and 300 μm or less.

[0106] As a material constituting the first electrode layer, a metal such as Cu, Ag, Au, Al, Ni, Cr, Ti, or a conductor containing these metals is exemplified.

[0107] In addition, the first metal layer can have two or more conductor layers composed of the above-described materials.

[0108] The thickness of the first electrode layer is not particularly limited, but is preferably 0.3 μm or more and 10 μm or less, and more preferably 0.5 μm or more and 3 μm or less.

[0109] As a material constituting the dielectric layer, a material having dielectricity or insulation, such as an oxide such as SiO2, Al2O3, HfO2, Ta2O5, ZrO2, or a nitride such as Si3N4, is exemplified.

[0110] The thickness of the dielectric layer is not particularly limited, but is preferably 0.02 μm or more and 2 μm or less.

[0111] As a material constituting the second electrode layer, the same material as that constituting the first electrode layer can be appropriately used.

[0112] The thickness of the second electrode layer is not particularly limited, but is preferably 0.3 μm or more and 10 μm or less, and more preferably 0.5 μm or more and 5 μm or less.

[0113] As the material constituting the first external electrode and the second external electrode, Cu, Al, and the like are exemplified.

[0114] A plating layer can be formed on the most surface of the first external electrode and the second external electrode.

[0115] As the plating layer, a Au-plated layer, a Sn-plated layer, and the like are exemplified.

[0116] The material constituting the first external electrode and the material constituting the second external electrode can be the same as each other or different from each other.

[0117] The semiconductor device of the present application can be provided with an insulating layer between the first main surface of the semiconductor substrate and the first electrode layer.

[0118] If the insulating layer is provided between the first main surface of the semiconductor substrate and the first electrode layer, the current flowing from the first electrode layer to the semiconductor substrate can be suppressed.

[0119] As the material constituting the insulating layer, a material having higher electrical insulation than the semiconductor substrate is preferred, and for example, oxides such as SiO2, Al2O3, HfO2, Ta2O5, ZrO2, nitrides such as Si3N4, and the like are exemplified.

[0120] The thickness of the insulating layer is not particularly limited, but is preferably 0.5 μm or more and 3 μm or less.

[0121] The semiconductor device of the present application can be provided with a protective layer for protecting the dielectric layer and / or the second electrode layer from moisture on a part of the dielectric layer and the second electrode layer.

[0122] As the material constituting the protective layer, SiO2, Si3N4, and the like are exemplified.

[0123] The thickness of the protective layer is not particularly limited, but is preferably 0.5 μm or more and 5 μm or less.

[0124] The thickness of the entire circuit layer is preferably 5 μm or more and 30 μm or less.

[0125] [Method for manufacturing semiconductor device]

[0126] As a method of manufacturing the semiconductor device of the present application, for example, a method in which, for a semiconductor device in which a circuit layer is provided on a first main surface of a semiconductor substrate, a chamfering process is performed on a ridge line portion of the first main surface on the side of a second external electrode in the length direction of the semiconductor substrate (first end surface in the semiconductor device of the present application). At this time, a part of the circuit layer formed on the first main surface and an insulating layer provided on the semiconductor substrate side of the dielectric layer as necessary can also be removed within a range that does not hinder the function of the semiconductor device.

[0127] On the other hand, as a method of simultaneously mass-producing the semiconductor device of the present application, for example, a method in which, after a circuit layer is formed on the surface of a semiconductor wafer (a surface that becomes a first main surface) by a photolithography method or the like, the semiconductor wafer is cut and divided by dicing.

[0128] Figure 9 A、 Figure 9 B and Figure 9 C is a process chart schematically showing one example of a manufacturing method of the semiconductor device of the present application.

[0129] As shown in Figure 9 A, first, a plurality of regions that become circuit layers 90 are formed on the surface of a semiconductor wafer 150.

[0130] Next, as shown in Figure 9 B, anisotropic etching is performed on regions of the semiconductor wafer 150 on which the circuit layers 90 are not formed. By performing the anisotropic etching, grooves 112 are formed in the regions of the semiconductor wafer 150 on which the circuit layers 90 are not formed. The grooves 112 formed by the anisotropic etching are inclined at a prescribed angle with respect to the surface of the semiconductor wafer 150 (a surface that becomes a first main surface).

[0131] Finally, as shown in Figure 9 C, the semiconductor wafer 150 is cut by a dicing machine or the like to divide the semiconductor wafer 150 by the grooves 112 formed by the anisotropic etching, and a semiconductor device 1 can be obtained. The grooves 112 formed by the anisotropic etching become first and second exposed portions 13 and 14 in the semiconductor device 1. In addition, the surface of the semiconductor wafer 150 exposed by the cutting by the dicing machine becomes first and second end surfaces 10c and 10d of a semiconductor substrate 10.

[0132] As a method of the anisotropic etching, for example, a method in which, in the case where the material of the semiconductor wafer is Si and the surface on which the circuit layer is formed is a Si (100) surface, the semiconductor wafer is immersed in an alkali solution such as NaOH.

[0133] By immersing the semiconductor substrate in an alkali solution, the Si (100) surface can be etched to form a groove along the Si (111) surface. The Si (111) surface is inclined at 54.7° with respect to the Si (100) surface. Therefore, the angle θ1 formed by the groove formed by the anisotropic etching and an imaginary line obtained by extending the first end surface 10c is 35.3°.

[0134] Figure 10 A, Figure 10 B and Figure 10 C are process diagrams schematically showing another example of the method of manufacturing the semiconductor device of the present application.

[0135] As Figure 10 A shows, first, a plurality of regions that become the circuit layer 90 are formed on the surface of the semiconductor wafer 150.

[0136] Next, as Figure 10 B shows, the regions of the semiconductor wafer 150 on which the circuit layer 90 is not formed are isotropically etched. By isotropic etching, the groove 114 is formed in the regions of the semiconductor wafer 150 on which the circuit layer 90 is not formed.

[0137] Finally, as Figure 10 C shows, the groove 114 formed by the isotropic etching is cut by a dicing machine or the like, so that the semiconductor device 2 after singulation can be obtained.

[0138] The groove 114 formed by the isotropic etching becomes the first exposed portion 13a in the semiconductor device 2. In addition, the surface of the semiconductor wafer 150 exposed by the cutting by the dicing machine becomes the first end surface 10c and the second end surface 10d of the semiconductor substrate 10.

[0139] The isotropic etching can be performed by, for example, a mixed acid of hydrofluoric acid and nitric acid.

[0140] Figure 11 A, Figure 11 B and Figure 11 C are process diagrams schematically showing another example of the method of manufacturing the semiconductor device of the present application.

[0141] As Figure 11 A shows, first, a plurality of regions that become the circuit layer 90 are formed on the surface of the semiconductor wafer 150.

[0142] Next, as Figure 11 B shows, the regions of the semiconductor wafer 150 on which the circuit layer 90 is not formed are isotropically etched. By isotropic etching, the groove 114 is formed in the regions of the semiconductor wafer 150 on which the circuit layer 90 is not formed.

[0143] Finally, as Figure 11C, a second cutting is performed using a scribe narrower than the scribe used in the first cutting, so that the singulated semiconductor device 3 can be obtained.

[0144] The groove formed by the first cutting becomes the first exposed portion 13b in the semiconductor device 3. In addition, the surface of the semiconductor wafer 150 exposed by the second cutting becomes the first end surface 10c and the second end surface 10d of the semiconductor substrate 10.

[0145] Figure 12 A, Figure 12 B, and Figure 12 C is a process chart schematically showing still another example of the manufacturing method of the semiconductor device of the present application.

[0146] As shown in Figure 12 A, first, a plurality of regions that become the circuit layer 90 are formed on the surface of the semiconductor wafer 150.

[0147] Next, as shown in Figure 12 B, a first cutting is performed using a scribe to a depth of 30 to 70% of the thickness of the semiconductor wafer 150 in regions of the semiconductor wafer 150 where the circuit layer 90 is not formed, so that a tapered groove 118 is formed. The tapered groove 118 can be formed by cutting using a tapered scribe such as a bevel scribe, two pieces of scribes arranged in a V shape, or the like.

[0148] Finally, as shown in Figure 12 C, a second cutting is performed using a scribe narrower than the scribe used in the first cutting, so that the singulated semiconductor device 4 can be obtained.

[0149] The groove formed by the first cutting becomes the first exposed portion 13c in the semiconductor device 4. In addition, the surface of the semiconductor substrate 10 exposed by the second cutting becomes the first end surface 10c and the second end surface 10d of the semiconductor substrate 10.

[0150] [Module]

[0151] The module of the present application is characterized by comprising: the semiconductor device of the present application; a first land electrically connected to the above-mentioned first external electrode; and a second land electrically connected to the above-mentioned second external electrode and provided so as to protrude outwardly of the above-mentioned circuit layer.

[0152] The module of the present application comprises the semiconductor device of the present application, so that even in the case where the second land electrically connected to the second external electrode protrudes outwardly of the circuit layer, the volume of the semiconductor substrate through which the electric power line generated from the first electrode layer toward the second land passes becomes small, so that the conductor loss caused by the resistance of the semiconductor substrate can be reduced.

[0153] Figure 13 is a sectional view schematically showing one example of a module of the present application.

[0154] As shown in Figure 13 the module 100 is provided with the semiconductor device 1, a first land 120 electrically connected to a first external electrode 70 of the semiconductor device 1, and a second land 130 electrically connected to a second external electrode 80 of the semiconductor device 1. The first external electrode 70 and the first land 120 and the second external electrode 80 and the second land 130 are connected to each other by a solder 140.

[0155] The second land 130 is provided so as to protrude outwardly of the circuit layer 90. The first land 120 and the second land 130 are respectively fixed to the substrate 110.

[0156] The total of the maximum thickness Ta of the first exposed portion 13 and the shortest distance Tb from the semiconductor substrate 10 to the second land 130 is preferably 35 μm or more and 235 μm or less.

[0157] The longer the shortest distance Tb from the semiconductor substrate 10 to the second land 130, the weaker the electric power line generated between the semiconductor substrate 10 and the second land 130, and thus the maximum thickness Ta of the first exposed portion 13 can be shortened. If the total of the maximum thickness Ta of the first exposed portion 13 and the shortest distance Tb from the semiconductor substrate 10 to the second land 130 is 35 μm or more and 235 μm or less, the effect of reducing conductor loss is reliably exerted.

[0158] The maximum thickness Ta of the first exposed portion 13 is preferably 15 μm or more and 175 μm or less.

[0159] The shortest distance Tb from the semiconductor substrate 10 to the second land 130 is preferably 20 μm or more and 60 μm or less.

[0160] In the module of the present application, it is preferable that an alternating current be applied between the first land and the second land.

[0161] In the case where an alternating current is applied between the first land and the second land, conductor loss generated between the land connected to the second external electrode and the first electrode layer is repeatedly generated each time the direction of current is changed. In contrast, in the module of the present application, it is possible to reduce conductor loss generated each time the direction of current is changed, and thus it is particularly possible to reduce conductor loss in the case where an alternating current is applied.

[0162] Examples of the material constituting the first land and the second land include copper, gold, and the like.

[0163] In the module of the present application, it is preferable that a molding resin such as an epoxy-based resin be disposed between the second land and the semiconductor substrate.

[0164] The molded resin has a relatively high relative dielectric constant compared to air, and thus if the molded resin is disposed between the second pad and the semiconductor substrate, conductor loss generated between the second pad and the semiconductor device becomes large. If the module of the present application is used, conductor loss can be suppressed, and thus even if the molded resin is disposed between the second pad and the semiconductor substrate, an increase in conductor loss can be suppressed.

[0165] Reference Signs Description

[0166] 1, 2, 3, 4, 5, 6…semiconductor device; 10…semiconductor substrate; 10a…first main surface; 10b…second main surface; 10c…first end surface; 10c’…imaginary line obtained by extending the first end surface; 10d…second end surface; 10e…first side surface; 10e’…imaginary line obtained by extending the first side surface; 10f…second side surface; 11…first end portion region; 11a…first region; 11b…second region; 12…second end portion region; 12a…third region; 12b…fourth region; 13, 13a, 13b, 13c…first exposed portion; 13a1…region on the first main surface side when the first exposed portion is divided into two in the thickness direction; 13a2…region on the second main surface side when the first exposed portion is divided into two in the thickness direction; 13b1…region in which the distance in the length direction from the imaginary line to the first exposed portion does not change; 13b2…region in which the distance in the length direction from the imaginary line to the first exposed portion changes; 13c1…region in which the distance in the length direction from the imaginary line to the first exposed portion changes linearly; 13c2…region in which the distance in the length direction from the imaginary line to the first exposed portion changes nonlinearly; 14…second exposed portion; 15…first side portion region; 15a…fifth region; 15b…sixth region; 16…second side portion region; 16a…seventh region; 16b…eighth region; 17…third exposed portion; 18…fourth exposed portion; 20…insulating layer; 30…first electrode layer; 40…dielectric layer; 50…second electrode layer; 60…protective layer; 70…first external electrode; 80…second external electrode; 90…circuit layer; 90c…end portion on the first end surface side of the circuit layer; 90d…end portion on the second end surface side of the circuit layer; 90e…end portion on the first side surface side of the circuit layer; 90f…end portion on the second side surface side of the circuit layer; 100…module; 110…substrate; 112…groove formed by anisotropic etching; 114…groove formed by isotropic etching; 116, 118…groove formed by a doctor blade; 120…first land; 130…second land; 140…solder; 150…semiconductor wafer; S1…area of the first region; S2…area of the second region; S3…area of the third region; S4…area of the fourth region; S5…area of the fifth region; S6…area of the sixth region; S7…area of the seventh region; S8…area of the eighth region; Ta…maximum thickness of the first exposed portion; Tb…shortest distance from the semiconductor substrate to the second land; θ1…angle formed by the imaginary line obtained by extending the first end surface and the first exposed portion; θ2…angle formed by the imaginary line obtained by extending the first side surface and the third exposed portion; Δd1, Δd2…change in the distance in the length direction from the imaginary line to the first exposed portion.

Claims

1. A semiconductor device comprising: A semiconductor substrate has a first main surface and a second main surface opposed in a thickness direction, a first end surface and a second end surface opposed in a length direction orthogonal to the thickness direction, and a first side surface and a second side surface opposed in a width direction orthogonal to both the thickness direction and the length direction; and A circuit layer is disposed on the first main surface of the semiconductor substrate. The semiconductor device is characterized in that... The circuit layer includes: a first electrode layer disposed on the semiconductor substrate side; and a dielectric layer disposed on the first electrode layer; A second electrode layer disposed on the dielectric layer; a first external electrode electrically connected to the first electrode layer and led out to the surface of the circuit layer opposite to the semiconductor substrate; And a second external electrode that is electrically connected to the second electrode layer and led out to the surface of the circuit layer opposite to the semiconductor substrate. The semiconductor substrate has a first end region on the end face of the second external electrode side in the length direction, i.e., the first end face side, where no circuit layer is disposed on the semiconductor substrate. A first exposed portion is provided in the first end region. This first exposed portion is the portion exposed between the first main surface and the first end surface, excluding the first main surface of the semiconductor substrate. In a cross-section of the semiconductor substrate that cuts the semiconductor substrate in a direction parallel to the thickness direction and the length direction, when the first end region is divided into two parts along the thickness direction by a dividing line that divides the semiconductor substrate in the portion on the first main surface where the circuit layer is provided, with the center of the thickness direction as the boundary, the area of ​​the first region, which is the region on the first main surface side, is smaller than the area of ​​the second region, which is the region on the second main surface side.

2. The semiconductor device according to claim 1, wherein, In a cross-section of the semiconductor substrate cut in a direction parallel to the thickness direction and the length direction of the semiconductor substrate, the first exposed portion is an inclined shape in which the distance in the length direction from the first main surface to the second main surface is linearly varied from the first main surface to the second main surface, from an imaginary line obtained by extending the first end face to the first exposed portion.

3. The semiconductor device according to claim 2, wherein, In a cross-section of the semiconductor substrate cut in a direction parallel to the thickness direction and the length direction of the semiconductor substrate, the angle between the imaginary line obtained by extending the first end face and the first exposed portion is 4° or more and 36° or less.

4. The semiconductor device according to claim 1, wherein, In a cross-section that cuts the semiconductor substrate in a direction parallel to both the thickness and length directions, the first exposed portion is a shape in which the distance along the length direction from the first main surface to the second main surface changes non-linearly from the first main surface to the second main surface, from an imaginary line obtained by extending the first end face to the first exposed portion. When the first exposed portion is divided into two parts along the thickness direction at its maximum thickness, the change in distance along the length direction from the imaginary line obtained by extending the first end face to the first exposed portion in the region of the first main surface is less than the change in distance along the length direction from the imaginary line obtained by extending the first end face to the first exposed portion in the region of the second main surface.

5. The semiconductor device according to claim 1, wherein, In a cross-section that cuts the semiconductor substrate in a direction parallel to the thickness direction and the length direction of the semiconductor substrate, the first exposed portion has a shape having two regions: a region located on the first main surface side where the distance in the length direction from the imaginary line obtained by extending the first end face to the first exposed portion does not change, and a region located on the second main surface side where the distance in the length direction from the imaginary line obtained by extending the first end face to the first exposed portion changes.

6. The semiconductor device according to claim 1, wherein, In a cross-section that cuts the semiconductor substrate in a direction parallel to the thickness direction and the length direction of the semiconductor substrate, the first exposed portion has a shape having two regions: a region located on the first main surface side where the distance along the length direction changes linearly from the imaginary line obtained by extending the first end face to the first exposed portion, and a region located on the second main surface side where the distance along the length direction changes non-linearly from the imaginary line obtained by extending the first end face to the first exposed portion.

7. The semiconductor device according to any one of claims 1 to 6, wherein, In a cross-section of the semiconductor substrate cut in a direction parallel to the thickness direction and the length direction of the semiconductor substrate, the maximum thickness of the first exposed portion is 30% or more and 70% or less relative to the thickness of the semiconductor substrate.

8. The semiconductor device according to any one of claims 1 to 7, wherein, In a cross-section of the semiconductor substrate cut in a direction parallel to the thickness direction and the length direction of the semiconductor substrate, the maximum length of the distance in the length direction from the imaginary line obtained by extending the first end face to the first exposed portion is 5 μm or more and 20 μm or less.

9. The semiconductor device according to any one of claims 1 to 8, wherein, The semiconductor substrate has a second end region on the end face of the first external electrode side in the length direction, which is also the second end face side. The circuit layer is not disposed on the first main surface in this second end region. A second exposed portion is provided in the second end region. This second exposed portion is the portion exposed between the first main surface and the second end surface, excluding the first main surface of the semiconductor substrate. In a cross-section that cuts the semiconductor substrate in a direction parallel to the thickness direction and the length direction of the semiconductor substrate, when the second end region is divided into two parts along the thickness direction by a dividing line that divides the semiconductor substrate in the portion on the first main surface where the circuit layer is provided, with the center of the thickness direction as the boundary, the area of ​​the third region, which is the region on the first main surface side, is smaller than the area of ​​the fourth region, which is the region on the second main surface side.

10. The semiconductor device according to claim 9, wherein, In a cross-section that cuts the semiconductor substrate in a direction parallel to the thickness direction and the length direction of the semiconductor substrate, the shape of the first exposed portion is approximately linearly symmetrical to the shape of the second exposed portion.

11. The semiconductor device according to any one of claims 1 to 10, wherein, The semiconductor substrate has a first side region on the first side surface, and the circuit layer is not disposed on the first main surface of the first side region. A third exposed portion is provided in the first side region. This third exposed portion is the portion exposed between the first main surface and the first side surface, excluding the first main surface of the semiconductor substrate. In a cross-section of the semiconductor substrate that cuts the semiconductor substrate in a direction parallel to the thickness direction and the width direction, when the first side region is divided into two parts along the thickness direction by a dividing line that divides the semiconductor substrate in the portion on the first main surface where the circuit layer is provided, with the center of the thickness direction as the boundary, the area of ​​the fifth region, which is the region on the first main surface side, is smaller than the area of ​​the sixth region, which is the region on the second main surface side.

12. The semiconductor device according to claim 11, wherein, The semiconductor substrate has a second side region on the second side surface, and the circuit layer is not disposed on the first main surface in this second side region. A fourth exposed portion is provided in the second side region. This fourth exposed portion is the portion exposed between the first main surface and the second side surface, excluding the first main surface of the semiconductor substrate. In a cross-section that cuts the semiconductor substrate in a direction parallel to the thickness direction and the width direction of the semiconductor substrate, when the second side region is divided into two parts along the thickness direction by a dividing line that divides the semiconductor substrate in the portion on the first main surface where the circuit layer is provided, with the center of the thickness direction as the boundary, the area of ​​the seventh region, which is the region on the first main surface side, is smaller than the area of ​​the eighth region, which is the region on the second main surface side.

13. The semiconductor device according to claim 12, wherein, In a cross-section that cuts the semiconductor substrate in a direction parallel to the thickness and width directions of the semiconductor substrate, the shape of the third exposed portion is approximately linearly symmetrical to the shape of the fourth exposed portion.

14. The semiconductor device according to any one of claims 1 to 13, wherein, An insulating layer is provided between the first main surface of the semiconductor substrate and the circuit layer.

15. A module, characterized in that, have: The semiconductor device as described in any one of claims 1 to 14; The first pad is electrically connected to the first external electrode; and The second pad is electrically connected to the second external electrode and is provided to protrude outward from the circuit layer.

16. The module according to claim 15, wherein, An alternating current is applied between the first pad and the second pad.

17. The module according to claim 15 or 16, wherein, A molding resin is disposed between the second pad and the semiconductor substrate.

18. The module according to any one of claims 15 to 17, wherein, The sum of the maximum thickness of the first exposed portion and the shortest distance from the semiconductor substrate to the second pad is more than 35 μm and less than 235 μm.

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