A test system for the time delay characteristics of a phase-stabilized cable

Abstract

The present invention discloses a test system for the time delay characteristic of a phase-stabilized cable. The test system includes: a high-stability clock module, an FPGA chip, a digital-to-analog converter DA, an analog-to-digital converter AD, and a band-pass filter. The high-frequency cable to be tested is connected between the band-pass filter and the analog-to-digital converter AD. The high-stability clock module is configured to generate a high-stability working clock for the FPGA chip, the digital-to-analog converter DA, and the analog-to-digital converter AD. The FPGA chip is provided with a reference signal generation module, a phase calculation branch, a time delay calculation module, a digital up-conversion module, and a digital down-conversion module. This test system is used for the high-precision test of the high-frequency signal transmission time delay characteristic of the phase-stabilized cable. The precision is very high, and real-time observation at the sub-millimeter level can be achieved. At the same time, the implementation is simple and the cost is low, and it can be well applied to the high-precision measurement of the transmission time delay characteristic of the phase-stabilized cable.

Description

Technical Field

[0001] The present invention belongs to the field of aerospace measurement and relates to a test system for the time delay characteristics of a phase-stabilized cable. Background Art

[0002] Range measurement is one of the most core functions in the aerospace TT&C system. Currently, the mainstream TT&C systems in China include the standard TT&C system, the spread-spectrum TT&C system, the integrated TT&C and data transmission system, the spread-spectrum and frequency-hopping TT&C system, etc. Among them, the spread-spectrum TT&C system in the non-coherent mode is the most widely used, and at the same time, the range measurement accuracy is the highest. For the ground measurement system, the ranging accuracy can reach about 1 meter. In order to build a new generation of high-precision orbit determination system, the high-resolution special project system construction project has put forward higher requirements for the orbit measurement of high-orbit satellites, requiring the ranging error accuracy of the ground TT&C system to be further improved to the sub-centimeter level, which is two orders of magnitude higher than the existing ranging accuracy. It is a great challenge to overcome the new generation of ground TT&C technology and develop the equipment.

[0003] The aerospace ground TT&C system is a complex large system composed of hundreds of devices or components, including antennas, feeds, power amplifiers, low-noise amplifiers, frequency conversion channels, basebands, system monitors, etc. For the sub-centimeter level high-precision range measurement technology, any slight change in the transmission time delay introduced by the high-frequency measurement signal on any high-frequency transmission cable in the link may be catastrophic. This requires us to select high-frequency phase-stabilized cables with extremely high transmission time delay stability.

[0004] The mainstream method for testing and screening the transmission time delay characteristics of phase-stabilized cables is to use a network vector analyzer for testing. The current most advanced network analyzer has a time delay measurement accuracy better than 1 ns, and the accuracy can reach 0.1 ns (the measurement error in terms of distance is about 3 cm) when using a large number of averages. If the phase method is selected for testing, the test accuracy can reach better than 0.01 ns (the measurement error in terms of distance reaches the sub-centimeter level), barely meeting the test requirements. However, during the actual measurement in the process of developing the sub-centimeter level aerospace ground measurement system project, it is found that for the same batch of phase-stabilized cables that meet the index requirements when measured with a high-precision network vector analyzer, there are still differences in the ranging errors generated by different cable individuals for high-precision range measurement in the aerospace ground TT&C system. This is because of the extremely subtle short-term or long-term changes caused by the impedance matching or self-excitation of the cables, which cannot be reflected even in the advanced network vector analyzer and cannot meet the requirements of high-precision measurement and screening; moreover, the high-precision network vector analyzer equipment itself is very expensive, which also greatly increases the R & D cost. Summary of the Invention

[0005] The object of the present invention is to provide a test system for the time-delay characteristics of a phase-stabilized cable to overcome the defects of the prior art. This test system is used for the high-precision measurement of the time-delay characteristics of high-frequency signal transmission in a phase-stabilized cable. The precision is very high, enabling real-time observation at the sub-millimeter level. Meanwhile, it is simple to implement and low in cost, and can be well applied to the high-precision measurement of the transmission time-delay characteristics of a phase-stabilized cable.

[0006] The object of the present invention is achieved through the following technical solutions:

[0007] A test system for the time-delay characteristics of a phase-stabilized cable, the test system comprising: a high-stability clock module, an FPGA chip, a digital-to-analog converter DA, an analog-to-digital converter AD, and a band-pass filter. The high-frequency cable to be tested is connected between the band-pass filter and the analog-to-digital converter AD;

[0008] The high-stability clock module is configured to generate a high-stability working clock for the FPGA chip, the digital-to-analog converter DA, and the analog-to-digital converter AD;

[0009] The FPGA chip is provided with a reference signal generation module, a phase calculation branch, a time-delay calculation module, a digital up-conversion module, and a digital down-conversion module;

[0010] The reference signal generation module generates a digital reference signal under the drive of the high-stability working clock;

[0011] The digital up-conversion module is combined with the digital-to-analog converter DA to modulate the digital reference signal to the radio frequency frequency point to be tested, and filter out harmonic and clutter components through a series-connected band-pass filter;

[0012] The analog-to-digital converter AD is combined with the digital down-conversion module in the FPGA chip to complete the digital sampling of the loopback test signal and digital down-conversion to the reference signal frequency;

[0013] The received signal after digital down-conversion enters the phase calculation branch, and phase information is obtained through the phase calculation branch;

[0014] The time-delay calculation module calculates the received phase information, outputs the real-time phase value τ(b) externally according to the set refresh rate, continuously monitors the peak-to-peak value of the real-time time-delay value, and obtains the output time-delay consistency level index P T 。

[0015] According to a preferred embodiment, a high-stability clock source and a high-stability frequency synthesizer are connected in series in the high-stability clock module; the high-stability clock module generates a high-stability working clock by passing the reference clock signal generated by the high-stability clock source through the high-stability frequency synthesizer.

[0016] According to a preferred embodiment, the phase calculation branch includes: a conjugate correlation module and an integration and clearing module. The conjugate correlation module performs conjugate multiplication on the received test signal and the reference signal, and through the filtering process of the integration and clearing module, the sampled phase information is obtained.

[0017] According to a preferred embodiment, the reference signal generation module generates a digital reference signal as a sine single-tone signal, and configures the frequency control word through the direct digital synthesizer DDS according to the formula ctrl = f0 / f s ×2 N where f0 is the frequency of the reference single-tone signal, f

[0018] is the working clock of the FPGA system, and N is the bit width generated by the direct digital synthesizer DDS. The reference signal generation module generates a reference complex signal s(n) with a frequency of f0. s

[0019] According to a preferred embodiment, the received signal after digital down-conversion is r(n), which enters the phase calculation branch, performs conjugate multiplication with the reference complex signal s(n), and the obtained result is processed through a series-connected integration and clearing module. The integration sampling rate f ds s =f s / I, where f ds is the working clock of the FPGA system, I is the number of points for the first integration, and the clear pulse is generated by an accumulator with an overflow limit of I, so as to obtain the real-time phase information with a sampling rate of f ds ds

[0020] According to a preferred embodiment, the time delay calculation module performs an arctangent calculation on the real-time phase information processed by the previous-stage module at a sampling rate of f ds to obtain the real-time phase value with a sampling rate of f ds

[0021] If it is set to output the real-time phase value τ(b) externally at a refresh rate of f b b ds where f b <f ds The calculation process of τ(b) is obtained by using an accumulator to calculate the average, and is calculated according to the following formula:

[0022]

[0023] T At the same time, the time delay calculation module outputs the time delay consistency level index P T The calculation of P

[0024]

[0025] Among them, by continuously comparing real-time phase values within a preset time period the maximum phase value is obtained and the minimum phase value c is the speed of light, and f RF is the radio frequency.

[0026] The main solution of the present invention and its various further alternative solutions can be freely combined to form multiple solutions, all of which are solutions that can be adopted and claimed by the present invention. Those skilled in the art can understand that there are various combinations according to the prior art and common general knowledge after understanding the solution of the present invention, and all of them are the technical solutions to be protected by the present invention, and will not be enumerated here.

[0027] Advantages of the present invention:

[0028] High test accuracy. The test system adopted by the present invention can monitor the phase mean value and time-delay consistency level of the high-frequency electrical conduction of the phase-stabilized cable in real time according to the set refresh rate for high-precision monitoring. In the case of an externally supplied high-stability clock source, the measured time-delay monitoring accuracy can achieve a monitoring accuracy better than 0.003 ns, and the converted distance test accuracy can reach the sub-millimeter level, which can very finely monitor the transmission stability of the high-frequency electrical signal by the phase-stabilized cable to meet the high-precision test and screening requirements for the phase-stabilized cable in the development process of the satellite high-precision distance measurement system.

[0029] Good real-time processing. The test system adopted by the present invention only requires a small number of integration points to meet the requirements of high-precision phase detection. By setting a higher refresh rate, the transient transmission characteristics of the signal in the phase-stabilized cable can be reflected very real-time.

[0030] The phase consistency level can be continuously tracked. The present invention can realize long-term tracking of the phase consistency level of the phase-stabilized cable through extreme value detection and continuous update of the real-time phase value.

[0031] The implementation circuit is simple and the cost is low. The hardware circuit involved in the present invention is a circuit mainly composed of an FPGA, an analog-to-digital converter AD, a digital-to-analog converter DA, and a high-stability frequency synthesizer, all of which belong to very common and mature circuit designs on the market. The circuit structure is generally simple and the cost is low. Description of the drawings

[0032] Figure 1 is a schematic diagram of the principle structure of the test system of the present invention. Detailed implementation manners

[0033] The following describes the implementation manners of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0034] It should be noted that, for the purpose of making the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be described clearly and completely below. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments.

[0035] In addition, the present invention points out that in the present invention, if the specifically involved structures, connection relationships, position relationships, power source relationships, etc. are not particularly written out, the structures, connection relationships, position relationships, power source relationships, etc. involved in the present invention are all known to those skilled in the art based on the prior art without creative labor.

[0036] Embodiment 1:

[0037] The present invention discloses a test system for the time-delay characteristic of a phase-stabilized cable. The test system includes: a high-stability clock module, an FPGA chip, a digital-to-analog converter DA, an analog-to-digital converter AD, and a band-pass filter. The high-frequency cable to be tested is connected between the band-pass filter and the analog-to-digital converter AD.

[0038] A high-stability clock source and a high-stability frequency synthesizer are connected in series in the high-stability clock module.

[0039] A reference signal generation module, a phase calculation branch, a time-delay calculation module, a digital up-conversion module, and a digital down-conversion module are provided in the FPGA chip.

[0040] Referring to Figure 1 , Figure 1 shows the working principle of the test system of the present invention. Specifically:

[0041] The high-stability clock module realizes generating a high-stability working clock for the FPGA chip, the digital-to-analog converter DA, and the analog-to-digital converter AD by the high-stability frequency synthesizer from the reference clock signal generated by the high-stability clock source.

[0042] The reference signal generation module generates a digital reference signal driven by the high-stability working clock.

[0043] The digital up-conversion module is combined with the digital-to-analog converter DA to modulate the digital reference signal to the radio frequency frequency point to be tested, and filter out harmonic and clutter components through the series-connected band-pass filter.

[0044] The analog-to-digital converter AD is combined with the digital down-conversion module in the FPGA chip to complete the digital sampling of the loopback test signal and the digital down-conversion to the reference signal frequency.

[0045] The received signal after digital down-conversion enters the phase calculation branch, and the phase information is obtained through the phase calculation branch.

[0046] Specifically, the phase calculation branch includes: a conjugate correlation module and an ID integral clearing module. The conjugate correlation module performs conjugate multiplication on the received test signal and the reference signal, and through the filtering process of the integral clearing module, the sampled phase information is obtained.

[0047] The time delay calculation module calculates the received phase information, outputs the real-time phase value τ(b) externally according to the set refresh rate, continuously monitors the peak-to-peak value of the real-time time delay value, and obtains the output time delay consistency level index P T 。

[0048] Preferably, the reference signal generation module generates a digital reference signal as a sine single-tone signal, and configures the frequency control word according to the formula ctrl = f0 / f s ×2 N through the direct digital synthesizer DDS,

[0049] where f0 is the frequency of the reference single-tone signal, f s is the working clock of the FPGA system, N is the bit width generated by the direct digital synthesizer DDS, and the reference signal generation module generates a reference complex signal s(n) with a frequency of f0.

[0050] Preferably, the received signal r(n) after digital down-conversion enters the phase calculation branch, performs conjugate multiplication with the reference complex signal s(n), and the obtained result is processed through a series-connected integral clearing module. The integral sampling rate f ds = f s / I, where f s is the working clock of the FPGA system, I is the number of points for one-time integration, and the clear pulse is generated by an accumulator with an overflow limit of I, so as to obtain the real-time phase information with a sampling rate of f ds .

[0051] Preferably, the time delay calculation module performs an arctangent calculation on the real-time phase information processed by the previous-stage module at the sampling rate f ds to obtain the real-time phase value at the sampling rate f ds

[0052] If it is set to output the real-time phase value τ(b) externally at the refresh rate of f b where f​b <f ds The calculation process of τ(b) is obtained by using an accumulator to calculate the average, and the calculation is performed according to the following formula:

[0053]

[0054] At the same time, the time delay resolution module outputs the time delay consistency level index P T ,P T The calculation of P is performed according to the following formula:

[0055]

[0056] Among them, by continuously comparing the real-time phase value within a preset time period to obtain the maximum phase value and the minimum phase value c is the speed of light, which is 299792458 m / s, f RF is the radio frequency.

[0057] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A test system for the time delay characteristic of a phase-stabilized cable, characterized in that, The described test system includes: a high-stability clock module, an FPGA chip, a digital-to-analog converter DA, an analog-to-digital converter AD, and a band-pass filter. The high-frequency cable to be tested is connected between the band-pass filter and the analog-to-digital converter AD; The high-stability clock module is configured to generate high-stability working clocks for the FPGA chip, the digital-to-analog converter DA, and the analog-to-digital converter AD; The FPGA chip is provided with a reference signal generation module, a phase calculation branch, a time delay resolution module, a digital up-conversion module, and a digital down-conversion module; The reference signal generation module generates a digital reference signal under the drive of the high-stability working clock; The digital up-conversion module is combined with the digital-to-analog converter DA to modulate the digital reference signal to the radio frequency frequency point to be tested, and filter out harmonic and clutter components through a series-connected band-pass filter; The analog-to-digital converter AD is combined with the digital down-conversion module in the FPGA chip to complete digital sampling of the loopback test signal and digital down-conversion to the reference signal frequency; The received signal after digital down-conversion enters the phase calculation branch, and phase information is obtained through the phase calculation branch; The reference signal generation module generates a digital reference signal as a sine single-tone signal, and configures a frequency control word according to the formula ctrl=f0 / f through a direct digital synthesizer (DDS). s ×2 N ​ Among them, f0 is the reference single-tone signal frequency, f s is the working clock of the FPGA system, N is the bit width produced by the direct digital synthesizer DDS, and the reference signal generation module generates a reference complex signal s(n) with a frequency of f0; The time delay calculation module calculates the received phase information, outputs the real-time phase value τ(b) externally according to the set refresh rate, continuously monitors the peak-to-peak value of the real-time time delay value, and obtains the output time delay consistency level index P T ; The time delay calculation module performs arctangent calculation on the real-time phase information obtained by the previous-stage module at a sampling rate of f ds to obtain a real-time phase value at a sampling rate of f ds ​ If it is set to output the real-time phase value τ(b) externally at a refresh rate of f b , where f b < f ds , the calculation process of τ(b) is obtained by using an accumulator to calculate the average, and the calculation is performed according to the following formula: Meanwhile, the time delay calculation module outputs the time delay consistency level index P T , P T is calculated according to the following formula: Among them, by continuously comparing the real-time phase values within a preset time period the maximum phase value is obtained and the minimum phase value c is the speed of light, and f RF is the radio frequency.

2. The phase-stabilized cable time-delay characteristic test system according to claim 1, wherein A high-stability clock source and a high-stability frequency synthesizer are sequentially connected in series in the high-stability clock module; The high-stability clock module generates a high-stability working clock by passing the reference clock signal generated by the high-stability clock source through the high-stability frequency synthesizer.

3. The phase-stabilized cable time-delay characteristic test system according to claim 1, wherein The phase calculation branch includes: a conjugate correlation module and an integration and clearing module, The conjugate correlation module performs conjugate multiplication on the received test signal and the reference signal, and obtains the sampled phase information through the filtering process of the integration and clearing module.

4. The phase-stabilized cable time-delay characteristic test system according to claim 3, wherein, The reference signal generation module generates a digital reference signal as a sinusoidal single-tone signal, and configures the frequency control word according to the formula ctrl = f0 / f through a direct digital synthesizer (DDS). s ×2 N ​ Among them, f0 is the reference single-tone signal frequency, f s is the working clock of the FPGA system, N is the bit width produced by the direct digital synthesizer DDS, and the reference signal generation module generates a reference complex signal s(n) with a frequency of f0.

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