Overcurrent Detection Circuit and Overcurrent Detection Method for High-Voltage Driving Chip

Abstract

The present application discloses an overcurrent detection circuit and an overcurrent detection method for a high-voltage drive chip, belonging to the technical field of integrated circuits. In the circuit, when the falling-edge detection circuit detects the falling edge of the floating ground in the high-voltage region and the output of the low-voltage output port is a high-level signal, the logic control circuit is used to output a high-level signal to the high-precision voltage detection circuit; when the output of the low-voltage output port is a low-level signal, the logic control circuit is used to output a low-level signal to the high-precision voltage detection circuit; the high-precision voltage detection circuit is used to turn on overcurrent detection when receiving a high-level signal and turn off overcurrent detection when receiving a low-level signal; the comparator is used to generate an overcurrent detection result according to the detected voltage and the reference voltage. The present application can improve the overcurrent detection accuracy, avoid the problem of easy misjudgment due to too early detection time and easy omission of narrow pulse widths due to too late detection time, and improve the timeliness of overcurrent detection.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit technologies, and particularly to an overcurrent detection circuit and an overcurrent detection method for a high-voltage drive chip. Background Art

[0002] Power drive circuits are widely used in fields such as new energy vehicles, motor drives, electronic ballasts, and switched-mode power supplies. They can be used to drive two power MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) transistors or IGBT (Insulated Gate Bipolar Transistor) transistors connected in a totem-pole form to make them conduct alternately. Since N-type power devices have lower on-resistance and smaller parasitic capacitance compared to P-type power devices, in high-voltage applications above 60V and even up to 600V, usually two N-type power devices are used, such as Figure 1 as shown, M H is the above-mentioned high-side switching device, and M L is the above-mentioned low-side switching device. Usually, a high-voltage drive chip is used to effectively drive the high-side switching device M H . The high-voltage drive chip includes a high-voltage region gate drive circuit and a low-voltage region gate drive circuit. LIN is the input signal of the low-voltage region gate drive circuit, HIN is the input signal of the high-voltage region gate drive circuit, and the control signals of LIN and HIN come from an external microcontroller. LO is the output signal of the low-voltage region gate drive circuit, connected to the gate of M L , and HO is the output signal of the high-voltage region gate drive circuit, connected to the gate of M H . The voltage domain from the low-voltage power supply VCC to the low-voltage region ground GND supplies power to the low-voltage region gate drive circuit, and the floating voltage domain from the high-side power supply VB to the high-voltage region floating ground VS supplies power to the high-voltage region gate drive circuit. VS is connected to the source of M H and the drain of M L . A high-voltage diode D B and a bootstrap capacitor C B are used to supply power to VB. When M L is turned on, VCC charges C B through D B and supplies power to the high-voltage region gate drive circuit; when M H is turned on, C B takes on the task of supplying power to the high-voltage region gate drive circuit, and so on. One end of the inductor L is connected to VS, and the other end is connected to the output voltage Vout. The capacitor C and the resistor R0 are connected in parallel, with one end connected to Vout and the other end connected to GND. In the application of the high-voltage drive chip, usually a series resistor R SENSEConnected in series between the source of M L and ground, the error amplifier is used as a comparator to compare V SENSE with the reference voltage Vref, and the obtained over-current signal is transmitted to the microcontroller. After receiving the over-current signal, the microcontroller shuts off the transmission signals of the high-side and low-side. This over-current detection method has high requirements for system-level configuration, and the application system is complex with low detection accuracy.

[0003] To solve the over-current protection problem of the high-voltage drive chip, a bidirectional current detection circuit in on-chip integration was proposed in US Patent US7548029B2, as Figure 2 shown. The bidirectional current detection circuit includes a high-voltage power MOSFET M1, medium- and low-voltage MOSFETs M2 to M9, Zener diodes D1 and D2, a resistor R S1 and current sources I REF1 and I REF2 . Among them, the sources of PMOS transistor M6 and PMOS transistor M7 are connected to the low-voltage power supply VCC. The gate of M6 is connected to the drain of M6, the gate of M7, and the input end of I REF2 . The drain of M7 is connected to the drain of NMOS transistor M8, the gate of M8, and the gates of NMOS transistors M9. The output end of current source I REF2 is connected to the sources of M8 and M9 and the anode of D1, and is connected to GND. The drain of M9 is connected to the source of M1 and the cathode of D1 and serves as the over-current detection voltage output V SENSE . The gate of M1 is connected to the control signal to ensure that M L is turned on after being turned on for a period of time, and over-current detection is performed. The drain of M1 is connected to the source of NMOS transistor M5 and the anode of D2. The gate of M5 is connected to the gate of NMOS transistor M4, the drain of M4, and the drain of PMOS transistor M3. The gate of PMOS transistor M2 is connected to its drain, the gate of M3, and the input port of I REF1 . The drain of M5 is connected to the cathode of D2, the sources of M3 and M2, and is connected to VB. The source of M4 is connected to one end of R S1 . The other end of R S1 is connected to the output port of IREF1 and is connected to VS. The above bidirectional current detection circuit can effectively integrate the over-current protection circuit into the high-voltage drive chip, but there are two problems: (1) The EN terminal, as the start port of over-current detection, must be turned on and delayed for a period of time before it can be performed. A relatively large delay time will cause the over-current judgment to be impossible for a relatively narrow LO pulse width, as Figure 3 shown. A too short delay time will cause an over-current misjudgment caused by the voltage in the high-voltage area not yet decreasing, ultimately resulting in the high-voltage drive chip not being able to work; (2) The voltage of V SENSE is the drain voltage of M1 minus the on-voltage drop of M1. Even using RS1 It is still very difficult to accurately detect the drain voltage of M1, especially under very harsh conditions such as automotive electronics, where the detected voltage of V SENSE varies greatly. It is possible that overcurrent has occurred but not detected, which may damage the high-voltage drive chip. It is also possible that overcurrent protection operation is triggered without overcurrent, causing false triggering and affecting the normal operation of the high-voltage drive chip. Summary of the Invention

[0004] An embodiment of the present application provides an overcurrent detection circuit and an overcurrent detection method for a high-voltage drive chip, which are used to solve the problems of detection accuracy, easy misjudgment due to too early detection time, and easy omission of narrow pulse width due to too late detection time. The technical solutions are as follows:

[0005] On the one hand, an overcurrent detection circuit for a high-voltage drive chip is provided. The overcurrent detection circuit includes: a falling edge detection circuit, a logic control circuit, a high-precision voltage detection circuit, and a comparator;

[0006] The first input port of the falling edge detection circuit is connected to the high-voltage side power supply or the high-voltage area floating ground, the second input port is connected to the low-voltage power supply, and the output port is connected to the first input port of the logic control circuit;

[0007] The second input port of the logic control circuit is connected to the low-voltage output port of the low-voltage area gate drive circuit, the third input port is connected to the output port of the power-on reset circuit, the fourth input port and the power supply port are respectively connected to the low-voltage power supply, the grounding port is connected to the low-voltage area ground, and the output port is connected to the first input port of the high-precision voltage detection circuit;

[0008] The second input port of the high-precision voltage detection circuit is connected to the high-voltage area floating ground, the power supply port is connected to the low-voltage power supply, the grounding port is connected to the low-voltage area ground, and the output port is connected to the non-inverting input port of the comparator;

[0009] The inverting input port of the comparator is connected to the reference voltage, and the output port is connected to the low-voltage area gate drive circuit;

[0010] When the falling edge detection circuit detects the falling edge of the high-voltage area floating ground and the output of the low-voltage output port is a high-level signal, the logic control circuit is used to output a high-level signal to the high-precision voltage detection circuit; when the output of the low-voltage output port is a low-level signal, the logic control circuit is used to output a low-level signal to the high-precision voltage detection circuit;

[0011] The high-precision voltage detection circuit is used to start overcurrent detection when receiving a high-level signal and turn off overcurrent detection when receiving a low-level signal;

[0012] The comparator is used to generate an overcurrent detection result according to the detected voltage and the reference voltage.

[0013] In a possible implementation, the falling edge detection circuit includes: a capacitive device, a first current source, and a diode;

[0014] One port of the capacitive device serves as the first input port of the falling edge detection circuit, and the other port is connected to the output port of the first current source and the anode of the diode and then serves as the output port of the falling edge detection circuit. The input port of the first current source is connected to the cathode of the diode and then serves as the second input port of the falling edge detection circuit.

[0015] In a possible implementation, the capacitive device is any one or a combination of a capacitor, the source-drain parasitic capacitance of an NMOS transistor with its gate-source shorted, and the source-drain parasitic capacitance of a PMOS transistor with its gate-source shorted.

[0016] In a possible implementation, the logic control circuit includes: a first AND gate, a second AND gate, a D flip-flop, and a falling edge pulse generation circuit;

[0017] The two input ports of the first AND gate respectively serve as the second input port and the third input port of the logic control circuit; the output port of the first AND gate is respectively connected to the input port of the falling edge pulse generation circuit and one input port of the second AND gate; the output port of the falling edge pulse generation circuit is connected to the reset port of the D flip-flop; the input port of the D flip-flop serves as the fourth input port of the logic control circuit; the clock input port of the D flip-flop serves as the first input port of the logic control circuit; the output port of the D flip-flop is connected to the other input port of the second AND gate; the power supply ports of the first AND gate, the second AND gate, the D flip-flop, and the falling edge pulse generation circuit serve as the power supply port of the logic control circuit; the ground ports of the first AND gate, the second AND gate, the D flip-flop, and the falling edge pulse generation circuit serve as the ground port of the logic control circuit; the output port of the second AND gate serves as the output port of the logic control circuit.

[0018] In a possible implementation, the falling edge pulse generation circuit includes: second to fifth inverters and a NAND gate;

[0019] The input port of the second inverter INV2 serves as the input port of the falling-edge pulse generation circuit. The output port of the second inverter is respectively connected to the input port of the third inverter and one input port of the NAND gate. The output port of the third inverter is connected to the input port of the fourth inverter, and the output port of the fourth inverter is connected to the input port of the fifth inverter. The output port of the fifth inverter is connected to the other input port of the NAND gate. The output port of the NAND gate serves as the output port of the falling-edge pulse generation circuit. The power supply ports of the second to fifth inverters and the NAND gate serve as the power supply ports of the falling-edge pulse generation circuit, and the ground ports of the second to fifth inverters and the NAND gate serve as the ground ports of the falling-edge pulse generation circuit.

[0020] In a possible implementation, the high-precision voltage detection circuit includes: a first high-voltage power MOSFET, a second high-voltage power MOSFET, a second current source, a third current source I2, a first inverter, and a low-level controlled switch.

[0021] The gates of the first high-voltage power MOSFET and the second high-voltage power MOSFET and the input port of the first inverter are connected and serve as the first input port of the high-precision voltage detection circuit. The drain of the first high-voltage power MOSFET serves as the second input port of the high-precision voltage detection circuit. The source of the first high-voltage power MOSFET, the source of the second high-voltage power MOSFET, and the inflow port of the third current source are connected. The outflow port of the third current source is connected to one end of the low-level controlled switch and serves as the ground port of the high-precision voltage detection circuit. The drain of the second high-voltage power MOSFET is connected to the other end of the low-level controlled switch and the outflow port of the second current source and serves as the output port of the high-precision voltage detection circuit. The inflow port of the second current source serves as the power supply port of the high-precision voltage detection circuit. The output port of the first inverter is connected to the control port of the low-level controlled switch.

[0022] In a possible implementation, the current ratio of the second current source to the third current source is 1:2, and the sizes and specifications of the first high-voltage power MOSFET and the second high-voltage power MOSFET are the same.

[0023] In a possible implementation, the comparator includes: a first to fifth PMOS transistor and a first to fourth NMOS transistor.

[0024] The sources of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor are connected together and then connected to the low-voltage power supply. The gates of the first PMOS transistor and the second PMOS transistor are respectively connected to a bias voltage. The drain of the first PMOS transistor, the source of the fourth PMOS transistor, and the source of the fifth PMOS transistor are connected together. The gate of the fourth PMOS transistor serves as the non-inverting input port of the comparator, and the gate of the fifth PMOS transistor serves as the inverting input port of the comparator. The drain of the fourth PMOS transistor is connected to the gate and drain of the first NMOS transistor and the gate of the second NMOS transistor. The sources of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are connected together and then connected to the low-voltage area ground. The drain of the fifth PMOS transistor, the drain of the second NMOS transistor, and the gate of the third NMOS transistor are connected together. The drain of the second PMOS transistor, the drain of the third NMOS transistor, the gate of the third PMOS transistor, and the gate of the fourth NMOS transistor are connected together. The gate of the third PMOS transistor and the drain of the fourth NMOS transistor are connected together and serve as the output port of the comparator.

[0025] On the other hand, a method for overcurrent detection of a high-voltage driving chip is provided, which is used in the overcurrent detection circuit as described above. The method includes:

[0026] When the falling-edge detection circuit detects the falling edge of the high-voltage area floating ground and the output of the low-voltage output port is a high-level signal, the logic control circuit outputs a high-level signal to the high-precision voltage detection circuit; when receiving the high-level signal, the high-precision voltage detection circuit turns on the overcurrent detection and sends the detected voltage to the comparator;

[0027] When the output of the low-voltage output port is a low-level signal, the logic control circuit outputs a low-level signal to the high-precision voltage detection circuit; when receiving the low-level signal, the high-precision voltage detection circuit turns off the overcurrent detection;

[0028] The comparator generates an overcurrent detection result based on the detected voltage and the reference voltage.

[0029] In a possible implementation manner, the detected voltage is equal to the high-voltage area floating ground.

[0030] The beneficial effects of the technical solution provided by the embodiments of the present application at least include:

[0031] (1) This application utilizes a falling-edge detection circuit to promptly detect the floating ground in the high-voltage region, and combines it with the output signal of the low-voltage output port, thereby enabling timely overcurrent detection, avoiding the problems of false judgment easily caused by too early detection time and missed judgment of narrow pulse widths easily caused by too late detection time, and improving the timeliness of overcurrent detection.

[0032] (2) This application compensates using the on-resistance of high-voltage power MOSFETs of the same size and in the same working environment, greatly improving the detection accuracy, and the compensation effect will not deteriorate with temperature changes, process drift, and power supply voltage changes.

[0033] (3) The structure of this application directly detects the voltage of the floating ground in the high-voltage region without additional circuits in the high-voltage region, which can reduce the static power consumption in the high-voltage region. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following-described drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0035] Figure 1 is a schematic structural diagram of a power drive circuit;

[0036] Figure 2 is an on-chip integrated overcurrent detection circuit provided in the prior art;

[0037] Figure 3 is Figure 2 the waveform diagrams of the prior art shown in

[0038] Figure 4 when the LIN outputs wide pulses and narrow pulses;

[0039] Figure 5 is Figure 4 a schematic structural diagram of the falling-edge detection circuit and the logic control circuit in

[0040] Figure 6 is Figure 5 a schematic structural diagram of the capacitive device in

[0041] Figure 7 is Figure 5 a schematic structural diagram of the falling-edge pulse generation circuit in

[0042] Figure 8 is a working waveform diagram of the overcurrent detection circuit provided by this application when the VS voltage lags at the falling edge and the LO rises at the rising edge;

[0043] Figure 9 The working waveform diagram of the overcurrent detection circuit provided by this application when the falling edge of the VS voltage precedes the rising edge of the LO.

[0044] Figure 10 For Figure 4 The structural schematic diagram of the high-precision voltage detection circuit in

[0045] Figure 11 The overcurrent detection circuit provided by this application and Figure 2 The schematic diagram of the variation of the V SENSE value of the overcurrent detection circuit shown with respect to the VS voltage.

[0046] Figure 12 For Figure 4 The structural schematic diagram of the comparator in

[0047] Figure 13 The schematic diagram of the overcurrent detection circuit provided by this application for detecting switch signals under wide pulse and narrow pulse conditions.

[0048] Figure 14 The flowchart of the overcurrent detection method for the high-voltage drive chip provided by this application. Detailed implementation manners

[0049] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the following will further describe the implementation manners of this application in detail with reference to the accompanying drawings.

[0050] Please refer to Figure 4 , which shows the structural schematic diagram of the overcurrent detection circuit of the high-voltage drive chip provided by an embodiment of this application. The overcurrent detection circuit may include: a falling edge detection circuit, a logic control circuit, a high-precision voltage detection circuit, and a comparator. The connection relationships among these four circuits will be described below.

[0051] The falling edge detection circuit includes two input ports and one output port. Among them, the first input port of the falling edge detection circuit is connected to the high-voltage side power supply VB or the high-voltage area floating ground VS, the second input port is connected to the low-voltage power supply VCC, and the output port (its output V DT ) is connected to the first input port of the logic control circuit.

[0052] The logic control circuit includes four input ports, two power supply ports, and one output port. Among them, the first input port of the logic control circuit (which receives V DT) is connected to the output port of the falling edge detection circuit; the second input port is connected to the low-voltage output port of the low-voltage region gate driving circuit (which receives LO), the third input port is connected to the output port of the power-on reset circuit (which receives POR), the fourth input port (which receives VCC) and the power supply port are respectively connected to the low-voltage power supply VCC, the ground port is connected to the low-voltage region ground GND, and the output port (which outputs V G ) is connected to the first input port of the high-precision voltage detection circuit.

[0053] The high-precision voltage detection circuit includes two input ports, two power supply ports and one output port. Among them, the first input port in the high-precision voltage detection circuit (which receives V G ) is connected to the output port of the logic control circuit; the second input port is connected to the high-voltage region floating ground VS, the power supply port is connected to the low-voltage power supply VCC, the ground port is connected to the low-voltage region ground GND, and the output port (which outputs V SENSE ) is connected to the non-inverting input port of the comparator.

[0054] The comparator includes two input ports and one output port. Among them, the non-inverting input port in the comparator (which receives V SENSE ) is connected to the output port of the high-precision voltage detection circuit; the inverting input port is connected to the reference voltage V ref is connected, and the output port is connected to the low-voltage region gate driving circuit.

[0055] In this embodiment, when the falling edge detection circuit detects the falling edge of the high-voltage region floating ground VS and the output of the low-voltage output port is a high-level signal (i.e., LO is a high-level signal), the logic control circuit is used to output a high-level signal (i.e., V G is a high-level signal) to the high-precision voltage detection circuit; when the output of the low-voltage output port is a low-level signal (i.e., LO is a low-level signal), the logic control circuit is used to output a low-level signal (i.e., V G is a low-level signal) to the high-precision voltage detection circuit; the high-precision voltage detection circuit is used to turn on overcurrent detection when receiving a high-level signal (i.e., V G is a high-level signal) and turn off overcurrent detection when receiving a low-level signal (i.e., V G is a low-level signal); the comparator is used to generate an overcurrent detection result according to the detected voltage V SENSE and the reference voltage V ref .

[0056] The circuit structures of the falling edge detection circuit, the logic control circuit, the high-precision voltage detection circuit and the comparator are described below respectively.

[0057] (1) The falling edge detection circuit includes: a capacitive device, a first current source I3 and a diode D3, asFigure 5 As shown. Among them, one port of the capacitive device serves as the first input port of the falling edge detection circuit, and the other port is connected to the output port of the first current source I3 and the anode of the diode D3 and then serves as the output port of the falling edge detection circuit. The input port of the first current source I3 is connected to the cathode of the diode D3 and then serves as the second input port of the falling edge detection circuit.

[0058] Among them, the capacitive device can be any one or a combination of a capacitor, the source-drain parasitic capacitance of an NMOS transistor with the gate-source shorted, and the source-drain parasitic capacitance of a PMOS transistor with the gate-source shorted. Please refer to Figure 6 , Figure 6 In which, (a) represents a capacitor, (b) represents the source-drain parasitic capacitance of an NMOS transistor with the gate-source shorted, and (c) represents the source-drain parasitic capacitance of a PMOS transistor with the gate-source shorted.

[0059] (2) The logic control circuit includes: a first AND gate AND1, a second AND gate AND2, a D flip-flop, and a falling edge pulse generation circuit. Among them, the two input ports of the first AND gate AND1 serve as the second input port and the third input port of the logic control circuit respectively; the output port of the first AND gate AND1 (its output V1) is connected to the input port of the falling edge pulse generation circuit and one input port of the second AND gate AND2 respectively; the output port of the falling edge pulse generation circuit (its output V R ) is connected to the reset port (Reset) of the D flip-flop; the input port (D) of the D flip-flop serves as the fourth input port of the logic control circuit; the clock input port (Clk) of the D flip-flop serves as the first input port of the logic control circuit; the output port (Q, its output V3) of the D flip-flop is connected to the other input port of the second AND gate AND2; the power supply ports of the first AND gate AND1, the second AND gate AND2, the D flip-flop, and the falling edge pulse generation circuit serve as the power supply port of the logic control circuit; the ground ports of the first AND gate AND1, the second AND gate AND2, the D flip-flop, and the falling edge pulse generation circuit serve as the ground port of the logic control circuit; the output port of the second AND gate AND2 (its output V G ) serves as the output port of the logic control circuit.

[0060] It should be noted that the power supply port of the logic control circuit is connected to the low-voltage power supply VCC, that is, the power supply ports of the first AND gate AND1, the second AND gate AND2, the D flip-flop, and the falling edge pulse generation circuit are connected to the low-voltage power supply VCC, Figure 5The power supply ports of the first AND gate AND1, the second AND gate AND2, the D flip-flop, and the falling-edge pulse generation circuit are not shown. The ground port of the logic control circuit is connected to the low-voltage area ground GND. That is, the ground ports of the first AND gate AND1, the second AND gate AND2, the D flip-flop, and the falling-edge pulse generation circuit are connected to the low-voltage area ground GND. Figure 5 The ground ports of the first AND gate AND1, the second AND gate AND2, the D flip-flop, and the falling-edge pulse generation circuit are not shown.

[0061] The falling-edge pulse generation circuit in this embodiment includes: the second to fifth inverters INV2-INV5 and the NAND gate NAND3, as Figure 7 shown. Among them, the input port of the second inverter INV2 serves as the input port of the falling-edge pulse generation circuit. The output port of the second inverter INV2 is respectively connected to the input port of the third inverter INV3 and one input port of the NAND gate NAND3. The output port of the third inverter INV3 is connected to the input port of the fourth inverter INV4. The output port of the fourth inverter INV4 is connected to the input port of the fifth inverter INV5. The output port of the fifth inverter INV5 is connected to the other input port of the NAND gate NAND3. The output port of the NAND gate NAND3 serves as the output port of the falling-edge pulse generation circuit. The power supply ports of the second to fifth inverters INV2-INV5 and the NAND gate NAND3 serve as the power supply ports of the falling-edge pulse generation circuit. The ground ports of the second to fifth inverters and the NAND gate NAND3 serve as the ground ports of the falling-edge pulse generation circuit.

[0062] It should be noted that the power supply interface of the falling-edge pulse generation circuit is connected to the low-voltage power supply VCC. That is, the power supply ports of the second to fifth inverters INV2-INV5 and the NAND gate NAND3 are connected to the low-voltage power supply VCC. Figure 7 The power supply ports of the second to fifth inverters INV2-INV5 and the NAND gate NAND3 are not shown. The ground interface of the falling-edge pulse generation circuit is connected to the low-voltage area ground GND. That is, the ground ports of the second to fifth inverters INV2-INV5 and the NAND gate NAND3 are connected to the low-voltage area ground GND. Figure 7 The ground ports of the second to fifth inverters INV2-INV5 and the NAND gate NAND3 are not shown.

[0063] The working principle of the logic control circuit will be described below.

[0064] Please refer to Figure 8 which shows the working waveform diagram of the overcurrent detection circuit when the falling edge of the VS voltage lags behind the rising edge of LO. When LO becomes high level, after a short period of time, the low-side power transistor M LFully turned on, the voltage of VS starts to drop. After the falling edge detection circuit detects this falling edge, it outputs a low-level pulse (V DT ), and this low-level pulse (V DT ) acts on the clock input port (Clk) of the D flip-flop, causing the level (VCC) of the input port (D) to be transmitted to the output port (Q), that is, V3 is at a high level. At this time, LO is still at a high level, and V G is pulled high to a high level, thereby triggering the start of overcurrent detection. When LO becomes low, the falling edge pulse generation circuit outputs a low-level pulse (V R ), and this low-level pulse (V R ) acts on the reset port (Reset) of the D flip-flop, causing the output V3 of the output port to be set to zero, which also sets V G to zero, thereby triggering the shutdown of overcurrent detection.

[0065] Please refer to Figure 9 , which shows the working waveform diagram of the overcurrent detection circuit when the falling edge of the VS voltage precedes the rising edge of LO. When the inductor current is positive in the direction of VO, the high-side power transistor M H turns off. Due to the freewheeling effect of M L , VS is instantaneously pulled to a negative voltage. After the falling edge detection circuit detects this falling edge, it outputs a low-level pulse (V DT ), and this low-level pulse (V DT ) acts on the clock input port (Clk) of the D flip-flop, causing the level (VCC) of the input port (D) to be transmitted to the output port (Q), that is, V3 is at a high level. When LO becomes high, V1 becomes high. After V1 and V3 are ANDed by the AND gate AND2, the result is high level, that is, the output V G of the AND gate AND2 is at a high level, thereby triggering overcurrent detection. When LO becomes low, the falling edge pulse generation circuit outputs a low-level pulse (V R ), and this low-level pulse (V R ) acts on the reset port (Reset) of the D flip-flop, causing the output V3 of the output port to be set to zero, which also sets V G to zero, thereby triggering the shutdown of overcurrent detection.

[0066] (3) The high-precision voltage detection circuit includes: the first high-voltage power MOSFET LM1, the second high-voltage power MOSFET LM2, the second current source I1, the third current source I2, the first inverter INV1, and the switch S1 controlled by a low level to turn on, as Figure 10As shown in the figure. Among them, the gate of the first high-voltage power MOSFET LM1 is connected to the gate of the second high-voltage power MOSFET LM2 and the input port of the first inverter INV1, and then serves as the first input port of the high-precision voltage detection circuit; the drain of the first high-voltage power MOSFET LM1 serves as the second input port of the high-precision voltage detection circuit; the source of the first high-voltage power MOSFET LM1, the source of the second high-voltage power MOSFET LM2 and the inflow port of the third current source I2 are connected (the signal at the node formed after connection is denoted as V1); the outflow port of the third current source I2 is connected to one end of the switch S1 controlled by low level to serve as the ground port of the high-precision voltage detection circuit; the drain of the second high-voltage power MOSFET LM2 is connected to the other end of the switch S1 controlled by low level and the outflow port of the second current source I1, and then serves as the output port of the high-precision voltage detection circuit; the inflow port of the second current source I1 serves as the power supply port of the high-precision voltage detection circuit; the output port of the first inverter INV1 is connected to the control port of the switch S1 controlled by low level.

[0067] In this embodiment, the current ratio of the second current source I1 and the third current source I2 is 1:2, and the sizes and specifications of the first high-voltage power MOSFET LM1 and the second high-voltage power MOSFET LM2 are the same.

[0068] Among them, the formula for the on-resistance of the MOS transistor is

[0069]

[0070] Among them, μ0 is the carrier mobility, C ox is the gate oxide capacitance, W and L are the width and length of the MOS transistor respectively, V GS is the gate-source voltage difference of the MOS transistor, V TH is the threshold voltage of the MOS transistor, and it can be obtained that

[0071] V SENSE = V1 + I1·R on2 (2)

[0072] Also

[0073] V1 = V S - (I2 - I1)·R on1 (3)

[0074] Among them, R on1 is the on-impedance of LM1, R on2 is the on-impedance of LM2. It can be seen from formula (1) that when the sizes and specifications of LM1 and LM2 are the same, the on-resistance of the MOS transistor is only related to its gate-source voltage difference. Figure 10The source electrodes of LM1 and LM2 are connected, and the gate electrodes are connected. Therefore, their on-resistances are the same, that is

[0075] R on1 = R on2 (4)

[0076] Since

[0077] I2 = 2 * I1 (5)

[0078] Substitute formulas (3) to (5) into formula (2) and simplify, we can get

[0079] V SENSE = VS (6)

[0080] Please refer to Figure 11 , which shows the schematic diagram of the change of the V SENSE value of the overcurrent detection circuit provided by this application and the overcurrent detection circuit in the prior art with respect to the VS voltage. It can be seen from Figure 11 that there is a large error between the detected voltage V SENSE value and the VS value in the prior art. When the VS voltage value is greater than 0.3V, the detected voltage V SENSE value of the overcurrent detection circuit provided by the application infinitely approaches the VS value and changes with the change of the VS voltage. This is because the sizes and specifications of LM1 and LM2 are the same. Therefore, the relationship between the detected voltage value V SENSE and the VS value of this application will not change with the changes of temperature and process drift.

[0081] (4) The comparator includes: the first to fifth PMOS transistors MP1 - MP5 and the first to fourth NMOS transistors MN1 - MN4, as Figure 12As shown in the figure. Among them, the sources of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are connected together and then connected to the low-voltage power supply VCC. The gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are respectively connected to the bias voltage Bias. The drain of the first PMOS transistor MP1, the source of the fourth PMOS transistor MP4, and the source of the fifth PMOS transistor MP5 are connected together. The gate of the fourth PMOS transistor MP4 serves as the non-inverting input port of the comparator, and the gate of the fifth PMOS transistor MP5 serves as the inverting input port of the comparator. The drain of the fourth PMOS transistor MP4 is connected to the gate and drain of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2. The sources of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are connected together and then connected to the ground in the low-voltage area. The drain of the fifth PMOS transistor MP5, the drain of the second NMOS transistor MN2, and the gate of the third NMOS transistor MN3 are connected together. The drain of the second PMOS transistor MP2, the drain of the third NMOS transistor MN3, the gate of the third PMOS transistor MP3, and the gate of the fourth NMOS transistor MN4 are connected together. The gate of the third PMOS transistor MP3 and the drain of the fourth NMOS transistor MN4 are connected together and serve as the output port of the comparator.

[0082] Please refer to Figure 13 , which shows a schematic diagram of the overcurrent detection circuit provided in the present application for detecting a switching signal under wide-pulse and narrow-pulse conditions. As can be seen from Figure 13 , compared with the prior art, the overcurrent detection circuit provided in the present application can output an overcurrent detection pulse signal in a timely manner for both wide pulses and narrow pulses, avoiding the problem of missed detection of narrow-pulse output caused by too long filtering time.

[0083] Please refer to Figure 14 , which shows a flowchart of an overcurrent detection method for a high-voltage driving chip provided in an embodiment of the present application. The overcurrent detection method may include:

[0084] Step 1401, when the falling-edge detection circuit detects the falling edge of the floating ground in the high-voltage area and the output of the low-voltage output port is a high-level signal, the logic control circuit outputs a high-level signal to the high-precision voltage detection circuit; when receiving the high-level signal, the high-precision voltage detection circuit starts overcurrent detection and sends the detected voltage to the comparator.

[0085] In this embodiment, the detected voltage V SENSE is equal to the floating ground VS in the high-voltage area.

[0086] Step 1402: When the output of the low-voltage output port is a low-level signal, the logic control circuit outputs a low-level signal to the high-precision voltage detection circuit; when receiving the low-level signal, the high-precision voltage detection circuit turns off the over-current detection.

[0087] Step 1403: The comparator generates an over-current detection result based on the detected voltage and the reference voltage.

[0088] Specifically, the working principle of the over-current detection circuit is as described above and will not be elaborated here.

[0089] In summary, for the over-current detection method provided in this embodiment, the falling-edge detection circuit can timely detect the floating ground in the high-voltage area, and combined with the output signal of the low-voltage output port, it can timely perform over-current detection, avoiding the problems of false judgment easily formed due to too early detection time and missed judgment of narrow pulse width easily caused by too late detection time, and improving the timeliness of over-current detection.

[0090] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware, or can be completed by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a magnetic disk or an optical disc, etc.

[0091] The above does not intend to limit the embodiments of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. An overcurrent detection circuit for a high-voltage drive chip, characterized in that, The overcurrent detection circuit includes: a falling edge detection circuit, a logic control circuit, a high-precision voltage detection circuit, and a comparator; The first input port of the falling edge detection circuit is connected to the high-voltage side power supply or the floating ground in the high-voltage area, the second input port is connected to the low-voltage power supply, and the output port is connected to the first input port of the logic control circuit; The second input port of the logic control circuit is connected to the low-voltage output port of the low-voltage area gate drive circuit, the third input port is connected to the output port of the power-on reset circuit, the fourth input port and the power supply port are respectively connected to the low-voltage power supply, the ground port is connected to the low-voltage area ground, and the output port is connected to the first input port of the high-precision voltage detection circuit; The second input port of the high-precision voltage detection circuit is connected to the floating ground in the high-voltage area, the power supply port is connected to the low-voltage power supply, the ground port is connected to the low-voltage area ground, and the output port is connected to the non-inverting input port of the comparator; The inverting input port of the comparator is connected to the reference voltage, and the output port is connected to the low-voltage area gate drive circuit; When the falling edge detection circuit detects the falling edge of the floating ground in the high-voltage area and the output of the low-voltage output port is a high-level signal, the logic control circuit is used to output a high-level signal to the high-precision voltage detection circuit; when the output of the low-voltage output port is a low-level signal, the logic control circuit is used to output a low-level signal to the high-precision voltage detection circuit; The high-precision voltage detection circuit is used to turn on overcurrent detection when receiving a high-level signal and turn off overcurrent detection when receiving a low-level signal; The comparator is used to generate an overcurrent detection result based on the detected voltage and the reference voltage.

2. The overcurrent detection circuit of the high-voltage drive chip according to claim 1, wherein The falling edge detection circuit includes: a capacitive device, a first current source, and a diode; One port of the capacitive device serves as the first input port of the falling edge detection circuit, and the other port is connected to the output port of the first current source and the anode of the diode and then serves as the output port of the falling edge detection circuit. The input port of the first current source is connected to the cathode of the diode and then serves as the second input port of the falling edge detection circuit.

3. The overcurrent detection circuit of the high-voltage driving chip according to claim 2, characterized in that, The capacitive device is any one or a combination of a capacitor, the source-drain parasitic capacitance of an NMOS transistor with its gate-source shorted, and the source-drain parasitic capacitance of a PMOS transistor with its gate-source shorted.

4. The overcurrent detection circuit of the high-voltage drive chip according to claim 1, characterized in that, The logic control circuit includes: a first AND gate, a second AND gate, a D flip-flop, and a falling edge pulse generation circuit; The two input ports of the first AND gate serve as the second input port and the third input port of the logic control circuit respectively; the output port of the first AND gate is connected to the input port of the falling-edge pulse generation circuit and one input port of the second AND gate respectively; the output port of the falling-edge pulse generation circuit is connected to the reset port of the D flip-flop; the input port of the D flip-flop serves as the fourth input port of the logic control circuit; the clock input port of the D flip-flop serves as the first input port of the logic control circuit; the output port of the D flip-flop is connected to the other input port of the second AND gate; the power supply ports of the first AND gate, the second AND gate, the D flip-flop and the falling-edge pulse generation circuit serve as the power supply port of the logic control circuit; the ground ports of the first AND gate, the second AND gate, the D flip-flop and the falling-edge pulse generation circuit serve as the ground port of the logic control circuit; the output port of the second AND gate serves as the output port of the logic control circuit.

5. The overcurrent detection circuit of the high-voltage drive chip according to claim 4, characterized in that, The falling-edge pulse generation circuit includes: the second to fifth inverters and a NAND gate; The input port of the second inverter INV2 serves as the input port of the falling-edge pulse generation circuit, and the output port of the second inverter is connected to the input port of the third inverter and one input port of the NAND gate respectively; the output port of the third inverter is connected to the input port of the fourth inverter, the output port of the fourth inverter is connected to the input port of the fifth inverter; the output port of the fifth inverter is connected to the other input port of the NAND gate; the output port of the NAND gate serves as the output port of the falling-edge pulse generation circuit; the power supply ports of the second to fifth inverters and the NAND gate serve as the power supply port of the falling-edge pulse generation circuit, and the ground ports of the second to fifth inverters and the NAND gate serve as the ground port of the falling-edge pulse generation circuit.

6. The overcurrent detection circuit of the high-voltage driving chip according to claim 1, wherein The high-precision voltage detection circuit includes: a first high-voltage power MOSFET, a second high-voltage power MOSFET, a second current source, a third current source I2, a first inverter and a switch controlled by a low-level signal to turn on; The gate of the first high-voltage power MOSFET is connected to the gate of the second high-voltage power MOSFET and the input port of the first inverter, and then serves as the first input port of the high-precision voltage detection circuit; the drain of the first high-voltage power MOSFET serves as the second input port of the high-precision voltage detection circuit; the source of the first high-voltage power MOSFET, the source of the second high-voltage power MOSFET and the inflow port of the third current source are connected; the outflow port of the third current source is connected to one end of the low-level controlled switch and then serves as the ground port of the high-precision voltage detection circuit; the drain of the second high-voltage power MOSFET is connected to the other end of the low-level controlled switch and the outflow port of the second current source, and then serves as the output port of the high-precision voltage detection circuit; the inflow port of the second current source serves as the power supply port of the high-precision voltage detection circuit; the output port of the first inverter is connected to the control port of the low-level controlled switch.

7. The overcurrent detection circuit of the high-voltage drive chip according to claim 6, characterized in that, The current ratio of the second current source to the third current source is 1:2, and the first high-voltage power MOSFET and the second high-voltage power MOSFET have the same size and specifications.

8. The overcurrent detection circuit of the high-voltage drive chip according to claim 1, characterized in that, The comparator includes: the first to fifth PMOS transistors and the first to fourth NMOS transistors; The sources of the first PMOS transistor, the second PMOS transistor and the third PMOS transistor are connected and then connected to the low-voltage power supply. The gates of the first PMOS transistor and the second PMOS transistor are respectively connected to the bias voltage. The drain of the first PMOS transistor, the source of the fourth PMOS transistor and the source of the fifth PMOS transistor are connected. The gate of the fourth PMOS transistor serves as the in-phase input port of the comparator. The gate of the fifth PMOS transistor serves as the anti-phase input port of the comparator. The drain of the fourth PMOS transistor is connected to the gate and drain of the first NMOS transistor and the gate of the second NMOS transistor. The sources of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are connected and then connected to the low-voltage area ground. The drain of the fifth PMOS transistor, the drain of the second NMOS transistor and the gate of the third NMOS transistor are connected. The drain of the second PMOS transistor, the drain of the third NMOS transistor, the gate of the third PMOS transistor and the gate of the fourth NMOS transistor are connected. The gate of the third PMOS transistor and the drain of the fourth NMOS transistor are connected and then serve as the output port of the comparator.

9. A method for overcurrent detection of a high-voltage drive chip, characterized in that, For use in the overcurrent detection circuit according to any one of claims 1 to 8, the method includes: When the falling edge detection circuit detects the falling edge of the high-voltage area floating ground and the output of the low-voltage output port is a high-level signal, the logic control circuit outputs a high-level signal to the high-precision voltage detection circuit; the high-precision voltage detection circuit starts overcurrent detection when receiving the high-level signal and sends the detected voltage to the comparator; When the output of the low-voltage output port is a low-level signal, the logic control circuit outputs a low-level signal to the high-precision voltage detection circuit; when receiving the low-level signal, the high-precision voltage detection circuit turns off the overcurrent detection. The comparator generates an overcurrent detection result based on the detected voltage and the reference voltage.

10. The overcurrent detection method of the high-voltage driving chip according to claim 9, characterized in that The detected voltage is equal to the floating ground in the high-voltage region.

Images