Accelerates configuration updates of storage devices

Abstract

The present application relates to accelerating configuration updates of a memory device. A configuration setting manager of a memory device receives a request to perform an adjustment operation on a set of configuration setting values ​​of the memory device, wherein each configuration setting value in the set of configuration setting values ​​is stored in a corresponding configuration register in a set of configuration registers; determines a configuration adjustment definition associated with one or more configuration setting values ​​in the set of configuration setting values; calculates a set of updated configuration setting values ​​by applying a multiplier value to the configuration adjustment definition, wherein the multiplier value is associated with a number of programming operations performed on the memory device; and stores the set of updated configuration setting values ​​in the corresponding configuration register.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to accelerating configuration updates of memory devices. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Typically, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] According to one aspect of the present application, a method is provided. The method includes: receiving, by a processing device, a request to perform an adjustment operation on a set of configuration setting values ​​of a memory device, wherein each configuration setting value in the set of configuration setting values ​​is stored in a corresponding configuration register in a set of configuration registers; determining a configuration adjustment definition associated with one or more configuration setting values ​​in the set of configuration setting values; calculating, by the processing device, a set of updated configuration setting values ​​by applying a multiplier value to the configuration adjustment definition, wherein the multiplier value is associated with a number of programming operations performed on the memory device; and storing the set of updated configuration setting values ​​in the corresponding configuration register.

[0004] According to another aspect of the present application, a method is provided. The method includes: monitoring, by a processing device, a number of programming operations performed on memory cells of a memory device; determining whether the number of programming operations performed on the memory cells of the memory device satisfies a threshold criterion associated with a set of configuration setting values ​​of the memory device; and in response to determining that the number of programming operations performed on the memory cells of the memory device satisfies the threshold criterion, sending a request to the memory device to cause the memory device to perform an adjustment operation on the set of configuration setting values ​​of the memory device.

[0005] According to another aspect of the present application, a system is provided, the system comprising: a memory device; and a processing device operably coupled to the memory device to perform operations, the operations comprising: receiving a request to perform an adjustment operation on a set of configuration setting values ​​of the memory device, wherein each configuration setting value in the set of configuration setting values ​​is stored in a corresponding configuration register in a set of configuration registers; determining a configuration adjustment definition associated with one or more configuration setting values ​​in the set of configuration setting values; calculating a set of updated configuration setting values ​​by applying a multiplier value to the configuration adjustment definition, wherein the multiplier value is associated with the number of programming operations performed on the memory device; and storing the set of updated configuration setting values ​​in the corresponding configuration register. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure. However, the accompanying drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is illustrated.

[0008] Figure 2 is a flow chart of an example method that facilitates accelerated configuration updates of a memory device according to some embodiments of the present disclosure.

[0009] Figure 3 Illustrated is a simplified block diagram of a memory device in communication with a memory subsystem controller of a memory subsystem to facilitate accelerated configuration updates of the memory device in accordance with some embodiments of the present disclosure.

[0010] Figure 4 is a flow chart of an example method for controlling accelerated configuration updates of a memory device according to some embodiments of the present disclosure.

[0011] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0012] Various aspects of the present disclosure relate to accelerating configuration updates of memory devices. The memory subsystem may be a memory device, a memory module, or a combination of a memory device and a memory module. Figure 1 Examples of storage devices and memory modules are described. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device that stores data. The host system may provide data to be stored at the memory subsystem and may request retrieval of data from the memory subsystem.

[0013] The memory subsystem may include a high-density non-volatile memory device where data needs to be retained when power is not supplied to the memory device. An example of a non-volatile memory device is a NAND memory device. Figure 1Other examples of nonvolatile memory devices are described. A nonvolatile memory device is a package of one or more dies. Each die may be composed of one or more planes. For certain types of nonvolatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more binary bits of information and have various logical states related to the number of bits stored. The logical state can be represented by a binary value (e.g., "0" and "1") or a combination of such values.

[0014] The memory subsystem controller may perform access operations on the memory device, such as read operations, program operations, erase operations, etc. The memory device may include configuration settings (also referred to as "fine tuning settings") that may control the operation and / or performance characteristics of the memory device. The fine tuning settings may include several parameters that may control the operation and performance of the memory device. The fine tuning setting configuration used by the memory device may control the operating characteristics of the memory device so that the memory device can perform at (or closer to) the desired operating characteristics rather than the previous operating characteristics of the memory device. The memory device may include registers, buffers, and / or memory to store fine tuning settings that define the fine tuning of data in the memory device.

[0015] The fine tuning settings may include parameters such as programming signal magnitude (e.g., voltage and / or current level), erasing signal magnitude (e.g., voltage and / or current level), sensing signal magnitude (e.g., voltage and / or level), programming signal length, erasing signal length, sensing signal length, number of bits per cell, number of programming signals in a programming operation, number of sensing signals in a sensing operation, allowable programming operation rate of the memory device, or other similar information. In some cases, the operating characteristics of the memory device may include the life of the memory device, data retention characteristics of data in the memory device, storage density of the memory device (e.g., number of bits stored), disturbance characteristics of data in the memory device, programming speed of the memory device, power consumption of the memory device, sensing speed of the memory device, operating temperature of the memory device, and / or programming operation rate of the memory device, etc.

[0016] For example, when reading memory cells of a selected access line of a block of memory cells, conventional systems provide different voltages to the unselected access lines of the block of memory cells based on their relative positions to the selected access line. A trim setting associated with a read operation may specify the voltages to be used for the unselected access lines and the selected access line.

[0017] In a conventional memory subsystem, over time, the use of a memory device causes changes in the threshold voltage level of a memory cell and / or the amount of charge stored therein, which in turn causes reliability and performance degradation as the memory device ages. To address this problem, a conventional memory subsystem may adjust the trimming settings over time to account for these changes in order to maintain the performance and reliability of the memory device. In such embodiments, a memory subsystem controller may modify the trimming value by reading the trimming value from the memory device, adjusting the value, and rewriting the trimming value back to the memory device. However, in many cases, this process itself may cause a negative impact on the operation of the memory device. In the case where a memory device is configured with a large number of trimming values, this conventional process may result in repeated read-modify-write iterations for each trimming value on the memory device. This may result in increased preparation time (TTR) during power-on, significant degradation of performance during the adjustment cycle and during the life of the device, and increased risk of errors due to interruptions to trimming updates. In addition, additional communications between the memory subsystem controller and the memory device may result in increased wear on the device, which may further shorten the operating life of the memory device.

[0018] Conventional memory subsystems attempt to mitigate these problems by limiting the adjustments made to the trim values. However, this may result in non-uniform trim adjustments of the memory devices in the memory subsystem and degradation of the performance and / or reliability of a particular memory device.

[0019] Aspects of the present disclosure address the above and other deficiencies by accelerating configuration updates to a memory device. In one embodiment, a configuration settings control component of a memory subsystem controller may monitor programming operations performed on memory cells of a memory device. When the number of programming operations meets a threshold criterion associated with a fine-tuning setting of the memory device, the configuration settings control component may determine that the fine-tuning setting will be adjusted. In response, the configuration settings control component may send a single request to update the fine-tuning setting of the device. The fine-tuning settings may be configured such that each setting is associated with an adjustment definition that can be used to update the setting. The request sent by the configuration settings control component may include a multiplier value calculated by the memory subsystem controller, which multiplier value may be applied to each adjustment definition to update the fine-tuning setting of the memory device.

[0020] Advantages of the present disclosure include, but are not limited to, simplification and acceleration of the configuration setting update process. Utilizing a single request to cause a memory device to perform multiple configuration setting updates significantly reduces the number of read-update-write operations performed by conventional systems. This, in turn, reduces wear on the memory device, which can significantly improve performance and reliability over time. Additionally, by reducing read-update-write operations, the number of adjustment operations performed on the memory device can be maintained at an optimal level, thereby eliminating the need to reduce or limit the number of adjustments performed or the number of settings adjusted. This, in turn, can provide the maximum benefit from fine-tuning adjustments without the typical performance and / or reliability costs experienced by conventional systems.

[0021] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0022] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0023] Computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation), an Internet of Things (IoT) enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked business device), or such a computing device that includes a memory and a processing device.

[0024] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0025] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses, for example, the memory subsystem 110 to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0026] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect (PCIe) interface, a universal serial bus (USB) interface, a fiber channel, a serial attached SCSI (SAS), a double data rate (DDR) memory bus, a small computer system interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM slot interface supporting double data rate (DDR)), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a physical host interface (e.g., a PCIe bus), the host system 120 may also utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0027] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0028] Some examples of non-volatile memory devices (e.g., memory device 130) include negative AND (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0029] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of a memory cell, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory, such as NAND, pages may be grouped to form blocks.

[0030] Although nonvolatile memory components such as a 3D cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0031] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuits with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0032] The memory subsystem controller 115 may include a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0033] In some embodiments, local memory 119 may include memory registers for storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 is shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem).

[0034] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations associated with the memory device 130, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBA), name space) and physical addresses (e.g., physical block addresses). The memory subsystem controller 115 may also include host interface circuitry that communicates with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0035] The memory subsystem 110 may also include additional circuits or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0036] In some embodiments, the memory device 130 includes a local media controller 135 that operates with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory subsystem 110 is a managed memory device that includes the original memory device 130 with control logic (e.g., the local controller 132) on the die and a controller (e.g., the memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0037] The memory subsystem 110 may include a configuration settings control component 113 that can be used to control accelerated updates of configuration settings of the memory device 130. In some embodiments, the memory subsystem controller 115 includes at least a portion of the configuration settings control component 113. In some embodiments, the configuration settings control component 113 is part of the host system 110, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the configuration settings control component 113 and is configured to perform the functions described herein.

[0038] In various embodiments, the configuration setting control component 113 can monitor the number of programming operations (e.g., program / erase cycles) performed on the memory cells of the memory devices 130, 140. The memory device 130 can be configured with one or more configuration settings (e.g., fine-tuning settings) that can be used to manage the operation and / or performance characteristics of the memory device 130. The configuration setting control component 113 can be configured to send a single request to the memory device 130 to cause the memory device 130 to update its configuration settings. In some embodiments, the configuration setting control component 113 can determine when to send the request based on the number of programming operations performed on the memory device 130. If the number of programming operations meets a threshold criteria associated with the fine-tuning settings, the configuration setting control component 113 can send the request to the memory device 130.

[0039] In some embodiments, the request may include additional information to be used by the memory device to complete the update of the configuration settings. In one example, the request may include a multiplier value calculated by the configuration settings control component 113 based on the number of programming operations performed. As described in further detail below, the memory device 130 may use the multiplier value to update its configuration settings. In another example, the request may include the number of programming operations performed, which the memory device 130 may use to update its configuration settings. Further details on the operation of the configuration settings control component 113 are provided below in reference to Figure 4 Give a description.

[0040] In one embodiment, local media controller 135 may include configuration settings manager 134 to facilitate accelerated updating of configuration settings on memory device 130. In various embodiments, configuration settings manager 134 may configure configuration settings of memory device 130 such that each setting is associated with a configuration adjustment definition that specifies how to update the configuration setting. As described in further detail below, a configuration adjustment definition may include a polynomial equation that includes a plurality of operands, at least one of which may be modified by a multiplier value indicated in a request received from configuration settings control component 113 to perform an adjustment operation.

[0041] Configuration settings manager 134 may, in response to receiving the request, apply the multiplier value to the configuration adjustment definition to calculate an updated set of configuration settings for memory device 130. The updated settings may then be stored in registers or memory space dedicated to those settings. Thus, a single request received from configuration settings control component 113 may cause configuration settings manager 134 to update all (or a set of) fine-tuning settings for memory device 130. Further details regarding the operation of configuration settings manager 134 are provided below with reference to Figure 2 Give a description.

[0042] Figure 2 2 is a flow chart of an example method 200 for facilitating accelerated configuration updates of a memory device according to some embodiments of the present disclosure. The method 200 may be performed by a processing logic that may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by Figure 1 The configuration settings manager 134 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the processes can be modified. Therefore, the embodiments shown should be understood as examples only, and the processes shown can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0043] At operation 210, processing logic receives a request to a memory device (eg, Figure 1 130 in the memory device 130). As described above, the configuration setting values ​​can be implemented as fine-tuning values ​​stored in fine-tuning registers of the memory device. In various embodiments, the configuration settings can be used to customize the access operation of the memory device. Also as described above, the firmware or control component of the memory subsystem controller (e.g., Figure 1 A configuration setting control component 113 of a memory subsystem controller 115 in the memory device may control adjustments to configuration settings during the life of a memory device based on a determined range of programming operations (e.g., program / erase cycles) performed on the memory device. These adjustments may be performed to maintain the performance and reliability of the memory device as the device ages.

[0044] In various embodiments, a request may be received from a firmware component of a memory subsystem controller associated with a memory device. As described above, the memory subsystem controller may monitor the programming erase cycles performed on the memory device to determine when the configuration setting values ​​should be adjusted. In some embodiments, the request may specify which configuration settings (e.g., which fine-tuning settings) are adjusted in response to the request. For example, the request may specify that all configuration setting values ​​(e.g., all fine-tuning settings) are adjusted in response to receiving the request. Alternatively, the request may specify a subset of configuration setting values ​​to be adjusted. In the latter case, the configuration setting values ​​may be configured in groups, where each group is associated with a unique identifier. The configuration setting control component of the memory subsystem may include a unique identifier in the request to indicate which group of configuration settings are to be adjusted. In response to receiving the request, the processing logic may determine which configuration setting values ​​are to be adjusted based on the format of the request.

[0045] At operation 220, processing logic determines a configuration adjustment definition associated with one or more configuration setting values ​​in the set of configuration setting values. In some embodiments, the configuration adjustment definition may specify parameters for performing an adjustment operation on the configuration setting value specified in the request. In an exemplary example, the configuration adjustment definition may be configured as a polynomial equation containing multiple operands for calculating a final configuration setting value. For example, one type of configuration adjustment definition may contain one operand representing a default setting and a second operand representing an incremental change value associated with an expected slope of change of the configuration setting relative to a number of programming operations performed over time.

[0046] In some embodiments, one of the operands may be modified by a multiplier value associated with the number of programming operations performed at a particular point in time. In this case, an exemplary adjustment definition may be expressed as a product of an incremental value and a multiplier, which is then added to a default value. In other words, an equation such as VALUE=DEFAULT VALUE+(INCREMENTAL VALUE*MULTIPLIERVALUE). Although one particular definition has been described for ease of illustration, in other embodiments, other configuration adjustment equation definitions may be specified that include more or fewer operands associated with the execution and adjustment of that particular configuration setting. In various embodiments, a single multiplier may be used to direct the adjustment of multiple (or all) adjustment definitions for a memory device, as described below with respect to operation 230.

[0047] In various embodiments, the operands of the adjustment definition may be specified as constant values ​​within the definition. Alternatively, the operands may be associated with separately stored configuration setting values ​​(e.g., other fine-tuning setting values) that may be modified by processing logic based on observed behavior of the memory device. For example, to continue the above example, the value of the INCREMENTAL VALUE operand may be stored in a separate fine-tuning register, and the value may be modified over time based on observed device behavior. If the processing logic determines that the incremental change of a particular configuration setting does not meet the expected performance of the driver, the processing logic may modify the fine-tuning setting of the operand to account for any observed deviations. For example, if the definition equation is associated with a configuration setting for a read operation, the equation may be directed to a voltage level value associated with the performance of the read operation. Over time, if the voltage level of the observed device memory cell drops or drifts at an unexpected rate, the processing logic may modify the value stored in the fine-tuning setting of the INCREMENTAL VALUE operand as an adjustment.

[0048] In various embodiments, each configuration setting value may be associated with a specific configuration adjustment definition that is configured to adjust that specific setting. In other words, each fine-tuning setting may have a corresponding adjustment definition that may be used to direct the adjustment operation of that specific fine-tuning setting. In other embodiments, a group of configuration setting values ​​may be associated with a single adjustment definition. In this case, the same adjustment definition may be used to adjust multiple configuration settings (e.g., multiple fine-tuning settings).

[0049] At operation 230, processing logic calculates a set of updated configuration setting values ​​by applying the multiplier value to the configuration adjustment definition. As described above, the configuration adjustment definition may include an operand modified by the multiplier value. In various embodiments, the multiplier value may be associated with the number of programming operations performed on the memory device (e.g., the number of programming erase cycles). Depending on the total number of programming operations at a particular point in time, the multiplier value may be set to different values. In one example, as the number of programming operations performed increases, the multiplier value may be increased to appropriately adjust the configuration setting values. For example, after performing 750 programming operations, the multiplier value may be set to 2. Following the above definition example, this will result in an increase of 2 times in the incremental value. Subsequently, after performing 1200 programming operations, the multiplier value may be set to 5. In other examples, other combinations of programming operations and multiplier values ​​may be used.

[0050] In some embodiments, the multiplier value may be included in the request received at operation 210. As described above, the configuration setting control component of the memory subsystem controller can monitor the number of programming operations performed and determine when to send a request to perform an adjustment. When making this determination, the configuration setting control component can also determine the multiplier value to send in the request. In this case, the processing logic can apply the multiplier value in the request to the adjustment definition equation to calculate an updated configuration setting value (or a set of updated configuration setting values). It is worth noting that a single request can drive the adjustment of multiple configuration setting values ​​using the same multiplier value.

[0051] In other embodiments, the processing logic may calculate the multiplier in response to receiving the request. In this case, the request received at operation 210 may include information indicating the number of programming operations performed for the memory device. For example, the request may include the number of programming operations. In this case, the processing logic may access a predefined mapping that maps a number of programming operations to corresponding multiplier values. Alternatively, the request may include a value indicating a range of programming operations performed (e.g., "1" for 500 or less, "2" for 501 to 750, "3" for 751 to 1000, etc.). In this case, the processing logic may determine whether the number of programming operations in the request has met a threshold indicating that an adjustment should be performed on the configuration setting value. If the threshold has been met, the processing logic may calculate a multiplier value for the applicable configuration adjustment definition based on the information received in the request. As described above, once a single multiplier value is calculated, it can be used to guide the adjustment of multiple configuration setting values.

[0052] At operation 240, processing logic stores the set of updated configuration setting values ​​in corresponding registers. As described above, each configuration setting value (e.g., each trim value) may be stored in a dedicated register for that setting value (e.g., a dedicated trim register). Thus, the adjustment operation may update the value stored in each register using the adjustment definition equation associated with each configuration setting value.

[0053] Figure 3 The present disclosure illustrates some embodiments of the present disclosure in accordance with a memory subsystem (eg, Figure 1 10) communicates with a memory subsystem controller 115 of a memory subsystem 110 to facilitate accelerating configuration updates of a memory device 130 (e.g., Figure 1 130). A memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device that may include a configuration settings control component 113 that monitors access operations performed on the memory device 130 and determines when to send a request to the memory device 130 to adjust configuration settings stored on the memory device 130.

[0054] like Figure 3 As shown in , a local media controller 135 within the memory device 130 controls access to memory cells of a memory device (not depicted) in response to commands received from the memory subsystem controller 115. The local media controller 135 is configured to perform access operations (e.g., read operations, program operations, erase operations, etc.) on the memory cells of the memory device 130 and to perform configuration adjustment operations on the memory device 130. As shown, the memory device 130 may be configured with configuration settings (e.g., fine-tuning settings) 320-1 to 320-N, where N is a positive integer. In various embodiments, as described above with reference to Figures 1 to 2 As described above, configuration settings 320 - 1 through 320 -N may be used to customize access operations of memory cells of memory device 130 .

[0055] As also described above, memory device 130 may be configured with multiple configuration adjustment definitions 310 that may be used to perform adjustment operations on configuration settings 320. In some embodiments, each configuration setting 320 may be associated with a corresponding configuration adjustment definition 310. In this case, configuration adjustment definition 310 may be used to update a single configuration setting 320. For example, Figure 3As shown, configuration adjustment definition 310-1 may be used to update configuration setting 320-1, configuration adjustment definition 310-2 may be used to update configuration setting 320-2, configuration adjustment definition 310-3 may be used to update configuration setting 320-3, and so on. In some embodiments, a single configuration setting 310 may be used to update multiple configuration settings 320. For example, as shown, configuration adjustment definition 310-4 may be used to update configuration settings 320-4 and 320-5. Although for ease of illustration, in Figure 3 A particular mapping of configuration adjustment definitions 310 to configuration settings 320 is depicted in FIG. 3 , but in other implementations, memory device 130 may be configured with other mappings.

[0056] As shown, the configuration setting control component 113 of the memory subsystem controller 115 can monitor the access operations performed on the memory device 130. In various embodiments, as described above, the configuration setting control component 113 can monitor the programming operations 301 performed on the memory device 130 until the number of operations meets the threshold criteria associated with the configuration setting value (e.g., fine-tuning setting). In one embodiment, the threshold criteria are met, wherein the number of operations performed reaches or exceeds the threshold. Therefore, when the number of operations performed is below the threshold, the threshold criteria are still not met. When the threshold criteria are met, the configuration setting control component 113 can send a request 302 to the configuration setting manager 134 to adjust the configuration settings 320 of the memory device 130. It is worth noting that a single request 302 can cause the configuration setting manager 134 to update multiple configuration settings 320 using the information contained in the request.

[0057] In various embodiments, as described above, configuration setting control component 113 may include additional information in request 320 that may be used by configuration setting manager 134 to apply to configuration adjustment definition 310 to adjust configuration setting 320. In some embodiments, request 302 may include a multiplier value (e.g., multiplier 305) in the request. In this case, configuration setting manager 134 may apply the multiplier directly to configuration adjustment definition 310 to update configuration setting 320. In other embodiments, request 302 may include the number of programming operations 301 performed, thereby causing configuration setting manager 134 to calculate multiplier 305. Figure 4 The configuration settings control component 113 is described in further detail.

[0058] As shown, configuration settings manager 134 receives request 302. Configuration settings manager 134 then identifies the configuration settings to be updated and determines configuration adjustment definitions 310 associated with those settings. Figure 3As shown, request 302 causes configuration setting manager 134 to adjust all configuration settings 320 to be updated. In other embodiments (not shown), request 302 may specify a subset of configuration settings 320 to be updated. As shown, configuration setting manager 134 applies multiplier 305 to each configuration adjustment definition 310 (operation 330). As described above, configuration adjustment definition 310 may be a polynomial equation containing multiple operations, where at least one of the operands is modified by a multiplier value. Operation 310 depicts applying the multiplier value to the applicable configuration adjustment definition equation 310.

[0059] The configuration settings manager 134 then calculates a set of updated configuration settings 320 by applying the multipliers 305 to the applicable adjustment definitions 310. As shown, the multiplier is applied to definition 310-1 to update configuration setting 320-1 (341), the multiplier is applied to definition 310-2 to update configuration setting 320-2 (342), the multiplier is applied to definition 310-3 to update configuration setting 320-3 (343), the multiplier is applied to definition 310-4 to update configuration settings 320-4 and 320-5 (344), and the multiplier is applied to definition 310-N to update configuration setting 320-N (345). Each updated configuration setting is then stored in the register for that setting value.

[0060] In various embodiments, configuration settings control component 113 and configuration settings manager 134 may repeat the above process as additional programming operations are performed on memory device 130 , resulting in additional adjustment operations being performed on configuration settings 320 .

[0061] Figure 4 4 is a flow chart of an example method 400 for controlling accelerated configuration updates of a memory device according to some embodiments of the present disclosure. The method 400 may be performed by a processing logic that may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The configuration settings control component 113 is executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the process can be modified. Therefore, the embodiments shown should be understood as examples only, and the processes shown can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0062] At operation 410, processing logic monitors a number of programming operations performed on memory cells of a memory device.

[0063] At operation 420, processing logic determines whether the number of programming operations performed on the memory cells of the memory device meets the threshold criteria associated with the fine-tuning setting (e.g., reaches or exceeds the threshold). In various embodiments, the threshold may be configured to determine when the adjustment of the configuration setting value (e.g., the fine-tuning setting value) of the memory device should be adjusted. In one example, the threshold may be configured so that the threshold is met after a specific number of programming operations are performed. In this case, a counter may maintain the number of operations performed, and once the threshold has been met, the counter may be reset to zero. In another example, the threshold may be configured to indicate a specific number of total programming operations performed. In these cases, the threshold may be met when the total number of operations performed reaches 500, 750, 1000, 1250, etc. In other embodiments, other monitoring threshold schemes may be used.

[0064] At operation 420 , if processing logic determines that the threshold criteria have not been met, processing returns to operation 410 to continue monitoring the number of programming operations performed. However, if processing logic determines that the threshold criteria have been met, processing proceeds to operation 430 .

[0065] At operation 430, in response to determining that the number of programming operations performed on the memory cells of the memory device satisfies the threshold criteria, the processing logic sends a request to the memory device to cause the memory device to perform an adjustment operation on a set of configuration setting values ​​(e.g., a set of trim setting values) of the memory device. Notably, a single request causes the memory device to perform an adjustment operation on multiple configuration setting values. As described above, the request may include information directing the memory device to apply a multiplier value to one or more configuration adjustment definition equations to perform an adjustment operation on the configuration setting values. Additionally, the request may include information specifying which configuration setting values ​​are to be adjusted by the adjustment operation.

[0066] As described above, in some embodiments, the processing logic may include in the request the number of programming operations performed on the memory device based on the monitoring performed at operation 410. In this case, the memory device may determine the applicable multiplier value to be used to adjust the operation after receiving the request. Alternatively, the request may include a value indicating the range of programming operations performed (e.g., "1" represents 500 or less, "2" represents 501 to 750, "3" represents 751 to 1000, etc.). In these cases, the memory device may determine the applicable multiplier based on the value included in the request. In other embodiments, the request may include the multiplier value itself. In this case, the processing logic may determine the multiplier value based on the number of programming operations. As described above, the processing logic may access a predefined mapping that maps several programming operations to corresponding multiplier values. In these cases, the mapping may be configured based on characteristics associated with the memory device, the configuration of the memory cells, the expected use of the memory device, or other similar information. In other embodiments, the processing logic may apply a mathematical function to the number of programming operations to calculate the multiplier value.

[0067] In some embodiments, the request may specify that the adjustment operation is to be performed on all configuration setting values ​​(e.g., all fine-tuning setting values) of the memory device. Alternatively, the request may specify that the adjustment operation is to be performed on a subset of the configuration setting values ​​of the memory device. In the latter case, the configuration setting values ​​can be configured in groups, where each group is associated with a unique identifier. The processing logic can determine which group of configuration settings to adjust and include an identifier of the group in the request to perform the adjustment operation. In various embodiments, the processing logic can monitor programming cycles and utilize different thresholds for different configuration setting groups. In this case, the processing logic can group configuration setting groups (e.g., different fine-tuning setting groups) based on functionality and trigger adjustment operations on the groups differently based on different programming cycle thresholds.

[0068] Figure 5 An example machine of a computer system 500 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 500 may correspond to a computer system that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, execute the operating system to execute the corresponding Figure 1 Configuration settings manager 134 operation) of the host system (e.g., Figure 1In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client user machine in a server-client user network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0069] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Further, while a single machine is illustrated, the term "machine" shall also be construed to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0070] The example computer system 500 includes a processing device 502 that communicates with each other via a bus 530, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518.

[0071] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 502 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 to communicate via a network 520.

[0072] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. During execution of the instructions 526 by the computer system 500, the instructions may also reside completely or at least partially within the main memory 504 and / or within the processing device 502, which also constitute machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0073] In one embodiment, instructions 526 include implementing instructions corresponding to a configuration settings manager (e.g., Figure 1 The machine-readable storage medium 524 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be understood to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be understood to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0074] Some portions of the foregoing detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the substance of their work to others skilled in the art. Algorithms are generally considered herein to be self-consistent sequences of operations that result in a desired result. Operations are those operations that require physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Mainly for general reasons, it sometimes proves to be convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0075] It should be remembered, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve the actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0076] The present disclosure also relates to an apparatus for performing the operations described herein. Such an apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including a floppy disk, an optical disk, a CD-ROM, and a magneto-optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic card or an optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0077] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform this method. The structures of various these systems will be set forth in the following description. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0078] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0079] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader scope and spirit of the embodiments of the present disclosure as set forth in the appended claims. Therefore, this specification and the accompanying drawings should be understood in an illustrative rather than a restrictive sense.

Claims

1. A method for accelerating configuration update of a memory device, comprising: receiving, by a processing device, a request to perform an adjustment operation on a set of configuration settings of a memory device, wherein each configuration setting of the set of configuration settings is stored in a corresponding configuration register of a set of configuration registers; determining a configuration adjustment definition associated with one or more configuration setting values ​​in the set of configuration setting values; calculating, by the processing device, a set of updated configuration setting values ​​by applying a multiplier value to the configuration adjustment definition, wherein the multiplier value is associated with a number of programming operations performed on the memory device; as well as The updated set of configuration setting values ​​are stored in the corresponding configuration register. The method of claim 1 , wherein the request includes an indication of the multiplier value.

3. The method of claim 1 , wherein the request comprises a number of the programming operations to be performed on the memory device, the method further comprising: determining whether the number of programming operations satisfies a threshold criterion associated with the set of configuration setting values; as well as In response to determining that the number of programming operations satisfies the threshold criterion, the multiplier value is calculated based on the number of programming operations.

4. The method of claim 1 , wherein determining the configuration adjustment definition associated with one or more configuration setting values ​​in the set of configuration setting values ​​further comprises: determining a set of configuration adjustment definitions, wherein each configuration adjustment definition is associated with a corresponding configuration setting value in the set of configuration setting values; as well as The set of updated configuration setting values ​​is calculated by applying the multiplier value to each configuration adjustment definition. 5 . The method of claim 1 , wherein the request comprises an identifier associated with the set of configuration setting values, and wherein the set of configuration values ​​comprises a subset of a total number of configuration setting values ​​of the memory device.

6. The method according to claim 5, further comprising: The set of configuration setting values ​​is determined based on the received identifier. The method of claim 1 , wherein the set of configuration values ​​comprises a total number of configuration setting values ​​for the memory device.

8. The method of claim 1 , wherein the configuration adjustment definition is a polynomial equation comprising a plurality of operands, wherein a first operand of the plurality of operands comprises a default configuration setting value, wherein a second operand of the plurality of operands comprises an incremental change value associated with an expected slope of change for the configuration setting, and wherein the incremental change value is modified by the multiplier value.

9. A method for accelerating configuration update of a memory device, comprising: monitoring, by a processing device, a number of programming operations performed on memory cells of a memory device; determining whether a number of the programming operations performed on the memory cells of the memory device satisfies a threshold criterion associated with a set of configuration setting values ​​for the memory device; as well as In response to determining that the number of programming operations performed on the memory cells of the memory device satisfies the threshold criteria, sending a request to the memory device to cause the memory device to perform an adjustment operation on the set of configuration setting values ​​for the memory device, wherein the request includes a value indicating a corresponding range of the number of programming operations performed on the memory cells of the memory device, wherein the corresponding range represents a total number of programming operations between two range thresholds in a set of range thresholds.

10. The method according to claim 9, further comprising: determining a multiplier value based on the range of the number of programming operations, wherein the multiplier value indicates an adjustment factor of the memory device to apply to an adjustment definition associated with the set of configuration setting values; as well as An indication of the multiplier value is sent to the memory device in the request.

11. The method of claim 9, wherein the request specifies that a memory device is to perform the adjustment operation on all configuration setting values ​​of the memory device.

12. The method of claim 9, wherein the request includes an identifier associated with the set of configuration setting values, and wherein the set of configuration values ​​includes a subset of a total number of configuration setting values ​​of the memory device.

13. A computing system comprising: Memory device; as well as a processing device operatively coupled to the memory device to perform operations comprising: receiving a request to perform an adjustment operation on a set of configuration settings of a memory device, wherein each configuration setting in the set of configuration settings is stored in a corresponding configuration register in a set of configuration registers; determining a configuration adjustment definition associated with one or more configuration setting values ​​in the set of configuration setting values; calculating an updated set of configuration setting values ​​by applying a multiplier value to the configuration adjustment definition, wherein the multiplier value is associated with a number of programming operations performed on the memory device; and The updated set of configuration setting values ​​are stored in the corresponding configuration register.

14. The computing system of claim 13, wherein the request includes an indication of the multiplier value.

15. The computing system of claim 13, wherein the request includes a number of the programming operations to be performed on the memory device, and wherein the processing device is to perform further operations, the further operations comprising: determining whether the number of programming operations satisfies a threshold; as well as In response to determining that the number of program operations satisfies the threshold, the multiplier value is calculated according to the number of program operations.

16. The computing system of claim 13, wherein to determine the configuration adjustment definition associated with one or more configuration setting values ​​in the set of configuration setting values, the processing device is to perform further operations, the further operations comprising: determining a set of configuration adjustment definitions, wherein each configuration adjustment definition is associated with a corresponding configuration setting value in the set of configuration setting values; as well as The set of updated configuration setting values ​​is calculated by applying the multiplier value to each configuration adjustment definition.

17. The computing system of claim 13, wherein the request includes an identifier associated with the set of configuration setting values, and wherein the set of configuration values ​​includes a subset of a total number of configuration setting values ​​of the memory device.

18. The computing system of claim 17, wherein the processing device is to perform further operations, the further operations comprising: The set of configuration setting values ​​is determined based on the received identifier.

19. The computing system of claim 13, wherein the configuration adjustment definition is a polynomial equation comprising a plurality of operands, wherein a first operand of the plurality of operands comprises a default configuration setting value, wherein a second operand of the plurality of operands comprises an incremental change value associated with an expected slope of change of the configuration setting, and wherein the incremental change value is modified by the multiplier value.

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