EEPROM data writing processing method for non-preemptive real-time operating systems

Abstract

This invention discloses a method for writing EEPROM data in a non-preemptive real-time operating system. It enables EEPROM write operations without interrupting the operating system's timing. A state machine is introduced into the implementation, dividing the operation steps into five different states for easy statistical analysis and differentiation. A mutex lock is also introduced during the write process to prevent the EEPROM from accepting other write requests while it is being written, thus preventing data corruption and improving system security. This invention provides an EEPROM data writing method adapted to a non-preemptive real-time operating system, ensuring the continuity of the operating system's timing during EEPROM data writing and effectively avoiding unpredictable fatal failures caused by operating system task timeouts. It has promising application prospects.

Description

Technical Field

[0001] This invention relates to the field of electronic product data storage technology, specifically to an EEPROM data writing processing method for a non-preemptive real-time operating system. Background Technology

[0002] In the field of non-volatile memory technology, EEPROM (Electrically Erasable Programmable Read-Only Memory) can be read and written in bytes, which is more flexible than the sector-based read and write method of FLASH (Flash EEPROM Memory). However, due to its small capacity, EEPROM is usually used to store some important parameters. Moreover, EEPROM data writing takes a long time. In short-cycle operating systems (software systems commonly used in electronic products), if important process parameters need to be saved, traditional EEPROM writing methods require waiting for the EEPROM to complete writing before subsequent tasks can be executed. This inevitably disrupts the operating system's timing, causing tasks to fail to execute in a timely manner and leading to unpredictable failures in the operating system.

[0003] Therefore, in a short-cycle operating system, existing solutions cannot modify and save parameters to EEPROM during electronic product operation without affecting the normal operation of the operating system. Therefore, solving this problem is a current priority. Summary of the Invention

[0004] The purpose of this invention is to overcome the problem that existing small-cycle operating systems cannot modify and save parameters to EEPROM during the operation of electronic products without affecting the normal operation of the operating system. The non-preemptive real-time operating system EEPROM data writing method of this invention can realize EEPROM writing operations without interrupting the operating system timing, enhancing the robustness of the operating system, improving the competitiveness of electronic products to a certain extent, and showing good application prospects.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A method for writing EEPROM data in a non-preemptive real-time operating system, wherein the EEPROM data writing time exceeds the cycle time of the non-preemptive real-time operating system, specifically includes the following steps:

[0007] Step (A): Read the WIP flag bit of the EEPROM status register. If WIP=0, jump to step (B); otherwise, maintain step (A).

[0008] Step (B): Send the WREN command to the EEPROM to activate the data writing function;

[0009] Step (C): Read the WEL flag bit of the EEPROM status register. If the WEL flag bit is read as 1 within the set time, the EEPROM write function is successfully activated and the process jumps to step (D); otherwise, the EEPROM data write function activation timeout occurs, the process jumps to step (A), and a fault is reported.

[0010] Step (D): Write data to the EEPROM, first pull the chip select signal low. Then, send the WRITE command, address, and data in sequence, and finally pull the chip select signal high. And jump to step (E);

[0011] Step (E): Read the WIP flag bit of the EEPROM status register. If the WIP changes from 1 to 0 within the set time, jump to step (F); otherwise, consider the data write timeout to have occurred, jump to step (A), and report the fault.

[0012] Step (F): Data verification. Read the EEPROM. If the read content matches the written content, the verification is successful, and proceed to step (A); otherwise, the verification is deemed to have failed and a fault is reported.

[0013] Preferably, the time taken for each step (A) to step (F) to be executed sequentially is the EEPROM data writing time, the EEPROM data writing time is 3.2ms, and the cycle period of the non-preemptive real-time operating system is 2ms.

[0014] Preferably, steps (A) to (F) are introduced into the state machine, specifically: in the Ready state, steps (A) and (B) are executed; in the EnableWrite state, step (C) is executed; in the Write state, step (D) is executed; in the Writing state, step (E) is executed; and in the Verify state, step (F) is executed.

[0015] Preferably, when a state machine is introduced in steps (A)-(F), the transition conditions of the state machine are as follows: if the Ready state is completed without failure, the transition is to the EnableWrite state; if the EnableWrite state is completed without failure, the transition is to the Write state; if a failure occurs, the transition is to the Ready state; if the Write state is completed, the transition is to the Writing state; if the Writing state is completed without timeout failure, the transition is to the Verify state; otherwise, the transition is to the Ready state; if the Verify state is completed, the transition is to the Ready state.

[0016] Preferably, the Writing state is the longest-running step, taking 3.16ms. The relationship between the state machine state and the cycle of the non-preemptive real-time operating system is established as follows: If the EEPROM is in an idle state and an EEPROM data write request is received, the current cycle of the non-preemptive real-time operating system is t. The four states Ready, EnableWrite, Write, and Writing are executed sequentially. In cycle t+2, Verify is executed.

[0017] Preferably, during step (A) of the EEPROM data writing process, a mutex lock is introduced to prevent the EEPROM from receiving other write requests while it is being written, which could cause data corruption. This includes the following process:

[0018] (A1) During the MCU power-on initialization process, create two static variables, WritingFlag and AddressLatch, to record the current write operation status of the EEPROM and the write address of the EEPROM, respectively. When WritingFlag is 1, it indicates that the EEPROM is being written to, and when WritingFlag is 0, it indicates that the EEPROM is not being written to. AddressLatch records the current write address of the EEPROM. The initial values ​​of both WritingFlag and AddressLatch are 0.

[0019] (A2) When there is an EEPROM data write request, first check the values ​​of WritingFlag and AddressLatch. If WritingFlag is equal to 0, it indicates that there is no write operation in EEPROM. At this time, set WritingFlag to 1, and at the same time, AddressLatch saves the current write address of EEPROM.

[0020] (A3) Whenever the non-preemptive real-time operating system executes steps (A)-(F) in a loop, it needs to check WritingFlag and AddressLatch. When WritingFlag is equal to 1, the EEPROM writing process is allowed only if the EEPROM write address matches AddressLatch; otherwise, it is refused.

[0021] (A4) When the EEPROM data writing process is completed or a failure occurs during the execution of steps (A)-(F), the WritingFlag and AddressLatch are reinitialized to 0 in order to receive new EEPROM data writing requests.

[0022] Preferably, the time set for both steps (C) and (E) is 2 seconds.

[0023] The beneficial effects of this invention are as follows: The non-preemptive real-time operating system EEPROM data writing method of this invention can realize EEPROM writing operations without interrupting the operating system timing. A state machine is introduced into the implementation process, dividing the operation steps into five different states for easy statistics and differentiation. A mutex lock is also introduced during the writing process to prevent the EEPROM from accepting other write requests while it is being written, thus preventing data corruption and improving system security. This invention achieves EEPROM data writing without interrupting the real-time operating system timing, ensuring the continuity and determinism of the operating system timing, effectively avoiding unpredictable fatal failures caused by operating system task timeouts, improving product competitiveness, and demonstrating good application prospects. Attached Figure Description

[0024] Figure 1 This is a flowchart of a method for reducing standby power consumption of the wide input range linear voltage regulator circuit of the present invention;

[0025] Figure 2 This is a system block diagram of a switching power supply with a wide input range linear voltage regulator circuit according to an embodiment of the present invention;

[0026] Figure 3 This is a detailed flowchart of a control method according to an embodiment of the present invention. Detailed Implementation

[0027] The present invention will now be further described with reference to the accompanying drawings.

[0028] like Figure 1 As shown, the EEPROM data writing method of the non-preemptive real-time operating system of the present invention, wherein the EEPROM data writing time exceeds the cycle period of the non-preemptive real-time operating system, specifically includes the following steps:

[0029] Step (A): Read the WIP flag bit of the EEPROM status register. If WIP=0, jump to step (B); otherwise, maintain step (A).

[0030] Step (B): Send the WREN command to the EEPROM to activate the data writing function;

[0031] Step (C): Read the WEL flag bit of the EEPROM status register. If the WEL flag bit is read as 1 within the set time, the EEPROM write function is successfully activated and the process jumps to step (D); otherwise, the EEPROM data write function activation timeout occurs, the process jumps to step (A), and a fault is reported.

[0032] Step (D): Write data to the EEPROM, first pull the chip select signal low. Then, send the WRITE command, address, and data in sequence, and finally pull the chip select signal high. And jump to step (E);

[0033] Step (E): Read the WIP flag bit of the EEPROM status register. If the WIP changes from 1 to 0 within the set time, jump to step (F); otherwise, consider the data write timeout to have occurred, jump to step (A), and report the fault.

[0034] Step (F): Data verification. Read the EEPROM. If the read content matches the written content, the verification is successful, and proceed to step (A); otherwise, the verification is deemed to have failed and a fault is reported.

[0035] The aforementioned time setting can be 2 seconds depending on the selected non-preemptive real-time operating system. It can be adjusted as needed to accommodate different non-preemptive real-time operating systems and EEPROM chip selections. This 2-second setting is the response time reserved for the EEPROM data writing process. If the EEPROM response time exceeds 2 seconds, the EEPROM is considered to have malfunctioned.

[0036] The time taken for each sequential execution of steps (A)-(F) in this invention is the EEPROM data write time, which is 3.2ms. The cycle time of the non-preemptive real-time operating system is 2ms. Clearly, the EEPROM data write time is longer than the cycle time of the non-preemptive real-time operating system. To facilitate system management, this invention introduces steps (A)-(F) into a state machine. Specifically: in the Ready state, steps (A) and (B) are executed; in the EnableWrite state, step (C) is executed; in the Write state, step (D) is executed; and in the Writing state, step (F) is executed. (E); In the Verify state, execute step (F). If a state machine is introduced in steps (A)-(F), the transition conditions of the state machine are as follows: If the Ready state is completed without failure, transition to the EnableWrite state; If the EnableWrite state is completed without failure, transition to the Write state; If a failure occurs, transition to the Ready state; If the Write state is completed, transition to the Writing state; If the Writing state is completed without timeout failure, transition to the Verify state; Otherwise, transition to the Ready state; If the Verify state is completed, transition to the Ready state.

[0037] Preferably, the Writing state is the longest-running stage, taking 3.16ms (accounting for 98.75% of the total time, with a total time of 3.2ms). The relationship between the state machine state and the cycle of the non-preemptive real-time operating system is established as follows: If the EEPROM is in an idle state and an EEPROM data write request is received, the current cycle of the non-preemptive real-time operating system is denoted as t. The four states Ready, EnableWrite, Write, and Writing are executed sequentially. In cycle t+2, Verify is executed.

[0038] Preferably, during step (A) of the EEPROM data writing process, a mutex lock is introduced to prevent the EEPROM from receiving other write requests while it is being written, which could cause data corruption. This includes the following process:

[0039] (A1) During the MCU power-on initialization process, create two static variables, WritingFlag and AddressLatch, to record the current write operation status of the EEPROM and the write address of the EEPROM, respectively. WritingFlag is 1, indicating that the EEPROM is being written to, and WritingFlag is 0, indicating that the EEPROM is not being written to. AddressLatch records the current write address of the EEPROM. The initial values ​​of WritingFlag and AddressLatch are both 0.

[0040] (A2) When there is an EEPROM data write request, first check WritingFlag and AddressLatch; if WritingFlag is equal to 0, it indicates that there is no write operation in EEPROM. At this time, set WritingFlag to 1, and at the same time, AddressLatch saves the current write address of EEPROM.

[0041] (A3) Whenever the non-preemptive real-time operating system loops through steps (A)-(F) (where steps (A)-(F) constitute a complete data write process; while one write operation is in progress, other data write requests must be rejected, therefore each step (A)-(F) must be checked), WritingFlag and AddressLatch must be checked. When WritingFlag equals 1, only if the EEPROM write address matches the AddressLatch is the EEPROM write process allowed; otherwise, entry is rejected.

[0042] (A4) When the EEPROM data writing process is completed or a failure occurs during the execution of steps (A)-(F), the WritingFlag and AddressLatch are reinitialized to 0 in order to receive new EEPROM data writing requests.

[0043] The following describes a specific embodiment of the EEPROM data writing processing method of the non-preemptive real-time operating system of the present invention, which is used in ST's M95080-DRE chip, but is not limited to this chip, as follows:

[0044] like Figure 2 As shown, when the MCU of an electronic product is powered on, it first performs initialization operations on peripherals and the operating system. After initialization, it enters the main loop of the operating system (a non-preemptive real-time operating system), with a loop period of 2ms. Each main loop cycle contains N tasks, each task performing its specific work. Because the operating system is non-preemptive, each task is executed sequentially within one operating system loop cycle: task 1 is executed first, then task 2; task 2 is executed, then task 3, and so on, until task N is completed. After 2ms, the next loop begins, executing task 1, task 2, ..., task N in sequence. Therefore, it is essential to ensure that the execution time of task 1 to task N is less than 2ms; otherwise, the timing of the non-preemptive real-time operating system will be disrupted, and it will not function properly. If the MCU is not powered on, the operating system will continue to execute in a loop until the MCU is powered off.

[0045] Combination Figure 1 The schematic diagram of the implementation scheme of this invention illustrates the EEPROM data writing process executed within a task of the operating system, taking task 3 as an example. When the operating system executes task 3, it enters the EEPROM write operation state machine, which has five states: Ready, EnableWrite, Write, Writing, and Verify. Each state corresponds to its own EEPROM writing steps, and after the steps in the current state are completed, it jumps to the next state. After the Verify state is completed, the operating system ends the execution of task 3 and jumps to task 4. Of the five states, Writing takes approximately 3.16ms, and the other four states each take approximately 0.01ms, so the total execution time is 3.2ms. Since the operating system's cycle time is 2ms, a complete EEPROM data writing operation requires spanning multiple operating system cycle times. If step 1 is executed starting in cycle t, the optimal scenario is that the data writing operation needs to be completed in cycle t+2.

[0046] like Figure 3As shown in the flowchart of this embodiment of the invention, the process first checks whether the current task has an EEPROM data write request. If not, it jumps directly to the next task; if so, it further checks the value of WritingFlag. There are two cases here:

[0047] The first scenario: The value of WritingFlag is 0.

[0048] At this point, the EEPROM is in a write idle state, and data can be written to it. First, the internal static variable `WritingFlag` is set to 1, and the EEPROM address to be written to is saved to the internal static variable `AddressLatch`. `WritingFlag` and `AddressLatch` together act as a mutex, preventing EEPROM write requests from other tasks from interfering. Then, the complete EEPROM write process is executed, as follows:

[0049] Step 1: Set the state machine's eState to Ready. In this state, send the "RDSR" instruction to read the EEPROM status register. If the EEPROM status register's "WIP" is 0, it indicates that the EEPROM is in an idle state. Then, send the "WREN" instruction to activate the EEPROM write function. Simultaneously, set eState to EnableWrite and jump to Step 2. If the EEPROM status register's "WIP" is 1, it indicates that the EEPROM is writing data, and you need to wait for the EEPROM to complete the data writing. At this point, start the timeout counter, end the current task, and wait for the next system cycle.

[0050] Step 2: When the state machine state eState is EnableWrite, the WEL flag in the EEPROM status register needs to be read. If WEL is 1, it indicates that the EEPROM write enable was successful, eState is set to Write, and the process jumps to step 3. If WEL is 0, the timeout counter is started, the current task is terminated, and the process waits for the next system cycle.

[0051] Step 3: When the state machine's eState is set to Write, the operation address and data are written to the EEPROM sequentially. Then, eState is set to Writing, the current task ends, and the system waits for the next cycle.

[0052] Step 4: The state machine state eState is Writing. Read the WIP flag bit of the EEPROM status register. If the data in Step 3 was successfully written, WIP is 0; otherwise, it is 1. Accordingly, if WIP is 0, set eState to Verify and jump to Step 5; otherwise, end the current task and wait for the next system cycle.

[0053] Step 5: The state machine state eState is set to Verify. The data written in step 3 is read. If it matches the written data, the verification is successful. Otherwise, the verification fails, and a fault is reported. Then, eState is set to Ready, and WritingFlag is cleared. This completes a full EEPROM data writing process.

[0054] The second scenario: The value of WritingFlag is 1.

[0055] At this point, the EEPROM is performing a data write operation, and it is necessary to further determine whether the EEPROM operation address and the AddressLatch are consistent.

[0056] If they are inconsistent, data can only be written to the EEPROM after WritingFlag reaches 0. Specifically, each system cycle reads the WritingFlag flag. If WritingFlag is 1, the current task ends and waits for the next system cycle; if WritingFlag is 0, the first scenario described above is executed. If they are consistent, the corresponding action is performed based on the current state of eState.

[0057] In summary, the non-preemptive real-time operating system EEPROM data writing method of the present invention can realize EEPROM writing operations without interrupting the operating system timing. A state machine is introduced into the implementation process, dividing the operation steps into five different states: Ready, EnableWrite, Write, Writing, and Verify. This facilitates state statistics and differentiation. Furthermore, a mutex lock is introduced during the writing process to prevent the EEPROM from accepting other write requests while it is being written, thus preventing data corruption and improving system security. This invention achieves EEPROM data writing without interrupting the real-time operating system timing, ensuring the continuity and determinism of the operating system timing, effectively avoiding unpredictable fatal failures caused by operating system task timeouts, improving product competitiveness, and demonstrating promising application prospects.

[0058] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for EEPROM data write processing of a non-preemptive real-time operating system, characterized by: The EEPROM data write time exceeds the cycle period of the non-preemptive real-time operating system, and specifically includes the following steps, Step (A): read the WIP flag bit of the EEPROM status register, if WIP=0, jump to step (B); otherwise, maintain step (A); Step (B): send WREN instruction to EEPROM to activate data write function; Step (C): read the WEL flag bit of the EEPROM status register, if the WEL flag bit is read as 1 within a set time, the EEPROM write function is successfully activated, and jump to step (D); otherwise, the EEPROM data write function activation times out, jump to step (A), and report the fault; Step (D): Write data to EEPROM, pull down the chip select signal first , then send the WRITE instruction, address, data in turn, and finally pull up the chip select signal , and jump to step (E); Step (E): read the WIP flag bit of the EEPROM status register, if WIP changes from 1 to 0 within a set time, jump to step (F); otherwise, consider that the write data has timed out, jump to step (A), and report the fault; Step (F): data verification, read EEPROM, if the read content and the written content are consistent, the verification is successful, and jump to step (A); otherwise, it is judged as verification failure and fault is reported, Steps (A)-(F) are introduced into the state machine, specifically: in the Ready state, steps (A) and (B) are executed; in the EnableWrite state, step (C) is executed; in the Write state, step (D) is executed; in the Writing state, step (E) is executed; in the Verify state, step (F) is executed, when step (A) of the EEPROM write data process is executed, a mutual exclusion lock is introduced to prevent the EEPROM from receiving other write requests during the write process, causing data errors, including the following processes: (A1) In the MCU power-on initialization process, new static variables WritingFlag and AddressLatch are created to record the current write operation state of the EEPROM and the EEPROM write address; WritingFlag is 1, indicating that the EEPROM is writing, WritingFlag is 0, indicating that the EEPROM is not writing; AddressLatch records the current EEPROM write address, the initial values of WritingFlag and AddressLatch are both 0; (A2) When there is an EEPROM data write request, first check the values of WritingFlag and AddressLatch, if WritingFlag is equal to 0, it indicates that the EEPROM has no write operation, at this time, WritingFlag is set to 1, and AddressLatch saves the current EEPROM write address; (A3) Whenever the non-preemptive real-time operating system cyclically executes steps (A)-(F), it is necessary to check WritingFlag and AddressLatch. When WritingFlag equals 1, only if the writing address of EEPROM and AddressLatch are consistent, it is allowed to enter the EEPROM writing flow; otherwise, it is refused to enter; (A4) When the EEPROM data writing flow is executed to completion or a fault occurs in the execution of steps (A)-(F), WritingFlag and AddressLatch are reinitialized to 0, so as to receive a new EEPROM data writing request.

2. The EEPROM data write processing method of the non-preemptive real-time operating system according to claim 1, characterized in that: The time for sequentially executing steps (A)-(F) once is the EEPROM data writing time, which is 3.2 ms, and the cycle period of the non-preemptive real-time operating system is 2 ms.

3. The EEPROM data write processing method of the non-preemptive real-time operating system according to claim 1, characterized in that: In the case of introducing a state machine in steps (A)-(F), the jump conditions of the state machine are as follows: jumping to the EnableWrite state when the Ready state is executed to completion and no fault occurs; jumping to the Write state when the EnableWrite state is executed to completion and no fault occurs, and jumping to the Ready state when a fault occurs; jumping to the Writing state when the Write state is executed to completion; jumping to the Verify state when the Writing state is executed to completion and no timeout fault occurs, and jumping to the Ready state when a fault occurs; jumping to the Ready state when the Verify state is executed to completion.

4. The EEPROM data write processing method of the non-preemptive real-time operating system according to claim 1, characterized in that: The longest time-consuming link of the Writing state is 3.16 ms, and the relationship between the state machine states and the cycle period of the non-preemptive real-time operating system is as follows: if the EEPROM is in an idle state and an EEPROM data writing request is received, the current cycle period of the non-preemptive real-time operating system is recorded as t, and the four states of Ready, EnableWrite, Write and Writing are sequentially executed, t+2 cycles, and Verify is executed.

5. The EEPROM data write handling method for a non-preemptive real-time operating system according to claim 1, wherein: The time set in steps (C) and (E) is both 2 seconds.

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