A lookup table-based operation method, device, medium, and electronic device

Abstract

This application provides a lookup table-based computation method, apparatus, medium, and electronic device. The method includes: obtaining a lookup table of convolution results corresponding to each convolution weight, wherein the lookup table records at least one input data and a corresponding convolution result; deploying each convolution result lookup table in a NOR flash unit; inputting an input signal into the NOR flash unit, and obtaining the final convolution result from the convolution result output by the NOR flash unit through at least one bit line, wherein the input signal includes input data and convolution weight data. The technical solution of this application embodiment can, to a certain extent, improve the computation speed and accuracy of the NOR flash in-memory computing method, thereby reducing computational costs and optimizing the user experience.

Description

A lookup table-based operation method, apparatus, medium, and electronic device. Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to a lookup table-based arithmetic method, apparatus, medium, and electronic device. Background Technology

[0002] Current NOR flash in-memory computing methods primarily achieve analog multiplication of drain-source voltage and threshold voltage by subtracting the current flowing through two flash memory modules. Then, by leveraging the parallel characteristics of the NOR flash storage array bit lines, current convergence enables addition. Currently, a single flash memory module can store a maximum of 4 bits, allowing for 4-bit multiplication in a single computation. Existing methods are limited by the accuracy, latency, and area of ​​the ADC, resulting in insufficient accuracy, speed, and cost to meet practical requirements. Summary of the Invention

[0003] The embodiments of this application provide a lookup table-based computation method, apparatus, medium, and electronic device, which can at least to some extent improve the computation speed and accuracy of the NOR flash in-memory computing method, thereby reducing computation costs and optimizing the user experience.

[0004] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0005] According to one aspect of the embodiments of this application, a lookup table-based computation method is provided, the method comprising: obtaining a convolution result lookup table corresponding to each convolution weight, the convolution result lookup table recording at least one input data and a corresponding convolution result; deploying each convolution result lookup table in a NOR flash unit; inputting an input signal into the NOR flash unit, and obtaining a final convolution result from the convolution result output by the NOR flash unit through at least one bit line, the input signal including input data and convolution weight data.

[0006] In some embodiments of this application, deploying each convolution result lookup table in a NOR flash cell includes: defining at least one OR array in the storage array of the NOR flash cell and connecting it to the address decoding array of the NOR flash cell; and deploying each convolution result lookup table in each OR array.

[0007] In some embodiments of this application, based on the foregoing scheme, the step of deploying each convolution result lookup table on each OR array includes: for the target convolution result lookup table, deploying each target convolution result on the bit lines of the target OR array respectively; establishing a correspondence between the target convolution weights and the word lines of the target OR array, so as to deploy the target convolution result lookup table on the target OR array; wherein, the target convolution result lookup table is any one of the convolution result lookup tables, and the target OR array is any one of the OR arrays.

[0008] In some embodiments of this application, based on the foregoing scheme, the step of inputting the input signal into the NOR flash unit and obtaining the final convolution result by the convolution result output by the NOR flash unit through at least one bit line includes: inputting the input signal into the address decoding array of the NOR flash unit; identifying the convolution weight data and input data in the input signal through the address decoding array; determining at least one target word line corresponding to the input signal based on the convolution weight data and the input data; reading the convolution result of the corresponding bit line through each target word line; and obtaining the final convolution result by the convolution result output by the NOR flash unit through at least one bit line.

[0009] In some embodiments of this application, based on the foregoing scheme, determining at least one target word line corresponding to the input signal according to the convolution weight data and the input data includes: determining the OR array corresponding to each convolution weight data according to at least one convolution weight data; and determining the target word line in the OR array corresponding to each convolution weight data according to the input data.

[0010] In some embodiments of this application, based on the foregoing scheme, obtaining the convolution operation result from the current output by the NOR flash unit through at least one bit line includes: accumulating the current output by at least one bit line through the adder circuit of the NOR flash unit to obtain the convolution operation result.

[0011] In some embodiments of this application, before obtaining the convolution result lookup table corresponding to each convolution weight, the method further includes: calculating the convolution operation result of at least one input data under each convolution weight, and constructing the convolution result lookup table corresponding to each convolution weight.

[0012] According to one aspect of the embodiments of this application, a lookup table-based computing apparatus is provided, the apparatus comprising: an acquisition unit, configured to acquire a convolution result lookup table corresponding to each convolution weight, the convolution result lookup table recording at least one input data and a corresponding convolution result; a deployment unit, configured to deploy each convolution result lookup table to a NOR flash unit; and an input unit, configured to input an input signal to the NOR flash unit, and obtain a final convolution result from the convolution result output by the NOR flash unit through at least one bit line, the input signal including input data and convolution weight data.

[0013] According to one aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein at least one piece of program code is stored therein, the at least one piece of program code being loaded and executed by a processor to perform the operations performed by the lookup table-based operation method described above.

[0014] According to one aspect of the embodiments of this application, a computer program product is provided, characterized in that the computer program product includes computer instructions stored in a computer-readable storage medium and adapted to be read and executed by a processor to cause a computer device having the processor to perform the above-described lookup table-based operation method.

[0015] According to one aspect of the embodiments of this application, an electronic device is provided, characterized in that it includes a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors, the one or more programs including instructions for performing the lookup table-based operation method as described above.

[0016] In some embodiments of this application, the technical solutions provided involve obtaining convolution result lookup tables corresponding to each convolution weight and deploying these lookup tables in the NOR flash unit. During actual convolution calculation, it is unnecessary to perform a complete convolution calculation based on the input signal; the convolution calculation can be completed simply by reading the convolution result output from the bitline on the NOR flash unit based on the input signal. Replacing computation with reading effectively improves the computation speed in the actual calculation process. Furthermore, the convolution results recorded in each lookup table can be pre-obtained through high-precision calculation, thus improving the computational accuracy in the actual calculation process, thereby effectively reducing computational costs and optimizing the user experience.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0019] Figure 1 shows a flowchart of a lookup table-based operation method according to an embodiment of this application;

[0020] Figure 2 illustrates a convolution result lookup table according to one embodiment of this application;

[0021] Figure 3 shows a flowchart of a lookup table-based operation method according to an embodiment of this application;

[0022] Figure 4 shows a flowchart of a lookup table-based operation method according to an embodiment of this application;

[0023] Figure 5 shows a simplified schematic diagram of an OR array and an AND array according to one embodiment of this application;

[0024] Figure 6 shows a simplified schematic diagram of an array of NOR flash cells according to one embodiment of this application;

[0025] Figure 7 shows a simplified schematic diagram of the physical block of a NOR flash cell according to one embodiment of this application;

[0026] Figure 8 shows a simplified connection diagram of a fully connected layer according to one embodiment of this application;

[0027] Figure 9 shows a simplified diagram of the physical block bitline space according to one embodiment of this application;

[0028] Figure 10 shows a simplified diagram of the convolution operation of a multidimensional convolutional layer according to an embodiment of this application;

[0029] Figure 11 shows a simplified diagram of the physical block bitline space according to one embodiment of this application;

[0030] Figure 12 shows a simplified diagram of the computation method for a single convolution calculation according to one embodiment of this application;

[0031] Figure 13 shows a flowchart of a lookup table-based operation method according to an embodiment of this application;

[0032] Figure 14 shows a flowchart of a lookup table-based operation method according to an embodiment of this application;

[0033] Figure 15 illustrates a lookup table-based computing device according to an embodiment of this application;

[0034] Figure 16 shows a schematic diagram of the structure of a computer system suitable for implementing the electronic device of the present application. Detailed Implementation

[0035] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0036] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0037] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0038] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0039] It should be noted that "multiple" in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0040] The embodiments in this application involve technical content related to NOR flash. Intel first developed NOR flash technology in 1988. The characteristic of NOR is execution-in-place (XIP), which allows applications to run directly in the flash memory without having to load code into system RAM. NOR has high transfer efficiency and is very cost-effective for small capacities of 1-4MB, but its very low write and erase speeds significantly affect its performance.

[0041] The embodiments in this application involve technical content related to convolution. In functional analysis, convolution, spin-product, or convolution is a mathematical operation that generates a third function from two functions f and g. Essentially, it is a special integral transformation, representing the integral of the product of the overlapping function values ​​of functions f and g after flipping and translation, over the overlap length. If one of the functions involved in the convolution is considered as an indicator function of the interval, convolution can also be seen as a generalization of "moving average." Convolution has many applications in engineering and mathematics: In statistics, a weighted moving average is a type of convolution. In probability theory, the probability density function of the sum of two statistically independent variables X and Y is the convolution of the probability density functions of X and Y. In optics, reflected light can be represented by the convolution of a light source with a function reflecting various reflection effects. In electronic engineering and signal processing, the output of any linear system can be obtained by convolving the input signal with the system function (the system's impulse response). In physics, any linear system (compliant with the superposition principle) exhibits convolution.

[0042] Please refer to Figures 1 and 2.

[0043] Figure 1 shows a flowchart of a lookup table-based operation method according to an embodiment of this application. As shown in Figure 1, the lookup table-based operation method includes at least steps S101 to S103, which are described in detail below:

[0044] Step S101: Obtain the convolution result lookup table corresponding to each convolution weight. The convolution result lookup table records at least one input data and the corresponding convolution result.

[0045] Step S102: Deploy the lookup tables for each convolution result in the NOR flash unit.

[0046] Step S103: Input the input signal into the NOR flash unit, and obtain the final convolution result from the convolution result output by the NOR flash unit through at least one bit line. The input signal includes input data and convolution weight data.

[0047] In this application, a convolution result lookup table corresponding to each convolution weight can be obtained and deployed in a NOR flash cell. During the actual convolution calculation, it is not necessary to perform a complete convolution calculation based on the input signal. The convolution calculation can be completed simply by reading the convolution result output from the bit line on the NOR flash cell based on the input signal. Replacing the calculation with the reading behavior can effectively improve the calculation speed in the actual calculation process. Furthermore, the convolution results recorded in each convolution result lookup table can be obtained in advance through high-precision calculation, which can also improve the calculation accuracy in the actual calculation process, thereby effectively reducing the calculation cost and optimizing the user experience.

[0048] In this application, before obtaining the convolution result lookup table corresponding to each convolution weight, the method may further include: calculating the convolution operation result of at least one input data under each convolution weight, and constructing the convolution result lookup table corresponding to each convolution weight.

[0049] In this application, the input data is typically 4 bits. With a fixed weight, the input data can have a total of 16 forms, thus requiring 16 corresponding output data. The convolution result lookup table can record the correspondence between the 16 inputs and 16 outputs under a certain convolution weight.

[0050] For example, referring to Figure 2, Figure 2 shows a convolution result lookup table according to one embodiment of the present application. When performing convolution calculation, the convolution weights are known. When the convolution weights are known, the output of the 4-bit multiplication is Y = W * A, where A is the input data. When the weight W = 3, the convolution result lookup table of the output data Y can be as shown in Figure 2.

[0051] Please refer to Figures 3 through 12.

[0052] Figure 3 shows a flowchart of a lookup table-based operation method according to an embodiment of this application. As shown in Figure 3, the method of deploying the various convolution result lookup tables in the NOR flash unit may include steps S301-S302:

[0053] Step S301: Define at least one OR array in the storage array of the NOR flash cell and connect it to the address decoding array of the NOR flash cell.

[0054] Step S302: Deploy the lookup tables of each convolution result in each OR array.

[0055] Figure 4 shows a flowchart of a lookup table-based operation method according to an embodiment of this application. As shown in Figure 4, in step S302, the method of deploying the respective convolution result lookup tables in respective OR arrays may include steps S401-S402:

[0056] Step S401: For the target convolution result lookup table, deploy each target convolution result on the bit lines of the target or array respectively.

[0057] Step S402: Establish the correspondence between the target convolution weights and the word lines of the target or array, so as to deploy the target convolution result lookup table on the target or array; wherein, the target convolution result lookup table is any one of the various convolution result lookup tables, and the target or array is any one of the various or arrays.

[0058] In this application, at least one OR array and an AND array can be defined. The AND array is used to implement 4-bit decoding, and the OR array is used to output the convolution result lookup table. Multiple output signals corresponding to each convolution weight can be deployed on the bit lines of an OR array, and a correspondence between the convolution weights and the word lines of the OR array can be established. When an input signal is received, the corresponding OR array can be determined by the weights, and the bit lines in the OR array can be determined by the input data of the input signal. At this point, the convolution operation can be completed simply by reading the output signals on the bit lines.

[0059] For example, please refer to Figure 5, which shows a simplified schematic diagram of an OR array and an AND array according to one embodiment of this application. As shown in Figure 5, when a 4-bit signal A[3:0] is input to the NAND array, the 4-bit signal A corresponds to the input signal on the convolution result lookup table, and only one W signal is valid. At this time, the NOR array will only send the signal on the corresponding W signal to the Y signal, thereby outputting the output signal based on the convolution result lookup table.

[0060] For example, please refer to Figure 6, which shows a simplified schematic diagram of an array of NOR flash cells according to one embodiment of this application. The array corresponds exactly to the address decoding array in the NOR flash; during programming and reading, only one word line is selected. The NOR array corresponds exactly to the storage array of the NOR flash, with convolution weights deployed in multiple OR arrays. During a read operation, the lower 3 bits of the address data are used as input to ADDINT[3:0], and other operations are completely consistent with the NOR flash read operation; the read 8-bit structure is the calculation result. The 8-bit data width is completely consistent with the NOR flash operation byte, allowing complete reuse of the NOR flash bit-line decoding logic. Simultaneously, only one word line is selected in each operation, and the current on the bit line is only the current of one flash cell; the current consumption during calculation is the same as the read operation power consumption of the NOR flash.

[0061] In this application, the physical block size of a traditional NOR flash memory array is generally 8M or 4M. Taking 8M as an example, the corresponding number of word lines and bit lines is 1024 (word lines) x 8192 (bit lines). That is, an 8M physical block can be configured with 1024 word lines and 8192 bit lines, which is equivalent to one word line corresponding to 8 bit lines.

[0062] For example, please refer to Figure 7, which shows a simplified schematic diagram of the physical block of a NOR flash cell according to one embodiment of this application. As shown in Figure 7, an 8M physical block can be configured with 1024 word lines and 8192 bit lines, which is equivalent to one word line corresponding to 8 bit lines. The other flash cells are also in an open state, and the output results are invalid. Therefore, in order to maximize the utilization of storage space, the deployment of convolution weights needs to be optimized.

[0063] The following section will explain the methods for deploying convolution weights in different convolution operation environments.

[0064] First, the deployment of convolution weights in fully connected layers will be explained.

[0065] The input to a fully connected layer is a 1D array. Multi-dimensional arrays need to be flattened into 1D arrays before being connected to the fully connected layer. Each node in a fully connected layer is connected to every node in the layer above it.

[0066] For example, please refer to Figure 8, which shows a simplified connection diagram of a fully connected layer according to one embodiment of this application. Taking a fully connected layer with 3 input signals and 3 outputs as an example, the fully connected diagram can be as shown in Figure 8. The input parameters are X1, X2, and X3, and the output parameters are Y1, Y2, and Y3. The number of convolution weight parameters is equal to the number of input parameters multiplied by the number of output parameters.

[0067] The calculation formula can be as follows:

[0068] Y1 = W 11 ×X1+W 12 ×X2+W 13 ×X3;

[0069] Y2 = W 21 ×X1+W 22 ×X2+W 33 ×X3;

[0070] Y3 = W 31 ×X1+W 22 ×X2+W 33 ×X3.

[0071] At this point, the computation of the fully connected layer can be represented by vector-matrix multiplication:

[0072]

[0073] The input vector is selected by the ADDINT decoding circuit to select the corresponding word line. After each input signal is decoded by the address decoding array, the convolution weights and input data are identified. Each convolution weight can correspond to a set of word lines, and each word line corresponds to at least one bit line. The bit line can be used to read the output signal.

[0074] For example, please refer to Figure 9, which shows a simplified diagram of the physical block bitline space according to one embodiment of this application. After X1 decoding, at least one word line in the first group (Group 0) of 16 word lines can be selected. W 11 W 21 W 31 The three convolution weights are deployed in the memory areas corresponding to the set of word lines. During a read operation, the word lines decoded by X1 are opened, and W is read simultaneously through the corresponding bit lines. 11 ×X1,W 21 ×X1,W 31 The calculation results for ×X1. Similarly, X2 and X3 are deployed in the second and third WL regions.

[0075] In this application, three sets of word lines can be opened simultaneously, and the calculated results are read by the ADC circuit at the bit line end to obtain the accumulated current. Alternatively, the results can be read in stages, in which case the bit line end only needs a sensitive amplifier circuit to determine the current and read the result as 0 or 1, thus eliminating the need to change the circuit structure of the traditional NOR flash bit line receiver. The read results are then passed through an adder circuit and added to the results of the second and third sets to obtain the final convolution operation result.

[0076] In this application, the input groups are not limited to being deployed in different word line groups; they can also be deployed in the same word line group. The choice depends on the size of the matrix, the capacity of the memory, and the computation speed. The technical solution provided in this application can achieve up to 16 4-bit multiplication operations in a single operation (not considering parallel operation of multiple word lines). It is applicable to fully connected layers with fewer than 16 output features. When the number of outputs is greater than 16, large-scale fully connected layer computation can be achieved through multiple consecutive read operations.

[0077] In this application, up to 1024 sets of convolution weights can be deployed in the entire bitline space of a physical block of a NOR flash cell, and different sets can be computed by switching column addresses.

[0078] The deployment of convolution weights in multidimensional convolutional layers will be explained next.

[0079] Four-dimensional tensors are widely used in convolutional neural networks to store feature map data. Please refer to Figure 10, which shows a simplified diagram of the convolution operation of a multi-dimensional convolutional layer according to an embodiment of this application. As shown in Figure 10, taking the first convolutional layer of the YOLO algorithm as an example, the input is 416x416x3 3-channel image data, and the convolution kernel is 32x3x3x3, where kernel_size = 3 and output = 32, meaning that one convolution kernel "convolves" multiple dimensions simultaneously.

[0080] In this convolution operation, 32 sets of convolution calculations can be performed simultaneously. Due to the limitation on the number of sensitive amplifiers in the NOR flash circuit structure, only 16 bytes of data can be read at a time, that is, only 16 output signals can be read at a time, which is equivalent to performing a maximum of 16 4-bit multiplications simultaneously. Therefore, for the above 32 sets of convolution multiplication operations, it can be performed in two parts: first calculate the convolution results of the first 16 sets, and then calculate the convolution results of the last 16 sets.

[0081] The deployment of convolution weights for a single convolution will be explained next.

[0082] For a two-dimensional convolution kernel with one channel, arranging it diagonally can improve the parallelism of convolution computation.

[0083] For example, please refer to Figure 11, which shows a simplified diagram of the physical block bitline space according to one embodiment of this application. As shown in Figure 11, in the actual operation, the input data can be converted into several column vectors using the GEMM method. To improve the parallelism of a single convolution kernel operation, the convolution kernels are deployed diagonally in the storage array. A partition is set up with 256 word lines and 128 bit lines corresponding to the storage area. This partition can store up to 16 convolution weights, and a single read operation can complete 16 4-bit multiplication operations. The entire bitline space can deploy up to 64 sets of convolution weights, and different sets can be calculated by switching column addresses.

[0084] Next, please refer to Figure 12, which shows a simplified diagram of the calculation method for a single convolution according to an embodiment of this application. After the weights are deployed according to the above method, the calculation method of one 4x4 input and one 3x3 convolution kernel can be as shown in Figure 12. The 3x3 convolution kernel has a total of 9 convolution weights, which can be deployed in the storage array in a diagonal form.

[0085] Please refer to Figure 13.

[0086] Figure 13 shows a flowchart of a lookup table-based operation method according to an embodiment of this application. As shown in Figure 13, the method of inputting an input signal into the NOR flash unit and obtaining the final convolution result from the convolution result output by the NOR flash unit through at least one bit line may include steps S1301-S1303:

[0087] Step S1301: Input the input signal into the address decoding array of the NOR flash cell, and identify the convolution weight data and input data in the input signal through the address decoding array.

[0088] Step S1302: Based on the convolution weight data and the input data, determine at least one target word line corresponding to the input signal, and read the convolution result of the corresponding bit line through each target word line.

[0089] Step S1303: The final convolution result is obtained from the convolution result output by the NOR flash unit through at least one bit line.

[0090] Please refer to Figure 14.

[0091] Figure 14 shows a flowchart of a lookup table-based operation method according to an embodiment of this application. As shown in Figure 14, in step S1302, the method for determining at least one target word line corresponding to the input signal based on the convolution weight data and the input data may include steps S1401-S1402:

[0092] Step S1401: Determine the OR array corresponding to each convolution weight data based on at least one convolution weight data.

[0093] Step S1402: Based on the input data, determine the target word line in the array corresponding to each convolution weight data.

[0094] In step S1302, the method for obtaining the convolution operation result from the current output by the NOR flash cell through at least one bit line may include: accumulating the current output by at least one bit line through the adder circuit of the NOR flash cell to obtain the convolution operation result.

[0095] In this application, at least one OR array and an AND array can be defined. The AND array is used to implement 4-bit decoding, and the OR array is used to output the convolution result lookup table. Multiple output signals corresponding to each weight can be deployed on the bit lines of an OR array, and a correspondence between the convolution weights and the word lines of the OR array can be established. When an input signal is received, the corresponding OR array can be determined through the convolution weights, and the bit lines in the OR array can be determined through the input data of the input signal. At this point, the convolution operation can be completed simply by reading the output signals on the bit lines.

[0096] An embodiment of the apparatus of this application will now be described with reference to the accompanying drawings.

[0097] Please refer to Figure 15.

[0098] Figure 15 illustrates a lookup table-based computing device according to an embodiment of the present application. The lookup table-based computing device may include: an acquisition unit 1501, a deployment unit 1502, and an input unit 1503.

[0099] The specific configuration of the arithmetic unit based on the lookup table can be as follows:

[0100] The acquisition unit 1501 is used to acquire the convolution result lookup table corresponding to each convolution weight. The convolution result lookup table records at least one input data and the corresponding convolution result.

[0101] Deployment unit 1502 is used to deploy the various convolution result lookup tables in the NOR flash unit.

[0102] The input unit 1503 is used to input the input signal into the NOR flash unit, and the final convolution result is obtained by the convolution result output by the NOR flash unit through at least one bit line. The input signal includes input data and convolution weight data.

[0103] An embodiment of an electronic device according to this application will now be described with reference to the accompanying drawings.

[0104] Please refer to Figure 16.

[0105] Figure 16 shows a schematic diagram of the structure of a computer system suitable for implementing the electronic device of the present application.

[0106] It should be noted that the computer system 1600 of the electronic device shown in Figure 16 is only an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0107] As shown in Figure 16, the computer system 1600 includes a Central Processing Unit (CPU) 1601, which can perform various appropriate actions and processes based on programs stored in Read-Only Memory (ROM) 1602 or programs loaded from storage portion 1608 into Random Access Memory (RAM) 1603, such as performing the methods described in the above embodiments. The RAM 1603 also stores various programs and data required for system operation. The CPU 1601, ROM 1602, and RAM 1603 are interconnected via a bus 1604. An Input / Output (I / O) interface 1605 is also connected to the bus 1604.

[0108] The following components are connected to I / O interface 1605: an input section 1606 including a keyboard, mouse, etc.; an output section 1607 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 1608 including a hard disk, etc.; and a communication section 1609 including a network interface card such as a LAN (Local Area Network) card, modem, etc. The communication section 1609 performs communication processing via a network such as the Internet. A drive 1610 is also connected to I / O interface 1605 as needed. Removable media 1611, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 1610 as needed so that computer programs read from them can be installed into storage section 1608 as needed.

[0109] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 1609, and / or installed from removable medium 1611. When the computer program is executed by central processing unit (CPU) 1601, it performs various functions defined in the system of this application.

[0110] It should be noted that the computer-readable medium shown in the embodiments of this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such transmitted data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0111] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. Each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0112] The units described in the embodiments of this application can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0113] In another aspect, this application also provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the lookup table-based operation method described in the above embodiments.

[0114] In another aspect, this application also provides a computer-readable medium, which may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the electronic device. The computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to implement the lookup table-based operation method described in the above embodiments.

[0115] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of this application, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0116] Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, touch terminal, or network device, etc.) to execute the method according to the embodiments of this application.

[0117] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0118] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A lookup table-based operation method, characterized in that, The method includes: obtaining a convolution result lookup table corresponding to each convolution weight, wherein the convolution result lookup table records at least one input data and the corresponding convolution result; deploying each convolution result lookup table in a NOR flash cell; inputting an input signal into the NOR flash cell, and obtaining the final convolution result from the convolution result output by the NOR flash cell through at least one bit line, wherein the input signal includes input data and convolution weight data; the deployment of each convolution result lookup table in the NOR flash cell includes: defining at least one OR array in the storage array of the NOR flash cell and connecting it to the address decoding array of the NOR flash cell; deploying each target convolution result on the bit line of the target or array for each target convolution result lookup table; establishing a correspondence between the target convolution weights and the word lines of the target or array to deploy the target convolution result lookup table in the target or array; wherein the target convolution result lookup table is any one of the convolution result lookup tables, and the target or array is any one of the OR arrays; the convolution kernels are deployed in the storage array in a diagonal manner; the input signal is input into the NOR flash cell... The method for obtaining a final convolution result from the convolution result output by the NOR flash unit through at least one bit line includes: inputting an input signal into the address decoding array of the NOR flash unit; identifying convolution weight data and input data in the input signal through the address decoding array; determining at least one target word line corresponding to the input signal based on the convolution weight data and the input data; reading the convolution result of the corresponding bit line through each target word line; and obtaining the final convolution result from the convolution result output by the NOR flash unit through at least one bit line.

2. The method according to claim 1, characterized in that, The step of determining at least one target word line corresponding to the input signal based on the convolution weight data and the input data includes: determining an OR array corresponding to each convolution weight data based on at least one convolution weight data; and determining the target word line in the OR array corresponding to each convolution weight data based on the input data.

3. The method according to claim 1, characterized in that, The step of obtaining the convolution operation result from the current output by the NOR flash cell through at least one bit line includes: accumulating the current output by at least one bit line through the adder circuit of the NOR flash cell to obtain the convolution operation result.

4. The method according to claim 1, characterized in that, Before obtaining the convolution result lookup table corresponding to each convolution weight, the method further includes: calculating the convolution operation result of at least one input data under each convolution weight, and constructing the convolution result lookup table corresponding to each convolution weight.

5. A computational device based on a lookup table, characterized in that, The apparatus includes: an acquisition unit, configured to acquire a convolution result lookup table corresponding to each convolution weight, the convolution result lookup table recording at least one input data and a corresponding convolution result; a deployment unit, configured to deploy each convolution result lookup table to a NOR flash unit; and an input unit, configured to input an input signal to the NOR flash unit, and obtain a final convolution result from the convolution result output by the NOR flash unit through at least one bit line, the input signal including input data and convolution weight data; wherein, the deployment unit is specifically configured to: define at least one OR array in the storage array of the NOR flash unit, and connect it to the NOR flash unit. The address decoding array of the flash unit is connected; for the target convolution result lookup table, each target convolution result is deployed on the bit lines of the target or array respectively; the correspondence between the target convolution weights and the word lines of the target or array is established so as to deploy the target convolution result lookup table on the target or array; wherein, the target convolution result lookup table is any one of the various convolution result lookup tables, and the target or array is any one of the various or arrays; the convolution kernels are deployed in the memory array in a diagonal manner; the input unit is specifically used for: inputting the input signal into the address decoding array of the NOR flash unit, identifying the convolution weight data and input data in the input signal through the address decoding array; determining at least one target word line corresponding to the input signal according to the convolution weight data and the input data, reading the convolution result of the corresponding bit line through each target word line; and obtaining the final convolution result from the convolution result output by the NOR flash unit through at least one bit line.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one piece of program code, which is loaded and executed by a processor to perform the operations performed by the lookup table-based arithmetic method as described in any one of claims 1 to 4.

7. An electronic device, characterized in that, It includes a memory and one or more programs, wherein one or more programs are stored in the memory and configured to be executed by one or more processors, wherein the one or more programs include instructions for performing the lookup table-based operation method as described in any one of claims 1 to 4.

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