Display panel and display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes a display area and a peripheral area. The peripheral area includes at least one special-shaped area; a plurality of first driving signal lines; a plurality of second driving signal lines. The first driving signal lines and the second driving signal lines both extend to the display area, and the first driving signal lines and the second driving signal lines are cross-arranged in the display area; a plurality of scanning units located in the peripheral area; the output end of the scanning unit is connected to the first driving signal line to output a scanning signal to the first driving signal line; a plurality of dummy scanning units located in the special-shaped area, and the dummy scanning units are arranged between two scanning units; at least part of the structure of at least one dummy scanning unit is reused as a compensation load, and the compensation load is used to compensate the load of the connected first driving signal line or the connected second driving signal line. Accordingly, while realizing the load compensation of the driving signal line, the frame is reduced, and the narrow-bezel technology is realized.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] With the development of light emitting diode (LED) display technologies, display devices have been gradually applied to many fields such as smart phones, wearable devices, tablet computers, televisions, virtual display devices, etc.; meanwhile, various special-shaped designs have emerged in display devices, such as notch screens, waterdrop screens, hole-digging screens, non-rectangular screens, circular screens, etc.

[0003] However, the border of a special-shaped display device is relatively wide, which is not conducive to realizing a narrow border design. Summary of the Invention

[0004] The present invention provides a display panel and a display device to reduce the border of the display device and realize a narrow border design.

[0005] According to an aspect of the present invention, there is provided a display panel, the display panel including: a display area and a peripheral area located outside the display area, the peripheral area including at least one special-shaped area;

[0006] A plurality of first driving signal lines and a plurality of second driving signal lines, both the first driving signal lines and the second driving signal lines extend from the peripheral area to the display area, and the first driving signal lines and the second driving signal lines are cross-set in the display area;

[0007] A plurality of scanning units, located in the peripheral area, an output end of the scanning unit is connected to the first driving signal line to output a scanning signal to the first driving signal line;

[0008] A plurality of dummy scanning units, located in the special-shaped area, and the dummy scanning units are arranged between two of the scanning units; at least a part of the structure of at least one of the dummy scanning units is reused as a compensation load, the compensation load is connected to the first driving signal line or connected to the second driving signal line, and compensates the load of the connected first driving signal line or the connected second driving signal line.

[0009] Optionally, the display panel includes: a semiconductor layer, a first metal layer, a second metal layer, and a third metal layer which are stacked in sequence;

[0010] The third metal layer corresponding to the compensation load is integrally formed.

[0011] Optionally, the second metal layer corresponding to the compensation load includes strip-shaped electrodes and / or harpoon-shaped electrodes.

[0012] Optionally, the compensation load includes: a capacitor unit;

[0013] At least a part of the semiconductor layer, at least a part of the second metal layer, and at least a part of the third metal layer corresponding to the dummy scan unit form the capacitor unit.

[0014] Optionally, the second metal layer corresponding to the capacitor unit is connected to the first driving signal line or the second driving signal line, and the semiconductor layer and the third metal layer corresponding to the capacitor unit are both connected to a constant voltage;

[0015] Optionally, the display panel includes: a power supply line; the power supply line extends from the peripheral area to the display area, and the semiconductor layer and the third metal layer corresponding to the capacitor unit are both connected to the power supply line.

[0016] Optionally, the scan unit includes a thin film transistor;

[0017] The third metal layer corresponding to the scan unit includes the source electrode and the drain electrode of the thin film transistor, and the source electrode and the drain electrode are respectively connected to the semiconductor layer corresponding to the scan unit through vias;

[0018] The third metal layer corresponding to the compensation load is connected to the semiconductor layer corresponding to the compensation load through a via.

[0019] Optionally, in a direction perpendicular to the plane of the display panel, the structure of the dummy scan unit except for the compensation load is the same as the corresponding structure of the scan unit;

[0020] Optionally, both the scan unit and the dummy scan unit include a plurality of thin film transistors, and the number of thin film transistors in one scan unit is greater than or equal to the number of thin film transistors in one dummy scan unit.

[0021] Optionally, the dummy scan unit includes: a dummy input transistor, a dummy output control transistor, a dummy first output transistor, a dummy first output capacitor, a dummy second output transistor, a dummy second output capacitor, and a dummy voltage dividing transistor;

[0022] The first pole and the gate of the dummy input transistor are floating;

[0023] The second electrode plate of the dummy second output capacitor serves as the output end of the dummy scan unit;

[0024] The gate of the dummy output control transistor is connected to the second pole of the dummy input transistor and is connected to the second pole of the dummy voltage dividing transistor through a connection line. The first pole of the dummy output control transistor is floating, and the second pole of the dummy output control transistor is connected to the gate of the dummy first output transistor and the first plate of the dummy first output capacitor;

[0025] The first pole of the dummy first output transistor is connected to the second plate of the dummy first output capacitor, and the second pole of the dummy first output transistor is connected to the second plate of the dummy second output capacitor and the second pole of the dummy second output transistor;

[0026] The gate of the dummy second output transistor is connected to the first plate of the second output capacitor and the first pole of the dummy voltage dividing transistor, and the first pole of the dummy second output transistor is floating; the gate of the dummy voltage dividing transistor is floating;

[0027] Wherein, the source and drain of the dummy first output transistor are connected, and the source and drain of the dummy second output transistor are connected, serving as the first partial structure of the compensation load; the gates of the dummy first output transistor and the dummy second output transistor serve as the second partial structure of the compensation load.

[0028] Optionally, the display panel further includes a first insulating layer, a second insulating layer, and a third insulating layer;

[0029] The first insulating layer corresponding to the scanning unit is located between the semiconductor layer corresponding to the scanning unit and the first metal layer, the second insulating layer corresponding to the scanning unit is located between the first metal layer corresponding to the scanning unit and the second metal layer, and the third insulating layer corresponding to the scanning unit is located between the second metal layer corresponding to the scanning unit and the third metal layer;

[0030] The first insulating layer and the second insulating layer corresponding to the dummy scanning unit are located between the semiconductor layer corresponding to the dummy scanning unit and the second metal layer, the second insulating layer corresponding to the dummy scanning unit is located between the first insulating layer corresponding to the dummy scanning unit and the second metal layer, and the third insulating layer corresponding to the dummy scanning unit is located between the second metal layer corresponding to the dummy scanning unit and the third metal layer.

[0031] According to another aspect of the present invention, a display device is provided, including the display panel as described in the above aspect; wherein, a plurality of sub-pixels arranged in an array are disposed in the display area of the display panel,

[0032] The number of sub-pixels connected to at least two of the multiple first driving signal lines is different, and / or the number of sub-pixels connected to at least two of the multiple second driving signal lines is different.

[0033] In the technical solution of the embodiment of the present invention, the display panel includes a display area and a peripheral area, and the peripheral area includes at least one special-shaped area; the display panel includes: multiple first driving signal lines, multiple second driving signal lines, multiple scanning units, and multiple dummy scanning units; the first driving signal lines and the second driving signal lines are cross-arranged in the display area; multiple scanning units are located in the peripheral area, and the output ends of the scanning units are connected to the first driving signal lines to output scanning signals to the first driving signal lines; multiple dummy scanning units are located in the special-shaped area, and the dummy scanning units are arranged between two scanning units.

[0034] Based on this, at least part of the structure of at least one dummy scanning unit in the special-shaped area is reused as a compensation load, and the compensation load is connected to the first driving signal line that needs load compensation or the second driving signal line that needs load compensation, so that the compensation load compensates the load of the connected first driving signal line or the connected second driving signal line, thereby reducing the load difference of each first driving signal line or the load difference of each second driving signal line, and improving the brightness uniformity of the display.

[0035] At the same time, in the technical solution of this embodiment, at least part of the structure of the dummy scanning unit located between two adjacent scanning units is reused as a compensation load, thereby avoiding the additional setting of an independent compensation unit between the scanning unit and the display area, thus not occupying the screen border additionally, reducing the width of the border, making the border narrower, and thus realizing a narrow border design.

[0036] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0038] Figure 1 is a top view structural schematic diagram of a special-shaped display panel in the related art;

[0039] Figure 2 isFigure 1 Enlarged view of the middle special-shaped area;

[0040] Figure 3 It is a schematic top view structure diagram of a display panel provided by an embodiment of the present invention;

[0041] Figure 4 is Figure 3 Partial enlarged view of the shown display panel;

[0042] Figure 5 is Figure 4 Schematic top view structure diagram of adjacent scan units and dummy scan units shown;

[0043] Figure 6 is Figure 5 Schematic cross-sectional structure diagram along the section line QQ';

[0044] Figure 7 is Figure 5 Schematic structure diagram of a second metal layer of a compensation load shown;

[0045] Figure 8 is Figure 5 Schematic structure diagram of another second metal layer of a compensation load shown;

[0046] Figure 9 Schematic structure diagram of a scan unit provided by an embodiment of the present invention;

[0047] Figure 10 Schematic top view structure diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0048] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0049] It should be noted that the terms "first", "second", etc. in the description, claims and above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0050] As mentioned in the background art, the border of the special-shaped display device in the related art is relatively wide. After research by the inventor, it is found that the reason for the relatively wide border is as follows:

[0051] Figure 1 It is a schematic top view structure diagram of a special-shaped display panel in the related art. Figure 2 is Figure 1 The enlarged view of the special-shaped area in. Combining Figure 1 with Figure 2 , the special-shaped display panel includes a display area AA, a non-display area NAA, and a special-shaped area BB. In addition, a plurality of sub-pixels P for displaying images arranged in an array are located in the display area AA. The gate driving circuit (Gate In Panel circuit, GIP circuit) is located in the non-display area NAA. The gate driving circuit includes n-stage shift registers ST1 to STn, where n is a positive integer; the multi-stage shift register ST is arranged around the display area AA, and the multi-stage shift register ST is connected in a cascaded manner to sequentially generate gate driving signals. A plurality of row driving signal lines 110 and a plurality of column driving signal lines 120 extend from the non-display area NAA to the display area AA to transmit gate driving signals, data signals, initialization signals, etc. to the connected sub-pixels P (the sub-pixels may include light-emitting elements and corresponding pixel circuits).

[0052] Due to the existence of the irregular region BB, the number of sub-pixels in the pixel rows and / or pixel columns of the region in the display region AA corresponding to the irregular region BB is not exactly the same, so that the number of sub-pixels connected to the row driving signal lines 110 and / or column driving signal lines 120 is not exactly the same, resulting in the loads of each row driving signal line 110 and / or column driving signal line 120 not being exactly the same. For example, the number of sub-pixels P connected to the row driving signal line 110_1 is greater than the number of sub-pixels P connected to the row driving signal line 110_2, so that the load of the row driving signal line 110_1 is greater than the load of the row driving signal line 110_2; the number of sub-pixels P connected to the column driving signal line 120_1 is less than the number of sub-pixels P connected to the column driving signal line 120_2, so that the load of the column driving signal line 120_1 is less than the load of the column driving signal line 120_2.

[0053] Differences in the load magnitudes of the driving signal lines easily lead to the defect of uneven brightness when the display panel is displaying. Therefore, it is necessary to compensate for the load of the driving signal lines to improve the brightness uniformity of the display. However, currently, as Figure 2 shown, in the related art, in order to achieve the compensation of the load of the driving signal lines, an independent compensation unit 130 is additionally designed and the compensation unit 130 is arranged between the gate driving circuit and the display region AA, resulting in a relatively wide border.

[0054] In view of this, the embodiments of the present invention provide a display panel and a display device to reduce the border while achieving the load compensation of the driving signal lines and realizing a narrow border design. Figure 3 FIG. is a schematic top view structure diagram of a display panel provided by an embodiment of the present invention, Figure 4 is Figure 3 a partial enlarged view of the display panel shown in FIG. Combining Figure 3 with Figure 4, the display panel provided by the embodiment of the present invention includes a display area AA and a peripheral area NA, and the peripheral area NA includes at least one special-shaped area CC; and includes: a plurality of first driving signal lines 210; a plurality of second driving signal lines 220, both the first driving signal lines 210 and the second driving signal lines 220 extend from the peripheral area NA to the display area AA, and the first driving signal lines 210 and the second driving signal lines 220 are cross-arranged in the display area AA; a plurality of scanning units 230, located in the peripheral area NA; the output end of the scanning unit 230 is connected to the first driving signal line 210 to output a scanning signal to the first driving signal line 210; a plurality of dummy scanning units 240, located in the special-shaped area CC, and the dummy scanning units 240 are arranged between two scanning units 230; at least part of the structure of at least one dummy scanning unit 240 is reused as a compensation load, and the compensation load is connected to the first driving signal line 210 or the second driving signal line 220, and compensates the load of the connected first driving signal line 210 or the connected second driving signal line 220.

[0055] Specifically, a plurality of sub-pixels P for displaying images are arranged in an array in the display area AA. The first driving signal lines 210 may be row driving signal lines, and the second driving signal lines 220 may be column driving signal lines; the row driving signal lines are, for example, scanning signal lines, and the column driving signal lines are, for example, data signal lines or initialization signal lines, etc. The first driving signal lines 210 and the second driving signal lines 220 are cross-arranged in the display area AA, so as to define a plurality of pixel areas in the display area AA, and the sub-pixels P are arranged in the corresponding pixel areas.

[0056] A plurality of scanning units 230 are arranged in sequence around the display area AA in the peripheral area NA. Each scanning unit 230 may be a shift register, and a plurality of cascaded scanning units 230 are a plurality of cascaded shift registers; wherein, the output end of the upper-level scanning unit 230 may be connected to the input end of the lower-level scanning unit 230, and the input end of the first-level scanning unit 230 may access the start signal In. The scanning unit 230 can shift and output the start signal accessed from its own input end I1 through the output end according to the accessed clock signal. The output end of each scanning unit 230 is connected to the corresponding first driving signal line 210, and the scanning signal output from the output end O1 of the scanning unit 230 can be transmitted to the gate of the switching transistor of the pixel circuit of the sub-pixel connected to the first driving signal line 210, so as to drive the switching transistor to work.

[0057] The scan signal can be used as the scan signal Scan for driving data to be written into transistors and initializing the operation of switching transistors such as transistors, or as the emission control signal EM for driving the operation of the emission control transistor. Among them, the data writing transistor refers to the switching transistor in the pixel circuit for transmitting data signals to the driving transistor of the pixel circuit, the initialization transistor refers to the switching transistor for transmitting initialization signals to the gate of the driving transistor and / or the anode of the light-emitting element, and the emission control transistor refers to the switching transistor for preventing the pixel circuit from outputting a driving current to the light-emitting element during the non-emission stage.

[0058] The peripheral region NA includes at least one special-shaped region CC (such as special-shaped regions CC_1, CC_2, CC_3, and CC_4). Figure 3 The special-shaped region CC shown can also be regarded as a rounded corner region. The peripheral region NA may also include a non-special-shaped region DD other than the special-shaped region CC. Refer to Figure 4 , the gap L1 between the scan units 230 of two adjacent special-shaped regions CC is greater than the gap L2 between the scan units 230 of two adjacent non-special-shaped regions DD, that is, the number of scan units 230 per unit area of the special-shaped region CC is less than the number of scan units 230 per unit area of the non-special-shaped region DD, so there will be relatively more blank areas in the special-shaped region CC. The relatively more blank areas in the special-shaped region CC will cause uneven etching between the special-shaped region CC and the non-special-shaped region DD, resulting in problems such as easy occurrence of electrostatic shock damage, film layer fracture, or even peeling and packaging failure in the special-shaped region CC.

[0059] The dummy scan unit 240 is a virtual-designed scan unit. At least part of the structure of the dummy scan unit 240 can be similar or exactly the same as the corresponding structure of the scan unit 230, but the dummy scan unit 240 does not have to have the functions of the scan unit 230. That is, the dummy scan unit 240 does not have to be connected to any signal, nor does it need to generate or output a scan signal or other signals. Refer to Figure 4 , the technical solution of the embodiment of the present invention solves the problem of uneven etching in the special-shaped region CC by arranging at least one dummy scan unit 240 between the scan units 230 of two adjacent special-shaped regions CC, thereby filling the position where the scan unit 230 is not provided in the special-shaped region CC, improving the reliability and yield of the display panel.

[0060] Due to the existence of the irregular region CC, the number of sub-pixels P connected to each first driving signal line 210 and / or second driving signal line 220 is not exactly the same, resulting in the loads of each first driving signal line 210 and / or second driving signal line 220 not being exactly the same. For example, the number of sub-pixels connected to the first driving signal line 210_1 is greater than the number of sub-pixels connected to the first driving signal line 210_2, so the load of the first driving signal line 210_1 is greater than the load of the first driving signal line 210_2; for another example, the number of sub-pixels connected to the second driving signal line 220_1 is less than the number of sub-pixels connected to the second driving signal line 220_2, so the load of the second driving signal line 220_1 is less than the load of the second driving signal line 220_2.

[0061] The technical solution of the embodiment of the present invention is to reuse at least part of the structure of at least one dummy scanning unit 240 in the irregular region CC as a compensation load. The compensation load includes, for example, at least one capacitor unit and / or at least one resistor unit. The capacitor unit may include several capacitor elements connected in series or in parallel, and the resistor unit may include several resistor elements connected in series or in parallel. The compensation load is connected to the first driving signal line 210 that needs load compensation or the second driving signal line 220 that needs load compensation, that is, the compensation load is connected in series on the first driving signal line 210 or the second driving signal line 220 that needs load compensation, so that the compensation load compensates for the load of the connected first driving signal line 210 or the connected second driving signal line 220, thereby reducing the load difference of each first driving signal line 210 or the load difference of each second driving signal line 220, and improving the brightness uniformity of the display. At the same time, the technical solution of this embodiment is to reuse at least part of the structure of the dummy scanning unit 240 located between two adjacent scanning units 230 as a compensation load, thus avoiding the additional setting of an independent compensation unit between the scanning unit 230 and the display area AA, thereby not occupying the screen border additionally, reducing the width of the border, and making the border narrower. The technical solution of the embodiment of the present invention compared with Figure 2 the related technology shown can narrow the border by at least 200 to 300 μm.

[0062] Each signal line, scanning unit 230, and dummy scanning unit 240 of the display panel are composed of multiple metal layers with different patterns stacked on the substrate, combined with multiple insulating layers. Figure 5 is Figure 4 a top view structural schematic diagram of adjacent scanning units and dummy scanning units shown, Figure 5 in which part of the structure of the dummy scanning unit 240_1 shown is reused as a compensation load 250, Figure 6 is Figure 5Schematic cross-sectional structure diagram along the section line QQ’ Figure 5 not all of the insulating layers are shown. In combination with Figure 5 and Figure 6 , on the basis of the above embodiments, optionally, the display panel includes a semiconductor layer 310, a first metal layer 330, a second metal layer 350, and a third metal layer 370 that are sequentially stacked from bottom to top. Insulating layers are provided between the semiconductor layer 310 and each metal layer; the third metal layer 370 corresponding to the compensation load 250 is integrally formed.

[0063] Specifically, the first driving signal line 210 and the second driving signal line 220 may be located in the third metal layer 370 corresponding to the display area AA. The scanning unit 230 may include a plurality of thin film transistors (TFTs) and a plurality of coupling elements; for example, in the scanning unit 230_1, the channel of the thin film transistor is located in the semiconductor layer 310 corresponding to the scanning unit 230_1, the gate of the thin film transistor is located in the first metal layer 330 corresponding to the scanning unit 230_1, the source / drain of the thin film transistor is located in the third metal layer 370 corresponding to the scanning unit 230_1, and the electrodes of the coupling elements are located in the first metal layer 330 and the second metal layer 350 corresponding to the scanning unit 230_1( Figure 6 the second metal layer 350 corresponding to the scanning unit 230_1 is not shown). The dummy scanning unit 240 may also include a plurality of thin film transistors and a plurality of coupling elements; in the dummy scanning unit 240, the semiconductor layer of the thin film transistor is located in the semiconductor layer 310 corresponding to the dummy scanning unit 240, the gate of the thin film transistor is located in the second metal layer 350 corresponding to the dummy scanning unit 240, the source / drain of the thin film transistor is located in the third metal layer 370 corresponding to the dummy scanning unit 240, and the electrodes of the coupling elements are located in the second metal layer 350 and the third metal layer 370 corresponding to the dummy scanning unit 240.

[0064] The material of each metal layer can be molybdenum (Mo). The substrate of the semiconductor layer 310 can be polysilicon. Before forming the first metal layer 330, the semiconductor layer 310 is lightly doped and thus exhibits a high-resistance state. Since the gate of the thin-film transistor in the scan unit 230_1 is located in the first metal layer 330 corresponding to the scan unit 230_1, and the source / drain is located in the third metal layer 370 corresponding to the scan unit 230_1, in order to reduce the impedance of the source / drain of the thin-film transistor in the scan unit 230_1, after forming the first metal layer 330, the semiconductor layer 310 is heavily doped so that the semiconductor layer 310 has high conductivity. Among them, during the process of heavily doping the semiconductor layer 310, the semiconductor layer 310 self-aligned with the first metal layer 330 in the scan unit 230_1 will not be heavily doped due to the blocking effect of the first metal layer 330, while the dummy scan unit 240 generally does not have the first metal layer 330, so the semiconductor layer 310 in the dummy scan unit 240 will be heavily doped. However, since the thin-film transistor in the dummy scan unit 240 can only have the frame structure of the thin-film transistor and does not have to have the performance and characteristics of the thin-film transistor, the heavy doping of the semiconductor layer 310 in the dummy scan unit 240 is not a problem.

[0065] Based on this, the third metal layer 370 corresponding to the compensation load 250 is provided as an integral molding, that is, the third metal layer 370 in the structure of the dummy scan unit 240 that is reused as the compensation load 250 is integrally molded to form a whole planar metal layer. This setting is essentially the second metal layer 350 in the dummy scan unit 240, which can form two electrodes of a capacitive element with the integrally molded third metal layer 370, thereby implementing an implementation scheme with a capacitive element as the compensation load; at the same time, since the semiconductor layer 310 in the dummy scan unit 240 is heavily doped, it can form two electrodes of a capacitive element with the integrally molded third metal layer 370 or with the second metal layer 350, and also implements an implementation scheme with a capacitive element as the compensation load. The embodiment of the present invention thus realizes that at least part of the semiconductor layer 310, at least part of the second metal layer 350, and at least part of the third metal layer 370 corresponding to the dummy scan unit 240 form a capacitive unit.

[0066] On the basis of the above technical solution, as an implementation manner of the present invention, optionally, the second metal layer 350 corresponding to the capacitive unit is connected to the first driving signal line 210 or the second driving signal line 220, and both the semiconductor layer 310 and the third metal layer 370 corresponding to the capacitive unit are connected to a constant voltage.

[0067] Specifically, for the case where the second metal layer 350 and the integrally formed third metal layer 370 in the dummy scan unit 240 form two electrodes of a capacitive element (for example, the first capacitive element), and the second metal layer 350 and the semiconductor layer 310 corresponding to the integrally formed third metal layer 370 in the dummy scan unit 240 form two electrodes of a capacitive element (for example, the second capacitive element), the second metal layer 350 in the dummy scan unit 240 is the common electrode of the first capacitive element and the second capacitive element. In view of this, the second metal layer 350 in the dummy scan unit 240 can be connected to the first driving signal line 210 that needs load compensation or the second driving signal line 220 that needs load compensation, while the integrally formed third metal layer 370 and the semiconductor layer 310 corresponding to the integrally formed third metal layer 370 are both connected to a constant voltage, so as to achieve load compensation for the first driving signal line 210 or the second driving signal line 220.

[0068] As another embodiment of the present invention, optionally, the display panel includes a power supply line; the power supply line extends from the peripheral area NA to the display area AA; the second metal layer 350 corresponding to the capacitive unit is connected to the first driving signal line 210 or the second driving signal line 220, and the semiconductor layer 310 and the third metal layer 370 corresponding to the capacitive unit are both connected to the power supply line. Wherein, the power supply line is used to provide a higher power supply voltage ELVDD and a lower power supply voltage ELVSS to the pixel circuit, so that the semiconductor layer 310 and the third metal layer 370 corresponding to the capacitive unit are connected to the higher power supply voltage ELVDD or the lower power supply voltage ELVSS, which can avoid additionally providing a constant voltage to the capacitive unit, thereby reducing the cost of the display panel.

[0069] Based on the above technical solution, in combination with Figure 5 and Figure 6 , optionally, the scan power supply 230 includes a thin film transistor, the third metal layer 370 corresponding to the scan unit 230 includes the source and drain of the thin film transistor, and the source and drain are respectively connected to the semiconductor layer 310 corresponding to the scan unit 230 through vias 380; the third metal layer 370 corresponding to the compensation load is connected to the semiconductor layer 310 corresponding to the compensation load through vias 380.

[0070] Specifically, the source and drain in the scanning unit 230 are insulated from each other and are respectively connected to the semiconductor layer 310 in the scanning unit 230 through vias 380, thereby forming corresponding thin film transistors. The third metal layer 370 corresponding to the compensation load 250 is also connected to the semiconductor layer 310 corresponding to the compensation load 250 through vias 380. Thus, vias 380 are provided in both the scanning unit 230 and the compensation load 250, that is, the same semiconductor layer 310 design and via 380 design as in the scanning unit 230 are retained in the compensation load 250. Such a setting is beneficial to the consistency of the surrounding environment of the scanning unit 230, and further beneficial to the hydrogenation treatment of the thin film transistors in the scanning unit 230, making the electrical properties of the thin film transistors in the scanning unit 230 consistent.

[0071] Figure 7 is Figure 5 A schematic structural diagram of a second metal layer of the compensation load 250 as shown. Figure 8 is Figure 5 A schematic structural diagram of another second metal layer of the compensation load 250 as shown. Figure 7 and Figure 8 also show the semiconductor layer and part of the insulating layer. Combining Figure 7 with Figure 8 , on the basis of the above technical solution, optionally, the second metal layer 350 corresponding to the compensation load 250 includes a strip-shaped electrode 351 and / or a harpoon-shaped electrode 352.

[0072] Specifically, the third metal layer 370 corresponding to the compensation load 250 is integrally formed. When the second metal layer 350 corresponding to the compensation load 250 includes strip electrodes 351, one strip electrode 351 and the integrally formed third metal layer 370 can form a capacitive element, implementing an embodiment in which the capacitive element is used as the compensation load 250. When the third metal layer 370 corresponding to the compensation load 250 is integrally formed and the second metal layer 350 corresponding to the compensation load 250 includes harpoon-shaped electrodes 352, one harpoon-shaped electrode 352 and the integrally formed third metal layer 370 can also form a capacitive element, also implementing an embodiment in which a capacitive element is used as the compensation load 250. The difference is that the harpoon-shaped electrode 352 is substantially formed by connecting multiple strip electrodes 351. Therefore, the capacitance value of the capacitive element formed by one strip electrode 351 and the third metal layer 370 is smaller than the capacitance value of the capacitive element formed by one harpoon-shaped electrode 352 and the third metal layer 370. Thus, when the load to be compensated by the first driving signal line 210 or the second driving signal line 220 is small, the capacitive element formed by one strip electrode 351 and the third metal layer 370 can be connected to achieve small load compensation. When the load to be compensated by the first driving signal line 210 or the second driving signal line 220 is large, the capacitive element formed by one harpoon-shaped electrode 352 and the third metal layer 370 can be connected to achieve large load compensation.

[0073] Based on the above embodiments, optionally, the number of thin film transistors in one scanning unit 230 is greater than or equal to the number of thin film transistors in one dummy scanning unit 240.

[0074] Specifically, when a part of the structure of the dummy scanning unit 240 is reused as a compensation load, the number of thin film transistors in the dummy scanning unit 240 is generally smaller than the number of thin film transistors in the scanning unit 230. Among them, if the first driving signal line 210 or the second driving signal line 220 requires a compensation load with a large compensation effect, more or even all of the structure of the dummy scanning unit 240 can be reused as the compensation load. If the first driving signal line 210 or the second driving signal line 220 requires a compensation load with a small compensation effect, less structure of the dummy scanning unit 240 can be reused as the compensation load. This embodiment does not limit this and can be set according to actual needs.

[0075] When the structure of the dummy scan unit 240 is not reused as a compensation load, the structure of the dummy scan unit 240 can be exactly the same as that of the scan unit 230, so that the number of thin film transistors in the dummy scan unit 240 is equal to the number of thin film transistors in the scan unit 230 (the number of coupling elements can also be equal); when the structure of the dummy scan unit 240 is not reused as a compensation load, the number of thin film transistors in the dummy scan unit 240 can also be less than the number of thin film transistors in the scan unit 230.

[0076] Figure 9 is a schematic structural diagram of a scan unit 230 provided by an embodiment of the present invention. Combining Figure 5 with Figure 9 , as an embodiment of the present invention, optionally, the scan unit 230 includes: an input transistor T1, an output control transistor T2, a first output transistor T3, a first output capacitor C1, a second output transistor T4, a second output capacitor C2, a voltage dividing transistor T5, a sixth transistor T6, a seventh transistor T8, and an eighth transistor T8;

[0077] The first pole of the input transistor T1 is connected to the start signal In, and the gate is connected to the first clock signal SCK1; the second plate of the second output capacitor C2 serves as the output terminal of the scan unit 230;

[0078] The gate of the output control transistor T2 is connected to the second pole of the input transistor T1 and is connected to the second pole of the voltage dividing transistor T5 through a connection line. The first pole of the output control transistor T2 is connected to the first clock signal SCK1, and the second pole of the output control transistor T2 is connected to the gate of the first output transistor T3 and the first plate of the first output capacitor C1;

[0079] The first pole of the first output transistor T3 is connected to the second plate of the first output capacitor C1 and is connected to the second potential signal VGH; the second pole of the first output transistor T3 is connected to the second plate of the second output capacitor C2 and the second pole of the second output transistor T4;

[0080] The gate of the second output transistor T4 is connected to the first plate of the second output capacitor C2 and the first pole of the voltage dividing transistor T5. The first pole of the second output transistor T4 is connected to the second clock signal SCK2; the gate of the voltage dividing transistor T5 is connected to the first potential signal VGL;

[0081] The first pole of the sixth transistor T6 is connected to the second pole of the input transistor T1. The second pole of the sixth transistor T6 is connected to the first pole of the seventh transistor T7. The gate of the sixth transistor T6 is connected to the second clock signal SCK2;

[0082] The second pole of the seventh transistor T7 is connected to the second potential signal VGH, and the gate of the seventh transistor T7 is connected to the second pole of the output control transistor T2;

[0083] The first pole of the eighth transistor T8 is connected to the second pole of the output control transistor T2, the second pole of the eighth transistor T8 is connected to the first potential signal VGL, and the gate of the eighth transistor T8 is connected to the first clock signal SCK1;

[0084] Among them, the first clock signal SCK1 is provided by the first clock signal line 430, the second clock signal SCK2 is provided by the second clock signal line 440, the first potential signal VGL is provided by the first potential signal line 410, and the second potential signal VGH is provided by the first potential signal line 420.

[0085] Based on the above technical solution, optionally, in the direction perpendicular to the plane of the display panel (i.e., in the direction perpendicular to the xy plane), the structure of the dummy scan unit 240 except for the compensation load is the same as the corresponding structure of the scan unit 230. Refer to Figure 5 , as an embodiment of the present invention, optionally, the dummy scan unit 240 includes:

[0086] A dummy input transistor N1, a dummy output control transistor N2, a dummy first output transistor N3, a dummy first output capacitor C3, a dummy second output transistor N4, a dummy second output capacitor C4, a dummy voltage dividing transistor N5, a dummy sixth transistor N6, a dummy seventh transistor N7, and a dummy eighth transistor N8;

[0087] The first pole and the gate of the dummy input transistor N1 are floating;

[0088] The second plate of the dummy second output capacitor C4 serves as the output terminal of the dummy scan unit 240;

[0089] The gate of the dummy output control transistor N2 is connected to the second pole of the dummy input transistor N1 and is connected to the second pole of the dummy voltage dividing transistor N5 through a connection line. The first pole of the dummy output control transistor N2 is floating, and the second pole of the dummy output control transistor N2 is connected to the gate of the dummy first output transistor N3 and the first plate of the dummy first output capacitor C3;

[0090] The first pole of the dummy first output transistor N3 is connected to the second plate of the dummy first output capacitor C3, and the second pole of the dummy first output transistor N3 is connected to the second plate of the dummy second output capacitor C4 and the second pole of the dummy second output transistor N4;

[0091] The gate of the dummy second output transistor N4 is connected to the first plate of the dummy second output capacitor C4 and the first pole of the dummy voltage dividing transistor N5, and the first pole of the dummy second output transistor N4 is floating; the gate of the dummy voltage dividing transistor N5 is floating;

[0092] The first pole of the dummy sixth transistor N6 is connected to the second pole of the input transistor T1, the second pole of the dummy sixth transistor N6 is connected to the first pole of the dummy seventh transistor N7, and the gate of the dummy sixth transistor N6 is floating;

[0093] The second pole of the dummy seventh transistor N7 is floating, and the gate of the dummy seventh transistor N7 is connected to the second pole of the output control transistor T2;

[0094] The first pole of the dummy eighth transistor N8 is connected to the second pole of the output control transistor T2, the second pole of the dummy eighth transistor N8 is floating, and the gate of the dummy eighth transistor N8 is floating.

[0095] Among them, the sizes of the general first output transistor T3 and the second output transistor T4 are larger than those of other thin film transistors. Thus, the sizes of the dummy first output transistor N3 and the dummy second output transistor N4 are also larger than those of other dummy thin film transistors. Therefore, by connecting the source and drain of the dummy first output transistor N3 and connecting the source and drain of the dummy second output transistor N4, the first part of the structure of the compensation load with a larger compensation effect can be formed; and the gates of the dummy first output transistor N3 and the dummy second output transistor N4 can form the second part of the structure of the compensation load with a larger compensation effect. The dummy first output capacitor C3 and the dummy second output capacitor C4 are both disposed between the first metal layer 330 and the second metal layer 350; and in order to obtain a compensation load 250 with a larger capacitance value, the second metal layer 350 of the compensation load 250 can be connected to the second metal layers 350 corresponding to the dummy first output capacitor C3 and the dummy second output capacitor C4.

[0096] Based on the above technical solution, optionally, in combination with Figure 5 and Figure 6 , the display panel further includes a first insulating layer 320, a second insulating layer 340, and a third insulating layer 360; the first insulating layer 320 corresponding to the scanning unit 230 is located between the semiconductor layer 310 corresponding to the scanning unit 230 and the first metal layer 330, the second insulating layer 340 corresponding to the scanning unit 230 is located between the first metal layer 330 corresponding to the scanning unit 230 and the second metal layer 350, and the third insulating layer 360 corresponding to the scanning unit 230 is located between the second metal layer 350 corresponding to the scanning unit 230 and the third metal layer 370;

[0097] The first insulating layer 320 and the second insulating layer 340 corresponding to the dummy scanning unit 240 are located between the semiconductor layer 310 and the second metal layer 350 corresponding to the dummy scanning unit 240, and the third insulating layer 360 corresponding to the dummy scanning unit 240 is located between the second metal layer 350 and the third metal layer 370 corresponding to the dummy scanning unit 240.

[0098] Figure 10 It is a top view structural schematic diagram of a display device provided by an embodiment of the present invention. Refer to Figure 10 Moreover, an embodiment of the present invention further provides a display device, which includes the display panel described in any of the above technical solutions. Among them, the number of sub-pixels connected to at least two of the plurality of first driving signal lines 210 is different, and / or the number of sub-pixels connected to at least two of the plurality of second driving signal lines 220 is different. The display device and the display panel provided by the embodiment of the present invention belong to the same inventive concept and can achieve the same technical effects. The repeated content will not be elaborated here.

[0099] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A display panel, characterized in that, Comprising: A display area and a peripheral area located outside the display area, the peripheral area including at least one special-shaped area; A plurality of first driving signal lines and a plurality of second driving signal lines, both the first driving signal lines and the second driving signal lines extend from the peripheral area to the display area, and the first driving signal lines and the second driving signal lines are cross-arranged in the display area; A plurality of scanning units, located in the peripheral area, the output ends of the scanning units are connected to the first driving signal lines to output scanning signals to the first driving signal lines; A plurality of dummy scanning units, located in the special-shaped area, and at least one of the dummy scanning units is arranged between two of the scanning units; at least part of the structure of at least one of the dummy scanning units is reused as a compensation load, the compensation load is connected to the first driving signal line or the second driving signal line, and compensates the load of the connected first driving signal line or the connected second driving signal line.

2. The display panel according to claim 1, wherein The display panel includes: a semiconductor layer, a first metal layer, a second metal layer, and a third metal layer which are sequentially stacked; The third metal layer corresponding to the compensation load is integrally formed.

3. The display panel according to claim 2, wherein The second metal layer corresponding to the compensation load includes strip-shaped electrodes and / or harpoon-shaped electrodes.

4. The display panel according to any one of claims 2 or 3, characterized in that, The compensation load includes: a capacitor unit; At least part of the semiconductor layer, at least part of the second metal layer, and at least part of the third metal layer corresponding to the dummy scanning unit form the capacitor unit.

5. The display panel according to claim 4, wherein The second metal layer corresponding to the capacitor unit is connected to the first driving signal line or the second driving signal line, and the semiconductor layer and the third metal layer corresponding to the capacitor unit are both connected to a constant voltage.

6. The display panel according to claim 5, characterized in that, The display panel includes: a power supply line; the power supply line extends from the peripheral area to the display area, and the semiconductor layer and the third metal layer corresponding to the capacitor unit are both connected to the power supply line.

7. The display panel according to claim 2, wherein The scanning unit includes a thin film transistor; The third metal layer corresponding to the scanning unit includes the source electrode and the drain electrode of the thin film transistor, and the source electrode and the drain electrode are respectively connected to the semiconductor layer corresponding to the scanning unit through vias; The third metal layer corresponding to the compensation load is connected to the semiconductor layer corresponding to the compensation load through a via.

8. The display panel according to claim 1, wherein, In a direction perpendicular to the plane where the display panel is located, the structure of the dummy scanning unit except for the compensation load is the same as the corresponding structure of the scanning unit.

9. The display panel according to claim 8, wherein Both the scanning unit and the dummy scanning unit include a plurality of thin film transistors, and the number of thin film transistors in one scanning unit is greater than or equal to the number of thin film transistors in one dummy scanning unit.

10. The display panel according to claim 1 or 8, characterized in that, The dummy scanning unit includes: a dummy input transistor, a dummy output control transistor, a dummy first output transistor, a dummy first output capacitor, a dummy second output transistor, a dummy second output capacitor, and a dummy voltage dividing transistor; The first pole and the gate of the dummy input transistor are floating; The second electrode plate of the dummy second output capacitor serves as the output terminal of the dummy scan unit; The gate of the dummy output control transistor is connected to the second electrode of the dummy input transistor and is connected to the second electrode of the dummy voltage dividing transistor through a connection line. The first electrode of the dummy output control transistor is floating, and the second electrode of the dummy output control transistor is connected to the gate of the dummy first output transistor and the first electrode plate of the dummy first output capacitor; The first electrode of the dummy first output transistor is connected to the second electrode plate of the dummy first output capacitor, and the second electrode of the dummy first output transistor is connected to the second electrode plate of the dummy second output capacitor and the second electrode of the dummy second output transistor; The gate of the dummy second output transistor is connected to the first electrode plate of the second output capacitor and the first electrode of the dummy voltage dividing transistor. The first electrode of the dummy second output transistor is floating; the gate of the dummy voltage dividing transistor is floating; Wherein, the source and drain of the dummy first output transistor are connected, and the source and drain of the dummy second output transistor are connected, serving as the first partial structure of the compensation load; the gates of the dummy first output transistor and the dummy second output transistor serve as the second partial structure of the compensation load.

11. The display panel according to claim 2, wherein The display panel further includes a first insulating layer, a second insulating layer, and a third insulating layer; The first insulating layer corresponding to the scan unit is located between the semiconductor layer corresponding to the scan unit and the first metal layer. The second insulating layer corresponding to the scan unit is located between the first metal layer corresponding to the scan unit and the second metal layer. The third insulating layer corresponding to the scan unit is located between the second metal layer corresponding to the scan unit and the third metal layer; The first insulating layer and the second insulating layer corresponding to the dummy scan unit are located between the semiconductor layer corresponding to the dummy scan unit and the second metal layer. The third insulating layer corresponding to the dummy scan unit is located between the second metal layer corresponding to the dummy scan unit and the third metal layer.

12. A display device, characterized in that, A display panel according to any one of claims 1-11; wherein, a plurality of sub-pixels arranged in an array are disposed in the display area of the display panel, and the number of sub-pixels connected to at least two of the first driving signal lines among the plurality of first driving signal lines is different, and / or the number of sub-pixels connected to at least two of the second driving signal lines among the plurality of second driving signal lines is different.

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