An automatic control circuit based on magnetic tunnel junction and electronic equipment

Abstract

The application discloses an automatic control circuit based on a magnetic tunnel junction and electronic equipment, comprising: a core write-in module, comprising two write-in branches, each write-in branch comprising a magnetic tunnel junction; a write-in detection module, used for receiving a delay signal after delay processing, and generating a target detection signal in the case that the magnetic tunnel junction in the target branch is in a write-in completion state according to the delay signal; an enable control module, used for receiving a write-in enable signal sent by an external, a write-in signal and the target detection signal sent by the write-in detection module, and generating a target control signal for controlling the target branch to close the write-in state according to the write-in enable signal, the write-in signal and the target detection signal, so that the core write-in module closes the write-in of the target branch according to the target control signal. In the embodiment of the application, the problem of waste of magnetic tunnel junction power consumption can be solved by detecting the core write-in module, and the protection of the magnetic tunnel junction device is realized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an automatic control circuit and electronic device based on a magnetic tunnel junction. Background Technology

[0002] With the development of science and technology, people have placed higher demands on the performance of electronic devices such as mobile phones, computers, and tablets.

[0003] In the traditional von Neumann architecture, the memory module and processor module are set up separately, so the limited data bandwidth and increased power consumption are the main reasons affecting the efficiency of integrated circuits. In order to alleviate the problems caused by the traditional von Neumann architecture, memory logic structure has been gradually applied to integrated circuits. The most important feature of this structure is that it embeds computing power into memory and uses a pair of complementary magnetic tunnel junctions to store one bit of data.

[0004] However, since the write operation of the magnetic tunnel junction in the memory logic structure is random, the write current flow time of the traditional write circuit is much longer than the average switching time of the magnetic tunnel junction. This means that even after the magnetic tunnel junction has finished switching, the write current will still flow through the magnetic tunnel junction for a period of time, which results in a certain amount of energy waste. As a result, the memory logic structure will consume most of its power. In addition, the continuous flow of the write circuit will also cause wear and tear on the magnetic tunnel junction device. Summary of the Invention

[0005] The present invention aims to at least solve one of the technical problems existing in the prior art, and provide an automatic control circuit and electronic device based on a magnetic tunnel junction, which can solve the problem of power consumption waste in magnetic tunnel junctions and achieve protection of magnetic tunnel junction devices.

[0006] In a first aspect, the present invention provides an automatic control circuit based on a magnetic tunnel junction, comprising:

[0007] The core write module includes two write branches, each of which includes a magnetic tunnel junction;

[0008] A write detection module is connected to the core write module. The write detection module is used to receive a delayed signal after delay processing, and generate a target detection signal when the magnetic tunnel junction in the target branch is detected to be in a write-complete state according to the delayed signal. The target branch is at least one of the write branches.

[0009] An enabling control module is connected with the write detection module and the core write module respectively, and is used for receiving a write enabling signal and a write signal sent by an external device and a target detection signal sent by the write detection module, generating a target control signal for controlling the write-off state of the target branch according to the write enabling signal, the write signal and the detection signal, and sending the target control signal to the core write module so that the core write module turns off the write of the target branch according to the target control signal.

[0010] The automatic control circuit based on the magnetic tunnel junction has at least the following beneficial effects: the write detection module is started by receiving the delay signal processed by the delay, so that the write detection module detects the write state of the magnetic tunnel junction in the target branch, and generates the target detection signal when the magnetic tunnel junction in the target branch is in the write-off state, which facilitates the subsequent write-off of the target branch, and the target detection information is sent to the enabling control module, so that the enabling control module generates the target control signal for controlling the write-off state of the target branch according to the target detection information and the write enabling signal and the write signal sent by the external device, and sends the target control signal to the core write module, so as to realize the write-off of the target branch in the core write module. Therefore, the core write module is detected by the write detection module, and the write-off of the target branch is realized when the magnetic tunnel junction in the target branch is in the write-off state, so as to solve the problem of waste of magnetic tunnel junction power consumption and realize the protection of the magnetic tunnel junction device.

[0011] According to some embodiments of the present application, the automatic control circuit further comprises a delay module connected with the write detection module, which is used for delaying the write enabling signal to generate the delay signal and sending the delay signal to the write detection module, so as to facilitate the subsequent start of the domino logic unit, and the delay of the write enabling signal makes the voltage stable when the core write module is detected, so as to facilitate the detection of the state of the magnetic tunnel junction.

[0012] According to some embodiments of the present application, the core write module comprises a shared bus for controlling the write branch, the write branch comprises a first branch and a second branch, the first branch and the second branch are connected to the shared bus respectively, and the first branch is connected with the write detection module and the enabling control module respectively, the second branch is connected with the write detection module and the enabling control module respectively, and the shared bus is connected with the enabling control module, so as to realize the write-off of different branches, and the write-off of the shared bus is realized after the write-off of the two branches, thereby realizing the protection of the magnetic tunnel junction circuit.

[0013] According to some embodiments of the present application, the write detection module comprises a domino logic unit, the target detection signal comprises a first detection signal and a second detection signal, the domino logic unit is connected with the core write module and the enable control module respectively, the domino logic unit is configured to receive the delay signal and detect the write state of the first branch and the write state of the second branch, and generate the first detection signal and the second detection signal, wherein the first detection signal is used to represent that the first branch is in a write completion state, and the second detection signal is used to represent that the second branch is in a write completion state, so as to realize accurate detection of the write state of the first branch and the second branch.

[0014] According to some embodiments of the present application, the enable control module comprises a first control unit and a second control unit, and a bus control unit configured to receive the write enable signal and the write signal, the first control unit is connected with the first branch and the domino logic unit respectively to generate the target control signal according to the received first detection signal, the second control unit is connected with the second branch and the domino logic unit respectively to generate the target control signal according to the received second detection signal, and the bus control unit is connected with the shared bus, the first branch is controlled by the first control unit, and the second branch is controlled by the second control unit, so as to realize accurate control of the core write module.

[0015] According to some embodiments of the present application, the target control signal comprises a first control signal, a second control signal and a bus control signal, the first control unit is configured to generate the first control signal for controlling the first branch to close write according to the first detection signal, the second control unit is configured to generate the second control signal for controlling the second branch to close write according to the second detection signal, and the bus control unit is configured to generate the bus control signal for controlling the shared bus to close write according to the write signal and the write enable signal, so as to reduce the waste of write energy.

[0016] According to some embodiments of the present application, the first branch comprises a first PMOS tube, a first NMOS tube and a first magnetic tunnel junction, the drain of the first PMOS tube is connected with the drain of the first NMOS tube, the gates of the first PMOS tube and the first NMOS tube are connected with the first control unit respectively, the connection of the first PMOS tube and the first NMOS tube is connected with the first magnetic tunnel junction and the domino logic unit, one end of the first magnetic tunnel junction is connected with the connection of the first PMOS tube and the first NMOS tube, and the other end of the first magnetic tunnel junction is connected with the shared bus, so as to realize the transition of the write state of the first branch, and thus realize the opening or closing of the first branch.

[0017] According to some embodiments of the present application, the second branch includes a second PMOS transistor, a second NMOS transistor, and a second magnetic tunnel junction, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second PMOS transistor and the gate of the second NMOS transistor are connected to the second control unit respectively, the connection of the second PMOS transistor and the second NMOS transistor is connected to the second magnetic tunnel junction and the domino logic unit, one end of the second magnetic tunnel junction is connected to the connection of the second PMOS transistor and the second NMOS transistor, and the other end of the second magnetic tunnel junction is connected to the shared bus, so as to realize the transition of the write state of the second branch, thereby realizing the opening or closing of the second branch.

[0018] According to some embodiments of the present application, the shared bus includes a third PMOS transistor and a third NMOS transistor, the drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third PMOS transistor and the gate of the third NMOS transistor are connected to the bus control unit respectively, and the connection of the third PMOS transistor and the third NMOS transistor is connected in parallel between the first branch and the second branch, so as to realize the transition of the write state of the shared bus, thereby realizing the opening or closing of the first branch and the second branch.

[0019] In a second aspect, an embodiment of the present application provides an electronic device including the automatic control circuit based on the magnetic tunnel junction as described in the first aspect.

[0020] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or can be learned by practice of the present application. The objects and other advantages of the present application will be realized and achieved by means of the structures particularly pointed out in the description and appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the technical solutions of the present application, and constitute a part of the specification, and are used together with the embodiments of the present application to explain the technical solutions of the present application, and do not constitute a limitation on the technical solutions of the present application.

[0022] Figure 1 is a whole schematic diagram of the automatic control circuit based on the magnetic tunnel junction provided by an embodiment of the present application;

[0023] Figure 2 is a circuit schematic diagram of the automatic control circuit based on the magnetic tunnel junction provided by an embodiment of the present application;

[0024] Figure 3 is a circuit schematic diagram of the write detection module provided by an embodiment of the present application;

[0025] Figure 4is a circuit schematic diagram of the enabling control module provided by an embodiment of the present application;

[0026] Figure 5 is a circuit schematic diagram of the core writing module provided by an embodiment of the present application;

[0027] Figure 6 is a structural schematic diagram of the electronic device provided by an embodiment of the present application;

[0028] Figure 7 is a waveform diagram of the automatic control circuit based on the magnetic tunnel junction provided by a specific example of the present application. DETAILED DESCRIPTION

[0029] In order to make the objects, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0030] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, in which the same or similar reference signs represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and should not be understood as limiting the present application.

[0031] In the description of the present application, one or more is meant to be one or more, and more than two is meant to be two or more. Greater than, less than, more than, etc. are understood to not include the number itself. Above, below, within, etc. are understood to include the number itself. If it is described as first, second, etc., it is only used for the purpose of distinguishing technical features, and should not be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or the sequence of indicated technical features.

[0032] In the description of the present application, if it is described as first, second, etc., it is only used for the purpose of distinguishing technical features, and should not be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features or the sequence of indicated technical features.

[0033] In the description of the present application, unless otherwise explicitly limited, the words such as setting, installing, connecting, etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meaning of the above words in the present application in combination with the specific content of the technical solution.

[0034] The embodiments of the present application are further described below with reference to the accompanying drawings.

[0035] Reference Figures 1-2 , Figure 1It is the overall schematic diagram of the automatic control circuit based on magnetic tunnel junction provided by an embodiment of the application;

[0036] In an embodiment, the automatic control circuit based on magnetic tunnel junction comprises: a core write-in module 100 including two write-in branches, each write-in branch including a magnetic tunnel junction; a write-in detection module 200 connected with the core write-in module 100, the write-in detection module 200 being configured to receive a delay signal processed by delay, and generate a target detection signal in the case that the magnetic tunnel junction in a target branch is detected to be in a write-in completion state according to the delay signal, wherein the target branch is at least one write-in branch; an enable control module 300 connected with the write-in detection module 200 and the core write-in module 100 respectively, the enable control module 300 being configured to receive a write-in enable signal sent by an external device, a write-in signal and a detection signal sent by the write-in detection module 200, and generate a target control signal for controlling the target branch to close the write-in state according to the write-in enable signal, the write-in signal and the detection signal, and send the target control signal to the core write-in module 100, so that the core write-in module 100 closes the write-in of the target branch according to the target control signal.

[0037] Reference Figure 2 , Figure 2 It is the circuit schematic diagram of the automatic control circuit based on magnetic tunnel junction provided by an embodiment of the application;

[0038] In an embodiment, the write-in detection module 200 is started by receiving a delay signal processed by delay, so that the write-in detection module 200 detects the write-in state of the magnetic tunnel junction in the target branch, and generates a target detection signal in the case that the magnetic tunnel junction in the target branch is detected to be in a write-in completion state, so as to facilitate the subsequent closing of the target branch, and send the target detection information to the enable control module 300, so that the enable control module 300 generates a target control signal for controlling the target branch to close the write-in state according to the target detection information and the write-in enable signal and the write-in signal sent by the external device, and sends the target control signal to the core write-in module 100, so as to close the target branch in the core write-in module 100, thus the core write-in module 100 is detected by the write-in detection module 200, and the write-in of the target branch is closed in the case that the magnetic tunnel junction in the target branch is detected to be in a write-in completion state, so as to solve the problem of waste of magnetic tunnel junction power consumption, and realize the protection of the magnetic tunnel junction device.

[0039] It should be noted that the magnetic tunnel junction in the embodiment is a magnetic resistance of a three-layer structure composed of two ferromagnetic layers and an oxide barrier layer between the two ferromagnetic layers, and since the magnetization direction of the fixed layer of the magnetic tunnel junction is fixed and the magnetization direction of the free layer is variable, when the magnetization direction of the free layer is parallel to the fixed layer, the magnetic tunnel junction exhibits a low resistance state, which is defined as "0", and when the magnetization direction of the free layer is anti-parallel to the fixed layer, the magnetic tunnel junction exhibits a high resistance state, which is defined as "1".

[0040] It can be understood that when the state of the magnetic tunnel junction is in the open write state, a current of a specified direction needs to be added to it, and the current size exceeds the switching threshold current; when the magnetic tunnel junction is "0", a current is added from the fixed layer, and the current size exceeds the switching threshold current size, and after a preset time, the state of the magnetic tunnel junction is switched to "1", then the magnetic tunnel junction is in a write completion state; when the magnetic tunnel junction is "1", a current is added from the free layer, and the current size exceeds the switching threshold current size, and after a preset time, the state of the magnetic tunnel junction is switched to "0", then the magnetic tunnel junction is in a write completion state.

[0041] It should be noted that the state of the magnetic tunnel junction is determined by the write signal sent from the outside, for example, when the write signal is "0", the state of the magnetic tunnel junction is required to be converted to "1" and "0" respectively, and when the write signal W is "1", the state of the magnetic tunnel junction is required to be converted to "0" and "1" respectively.

[0042] Reference Figure 3 , Figure 3 is a circuit schematic diagram of a write detection module based on a magnetic tunnel junction provided by an embodiment of the application;

[0043] In an embodiment, the automatic control circuit further comprises a delay module 400, the delay module 400 is connected with the write detection module 200, the delay module 400 is used for delaying the write enable signal to generate a delay signal, and sending the delay signal to the write detection module 200, so as to facilitate subsequent start of the domino logic unit, and delaying the write enable signal so that the voltage is stable when the core write module 100 is detected, and facilitating detection of the state of the magnetic tunnel junction.

[0044] It should be noted that the delay module 400 comprises a second inverter I2, a third inverter I3 and a capacitor C, wherein one end of the second inverter I2 is used for receiving the write enable signal sent from the outside, the other end is connected with the third inverter I3, so as to output the delay signal after delay processing, and the third capacitor C is connected in parallel between the second inverter I2 and the third inverter I3, so as to delay the write enable signal from the outside and generate the delay signal, and realize delay start of the write detection module 200.

[0045] In an embodiment, the core write module 100 comprises a shared bus for controlling write branches, the write branches comprising a first branch and a second branch, the first branch and the second branch being connected to the shared bus respectively, and the first branch being connected to the write detection module 200 and the enable control module 300 respectively, the second branch being connected to the write detection module 200 and the enable control module 300 respectively, and the shared bus being connected to the enable control module 300, so that the enable control module 300 can control the write of different branches to be closed respectively, and the write of the shared bus to be closed after the write of the two branches is closed, thereby achieving the protection of the magnetic tunnel junction circuit.

[0046] Reference Figure 3 , Figure 3 is a circuit schematic diagram of the write detection module provided by an embodiment of the application;

[0047] In an embodiment, the write detection module 200 comprises a domino logic unit, the target detection signal comprises a first detection signal and a second detection signal, and the domino logic unit is connected to the core write module 100 and the enable control module 300 respectively, and is used for receiving a delay signal and detecting the write state of the first branch and the write state of the second branch to generate the first detection signal and the second detection signal, thereby achieving accurate detection of the write state of the first branch and the second branch.

[0048] It should be noted that the first detection signal is used to represent that the first branch is in a write completion state, and the second detection signal is used to represent that the second branch is in a write completion state.

[0049] In an embodiment, the domino logic unit comprises a first domino unit and a second domino unit, wherein the first domino unit comprises a first buffer B1, a second buffer B2, a fourth PMOS tube P4, a fourth NMOS tube N4, a fifth NMOS tube N5, a first NAND gate NA1 and a fourth inverter I4, one end of the first buffer B1 is connected to the first branch, and the other end is connected to the gate of the fourth NMOS tube N4, thereby facilitating the measurement of the voltage of the first branch, the source of the fourth PMOS tube P4 is connected to the drain of the fourth NMOS tube N4, the source of the fourth NMOS tube N4 is connected to the drain of the fifth NMOS tube N5, one end of the second buffer B2 is connected in parallel between the source of the fourth PMOS tube P4 and the drain of the fourth NMOS tube N4, the gate of the fifth NMOS tube N5 is connected to the delay module 400, and the other end is connected to the first NAND gate NA1, one end of the fourth inverter I4 is connected to the first NAND gate NA1, and the other end is connected to the first control unit.

[0050] It can be understood that the first domino unit is used for detecting the state change of the magnetic tunnel junction in the first branch, receiving the voltage of the first branch through the first buffer B1 to detect the state change of the magnetic tunnel junction, outputting a first voltage value, inputting the first voltage value and a write enable signal sent from outside into the first NAND gate NA1 and the fourth inverter I4, so as to generate a first detection signal for representing that the first branch is in a write completion state.

[0051] In an embodiment, the second domino unit includes a third buffer B3, a fourth buffer B4, a fifth PMOS tube P5, a fifth NMOS tube N5, a sixth NMOS tube N6, a second NAND gate NA2 and a fifth inverter I5, one end of the first inverter I1 is connected with the third buffer B3, and the other end is connected with the gate of the sixth NMOS tube N6, so as to facilitate the measurement of the voltage of the second branch, the source of the fifth PMOS tube P5 is connected with the drain of the sixth NMOS tube N6, the source of the sixth NMOS tube N6 is connected with the drain of the seventh NMOS tube, one end of the fourth buffer B4 is connected in parallel between the source of the fifth PMOS tube P5 and the drain of the sixth NMOS tube N6, the gate of the seventh NMOS tube is connected with the delay module 400, and the other end is connected with the second NAND gate NA2, one end of the fifth inverter I5 is connected with the first NAND gate NA1, and the other end is connected with the second control unit.

[0052] It can be understood that the second domino unit is used for detecting the state change of the magnetic tunnel junction in the second branch, receiving the voltage of the second branch through the third buffer B3 and the first inverter I1 to detect the state change of the magnetic tunnel junction, outputting a second voltage value, inputting the second voltage value and a write enable signal sent from outside into the second NAND gate NA2 and the fifth inverter I5, so as to generate a second detection signal.

[0053] Reference Figure 4 , Figure 4 is a circuit schematic diagram of the enable control module provided in an embodiment of the present application;

[0054] In an embodiment, the enable control module 300 includes a first control unit and a second control unit, and a bus control unit for receiving a write enable signal and a write signal, the first control unit is connected with the first branch and the domino logic unit respectively to generate a target control signal according to the received first detection signal, the second control unit is connected with the second branch and the domino logic unit respectively to generate a target control signal according to the received second detection signal, and the bus control unit is connected with a shared bus, the first branch is controlled through the first control unit, and the second branch is separately controlled through the second control unit, so as to realize the precise control of the core write module 100.

[0055] It should be noted that the first control unit includes the sixth inverter I6, the ninth inverter I9, the third NAND gate NA3 and the fourth NAND gate NA4, the third NAND gate NA3 includes a first pin, a second pin and a third pin, the fourth NAND gate NA4 includes a fourth pin, a fifth pin and a sixth pin, wherein the first pin is connected with the sixth inverter I6, the second pin is connected with the first domino unit, the third pin is connected with the first branch, the fourth pin is connected in parallel with the sixth inverter I6, the fifth pin is connected in parallel with the second pin, the sixth pin is connected with the ninth inverter I9, one end of the ninth inverter I9 is connected with the sixth pin, and the other end is connected with the first branch.

[0056] In an embodiment, the target control signal includes a first control signal, a second control signal and a bus control signal, the first control unit is configured to generate the first control signal for controlling the first branch to close the write-in according to the first detection signal, the second control unit is configured to generate the second control signal for controlling the second branch to close the write-in according to the second detection signal, and the bus control unit is configured to generate the bus control signal for controlling the shared bus to close the write-in according to the write-in signal and the write-in enable signal, thereby reducing the waste of write-in energy.

[0057] It can be understood that the first pin of the third NAND gate NA3 is configured to receive the write-in signal sent by the outside, the second pin is configured to receive the first detection signal, thereby outputting the write-in current for changing the state of the magnetic tunnel junction in the first branch, realizing the write-in of the first branch to be opened or closed, and achieving the purpose of controlling the write-in switch of the first branch.

[0058] It should be noted that the second control unit includes the seventh inverter I7, the tenth inverter I10, the fifth NAND gate NA5 and the sixth NAND gate NA6, the fifth NAND gate NA5 includes a seventh pin, an eighth pin and a ninth pin, the sixth NAND gate NA6 includes a tenth pin, an eleventh pin and a twelfth pin, wherein the seventh pin is connected with the seventh inverter I7, the eighth pin is connected with the second domino unit, the ninth pin is connected with the second branch, the tenth pin is connected in parallel with the seventh inverter I7, the eleventh pin is connected in parallel with the eighth pin, and the twelfth pin is connected with the tenth inverter I10, one end of the tenth inverter I10 is connected with the twelfth pin, and the other end is connected with the second branch.

[0059] It can be understood that the seventh pin of the fifth NAND gate NA5 is configured to receive the write-in signal sent by the outside, the eighth pin is configured to receive the second detection signal, thereby outputting the write-in current for changing the state of the magnetic tunnel junction in the second branch, realizing the write-in of the second branch to be opened or closed, and achieving the purpose of controlling the write-in switch of the second branch.

[0060] It should be noted that the bus control unit includes an eighth inverter I8, an eleventh inverter I11, a seventh NAND gate NA7 and an eighth NAND gate NA8, the seventh NAND gate NA7 includes a first shared pin, a second shared pin and a third shared pin, the eighth NAND gate NA8 includes a fourth shared pin, a fifth shared pin and a sixth shared pin, wherein the fourth shared pin is connected in parallel with the first shared pin, one end of the eighth inverter I8 is connected with the fifth shared pin, the other end is connected in parallel with the second shared pin, one end of the eleventh inverter I11 is connected with the sixth shared pin, the other end is connected with the shared bus.

[0061] It can be understood that the first shared pin and the second shared pin are used to receive the write enable signal and the write signal inputted by the outside, so as to output the bus control signal to control the opening or closing of the shared bus write state.

[0062] Reference Figure 5 , Figure 5 is a circuit schematic diagram of the core write module provided by an embodiment of the application;

[0063] In an embodiment, the first branch includes a first PMOS tube P1, a first NMOS tube N1 and a first magnetic tunnel junction MTJ0, the drain of the first PMOS tube P1 is connected with the drain of the first NMOS tube N1, the gates of the first PMOS tube P1 and the first NMOS tube N1 are connected with the first control unit respectively, the connection of the first PMOS tube P1 and the first NMOS tube N1 is connected with the first magnetic tunnel junction MTJ0 and the domino logic unit, one end of the first magnetic tunnel junction MTJ0 is connected at the connection of the first PMOS tube P1 and the first NMOS tube N1, the other end is connected with the shared bus, so as to realize the transition of the first branch write state, thereby realizing the opening or closing of the first branch.

[0064] In an embodiment, the second branch includes a second PMOS tube P2, a second NMOS tube N2 and a second magnetic tunnel junction MTJ1, the drain of the second PMOS tube P2 is connected with the drain of the second NMOS tube N2, the gates of the second PMOS tube P2 and the second NMOS tube N2 are connected with the second control unit respectively, the connection of the second PMOS tube P2 and the second NMOS tube is connected with the second magnetic tunnel junction MTJ1 and the domino logic unit, one end of the second magnetic tunnel junction MTJ1 is connected at the connection of the second PMOS tube P2 and the second NMOS tube N2, the other end is connected with the shared bus, so as to realize the transition of the second branch write state, thereby realizing the opening or closing of the second branch.

[0065] In an embodiment, the shared bus comprises a third PMOS transistor P3 and a third NMOS transistor N3, the drain of the third PMOS transistor P3 is connected with the drain of the third NMOS transistor N3, the gates of the third PMOS transistor P3 and the third NMOS transistor N3 are connected with the bus control unit respectively, and the connection of the third PMOS transistor P3 and the third NMOS transistor N3 is connected in parallel between the first branch and the second branch, so as to realize the transition of the write state of the shared bus, and thus the first branch and the second branch are turned on or turned off.

[0066] Reference Figure 6 , Figure 6 is a structural schematic diagram of an electronic device provided by an embodiment of the present application;

[0067] In addition, another embodiment of the present application further provides an electronic device comprising the automatic control circuit based on the magnetic tunnel junction as in any of the above embodiments. Therefore, the electronic device has the beneficial effects brought by the automatic control circuit based on the magnetic tunnel junction as in any of the above embodiments.

[0068] It can be understood that the electronic device in the embodiment can be a semiconductor device comprising the automatic control circuit based on the magnetic tunnel junction, a white household appliance comprising the automatic control circuit based on the magnetic tunnel junction, a financial machine comprising the automatic control circuit based on the magnetic tunnel junction, or a car comprising the automatic control circuit based on the magnetic tunnel junction, and the embodiment is not limited specifically.

[0069] In order to more clearly illustrate the execution process of the automatic control circuit based on the magnetic tunnel junction, the following will be described by specific examples.

[0070] Example 1

[0071] Figure 7 is a waveform diagram of the automatic control circuit based on the magnetic tunnel junction provided by a specific example of the present application;

[0072] First, a write enable signal EN and a write signal W sent by an external device are received for control, wherein the write enable signal EN is "0", which represents that the circuit does not perform a write operation, and the write enable signal EN is "1", which represents that the circuit performs a write operation, and the specific write state is determined by the write signal W. When the write signal W is "0", the states of the magnetic tunnel junctions MTJ0 and MTJ1 are required to be converted to "1" and "0" respectively, and when the write signal W is "1", the states of the magnetic tunnel junctions MTJ0 and MTJ1 are required to be converted to "0" and "1" respectively.

[0073] From Figure 7It can be seen that at 10 ns, the write enable signal EN changes from "0" to "1", the write is started, and the states of the current magnetic tunnel junctions MTJ0 and MTJ1 are "0" and "1" respectively. At this time, the write signal W is "0", and it is required to change the states of the magnetic tunnel junctions MTJ0 and MTJ1 to "1" and "0" respectively.

[0074] Since the voltages at the two points A and B detected by the domino logic unit are not completely stable at the beginning of the write stage, the write enable signal EN is input to the domino logic unit after passing through the very short delay module 400, so as to start the domino logic unit.

[0075] When the domino logic unit is not started, the output signals C1 and C2 are "1", and the branch control signals SEN1 and SEN2 generated after the write enable signal EN and the above two signals pass through the NAND gate and the inverter in the write completion detection circuit are also "1".

[0076] After the branch control signals SEN1 and SEN2 and the write enable signal EN and the write signal W pass through the enable control module 300, the values of the core write circuit control signals V0-V5 output by the enable control module 300 are "000011" respectively.

[0077] At this time, the write core circuit forms a write path, and the branches of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 generate write currents IW0 and IW1 respectively, and the directions are the same, which are both downward current directions. Since the two magnetic tunnel junctions are placed reversely and the current states are complementary, the current directions can switch the magnetic tunnel junction MTJ0 from "0" to "1" and switch the second magnetic tunnel junction MTJ1 from "1" to "0".

[0078] Since the average switching time is asymmetric when the magnetic tunnel junction state is switched from "0" to "1" and from "1" to "0", the two magnetic tunnel junctions are not necessarily switched at the same time.

[0079] When the first magnetic tunnel junction MTJ0 is switched from "0" to "1", due to the change of the resistance of the first magnetic tunnel junction MTJ0 and the voltage division relationship between the PMOS tube P1 and the first magnetic tunnel junction MTJ0 and the NMOS tube N3, the voltage at the point A rises from "0" to "1". After the signal is amplified by the buffer B1 and input to the domino logic unit, the domino logic unit is triggered, C1 is switched from "1" to "0", and then the first control signal SEN1 of the first branch is switched from "1" to "0" and input to the enable control module 300, the control signals V0 and V1 are switched from "00" to "10", the write branch of the first magnetic tunnel junction MTJ0 is closed, and the automatic termination write operation of the first magnetic tunnel junction is completed.

[0080] When the second magnetic tunnel junction MTJ1 switches from "1" to "0", due to the change of its resistance and the voltage division relationship between the PMOS tube P2 and the second magnetic tunnel junction MTJ1 and the NMOS tube N3, the voltage of point B drops from "1" to "0", and after the signal passes through the buffer B3 and the inverter I1, it is input to the domino logic unit, triggers the domino logic unit, and makes C2 switch from "1" to "0", so the second control signal SEN2 of the second branch also switches from "1" to "0", and after being input to the enable control module 300, the control signals V2 and V3 switch from "00" to "10", the write branch of the second magnetic tunnel junction MTJ1 is closed, and the automatic termination write operation of the second magnetic tunnel junction is completed.

[0081] After both magnetic tunnel junctions complete the write operation and the write branch performs the automatic termination operation, the core write circuit no longer has current passing through, and after a period of time, the write enable signal EN will be 0, and the control signals V4 and V5 switch from "11" to "10", and the write operation is completely finished.

[0082] The switched magnetic tunnel junctions MTJ0 and MTJ1 have states of "1" and "0" respectively.

[0083] As shown in Figure 7 At 30ns, the write enable signal EN is pulled high again, at this time the write signal W is "1", and the circuit needs to switch the values of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 to "0" and "1" respectively.

[0084] Since the write enable signal EN is delayed, the output signals C1 and C2 are "1", and the branch control signals SEN1 and SEN2 are also "1".

[0085] After the first control signal SEN1 and the second control signal SEN2 pass through the enable control module 300 and the write enable signal EN and the write signal W, the values of the output core write circuit control signals V0-V5 are "111100" respectively.

[0086] At this time, the write core circuit forms a write path, and the branches of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 generate IW0 and IW1 write currents respectively, and the directions are the same, both are upward current directions, and the third PMOS tube P3 generates an IW3 write current and the third NMOS tube N3 generates an IW2 write current, since the two magnetic tunnel junctions are placed in opposite directions and the current directions are complementary. So this current direction can switch the first magnetic tunnel junction MTJ0 from "1" to "0", and switch the second magnetic tunnel junction MTJ1 from "0" to "1".

[0087] When MTJ0 switches from "1" to "0", due to the change of its resistance and the voltage division relationship between PMOS P3 and the first magnetic tunnel junction MTJ0 and NMOS N1, the voltage at point A rises from "0" to "1", after being amplified by buffer B1, the signal is input to the domino logic unit, triggering the domino logic unit, making CI switch from "1" to "0", then the first control signal SEN1 also switches from "1" to "0", after being input to the enable control module 300, the control signals V0 and V1 switch from "11" to "10", the write branch of the first magnetic tunnel junction MTJ0 is closed, and the automatic termination write operation of the magnetic tunnel junction is completed.

[0088] When MTJ1 switches from "0" to "1", due to the change of its resistance and the voltage division relationship between PMOS P3 and the magnetic tunnel junction MTJ1 and NMOS N2, the voltage at point B drops from "1" to "0", after being amplified by buffer B3 and inverter I1, the signal is input to the domino logic unit, triggering the domino logic unit, making C2 switch from "1" to "0", then the second control signal SEN2 also switches from "1" to "0", after being input to the enable control module 300, the control signals V2 and V3 switch from "11" to "10", the write branch of the second magnetic tunnel junction MTJ1 is closed, and the automatic termination write operation of the magnetic tunnel junction is completed.

[0089] After both magnetic tunnel junctions complete the write operation and the write branch automatically terminates the operation, the core write circuit no longer has current passing through, after a period of time, the write enable signal EN will be 0, the control signals V4 and V5 switch from "00" to "10", and the write operation is completely finished.

[0090] In addition, at 50ns, the write enable signal EN is pulled high again, at this time the value of the write signal W is still "1", and it is required that the states of the first magnetic tunnel junction MTJ0 and the second magnetic tunnel junction MTJ1 are converted to "0" and "1" respectively, which is consistent with the current states of the two magnetic tunnel junctions, after a very short delay, due to the voltage division relationship of each branch, the voltages at points A and B quickly trigger the domino circuit, making the write current of the two branches quickly close, preventing repeated writing and saving a lot of energy.

[0091] It should be understood that in this application, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0092] Further, "at least one" means one or more, "multiple" means two or more. "And / or" is used to describe the association between associated objects, which means that there can be three relationships, for example, "A and / or B" can mean: only A, only B, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c, can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0093] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the exemplary description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0094] The preferred embodiments of the application are described above with reference to the accompanying drawings, and are not limited to the scope of the application. Any modifications, equivalent replacements and improvements made by those skilled in the art without departing from the scope and essence of the application shall be within the scope of the application.

[0095] Although the embodiments of the present application have been shown and described, those skilled in the art can understand that various changes, modifications, replacements and variations can be made to these embodiments without departing from the principles and purposes of the present application, and the scope of the present application is defined by the claims and their equivalents.

[0096] The embodiments of the present application are described in detail above with reference to the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the scope of knowledge possessed by those skilled in the art without departing from the purposes of the present application.

Claims

1. An automatic control circuit based on a magnetic tunnel junction, characterized in that, include: The core write module includes two write branches, each of which includes a magnetic tunnel junction; A write detection module is connected to the core write module. The write detection module is used to receive a delayed signal after delay processing, and generate a target detection signal when the magnetic tunnel junction in the target branch is detected to be in a write-complete state according to the delayed signal. The target branch is at least one of the write branches. An enable control module is connected to both the write detection module and the core write module. The enable control module receives a write enable signal and a write signal sent from an external source, as well as a target detection signal sent by the write detection module. Based on the write enable signal, the write signal, and the target detection signal, the enable control module generates a target control signal to control the write state of the target branch to be closed. The enable control module then sends the target control signal to the core write module, causing the core write module to close the write state of the target branch based on the target control signal. A delay module is connected to the write detection module. The delay module is used to delay the write enable signal to generate the delay signal and send the delay signal to the write detection module. The core write module includes a shared bus for controlling the write branch. The write branch includes a first branch and a second branch. The first branch and the second branch are respectively connected to the shared bus. The first branch is connected to the write detection module and the enable control module, and the second branch is connected to the write detection module and the enable control module. The shared bus is connected to the enable control module. The write detection module includes a domino logic unit, and the target detection signal includes a first detection signal and a second detection signal. The domino logic unit is connected to the core write module and the enable control module, respectively. The domino logic unit is used to receive the delay signal, delay and start the domino logic unit, and detect the write status of the first branch and the write status of the second branch, generating the first detection signal and the second detection signal. The first detection signal is used to indicate that the first branch is in the write completion state, and the second detection signal is used to indicate that the second branch is in the write completion state.

2. The automatic control circuit based on a magnetic tunnel junction according to claim 1, characterized in that, The enable control module includes a first control unit and a second control unit, as well as a bus control unit for receiving the write enable signal and the write signal. The target control signal includes a first control signal, a second control signal, and a bus control signal. The first control unit is connected to the first branch and the domino logic unit respectively to generate a first control signal controlling the first branch to disable writing based on the received first detection signal. The second control unit is connected to the second branch and the domino logic unit respectively to generate a second control signal controlling the second branch to disable writing based on the received second detection signal. The bus control unit is connected to the shared bus, and the bus control unit generates a bus control signal controlling the shared bus to disable writing based on the write signal and the write enable signal.

3. The automatic control circuit based on a magnetic tunnel junction according to claim 2, characterized in that, The first branch includes a first PMOS transistor, a first NMOS transistor, and a first magnetic tunnel junction. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The gates of the first PMOS transistor and the first NMOS transistor are respectively connected to the first control unit. The connection point of the first PMOS transistor and the first NMOS transistor is connected to the first magnetic tunnel junction and the domino logic unit. One end of the first magnetic tunnel junction is connected to the connection point of the first PMOS transistor and the first NMOS transistor, and the other end is connected to the shared bus.

4. The automatic control circuit based on a magnetic tunnel junction according to claim 2, characterized in that, The second branch includes a second PMOS transistor, a second NMOS transistor, and a second magnetic tunnel junction. The drain of the second PMOS transistor is connected to the drain of the second NMOS transistor. The gates of the second PMOS transistor and the second NMOS transistor are respectively connected to the second control unit. The connection point of the second PMOS transistor and the second NMOS transistor is connected to the second magnetic tunnel junction and the domino logic unit. One end of the second magnetic tunnel junction is connected to the connection point of the second PMOS transistor and the second NMOS transistor, and the other end is connected to the shared bus.

5. The automatic control circuit based on a magnetic tunnel junction according to claim 2, characterized in that, The shared bus includes a third PMOS transistor and a third NMOS transistor. The drain of the third PMOS transistor is connected to the drain of the third NMOS transistor. The gates of the third PMOS transistor and the third NMOS transistor are respectively connected to the bus control unit. The connection point of the third PMOS transistor and the third NMOS transistor is connected in parallel between the first branch and the second branch.

6. An electronic device, characterized in that, Includes an automatic control circuit based on a magnetic tunnel junction as described in any one of claims 1-5.

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