Chip, electronic device and processing method

Abstract

This application discloses a chip, electronic device, and processing method, belonging to the field of semiconductor technology. The chip comprises: a chip body including a first surface and a second surface adjacent to the first surface; pins disposed on the first surface of the chip body; and a fusible sealant disposed around the outside of at least some of the pins. The chip body has a receiving space for the fusible sealant, with a first opening of the receiving space facing the pins; alternatively, the fusible sealant is disposed on the second surface.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and specifically relates to a chip, an electronic device, and a processing method. Background Art

[0002] Currently, there are waterproof issues with chips installed inside mobile communication devices:

[0003] Typically, adding a shield to the chip can solve the chip's waterproofing problem. However, this approach increases the board area and the overall height of the device. Therefore, solving the chip's waterproofing problem has become a pressing issue. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a chip, an electronic device, and a processing method that can solve the waterproof problem of the chip.

[0005] In a first aspect, an embodiment of the present application provides a chip, comprising: a chip body, comprising a first surface and a second surface adjacent to the first surface; pins, arranged on the first surface of the chip body; and fusible sealant, wrapped around the outside of at least part of the pins; wherein the chip body has a accommodating space for accommodating the fusible sealant, and the first opening of the accommodating space faces the pin side; or, the fusible sealant is arranged on the second surface.

[0006] In a second aspect, an embodiment of the present application provides an electronic device, comprising: a chip as described in the first aspect; and a fusible sealant filling a gap between a circuit board and a first surface in the electronic device to seal at least part of the pins.

[0007] In a third aspect, an embodiment of the present application provides a processing method, comprising: heating a circuit board in an electronic device to solder the pins of a chip to the circuit board; during the process of heating the circuit board, the fusible sealant melts and flows out from a first opening, so that the fusible sealant fills the gap between the circuit board and the first surface to seal at least part of the pins.

[0008] In an embodiment of the present application, a chip body includes a first surface and a second surface adjacent to the first surface; pins are disposed on the first surface of the chip body; and a fusible sealant is disposed around the outside of at least some of the pins. The chip body includes a storage space for accommodating the fusible sealant, with a first opening of the storage space facing the pins. Alternatively, the fusible sealant is disposed on the second surface. With this solution, the chip includes a chip body, pins, and fusible sealant. Since the fusible sealant is disposed around the outside of at least some of the pins, during the chip mounting process, the fusible sealant can seal at least some of the pins, thereby protecting at least some of the pins disposed on the first surface of the chip from water ingress and water mist, thereby achieving the purpose of waterproofing the chip and avoiding the problem of increasing the board area and the height of the entire device due to the addition of a shielding cover.

[0009] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a cross-sectional schematic diagram of a chip provided in one embodiment of the present application;

[0011] Figure 2 is a cross-sectional schematic diagram of a chip provided in yet another embodiment of the present application;

[0012] Figure 3 This is a bottom view of a chip provided in another embodiment of the present application;

[0013] Figure 4 : is a schematic diagram of the position of the second pin of the chip provided in another embodiment of the present application; wherein, Figure 4 (a) is a cross-sectional view of the second pin's location. Figure 4 (b) is a bottom view schematic diagram of the setting position of the second pin;

[0014] Figure 5 : is a schematic diagram of the positions of the second pin and the first pin of a chip provided in another embodiment of the present application; wherein, Figure 5 (a) is a cross-sectional view of the arrangement positions of the first pin and the second pin, as shown in FIG. Figure 4 (b) is a bottom view schematic diagram of the arrangement positions of the first pin and the second pin;

[0015] Figure 6 is a cross-sectional view of a chip provided in yet another embodiment of the present application;

[0016] Figure 7 is a cross-sectional view of a chip provided in yet another embodiment of the present application;

[0017] Figure 8is a cross-sectional view of a chip provided in yet another embodiment of the present application;

[0018] Figure 9 is a schematic diagram of a first surface of a chip provided in yet another embodiment of the present application;

[0019] Figure 10 is a cross-sectional view of a chip and a circuit board included in an electronic device provided in one embodiment of the present application;

[0020] Figure 11 is a cross-sectional view of a circuit board assembly provided in one embodiment of the present application;

[0021] Figure 12 It is a flow chart of a method for processing a circuit board assembly provided in one embodiment of the present application.

[0022] Figure 13 This is a schematic diagram of a chip provided by an embodiment of the present application being attached to a circuit board through an SMT process;

[0023] Figure 14 This is a schematic diagram of a chip provided by another embodiment of the present application being attached to a circuit board through an SMT process;

[0024] in, Figures 1 to 12 The reference numerals in the figures are:

[0025] 10: chip;

[0026] 11: chip body, 111: first surface, 112: second surface, 113: accommodation space, 114: first opening, 115: main body, 116: shielding layer, 117: second opening;

[0027] 12: pin, 121: first pin, 122: second pin, 1221: function pin, 1222: RF pin, 123: third pin;

[0028] 13: Fusible sealant;

[0029] 20: Circuit board assembly;

[0030] 21: Circuit board; DETAILED DESCRIPTION

[0031] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0032] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0033] The chip 10 provided in the embodiment of the present application can be applied to electronic devices, specifically, can be applied to a scenario in which the electronic device is provided with a circuit board assembly 20 composed of at least two stacked circuit boards.

[0034] The electronic devices in the embodiments of the present application may be mobile electronic devices or non-mobile electronic devices. For example, the mobile electronic devices may be mobile phones, tablet computers, laptop computers, PDAs, in-vehicle electronic devices, wearable devices, ultra-mobile personal computers (UMPCs), netbooks, or personal digital assistants (PDAs), and the non-mobile electronic devices may be personal computers (PCs), televisions (TVs), ATMs, or self-service machines, etc., without specific limitations in the embodiments of the present application.

[0035] The chip, electronic device, and processing method provided in the embodiments of the present application are described in detail below with reference to specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0036] like Figure 1 As shown, the chip 10 may include: a chip body 11, including a first surface 111 and a second surface 112 adjacent to the first surface 111; pins 12, arranged on the first surface 111 of the chip body 11; and a fusible sealant 13, arranged around the outside of at least part of the pins; wherein the chip body 11 has a receiving space 113 for receiving the fusible sealant 13, and a first opening 114 of the receiving space 113 faces the pin 12 side; or as Figure 2 As shown, the fusible sealant 13 is disposed on the second surface 112 .

[0037] Optionally, in the embodiment of the present application, the thickness of the chip body 11 may be a preset thickness, and the chip body 11 may be rectangular, circular, or other possible shapes, which are not specifically limited in the embodiment of the present application.

[0038] In the embodiment of the present application, the first surface 111 of the chip body 11 is the bottom surface of the chip body 11. The second surface 112 is the side surface of the chip body 11, including four side surfaces: front, back, left, and right.

[0039] Optionally, in the embodiment of the present application, the number of the pins 12 can be one or more. Of course, usually, the number of the pins 12 is multiple.

[0040] Furthermore, in the embodiment of the present application, when there are multiple pins 12 , the multiple pins 12 can be evenly distributed on the first surface 111 of the chip body 11 , or non-uniformly distributed on the first surface 111 .

[0041] Optionally, when there are multiple pins 12 , the pins 12 may include at least one of the following: a function pin, a radio frequency pin, a ground pin, or other possible pins.

[0042] Optionally, the melting point of the fusible sealant 13 is lower than 300 degrees Celsius.

[0043] It should be noted that during the surface mounting process, when the heat from the pins of the soldered chip is transferred to the circuit board, the temperature of the circuit board can reach about 300 degrees Celsius.

[0044] That is, since the melting point of the fusible sealant 13 is lower than 300 degrees Celsius, when the chip is fixed to the circuit board through the surface mounting process, the temperature of the circuit board may reach about 300 degrees Celsius, and the fusible sealant 13 will melt from solid to liquid.

[0045] Of course, in the embodiment of the present application, the use of a fusible sealant with a melting point between 240 degrees Celsius and 250 degrees Celsius or a fusible sealant with a melting point below 240 degrees Celsius also meets the requirements.

[0046] Optionally, the fusible sealant 13 melts during the mounting process of the chip 10 to seal at least a portion of the pins 12 .

[0047] Optionally, since the fusible sealant 13 is used to seal at least a portion of the pins 12, if the chip 10 has a plurality of pins 12, in one possible scenario, the fusible sealant 13 is used to seal a portion of the plurality of pins 12; in another possible scenario, the fusible sealant 13 is used to seal all of the pins 12. This can be determined based on actual circumstances and is not limited in the present embodiment.

[0048] Optionally, in an embodiment of the present application, the surface mounting process may refer to a process of mounting a chip on a circuit board and soldering the pins of the chip.

[0049] It should be noted that, during the surface packaging process, when the fusible sealant 13 melts to form a closed space surrounding the pins 12 , the pins 12 will not be affected by water ingress and water mist, thereby sealing at least part of the pins 12 .

[0050] It should be noted that the above Figure 1 The chip body 11 is provided with a receiving space 113 for receiving the fusible sealant 13 as an example for exemplary description; Figure 2 As shown, the fusible sealant 13 is disposed on the second surface 112 .

[0051] Of course, the accommodating space 113 can also be provided at other locations of the chip body 11 , which will not be described in detail in the embodiment of the present application, and reference may be made to the detailed description in the following embodiments.

[0052] Optionally, in this embodiment, the accommodating space 113 may be as follows: Figure 3 An annular receiving groove 14 is shown disposed around at least a portion of the outer side of the pin 12 .

[0053] Optionally, the annular receiving groove 14 may be circular, square, elliptical or other possible shapes. The annular receiving groove is the first conductive groove to be connected.

[0054] Exemplarily, the opening of the annular receiving groove 14 is a first opening 114 .

[0055] The chip 10 provided in the embodiment of the present application includes a chip body 11, pins 12 and a fusible sealant 13. Since the fusible sealant 13 is wrapped around the outside of at least part of the pins 12, during the mounting process of the chip 10, the fusible sealant 13 can seal at least part of the pins 12, so that at least part of the pins 11 arranged on the first surface 111 of the chip 10 will not be affected by water ingress and water mist, thereby achieving the purpose of waterproofing the chip 10, and further avoiding the problem of increasing the board area and the height of the entire machine due to adding the shielding cover 116.

[0056] Optionally, combined Figure 1 and Figure 3 The pin 12 includes a first pin 121 and a second pin 122; wherein the second pin 122 is located on a side of the first pin 121 away from the edge of the first surface 111, and the second pin 122 includes at least one of the following: a functional pin and a radio frequency pin.

[0057] Further optionally, the first opening 114 of the accommodating space 113 is located on the first surface 111, and the accommodating space 113 is an annular receiving groove 14 formed on the first surface 111 of the chip body 11. The first opening 114 is located between the first lead 121 and the second lead 122, and the fusible sealant 13 is disposed in the annular receiving groove 14.

[0058] Optionally, in the embodiment of the present application, when the second pin 122 includes a function pin 1221 and a radio frequency pin 1222 , the function pin 1221 and the radio frequency pin 1222 are located in an area enclosed by the annular receiving groove 14 .

[0059] Optionally, when the second pins 122 include both the function pins 1221 and the radio frequency pins 1222, the number and distribution of the function pins and the radio frequency pins may be the same or different, which is not limited in this embodiment of the present application.

[0060] Because functional pins 1221 and RF pins 1222 are more susceptible to moisture, second pins 122 are sealed within the area enclosed by annular groove 113 using fusible sealant 13 to improve chip reliability. Furthermore, ground pins, which are less susceptible to moisture, are placed outside annular groove 14. This means that the ground pins are not sealed. This reduces the size of the sealing area, easing the sealing difficulty and improving the sealing effect.

[0061] For example, Figure 2 The chip body 11 shown has a receiving space 113 which is an annular receiving groove 14 . When the second pins 122 include functional pins and RF pins, the functional pins 1221 and RF pins 1222 are located in the area enclosed by the annular receiving groove 113 .

[0062] For example, take the RF pin 1222 as an example. Figure 4 The figure shows the signal propagation when the RF pin 1222 is located near the edge of the chip 10. At this time, the RF signal will leak through the edge gap between the shielding cover and the motherboard. The leakage path of the RF pin 1222 is as follows: Figure 4 As shown by the dotted arrow in .

[0063] Again illustratively, Figure 5The figure shows the signal propagation when the first pin 121 is positioned between the RF pin 1222 and the edge of the chip 10. In this case, the RF pin 1222 is located on the side of the first pin 121 away from the edge of the first surface 111. That is, the RF pin 1222 moves from the outer edge of the first surface 111 of the chip body 11 to a position within the first pin 121. When the RF pin 1222 leaks to the outside, it needs to pass through the gap between the pins, which significantly lengthens the leakage path. In addition, when the first pin 121 is a ground pin, it can further effectively shield the leakage of RF signals. Figure 5 The pinout shown is relative to Figure 4 It can significantly reduce (more than 10dB) the leakage of RF signals and reduce the risk of signal interference to external systems. If a shielding cover 116 is provided outside the chip body, the shielding effect of RF signals can be further improved, the isolation between the RF pin 1222 and other peripheral circuits can be increased, and the leakage of RF signals can be reduced; wherein, the leakage path of the RF pin 1222 is as follows: Figure 5 As shown by the dotted arrow in .

[0064] In an embodiment of the present application, the pin 12 includes a first pin 121 and a second pin 122. When the second pin 12 includes a functional pin 1221 and a RF pin 1222, since the functional pin and the RF pin are located in the area enclosed by the annular receiving groove, the fusible sealant 13 filled in the annular receiving groove can not only seal the functional pin and the RF pin, but also reduce leakage since the functional pin and the RF pin are away from the outer edge of the first surface of the chip body, and increase the isolation between the RF pin, the functional pin and the other peripheral circuits.

[0065] Optionally, the first pin 121 is adjacent to the second pin 122, and the distance between the orthographic projection of the second pin 122 on the first surface 111 and the first opening 114 is greater than or equal to the distance between the orthographic projection of the first pin 121 on the first surface 111 and the first opening 114; and / or, the pin 12 also includes a third pin 123, the third pin 123 is located on the side of the second pin 122 away from the first pin 121 and the edge of the first surface 111, the first pin 121 is adjacent to the second pin 122, and the third pin 123 is adjacent to the second pin 122; the distance between the second pin 122 and the first pin 121 is greater than the distance between the second pin 122 and the third pin 123.

[0066] It can be understood that, in one case, when the distance between the orthographic projection of the second pin 122 on the first surface 111 and the first opening 114 is greater than or equal to the distance between the orthographic projection of the first pin 121 on the first surface 111 and the first opening 114, the distance between the orthographic projection of the second pin 122 on the first surface 111 and the first opening 114 can be made long enough to ensure that there is enough avoidance space near the second pin; in another case, when the distance between the second pin 122 and the first pin 121 is greater than the distance between the second pin 122 and the third pin 123, the second pin can be kept away from the edge of the first surface.

[0067] Further optionally, in the embodiment of the present application, the distance between the orthographic projection of the second pin 122 on the first surface 111 and the first opening 114 is greater than or equal to a preset distance, which is one quarter of the distance between the second pin and the first pin.

[0068] Optionally, the preset distance may also be one third of the distance between the second pin and the first pin.

[0069] It is understandable that in order to avoid the influence of the fusible sealant 13 on the second pin 122 including the functional pin and the RF pin, the position of the first opening 114 of the accommodating space 113 can be adjusted to keep the distance between the first outlet 114 and the positive projection of the second pin 122 on the first surface 111 greater than the preset distance, ensuring that the solder ball can be fixed by the circuit board first during surface mounting and will not flow to the second pin 122.

[0070] Optionally, the distance between the orthographic projection and the first opening may specifically refer to the distance between the edge of the orthographic projection and the edge of the first opening, or the distance between the center of the orthographic projection and the center of the first opening. This embodiment of the application does not limit this.

[0071] For example, in the embodiment of the present application, when the second pin 122 includes the functional pin 1221 , the first distance between the orthographic projection of the functional pin 1221 on the first surface and the first opening 114 of the annular receiving groove 14 is greater than or equal to the preset distance.

[0072] For example, in the embodiment of the present application, when the second pin 122 includes the RF pin 1222 , the second distance between the orthographic projection of the RF pin 1222 on the first surface 111 and the first opening 114 of the annular receiving groove 14 is greater than or equal to the preset distance.

[0073] Optionally, in the embodiment of the present application, the first distance and the second distance may be the same or different, which may be determined based on actual conditions and are not limited in the embodiment of the present application.

[0074] For example, Figure 6 and Figure 7 As shown, to protect the second pin 122 from the influence of the fusible sealant 13, an avoidance structure is provided on the side of the annular receiving groove 14 near the second pin 122. Specifically, the distance d between the first opening 114 of the annular receiving groove 14 and the adjacent second pin 122 ensures that the fusible sealant 13 flows along a path d when melted, and d is greater than the aforementioned predetermined distance. As previously mentioned, the predetermined distance is at least 1 / 3 of the distance between the first pin 121 and the second pin 122. This ensures that the fusible sealant 13 does not affect the electrical properties of the RF pin while ensuring the flow rate of the fusible sealant 13.

[0075] Optionally, the chip body 11 has an accommodating space 113 , and an area of ​​the first opening 114 is smaller than an area of ​​a bottom surface of the accommodating space 113 away from the first surface 111 .

[0076] It should be noted that the distance between the orthographic projection of the second pin 122 on the first surface 111 and the first opening 114 is greater than or equal to a predetermined distance, that is, the annular receiving groove is disposed on the first surface 111 in a circumferential manner.

[0077] It can be understood that, when the fusible sealant 13 is disposed in the annular receiving groove, the distribution of the fusible sealant 13 is further improved, that is, the filling area where the fusible sealant is located is moved toward the inside of the chip.

[0078] It is understandable that since the area of ​​the first opening 114 is smaller than the area of ​​the bottom surface of the accommodating space 113 away from the first surface 111, it can ensure that the accommodating space 113 is filled with sufficient fusible sealant 13 and control the flow rate of the fusible sealant 13.

[0079] In the embodiment of the present application, since the distance between the orthographic projection of the second pin 12 on the first surface and the first opening 114 of the accommodating space 113 is greater than or equal to the preset distance, the flow path of the fusible sealant when melting is greater than the preset distance, so that there is sufficient avoidance space near the second pin, thereby avoiding the risk of device use and performance impact (such as impact on the electrical properties of the second pin) caused by the fusible sealant 13 being falsely attached to the second pin 122 (for example, a RF pin or a functional pin).

[0080] Optionally, combined Figure 1 ,like Figure 3 As shown, the pin 12 further includes a third pin 123 , which is a ground pin. The second pin 122 includes a radio frequency pin 1222 and a function pin 1221 , and the third pin is located between the radio frequency pin 1222 and the function pin 1221 .

[0081] It should be noted that when pin 12 includes a ground pin, since the ground pin is only for the purpose of ensuring the reliability of the impedance ground pin, the impact of the fusible sealant 13 on the ground pin 123 is relatively small. Therefore, the annular receiving groove 14 can be arranged to avoid the ground pin, or not. This is determined based on actual usage and is not limited in this embodiment of the present application.

[0082] Optionally, in the embodiment of the present application, when the pin 12 further includes a third pin 123 and the third pin 123 is a ground pin, at least part of the ground pin may be located in the area enclosed by the annular groove.

[0083] For example, Figure 3 The chip body 11 shown has an annular groove 14. The third pin 123 is located within the area enclosed by the annular groove, and the first pin 121 is located outside the area enclosed by the annular groove 14. However, both the first pin 121 and the third pin 123 are ground pins.

[0084] In an embodiment of the present application, when the pin 12 further includes a grounded third pin 123 , the third pin 123 is located between the RF pin 1222 and the functional pin 1221 , thereby preventing signal interference between the RF pin 1222 and the functional pin 1221 .

[0085] Combine Figure 1 and Figure 8 The chip body 11 includes: a main body 115, a first surface 111 located in the main body, and the pins 12 are arranged in the main body 115; a shielding layer 116, which is arranged outside the main body 115, and the shielding layer 116 has a second opening 117, and the first surface 111, the first opening 114 and the pins 12 are all exposed in the second opening 117.

[0086] Optionally, the accommodating space 113 is located between the main body 115 and the shielding layer 116 , and the fusible sealant 13 is disposed in the accommodating space 113 .

[0087] In the case that the chip body 11 includes a main body portion 115 and a shielding layer 116 , the fusible sealant 13 is disposed between the shielding layer 116 and the main body portion 115 .

[0088] It can be understood that since the first surface 111 and the pins 12 are both exposed at the second opening 117 , the melted fusible sealant 13 can flow out from the first opening 114 opened on the first surface 111 to wrap around the outside of at least part of the pins 12, thereby sealing at least part of the pins 12.

[0089] Optionally, the shielding layer 116 has a top and side walls connected to the top edge, the top is overlapped with the surface of the main body 115 opposite to the first surface 111, the side walls enclose to form a second opening 117, and there is a gap between the side walls and the main body 115 to form an accommodating space 113, and a fusible sealant 13 is arranged in the accommodating space 113.

[0090] It is understandable that, when there is a gap between the side wall and the main body 115 to form the accommodating space 113 , the opening of the gap is the first opening 114 of the accommodating space 113 .

[0091] Optionally, when the chip body 11 includes a main body 115 and a shielding layer 116 , the fusible sealant 13 may be provided on the surface of the shielding layer 116 located on the second surface.

[0092] like Figure 8 and Figure 9 As shown, when the chip body 11 includes a shielding layer 116 sleeved outside the main body 115 , the second surface 112 is the outer surface of the shielding layer 116 , and the fusible sealant 13 is disposed on the outer surface of the shielding layer 116 .

[0093] The shielding layer 116 has a top and side walls connected to the top edge. The top is overlapped with the surface of the main body 115 opposite to the first surface 111. The side walls enclose a second opening 117. A gap is provided between the side walls and the main body 115 to form an accommodating space 113. The fusible sealant 13 is arranged in the accommodating space 113. Therefore, during the chip mounting process, the fusible sealant 13 can flow out of the first opening 114 after melting to seal at least part of the pins.

[0094] In some embodiments of the present application, a receiving space 113 for accommodating a fusible sealant 13 is provided on the chip 10. During the process of soldering and fixing the chip 10 to the circuit board 21 through a surface mount process, the circuit board 21 needs to be heated. The fusible sealant 13 is melted by the heat and flows out along the first opening 114 to between the first surface 111 and the circuit board 21, thereby sealing the pins 12 enclosed by the inner side of the first opening 114. The present application pre-buries the fusible sealant 13 in the receiving space 113 of the chip 10, and then simultaneously melts the pre-set fusible sealant 13 during the subsequent chip soldering-related process. This allows the pins 12 to be sealed simultaneously during the soldering and fixing process of the chip 10 without the need for an additional pin sealing process, thereby greatly reducing the chip installation time and simplifying the chip installation process and steps.

[0095] In other embodiments of the present application, the fusible sealant 13 is directly preset on the second surface 112 of the chip 10, and the second surface 112 is adjacent to the first surface 111, so that when the chip 10 is soldered and fixed to the circuit board 21 through the surface mounting process, the circuit board 21 needs to be heated, and the fusible sealant 13 is melted by the heat and flows along the second surface 112 to between the first surface 111 and the circuit board 21, thereby sealing all the pins 12 of the chip 10. The present application pre-sets the fusible sealant 13 on the second surface 112 outside the chip 10, and then simultaneously melts the preset fusible sealant 13 in the subsequent chip soldering-related process, so that the sealing of all the pins 12 can be completed simultaneously in the soldering and fixing process of the chip 10 without adding an additional pin sealing process, which greatly reduces the chip installation time and simplifies the chip installation process and steps.

[0096] An embodiment of the present application provides an electronic device, the electronic device including the chip as described above. Figure 10 As shown, in the process of soldering and fixing the chip 10 to the circuit board 21 through the surface mounting process, the circuit board 21 needs to be heated, and the fusible sealant 13 is melted by the heat and flows between the first surface 111 and the circuit board 21, thereby allowing the fusible sealant 13 to fill the gap between the circuit board 21 and the first surface 111 in the electronic device to seal at least part of the pins 12.

[0097] Figure 11 A schematic structural diagram of a circuit board assembly provided in an embodiment of the present application is shown. The circuit board assembly 20 is applied to the above-mentioned electronic device. The circuit board assembly 20 includes a circuit board 21 and the chip 10 described above. The pins 12 of the chip 10 are soldered to the circuit board 21. During the process of soldering and fixing the chip 10 to the circuit board 21 through a surface mount process, the circuit board 21 needs to be heated. The fusible sealant 13 is simultaneously melted by the heat and flows between the first surface 111 and the circuit board 21, thereby allowing the fusible sealant 13 to fill the gap between the circuit board 21 and the first surface 111 in the electronic device to seal at least a portion of the pins 12.

[0098] It is understandable that the chip 10 can also be fixed to the circuit board 21 by other welding methods, as long as the melting point of the fusible sealant 13 is lower than the heating temperature of the welding method, which is not specifically limited here.

[0099] In the embodiment of the present application, since the fusible sealant 13 in the chip 10 can seal at least part of the pins 12, the pins at the bottom of the chip will not be affected by water ingress and water mist, so as to achieve the purpose of chip waterproofing, that is, the chip 10 is a waterproof chip, so that after the pins 12 of the chip 10 are soldered on the circuit board 21, there will be no problem of increasing the layout area and the height of the whole machine due to adding a shielding cover.

[0100] Based on the electronic device provided in the embodiment of the present application, the embodiment of the present application further provides a method for processing a circuit board assembly of the electronic device, which is used to process the circuit board assembly provided in the embodiment of the present application, such as Figure 12 As shown, the processing method includes steps 301 and 302:

[0101] Step 301: Heat a circuit board in an electronic device to solder the pins of a chip to the circuit board.

[0102] Optionally, in an embodiment of the present application, surface mount technology (SMT) is used to heat a circuit board in an electronic device to solder the pins of the chip to the circuit board.

[0103] Optionally, SMT is a surface mount technology. For a detailed description of SMT, please refer to the description in the relevant technology, and the embodiments of the present application will not go into details.

[0104] Optionally, in the above step 301, "heating the circuit board in the electronic device to solder the pins of the chip to the circuit board" specifically refers to: heating the solder balls at positions corresponding to the pins of the chip on the circuit board so that the pins of the chip are soldered to the circuit board.

[0105] Step 302: During the heating of the circuit board, the fusible sealant melts and flows out from the first opening, so that the fusible sealant fills the gap between the circuit board and the first surface to seal at least a portion of the pins.

[0106] It is understandable that during the process of heating the circuit board, the temperature of the circuit board will increase, thereby transferring the heat on the circuit board to the chip through heat conduction. Since the chip includes fusible sealant, the heat can continue to be transferred to the fusible sealant.

[0107] Furthermore, when the heat conducted from the circuit board to the fusible sealant in the chip reaches the melting point of the fusible sealant, the fusible sealant melts into a fluid to seal at least a portion of the pins.

[0108] Specifically, when the heat transferred from the circuit board to the fusible sealant reaches the fusible sealant's melting point, the sealant melts from a solid state to a fluid, flowing out of the chip's containment space and onto the bottom and / or sides of the chip. Thus, after SMT is completed, when the circuit board's temperature gradually drops to the fusible sealant's freezing point, the sealant changes from liquid to solid, creating a closed space around the chip's bottom pads. This space is then protected from water ingress and mist, and the chip's surface is inherently waterproof due to the shielding layer, further enhancing the chip's water resistance.

[0109] For example, Figure 13As shown, when the fusible sealant 13 is pre-embedded in the accommodation space 113 of the chip 10 , the melted fusible sealant fills the gap between the first surface of the chip and the circuit board, thereby sealing part of the pins located inside the accommodation space 113 .

[0110] For example, Figure 14 As shown, when the fusible sealant 13 is directly pre-set on the second surface 112 of the chip 10 , the melted fusible sealant 13 flows along the outer surface of the chip 10 onto the circuit board 21 and fills the gap between the first surface of the chip and the circuit board, thereby sealing all the pins 12 .

[0111] The processing method of the circuit board assembly provided in the embodiment of the present application adopts surface mount technology (SMT) to heat the circuit board in the circuit board assembly. During the heating process, the heat from the circuit board can be transferred to the fusible sealant in the chip. Therefore, when the heat transferred from the circuit board to the fusible sealant in the chip reaches the melting point of the fusible sealant, the fusible sealant melts into a fluid, thereby sealing at least a portion of the pins. In this way, through the SMT process, the chip with the added fusible sealant is processed, realizing the chip's self-sealing capability without the need for workers to apply glue to the chip, thereby simplifying the operation, reducing the layout area, and improving efficiency.

[0112] It should be noted that other devices that require self-sealing adhesive can also be operated using the method in the embodiments of the present application.

[0113] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0114] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0115] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A chip, characterized in that: The chip includes: a chip body comprising a first surface and a second surface adjacent to the first surface; Pins, arranged on the first surface of the chip body; a fusible sealant, disposed around at least a portion of the outer sides of the pins, wherein the melting point of the fusible sealant is lower than 300 degrees Celsius; Wherein, the chip body has a receiving space for receiving the fusible sealant, a first opening of the receiving space faces the pin side, and the fusible sealant is arranged in the receiving space; or, The fusible sealant is disposed on the second surface.

2. The chip according to claim 1, characterized in that The pins include a first pin and a second pin; The second pin is located on a side of the first pin away from an edge of the first surface, and the second pin includes at least one of the following: a functional pin and a radio frequency pin.

3. The chip according to claim 2, characterized in that The first opening of the accommodation space is located on the first surface, the first opening of the accommodation space is located between the first pin and the second pin, and the fusible sealant is provided in the accommodation space.

4. The chip according to any one of claims 1 to 3, characterized in that The accommodating space is an annular accommodating groove arranged around at least a portion of the outer side of the pin.

5. The chip according to claim 3, characterized in that The first pin is adjacent to the second pin, and a distance between an orthographic projection of the second pin on the first surface and the first opening is greater than or equal to a distance between an orthographic projection of the first pin on the first surface and the first opening; and / or, The pin also includes a third pin, which is located on a side of the second pin away from the first pin and the edge of the first surface, the first pin is adjacent to the second pin, and the third pin is adjacent to the second pin; the distance between the second pin and the first pin is greater than the distance between the second pin and the third pin.

6. The chip according to claim 3, characterized in that The distance between the orthographic projection of the second pin on the first surface and the first opening is greater than or equal to a preset distance, and the preset distance is one quarter of the distance between the second pin and the first pin.

7. The chip according to claim 2, characterized in that The pins further include a third pin, which is a ground pin. The second pins include a radio frequency pin and a function pin, and the third pin is located between the radio frequency pin and the function pin.

8. The chip according to claim 1, wherein: The chip body has the accommodation space, and the area of ​​the first opening is smaller than the area of ​​the bottom surface of the accommodation space away from the first surface.

9. The chip according to claim 1, characterized in that The chip body includes: a main body, wherein the first surface is located on the main body, and the pin is provided on the main body; The shielding layer is arranged outside the main body, and the shielding layer has a second opening. The first surface, the first opening, and the pins are all exposed at the second opening.

10. The chip according to claim 9, characterized in that The accommodating space is located between the main body and the shielding layer, and the fusible sealant is arranged in the accommodating space.

11. The chip according to claim 9, characterized in that The shielding layer has a top and a side wall connected to the top edge, the top is overlapped with the surface of the main body opposite to the first surface, the side wall encloses to form the second opening, and there is a gap between the side wall and the main body to form the accommodating space, and the fusible sealant is arranged in the accommodating space.

12. The chip according to claim 1, characterized in that The fusible sealant melts during the chip mounting process to seal at least a portion of the pins.

13. An electronic device, characterized in that: The electronic device comprises a chip according to any one of claims 1 to 12; The fusible sealant fills a gap between a circuit board in the electronic device and the first surface to seal at least a portion of the pins.

14. A processing method, applied to the electronic device according to claim 13, characterized in that: The method comprises: heating a circuit board in the electronic device to solder the pins of the chip to the circuit board; During the process of heating the circuit board, the fusible sealant melts and flows out from the first opening, so that the fusible sealant fills the gap between the circuit board and the first surface to seal at least a portion of the pins.

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