Array substrate, preparation method thereof and display panel

Abstract

The application discloses an array substrate, a preparation method thereof and a display panel. The array substrate comprises a substrate, a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode, a passivation layer, a planarization layer and a common electrode. The common electrode comprises a first conductive layer, a metal conductive layer and a second conductive layer which are sequentially stacked. The common electrode of the array substrate adopts the structure of the metal oxide conductive layer / metal conductive layer / metal oxide conductive layer, so that the metal layer in the electrode can be effectively prevented from being oxidized, and the stability of the array substrate device is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate, its fabrication method, and a display panel. Background Technology

[0002] In back-channel etched amorphous indium gallium zinc oxide (BCE) thin-film transistors (TFTs) using the novel Fringe Field Switching (FFS) technology, indium tin oxide (ITO) + copper (Cu) are typically used as a common electrode to improve product specifications. However, ITO + Cu often employs the HTM + 3W1D process, which is technically challenging and presents compatibility issues with HT residue and PR (photoresist) film breakage. Furthermore, during fabrication, to prevent Cu oxidation, ITO cannot undergo a heating (annealing) step, as this could lead to excessive ITO resistance and poor IGZO TFT stability.

[0003] Therefore, there is an urgent need to provide an array substrate that can solve the problem of copper oxidation. Summary of the Invention

[0004] The purpose of this application is to provide an array substrate that can effectively prevent the oxidation of conductive metals during the manufacturing process.

[0005] This application provides an array substrate, including:

[0006] Substrate

[0007] A gate, wherein the gate is disposed on the substrate;

[0008] A gate insulating layer, wherein the gate insulating layer is disposed on the gate;

[0009] An active layer, wherein the active layer is disposed on the gate insulating layer,

[0010] Source and drain, wherein the source and drain are disposed on the active layer;

[0011] A passivation layer is disposed on the source and drain electrodes;

[0012] A planarization layer disposed on the passivation layer;

[0013] A common electrode is disposed on the planarization layer; and the common electrode includes a first conductive layer, a metal conductive layer and a second conductive layer stacked sequentially.

[0014] Optionally, in some embodiments of this application, the material of the first conductive layer is indium tin oxide (ITO).

[0015] Optionally, in some embodiments of this application, the material of the metal conductive layer is copper (Cu).

[0016] Optionally, in some embodiments of this application, the material of the second conductive layer is indium tin oxide (ITO).

[0017] Optionally, in some embodiments of this application, the thickness of the first conductive layer is 400 to 800 angstroms.

[0018] Optionally, in some embodiments of this application, the thickness of the metal conductive layer is 2000 to 4000 angstroms.

[0019] Optionally, in some embodiments of this application, the thickness of the second conductive layer is 100 to 200 angstroms.

[0020] Optionally, in some embodiments of this application, the active layer is made of a conductive metal oxide;

[0021] The conductive metal oxide is selected from one or more of IGZO, IGZTO, IZO, and IGTO.

[0022] Optionally, in some embodiments of this application, the material of the gate insulating layer includes silicon oxide and / or silicon nitride.

[0023] Optionally, in some embodiments of this application, the material of the planarization layer is PFA.

[0024] Accordingly, embodiments of this application also provide a method for fabricating an array substrate, comprising the following steps:

[0025] Provide a substrate;

[0026] A gate is formed on the substrate.

[0027] A gate insulating layer is formed on the substrate and the gate;

[0028] An active layer is formed on the gate insulating layer;

[0029] A source and a drain are formed on the active layer;

[0030] A passivation layer is formed on the source and drain electrodes, the active layer, and the gate insulating layer;

[0031] A planarization layer is formed on the passivation layer;

[0032] A common electrode is formed on the planar layer; wherein the common electrode comprises a first conductive layer, a metal conductive layer and a second conductive layer formed in sequence.

[0033] Optionally, in some embodiments of this application, the material of the first conductive layer is indium tin oxide (ITO). The material of the metal conductive layer is copper (Cu). The material of the second conductive layer is indium tin oxide (ITO).

[0034] Optionally, in some embodiments of this application, the thickness of the first conductive layer is 400–800 angstroms. The thickness of the metallic conductive layer is 2000–4000 angstroms. The thickness of the second conductive layer is 100–200 angstroms.

[0035] Optionally, in some embodiments of this application, the active layer is made of a conductive metal oxide.

[0036] Optionally, in some embodiments of this application, the conductive metal oxide is selected from one or more of IGZO, IGZTO, IZO, and IGTO.

[0037] Optionally, in some embodiments of this application, the material of the gate insulating layer includes silicon oxide and / or silicon nitride.

[0038] Optionally, in some embodiments of this application, the material of the planarization layer is PFA.

[0039] In addition, this application embodiment also provides a display panel, including: an array substrate as described above, a pair of opposing substrates disposed opposite to the array substrate, and a liquid crystal layer sandwiched between the array substrate and the opposing substrate.

[0040] The beneficial effects of this application are as follows:

[0041] The array substrate of this application, by employing a structure of an oxide metal conductive layer / metal conductive layer / oxide metal conductive layer as a common electrode, effectively prevents the oxidation of the metal layer in the electrode and improves the stability of the array substrate device. Simultaneously, by adding an oxide metal conductive layer to prevent the oxidation of copper, the array substrate of this application can also reduce the etching steps in existing technologies, thereby reducing product costs. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of the structure of the array substrate provided in the embodiments of this application;

[0044] Figure 2This is a schematic diagram of the array substrate provided in the embodiments of this application during the fabrication process;

[0045] Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 This is a schematic diagram illustrating the fabrication process of the common electrode in the array substrate provided in this application embodiment;

[0046] Figure 8 This is a schematic diagram of the array substrate in Comparative Example 1 of this application. Detailed Implementation

[0047] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, in the description of this application, the term "comprising" means "including but not limited to". The terms first, second, third, etc. are used only as illustrative purposes and do not impose numerical requirements or establish an order. Various embodiments of the present invention may exist in the form of a range; it should be understood that the description in the form of a range is only for convenience and conciseness and should not be construed as a hard limitation on the scope of the present invention; therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single values ​​within that range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and single numbers within the range, such as 1, 2, 3, 4, 5 and 6, which applies regardless of the range. Additionally, whenever a numerical range is specified in this document, it means that any referenced number (fraction or integer) within the range is included.

[0048] The inventors of this application have discovered that if a typical process is used, namely, completing ITO patterning and heat treatment (annealing) before preparing Cu in the common electrode, Cu oxidation will not occur, resulting in good stability of the IGZO TFT; however, this process adds a Cu mask preparation step, increasing the cost.

[0049] This application provides an array substrate, a method for fabricating the same, and a display panel. These are described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0050] Please see Figure 1This application provides an array substrate 100, which includes a gate 110, a gate insulating layer 120, an active layer 130, a source 141, a drain 142, a passivation layer 150, a planarization layer 160 and a common electrode 170 disposed on a substrate 101.

[0051] In this embodiment, the common electrode 170 includes a first conductive layer 171, a metal conductive layer 172, and a second conductive layer 173 stacked sequentially. The second conductive layer 173 covers the metal conductive layer 172, effectively reducing the oxidation of the metal conductive layer 172.

[0052] The common electrode 170 is disposed on the planarization layer 160. Further, the first conductive layer 171 is disposed on the planarization layer 160, the metal conductive layer 172 is disposed on the first conductive layer 171, and the second conductive layer 173 is disposed on the metal conductive layer 172. Even further, the first conductive layer 171 covers or partially covers the planarization layer 160. The orthographic projection of the metal conductive layer 172 onto the first conductive layer 171 lies entirely on the first conductive layer 171; that is, the area of ​​the metal conductive layer 172 is smaller than the area of ​​the first conductive layer 171. The second conductive layer 173 covers the metal conductive layer 172, which can reduce the contact between the surface of the metal conductive layer 172 and air or oxygen.

[0053] In some embodiments of this application, the material of the first conductive layer 171 may be indium tin oxide (ITO). Further, the thickness of the first conductive layer 171 may be 400 angstroms, 450 angstroms, 500 angstroms, 550 angstroms, 600 angstroms, 650 angstroms, 700 angstroms, 750 angstroms, or 800 angstroms.

[0054] In some embodiments of this application, the material of the metal conductive layer 172 is copper (Cu). Further, the thickness of the metal conductive layer 172 can be 2000 angstroms, 2500 angstroms, 3000 angstroms, 3500 angstroms, or 4000 angstroms.

[0055] In some embodiments of this application, the material of the second conductive layer 173 is indium tin oxide (ITO). Further, the thickness of the second conductive layer 173 is 100 angstroms, 120 angstroms, 150 angstroms, 180 angstroms, or 200 angstroms.

[0056] In this embodiment, the gate 110 is disposed on the substrate 101. The gate insulating layer 120 is disposed on the gate 110. The active layer 130 is disposed on the gate insulating layer 120. The source 141 and the drain 142 are disposed on the active layer 130, and the source 141 and the drain 142 are disposed in the same layer and spaced apart from each other. The passivation layer 150 is disposed on the source 141 and the drain 142. The planarization layer 160 is disposed on the passivation layer 150; further, the planarization layer 160 covers or partially covers the passivation layer 150.

[0057] Furthermore, the active layer 130 is made of a conductive metal oxide. For example, the conductive metal oxide is selected from one or more of IGZO, IGZTO, IZO, and IGTO.

[0058] Furthermore, the material of the gate insulating layer 120 includes silicon oxide and / or silicon nitride.

[0059] Furthermore, the material of the planarization layer 160 may include PFA.

[0060] In this embodiment, the materials of the gate, source, drain, and passivation layer in the array substrate can be materials commonly used in the art.

[0061] This application also provides a method for fabricating an array substrate; please refer to the following embodiments. Figure 1 It includes the following steps:

[0062] A substrate 101 is provided;

[0063] A gate 110 is formed on the substrate 101;

[0064] A gate insulating layer 120 is formed on the substrate 101 and the gate 110;

[0065] An active layer 130 is formed on the gate insulating layer 120;

[0066] A source electrode 141 and a drain electrode 142 are formed on the active layer 130;

[0067] A passivation layer 150 is formed on the source 141 and drain 142, the active layer 130 and the gate insulating layer 120;

[0068] A planarization layer 160 is formed on the passivation layer 150;

[0069] A common electrode 170 is formed on the planarization layer 160; wherein the common electrode 170 includes a first conductive layer 171, a metal conductive layer 172 and a second conductive layer 173 formed in sequence.

[0070] In some embodiments of this application, combined with Figure 1 and Figure 2 The method for fabricating the array substrate includes the following steps:

[0071] A substrate 101 is provided;

[0072] A first metal layer is deposited on the substrate 101 to form a gate 110;

[0073] A gate insulating layer 120 is deposited on the substrate 101 and the gate 110;

[0074] A conductive metal oxide thin film is deposited on the gate insulating layer 120 and patterned to form an active layer 130;

[0075] A second metal layer is deposited and patterned on the active layer 130 and the gate insulating layer 120 to form a source 141 and a drain 142.

[0076] A passivation layer 150 is deposited on the source 141 and drain 142, the active layer 130 and the gate insulating layer 120;

[0077] A planarization layer 160 is deposited on the passivation layer 150;

[0078] A first conductive film 171a is deposited on the planarization layer 160 and the passivation layer 150, a metal conductive film 172a is deposited on the first conductive film 171a, and a second conductive film 173a is deposited on the metal conductive film 172a. A common electrode 170 is then obtained by patterning. For example, the common electrode can be obtained by etching.

[0079] Further, the first conductive film 171a, the metal conductive film 172a and the second conductive film 173a are etched to form the first conductive layer 171, the metal conductive layer 172 and the second conductive layer 173, which forms the common electrode 170 in the embodiments of this application.

[0080] Further, please refer to Figures 3 to 7 as well as Figure 1 The first conductive film 171a, the metal conductive film 172a, and the second conductive film 173a are patterned to obtain the first conductive layer 171, the metal conductive layer 172, and the second conductive layer 173.

[0081] For details, please continue reading Figures 3 to 7 as well as Figure 1 The fabrication process of the common electrode 170 includes the following steps:

[0082] Step 1: Please refer to Figure 3 As shown, after the first conductive film 171a, the metal conductive film 172a and the second conductive film 173a are sequentially deposited on the substrate 101, photoresist (PR) can be applied to the target area using a mask.

[0083] Step 2: Please refer to Figure 4 As shown, the portion of the second conductive film 173a not covered by photoresist and the portion of the metal conductive film 172a are etched. This step can utilize a fluorine (F)-containing acid to simultaneously etch the second conductive film (material such as ITO) and the metal conductive film, which can reduce the number of etching steps and thus reduce costs. For example, copper acid with a high fluorine (F) content can be used for etching.

[0084] Step 3: Please refer to Figure 5 As shown, the photoresist PR on the remaining metal conductive film is partially removed;

[0085] Step 4: Please refer to Figure 6 As shown, after removing part of the photoresist, the exposed portion of the first conductive film 171a and the portion of the second conductive film 173b obtained in the previous step are etched to obtain the first conductive layer 171 and the second conductive layer 173. This step can be divided into two steps to etch the two ITO layers separately or to etch the two ITO layers simultaneously in one step.

[0086] Step 5: Please refer to Figure 7 As shown, a portion of the metal conductive film 172b obtained in step 2 (without photoresist) is etched to obtain the metal conductive layer 172.

[0087] Step 6: Combining Figure 7 and Figure 1 Remove the top photoresist PR to form the array substrate of this application embodiment.

[0088] The common electrode in this embodiment can prevent the oxidation of copper, thus reducing the etching steps and consequently lowering production costs.

[0089] In some embodiments, the first conductive layer 171 is made of indium tin oxide (ITO). The metal conductive layer 172 is made of copper (Cu). The second conductive layer 173 is made of indium tin oxide (ITO). The thickness of the first conductive layer 171 is 400–800 angstroms. The thickness of the metal conductive layer 172 is 2000–4000 angstroms. The thickness of the second conductive layer 173 is 100–200 angstroms.

[0090] In some embodiments, the active layer 130 is made of a conductive metal oxide. The conductive metal oxide is selected from one or more of IGZO, IGZTO, IZO, and IGTO. The gate insulating layer 120 is made of silicon oxide and / or silicon nitride.

[0091] This application embodiment also provides a display panel, including: an array substrate as described above, a pair of opposing substrates disposed opposite to the array substrate, and a liquid crystal layer sandwiched between the array substrate and the opposing substrate.

[0092] This application has undergone multiple experiments, and some of the test results are presented here for reference to further describe the invention in detail. The following is a detailed description in conjunction with specific embodiments.

[0093] Example 1

[0094] This embodiment provides an array substrate 100. Please refer to [reference needed]. Figure 1 ,include:

[0095] Substrate 101,

[0096] A gate 110 is disposed on a substrate 101;

[0097] A gate insulating layer 120 is disposed on the gate 110 and the substrate 101;

[0098] An active layer 130 is disposed on the gate insulating layer 120; wherein the material of the active layer is IGZO;

[0099] Source 141 and drain 142 are disposed on the same layer of the active layer 130;

[0100] A passivation layer 150 is disposed on the source 141 and drain 142, and covers the active layer 130 and the gate insulating layer 120;

[0101] A planarization layer 160 is disposed on the passivation layer; the material of the planarization layer is PFA.

[0102] A common electrode 170 is disposed on the planarization layer 160. The common electrode 170 includes a first conductive layer 171, a metal conductive layer 172, and a second conductive layer 173 sequentially stacked on the planarization layer 160. In this embodiment, the metal conductive layer 172 is made of copper; the first conductive layer 171 and the second conductive layer 173 are made of indium tin oxide (ITO).

[0103] Comparative Example 1

[0104] This embodiment provides an array substrate 100'. Please refer to [link / reference]. Figure 8 ,include:

[0105] Substrate 101'

[0106] Gate 110' is disposed on substrate 101';

[0107] A gate insulating layer 120' is disposed on the gate 110';

[0108] An active layer 130' is disposed on the gate insulating layer 120';

[0109] The source electrode 141' and the drain electrode 142' are disposed on the same layer on the active layer 130';

[0110] A passivation layer 150' is disposed on the source electrode 141' and the drain electrode 142', and covers the active layer 130' and the gate insulating layer 120';

[0111] A planarization layer 160' is disposed on the passivation layer 150';

[0112] A common electrode 170' is disposed on the planarization layer 160'. The common electrode includes an ITO layer 171' and a metal layer (Cu) 172' stacked sequentially. It can be seen that the only difference between Comparative Example 1 and Example 1 is the structure of the common electrode.

[0113] In Comparative Example 1, the copper layer in the common electrode is prone to copper oxidation during the manufacturing process. To avoid copper oxidation, the copper layer is prepared after the ITO layer is patterned and annealed. This would significantly increase the copper mask preparation step and increase the production cost of the product.

[0114] However, using the array substrate of Embodiment 1 of this application, it can be found that the structure of the common electrode in the array substrate can not only effectively avoid the problem of copper oxidation, but also avoid the problem of increased manufacturing costs due to copper oxidation.

[0115] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0116] In summary, the common electrode in the array substrate of this application adopts a structure of metal oxide conductive layer / metal conductive layer / metal oxide conductive layer. This structure can effectively prevent the metal layer in the electrode from being oxidized, thereby improving the stability of the array substrate device. At the same time, the array substrate of this application prevents the oxidation of copper metal, which can reduce etching steps and thus reduce product costs.

[0117] The above provides a detailed description of an array substrate, its fabrication method, and a display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, those skilled in the art will recognize that there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An array substrate, characterized in that, include: Substrate A gate is disposed on the substrate. A gate insulating layer is disposed on the gate; An active layer is disposed on the gate insulating layer. The source and drain are disposed on the active layer; A passivation layer is disposed on the source and drain electrodes; A planarization layer is placed on top of the passivation layer; A common electrode is disposed on the planarization layer; and the common electrode includes a first conductive layer, a metal conductive layer and a second conductive layer stacked sequentially. Wherein, the material of the first conductive layer is indium tin oxide; the material of the metal conductive layer is copper; and the material of the second conductive layer is indium tin oxide. The thickness of the first conductive layer is 400-800 angstroms; the thickness of the metal conductive layer is 2000-4000 angstroms; and the thickness of the second conductive layer is 100-200 angstroms.

2. The array substrate according to claim 1, characterized in that, The active layer is made of a conductive metal oxide. The conductive metal oxide is selected from one or more of IGZO, IGZTO, IZO, and IGTO.

3. The array substrate according to claim 1, characterized in that, The material of the gate insulating layer includes silicon oxide and / or silicon nitride.

4. A method for fabricating an array substrate, characterized in that, Includes the following steps: Provide a substrate; A gate is formed on the substrate. A gate insulating layer is formed on the substrate and the gate; An active layer is formed on the gate insulating layer; A source and a drain are formed on the active layer; A passivation layer is formed on the source and drain electrodes, the active layer, and the gate insulating layer; A planarization layer is formed on the passivation layer; A common electrode is formed on the planar layer; wherein the common electrode comprises a first conductive layer, a metal conductive layer and a second conductive layer formed by sequentially stacking layers; Wherein, the material of the first conductive layer is indium tin oxide; the material of the metal conductive layer is copper; and the material of the second conductive layer is indium tin oxide. The thickness of the first conductive layer is 400-800 angstroms; the thickness of the metal conductive layer is 2000-4000 angstroms; and the thickness of the second conductive layer is 100-200 angstroms.

5. A display panel, characterized in that, include: An array substrate as described in any one of claims 1 to 3 or an array substrate prepared by the preparation method described in claim 4, a pair of opposing substrates disposed opposite to the array substrate, and a liquid crystal layer sandwiched between the array substrate and the opposing substrate.

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