Driving backboard, preparation method thereof and display panel

Abstract

The application discloses a driving backboard, a preparation method thereof and a display panel. The driving backboard comprises a substrate, an active layer, a source electrode, a drain electrode, a gate electrode, a metal oxide barrier portion and a transparent electrode arranged on the substrate. The source electrode and the drain electrode are arranged on the active layer and connected with the active layer respectively. The gate electrode is located on one side of the active layer close to or away from the source electrode. The metal oxide barrier portion is arranged on one side of the source electrode away from the active layer, covers the source electrode and is in contact with the surface of the source electrode. The transparent electrode is arranged on one side of the drain electrode away from the active layer and connected with the drain electrode. The application reduces the process manufacturing cost of the driving backboard under the premise of improving the electrical performance of the thin film transistor.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a driving backplane and its preparation method, and a display panel. Background Technology

[0002] In existing driving backplanes, a planarization layer is usually placed above the thin-film transistor. The planarization layer can protect the electrodes in the thin-film transistor, such as the source, from external water and oxygen erosion, thereby improving the electrical performance of the thin-film transistor. However, the addition of the planarization layer will increase the manufacturing cost. Summary of the Invention

[0003] This application provides a driving backplane and its preparation method, as well as a display panel, which eliminates the need for a planarization layer above the thin-film transistor while protecting the source electrode from external water and oxygen corrosion, thereby improving the electrical performance of the thin-film transistor and reducing the manufacturing cost of the driving backplane.

[0004] This application provides a drive backplane, which includes:

[0005] substrate;

[0006] An active layer is disposed on the substrate;

[0007] A source and a drain are disposed on the active layer, and the source and the drain are respectively connected to the active layer;

[0008] A gate is disposed on the substrate and located on the side of the active layer that is close to or far from the source electrode;

[0009] A metal oxide barrier portion is disposed on the side of the source electrode away from the active layer, the metal oxide barrier portion covering the source electrode and contacting the surface of the source electrode; and

[0010] A transparent electrode is disposed on the side of the drain electrode away from the active layer and connected to the drain electrode.

[0011] Optionally, in some embodiments of this application, the source electrode includes a source electrode portion, the metal oxide barrier portion is in contact with the source electrode portion, and the metal element in the source electrode portion is the same as the metal element in the metal oxide barrier portion.

[0012] Optionally, in some embodiments of this application, the material of the metal oxide barrier includes oxygen.

[0013] Optionally, in some embodiments of this application, the transparent electrode is in contact with the surface of the drain electrode away from the active layer.

[0014] Optionally, in some embodiments of this application, the gate is located on the side of the active layer away from the source, and the driving backplane further includes a gate insulating layer disposed between the gate and the active layer;

[0015] The drive backplane also includes a passivation layer disposed between the active layer and the source electrode. The passivation layer has a first via and a second via, both of which expose the active layer. The source electrode is connected to the active layer through the first via, and the drain electrode is connected to the active layer through the second via.

[0016] This application provides a display panel, which includes a driving backplate as described in any of the embodiments and a light-emitting structure disposed on the driving backplate.

[0017] This application also provides a method for preparing a drive backplate, which includes the following steps:

[0018] Provide substrate;

[0019] An active layer is formed on the substrate;

[0020] Conductive electrodes and drain electrodes are formed at intervals on the active layer;

[0021] A transparent electrode is formed on the drain electrode, and the transparent electrode is connected to the drain electrode; and

[0022] The conductive electrode is partially oxidized, and the oxidized portion of the conductive electrode forms a metal oxide barrier portion, while the unoxidized portion of the conductive electrode forms a source electrode. The metal oxide barrier portion covers the source electrode and is in contact with the surface of the source electrode.

[0023] Optionally, in some embodiments of this application, the thickness of the metal oxide barrier is one-quarter to one-half the thickness of the conductive electrode.

[0024] Optionally, in some embodiments of this application, the step of forming a spaced-apart conductive electrode and a drain electrode on the active layer includes:

[0025] A passivation layer is formed on the active layer;

[0026] A photoresist layer is formed on the passivation layer, and a first opening and a second opening are formed in the photoresist layer to expose the passivation layer;

[0027] Using the photoresist layer as a mask, the passivation layer is etched to form a first via and a second via on the passivation layer that expose the active layer. The first via is connected to the first opening, and the second via is connected to the second opening.

[0028] A source / drain metal layer is formed on the photoresist layer, and the source / drain metal layer fills the first opening, the first via, the second opening, and the second via;

[0029] The portion of the photoresist layer and the portion of the source / drain metal layer located on the photoresist layer are stripped off. The portion of the source / drain metal layer corresponding to the first opening is formed as a conductive electrode. The conductive electrode is connected to the active layer through the first via. The portion of the source / drain metal layer corresponding to the second opening is formed as a drain electrode. The drain electrode is connected to the active layer through the second via.

[0030] Optionally, in some embodiments of this application, the closed cross-sectional shape of the first opening and the closed cross-sectional shape of the second opening are both inverted trapezoids in the direction perpendicular to the plane of the substrate.

[0031] Optionally, in some embodiments of this application, the step of forming an active layer on the substrate includes:

[0032] A gate metal layer, a gate insulating layer, and an active layer are sequentially formed on the substrate.

[0033] The gate metal layer, the gate insulating layer, and the active layer on the entire surface are patterned using the same photomask to form the gate, the patterned gate insulating layer, and the patterned active layer, respectively.

[0034] Compared to existing drive backplanes, the drive backplane provided in this application protects the source electrode from external water and oxygen corrosion by providing a metal oxide barrier on the source electrode surface. This prevents source electrode corrosion and improves the conductivity of the source electrode, thereby enhancing the electrical performance of the thin-film transistor. Since the metal oxide barrier effectively prevents source electrode corrosion, this application eliminates the need for the planarization layer above the source electrode in existing technologies, thus reducing the manufacturing cost of the drive backplane. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. The accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the drive backplane provided in the first embodiment of this application.

[0037] Figure 2 yes Figure 1 The diagram shows the structure of the source electrode and the metal oxide barrier in the drive backplane.

[0038] Figure 3 This is a schematic diagram of the drive backplane provided in the second embodiment of this application.

[0039] Figure 4 This is a schematic diagram of the structure of the display panel provided in this application.

[0040] Figure 5 This is a schematic flowchart of the method for fabricating the drive backplate provided in this application.

[0041] Figures 6A to 6L This is a schematic diagram of the structure obtained sequentially in the preparation method of the driving backplate provided in Example 1 of this application.

[0042] Figures 7A to 7D This is a schematic diagram of the relevant steps in the fabrication method of the driving backplate provided in Example 2 of this application.

[0043] Figures 8A to 8P This is a schematic diagram of the structure obtained sequentially in the preparation method of the driving backplate provided in Example 3 of this application.

[0044] Figures 9A to 9D This is a schematic diagram of the relevant steps in the fabrication method of the driving backplate provided in Example 4 of this application. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0046] This application provides a driving backplane, its manufacturing method, and a display panel. These will be described in detail below.

[0047] This application provides a driving backplane, which includes a substrate and an active layer, a source electrode, a drain electrode, a gate electrode, a metal oxide barrier portion, and a transparent electrode disposed on the substrate. The source electrode and drain electrode are disposed on the active layer and are respectively connected to the active layer; the gate electrode is located on the side of the active layer near or away from the source electrode; the metal oxide barrier portion is disposed on the side of the source electrode away from the active layer, covering the source electrode and contacting its surface; the transparent electrode is disposed on the side of the drain electrode away from the active layer and is connected to the drain electrode.

[0048] Therefore, the driving backplane provided in this application protects the source electrode from external water and oxygen corrosion by providing a metal oxide barrier on the source electrode surface. This prevents source electrode corrosion and improves the conductivity of the source electrode, thereby enhancing the electrical performance of the thin-film transistor. Since the metal oxide barrier effectively prevents source electrode corrosion, this application eliminates the need for the planarization layer above the source electrode in existing technologies, thus reducing the manufacturing cost of the driving backplane.

[0049] The driving backplane provided in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of embodiments.

[0050] Please refer to Figure 1 and Figure 2 The first embodiment of this application provides a driving backplane 100. The driving backplane 100 includes a substrate 10 and a gate 11, a gate insulating layer 12, an active layer 13, a source 14, a drain 15, a metal oxide barrier portion 16, and a transparent electrode 17 disposed on the substrate 10. The gate 11, the active layer 13, the source 14, and the drain 15 constitute a thin-film transistor.

[0051] It should be noted that the thin-film transistor in this application can be a bottom-gate thin-film transistor or a top-gate thin-film transistor. The embodiments in this application are only described using a bottom-gate thin-film transistor as an example, but should not be construed as limiting this application.

[0052] Specifically, the substrate 10 can be a rigid substrate, such as a glass substrate; or the substrate 10 can be a flexible substrate, such as a polyimide substrate. This application does not specifically limit the material of the substrate 10.

[0053] A gate 11 is disposed on a substrate 10. The material of the gate 11 may include one or more of copper, aluminum, molybdenum and titanium, or may include an alloy composed of at least two of the above materials.

[0054] A gate insulating layer 12 is disposed on the side of the gate 11 away from the substrate 10. In this embodiment, the gate insulating layer 12 is disposed over its entire surface. The material of the gate insulating layer 12 may include one or more of silicon oxide, silicon nitride, or silicon oxynitride.

[0055] The active layer 13 is disposed on the side of the gate insulating layer 12 away from the gate 11. The material of the active layer 13 can be a metal oxide, such as IGZO, IGZTO, IGTO, IZTO, ITO or IZO, or it can be amorphous silicon, low-temperature polycrystalline silicon or organic materials, etc. This application does not specifically limit the material of the active layer 13.

[0056] The source electrode 14 and the drain electrode 15 are disposed on the side of the active layer 13 away from the gate insulating layer 12, and are respectively connected to the active layer 13. The source electrode 14 and the drain electrode 15 are made of the same material, which may include one or more of copper, aluminum, molybdenum, and titanium, or may include an alloy composed of at least two of the above materials. In this embodiment, the thickness of the source electrode 14 is less than the thickness of the drain electrode 15.

[0057] A metal oxide barrier portion 16 is disposed on the side of the source electrode 14 away from the active layer 13. The metal oxide barrier portion 16 covers the source electrode 14 and is in contact with the surface of the source electrode 14. With the above configuration, this embodiment protects the source electrode 14 from external water and oxygen corrosion by utilizing the barrier effect of the metal oxide barrier portion 16, thereby preventing corrosion of the source electrode 14 and improving the conductivity of the source electrode 14, thus improving the electrical performance of the thin-film transistor. Based on this, this embodiment can eliminate the planarization layer above the source electrode 14 in the prior art, thereby reducing the manufacturing cost of the drive backplane 100.

[0058] Specifically, the material of the metal oxide barrier portion 16 includes one or more of aluminum oxide, chromium oxide, molybdenum oxide, or titanium oxide. Since these metal oxides all possess good density, they can effectively block the intrusion of external water and oxygen, thereby preventing corrosion of the source electrode 14 and improving its conductivity.

[0059] In this embodiment, the source electrode 14 includes a first source electrode portion 141. A metal oxide barrier portion 16 is in contact with the first source electrode portion 141. The material of the first source electrode portion 141 can be a metal such as aluminum, chromium, molybdenum, or titanium, or it can be an alloy composed of at least two of the aforementioned metals.

[0060] Furthermore, the metal element in the metal oxide barrier portion 16 is the same as the metal element in the first source portion 141, and the metal element can be molybdenum, aluminum, titanium, or chromium. In this embodiment, the metal oxide barrier portion 16 and the first source portion 141 can be formed simultaneously to save manufacturing costs. Specifically, a conductive electrode can be formed first, and then the surface of the conductive electrode can be oxidized. The oxidized portion of the conductive electrode forms the metal oxide barrier portion 16, and the unoxidized portion of the conductive electrode forms the first source portion 141. In some embodiments, the metal oxide barrier portion 16 and the first source portion 141 can also be formed separately, that is, the metal oxide barrier portion 16 is formed separately after the first source portion 141 is formed, which will not be elaborated further here.

[0061] like Figure 2 As shown, the source electrode 14 also includes a second source electrode portion 142 and a third source electrode portion 143, with the second source electrode portion 142 located between the first source electrode portion 141 and the third source electrode portion 143. The material of the second source electrode portion 142 can be copper. The third source electrode portion 143 has a buffering function and can be used to improve the adhesion between the source electrode 14 and the active layer 13. The material of the third source electrode portion 143 can be conductive materials such as molybdenum, titanium, niobium, molybdenum-titanium alloy, molybdenum-niobium alloy, indium tin oxide, or indium zinc oxide.

[0062] In this embodiment, the drive backplane 100 further includes a passivation layer 18. The passivation layer 18 is disposed between the active layer 13 and the source electrode 14. A first via 181 and a second via 182 are formed on the passivation layer 18. Both the first via 181 and the second via 182 expose the active layer 13. The source electrode 14 is connected to the active layer 13 through the first via 181. The drain electrode 15 is connected to the active layer 13 through the second via 182.

[0063] Understandably, existing thin-film transistors (TFTs) driving backplanes 100 typically include back-channel etched TFTs, etch-block TFTs, and top-gate TFTs, with back-channel etched TFTs and etch-block TFTs being the industry's preferred types. Furthermore, etch-block TFTs incorporate a back-channel protection section 20 to effectively prevent damage to the channel during the etching processes of the source 14 and drain 15, thereby enabling wider applications for etch-block TFTs. However, the inclusion of the back-channel protection section 20 increases the number of process steps required for etch-block TFTs, thus increasing process costs.

[0064] To address the aforementioned technical problems in the prior art, this embodiment provides a passivation layer 18 between the active layer 13 and the source electrode 14. Before forming the source electrode 14, the active layer 13 is protected by the passivation layer 18. Therefore, during the formation of the source electrode 14, the etching process does not damage the channel of the active layer 13, thereby improving the electrical stability of the thin-film transistor. Furthermore, since this embodiment eliminates the back channel protection portion 20 provided for separately protecting the active layer 13 in the prior art etch-blocking thin-film transistors, the manufacturing process is simplified, thereby reducing process costs.

[0065] Furthermore, in this embodiment, the transparent electrode 17 and the drain electrode 15 are in contact with the surface away from the active layer 13. With the above configuration, this embodiment can eliminate the need for an insulating layer between the drain electrode 15 and the transparent electrode 17, thereby further reducing the manufacturing cost of the drive backplane 100.

[0066] The transparent electrode 17 can be made of indium tin oxide. It should be noted that the transparent electrode 17 can be a pixel electrode or a connection electrode. When the transparent electrode 17 is a connection electrode, it is used to connect the drain electrode 15 to an external light-emitting element.

[0067] It should be noted that, in this embodiment, the driving backplane 100 further includes a power signal trace 19. The power signal trace 19 includes a first trace 191 and a second trace 192. The first trace 191 is on the same layer as the gate 11 and spaced apart, and the second trace 192 is on the same layer as the drain 15 and spaced apart. The second trace 192 is connected to the first trace 191 through a third via 183 in the passivation layer 18. A protective portion 20 is provided on the surface of the power signal trace 19 to protect it from corrosion. The material of the protective portion 20 is the same as that of the metal oxide barrier portion 16. Technical details of the protective portion 20 can be found in the aforementioned description of the metal oxide barrier portion 16, and will not be repeated here.

[0068] Please refer to Figure 3 The second embodiment of this application provides a driving backplane 100. The driving backplane 100 provided in the second embodiment of this application differs from that in the first embodiment in that: the orthographic projection of the gate insulating layer 12 onto the plane where the substrate 10 is located is located within the orthographic projection of the gate 11 onto the plane where the substrate 10 is located, and the gate 11, the gate insulating layer 12, and the active layer 13 are fabricated under the same photomask.

[0069] This embodiment reduces the number of photomasks used in the manufacturing process of the drive backplane 100 by fabricating the gate 11, gate insulating layer 12 and active layer 13 under the same photomask, thereby further saving the manufacturing cost of the drive backplane 100.

[0070] Please refer to Figure 4 This application also provides a display panel 1000. The display panel 1000 includes a driving back plate 100 and a light-emitting structure 200 disposed on the driving back plate 100. The driving back plate 100 can be the driving back plate 100 described in the first or second embodiment above. The structure of the driving back plate 100 can be referred to the description of the first or second embodiment above, and will not be repeated here.

[0071] It should be noted that the display panel 1000 can be a liquid crystal display panel, an organic light-emitting diode display panel, a miniature light-emitting diode display panel, or a micro light-emitting diode display panel. This application does not limit the type of the display panel 1000.

[0072] Please refer to Figure 5 This application also provides a method for preparing a drive backplate, which includes the following steps:

[0073] 101: Provide substrate;

[0074] 102: An active layer is formed on the substrate;

[0075] 103: Conductive electrodes and drain electrodes are formed at intervals on the active layer;

[0076] 104: A transparent electrode is formed on the drain electrode, and the transparent electrode is connected to the drain electrode; and

[0077] 105: The conductive electrode is partially oxidized. The oxidized part of the conductive electrode forms a metal oxide barrier, and the unoxidized part of the conductive electrode is the source electrode. The metal oxide barrier covers the source electrode and is in contact with the surface of the source electrode.

[0078] Therefore, in the display panel fabrication method provided in this application, conductive electrodes are pre-formed on the active layer, and then the conductive electrodes are partially oxidized to simultaneously form a source electrode and a metal oxide barrier covering the source electrode. The metal oxide barrier protects the source electrode from external water and oxygen corrosion, thereby preventing source electrode corrosion and improving the conductivity of the source electrode, thus enhancing the electrical performance of the thin-film transistor. Since the formation of the metal oxide barrier effectively prevents source electrode corrosion, this application eliminates the need for the planarization layer above the source electrode in the prior art, thereby reducing the manufacturing cost of the drive backplane.

[0079] The method for preparing the drive backplane provided in this application will be described in detail below through specific embodiments.

[0080] Please refer to Figures 6A to 6L Example 1 of this application provides a method for manufacturing a drive backplate 100, which includes the following steps:

[0081] 201: Provide substrate 10, such as Figure 6A As shown.

[0082] Specifically, the substrate 10 can be a rigid substrate, such as a glass substrate; or the substrate 10 can be a flexible substrate, such as a polyimide substrate. This application does not specifically limit the material of the substrate 10.

[0083] 202: A gate 11, a gate insulating layer 12, and an active layer 13 are sequentially formed on the substrate 10, such as... Figures 6B to 6D As shown.

[0084] First, a gate electrode 11 is formed on the substrate 10 sequentially using physical vapor deposition and photolithography processes, such as... Figure 6B As shown. The material of the gate 11 may include one or more of copper, aluminum, molybdenum, and titanium, or may include an alloy composed of at least two of the above materials. In this embodiment, while forming the gate 11, a first trace 191, at the same layer as and spaced apart from the gate 11, is also formed on the substrate 10. The first trace 191 is used to transmit power signals.

[0085] Next, a gate insulating layer 12 is formed on the gate 11 using a chemical vapor deposition process, such as... Figure 6C As shown. The gate insulating layer 12 is formed over its entire surface. The material of the gate insulating layer 12 may include one or more of silicon oxide, silicon nitride, or silicon oxynitride.

[0086] Finally, an active layer 13 is formed on the gate insulating layer 12 using physical vapor deposition and photolithography processes, as follows: Figure 6D As shown. The active layer 13 can be a metal oxide, such as IGZO, IGZTO, IGTO, IZTO, ITO or IZO, or it can be amorphous silicon, low-temperature polycrystalline silicon or organic materials, etc. This application does not specifically limit the material of the active layer 13.

[0087] 203: A passivation layer 18 is formed on the active layer 13, such as... Figure 6E As shown.

[0088] Specifically, a passivation layer 18 is formed using a chemical vapor deposition process. The passivation layer 18 covers the active layer 13 and the gate insulating layer 12, such as... Figure 6E As shown. The material of the passivation layer 18 may include one or more of silicon oxide, silicon nitride, or silicon oxynitride.

[0089] 204: The passivation layer 18 is patterned to form a first via 181 and a second via 182 exposing the active layer 13, such as... Figures 6F to 6H As shown.

[0090] Step 204 specifically includes the following steps:

[0091] 2041: A photoresist layer 30 is formed on the passivation layer 18, and the photoresist layer 30 is etched to form a first opening 301, a second opening 302, and a third opening 303 exposing the passivation layer 18, as shown. Figure 6F As shown. The photoresist layer 30 is made of positive photoresist. In the direction perpendicular to the plane of the substrate 10, the closed cross-sectional shape of the first opening 301, the closed cross-sectional shape of the second opening 302, and the closed cross-sectional shape of the third opening 303 are all trapezoidal.

[0092] 2042: Using the photoresist layer 30 as a mask, the passivation layer 18 and the gate insulating layer 12 are etched to form a first via 181, a second via 182, and a third via 183 on the passivation layer 18. The first via 181 connects to the first opening 301, the second via 182 connects to the second opening 302, and both the first via 181 and the second via 182 expose the active layer 13. The third via 183 connects to the third opening 303, and the third via 183 penetrates the gate insulating layer 12 and exposes the first trace 191. Figure 6G As shown.

[0093] 2043: Peel off photoresist layer 30, as shown Figure 6H As shown.

[0094] 205: Conductive electrodes 14a and drain 15 are formed on the passivation layer 18 at intervals, such as Figure 6I and Figure 6J As shown.

[0095] First, a source / drain metal layer 14A is formed on the passivation layer 18 using a physical vapor deposition process. The source / drain metal layer 14A fills the first via 181, the second via 182, and the third via 183, as follows: Figure 6I As shown; next, the source / drain metal layer 14A is etched to form a conductive electrode 14a, a drain electrode 15, and a second trace portion 19a. The conductive electrode 14a is connected to the active layer 13 through a first via 181, the drain electrode 15 is connected to the active layer 13 through a second via 182, and the second trace portion 19a is connected to the first trace 191 through a third via 183, as shown. Figure 6J As shown.

[0096] 206: A transparent electrode 17 is formed on the drain electrode 15, such as Figure 6K As shown.

[0097] The transparent electrode 17 is formed sequentially using physical vapor deposition and photolithography. The material of the transparent electrode 17 can be indium tin oxide.

[0098] 207: Partial oxidation is performed on the conductive electrode 14a. The oxidized portion of the conductive electrode 14a forms a metal oxide barrier portion 16, and the unoxidized portion of the conductive electrode 14a forms the source electrode 14. The metal oxide barrier portion 16 covers the first source electrode portion 141 in the source electrode 14 and contacts the surface of the first source electrode portion 141, such as... Figure 6L As shown.

[0099] In this embodiment, the oxidation method for the conductive electrode 14a can be anodizing. Specifically, the anodizing method includes the following steps: placing the structure after the formation of the conductive electrode 14a in an electrolytic cell, wherein the electrolyte in the electrolytic cell is a mixture of ammonium tartrate, ethylene glycol, and water; and applying an electric current to the conductive electrode 14a to oxidize its surface. The degree of oxidation of the conductive electrode 14a is controlled by the voltage applied to the conductive electrode 14a and the current value of the conductive electrode 14a, i.e., controlling the thickness of the metal oxide barrier portion 16 formed after oxidation.

[0100] In this embodiment, the thickness of the metal oxide barrier portion 16 is one-quarter to one-half the thickness of the conductive electrode 14a. Within this range, while improving the water and oxygen barrier effect of the metal oxide barrier portion 16, good conductivity of the source electrode 14 can also be guaranteed. In some specific embodiments, the thickness of the metal oxide barrier portion 16 is one-quarter, one-third, or one-half the thickness of the conductive electrode 14a. In this embodiment, the thickness of the metal oxide barrier portion 16 is one-half the thickness of the conductive electrode 14a. Specifically, the thickness of the conductive electrode 14a can be 200 nm, the thickness of the metal oxide barrier portion 16 can be 100 nm, and in this case, the thickness of the source electrode 14 is also 100 nm.

[0101] It should be noted that while oxidizing the conductive electrode 14a, the second trace portion 19a is also partially oxidized. The oxidation method for the second trace portion 19a is the same as that for the conductive electrode 14a. After partial oxidation of the second trace portion 19a, the oxidized portion forms the protective portion 20, and the unoxidized portion forms the second trace 192. The protective portion 20 covers the second trace 192, and the second trace 192 and the first trace 191 constitute the power signal trace 19.

[0102] Thus, the fabrication method of the driving backplane 100 described in this embodiment is completed. In the fabrication method of the driving backplane 100 provided in this embodiment, photomasks are only used when fabricating the gate 11, active layer 13, passivation layer 18, drain 15, and transparent electrode 17. That is, this embodiment only requires five photomasks to complete the fabrication process of the driving backplane 100. Therefore, compared with the driving backplane 100 fabrication process in the prior art, this embodiment greatly reduces the number of photomasks used, thereby saving process costs.

[0103] Please refer to Figures 7A to 7D Example 2 of this application provides a method for fabricating a drive backplane 100. The method for fabricating the drive backplane 100 provided in Example 2 differs from that in Example 1 in that:

[0104] First, the photoresist layer 30 is made of a reversible photoresist. In steps 2041 and 2042, in the direction perpendicular to the plane of the substrate 10, the closed cross-sectional shapes of the first opening 301, the second opening 302, and the third opening 303 are all inverted trapezoids, as shown below... Figure 7A and Figure 7B As shown.

[0105] Second, step 2043 is omitted.

[0106] Third, step 205 specifically includes the following steps: First, a source / drain metal layer 14A is formed on the photoresist layer 30 using a physical vapor deposition process. The source / drain metal layer 14A fills the first opening 301, the second opening 302, the third opening 303, the first via 181, the second via 182, and the third via 183, as shown below. Figure 7C As shown; next, the portion of photoresist layer 30 and source / drain metal layer 14A above photoresist layer 30 is stripped off. The portion of source / drain metal layer 14A corresponding to the first opening 301 is formed as a conductive electrode 14a, which is connected to active layer 13 through first via 181. The portion of source / drain metal layer 14A corresponding to the second opening 302 is formed as a drain electrode 15, which is connected to active layer 13 through second via 182. The portion of source / drain metal layer 14A corresponding to the third opening 303 is formed as a second trace portion 19a, which is connected to first trace 191 through third via 183, as shown. Figure 7D As shown.

[0107] In the fabrication method of the drive backplane 100 in this embodiment, since a photomask is not required when forming the conductive electrode 14a and the drain electrode 15, this embodiment can save one photomask, and thus the process of fabricating the drive backplane 100 can be completed with four photomasks.

[0108] Please refer to Figures 8A to 8PExample 3 of this application provides a method for preparing a drive backplate 100, which includes the following steps:

[0109] 301: Provides substrate 10, such as Figure 8A As shown.

[0110] Specifically, the substrate 10 can be a rigid substrate, such as a glass substrate; or the substrate 10 can be a flexible substrate, such as a polyimide substrate. This application does not specifically limit the material of the substrate 10.

[0111] 302: A gate 11, a gate insulating layer 12, and an active layer 13 are formed on the substrate 10, such as... Figures 8B to 8H As shown.

[0112] Step 302 specifically includes the following steps:

[0113] First, a full-surface gate metal layer 11A, a gate insulating layer 12, and an active layer 13 are sequentially formed on the substrate 10, such as... Figure 8B As shown.

[0114] First, a gate metal layer 11A is formed using a physical vapor deposition (PVD) process. The material of the gate metal layer 11A may include one or more of copper, aluminum, molybdenum, and titanium, or an alloy composed of at least two of these materials. Next, a gate insulating layer 12 is formed on the gate metal layer 11A using a chemical vapor deposition (CVD) process. The gate insulating layer 12 is formed over its entire surface. The material of the gate insulating layer 12 may include one or more of silicon oxide, silicon nitride, or silicon oxynitride. Finally, an active layer 13 is formed on the gate insulating layer 12 using a physical vapor deposition (PVD) process. The material of the active layer 13 may be a metal oxide, such as IGZO, IGZTO, IGTO, IZTO, ITO, or IZO, or it may be amorphous silicon, low-temperature polycrystalline silicon, or an organic material. This application does not specifically limit the material of the active layer 13.

[0115] Second, a first photoresist layer 40 is formed on the active layer 13, and a halftone mask (not shown in the figure) is used to form a first photoresist portion 41 and a second photoresist portion 42 with different thicknesses, as shown in the figure. Figure 8C and Figure 8D As shown.

[0116] Third, using the first photoresist portion 41 and the second photoresist portion 42 as masks, the active layer 13, the gate insulating layer 12, and the gate metal layer 11A are etched sequentially to obtain the following... Figure 8E The structure shown has a patterned gate 11, a gate insulating layer 12 and an active layer 13 formed below the first photoresist portion 41, and a first trace 191 formed below the second photoresist portion 42.

[0117] Fourth, the second photoresist portion 42 is removed by an ashing process, and the first photoresist portion 41 is thinned to obtain the following result: Figure 8F The structure shown.

[0118] Fifth, using the thinned first photoresist portion 41 as a mask, the active layer portion on the first trace 191 is etched to form a shape as shown in the image. Figure 8G The structure shown.

[0119] Sixth, the thinned first photoresist portion 41 is peeled off to form a shape like... Figure 8H The structure shown.

[0120] 303: A passivation layer 18 is formed on the active layer 13, such as... Figure 8I As shown.

[0121] Specifically, a passivation layer 18 is formed using a chemical vapor deposition process. The material of the passivation layer 18 may include one or more of silicon oxide, silicon nitride, or silicon oxynitride.

[0122] 304: The passivation layer 18 is patterned to form a first via 181 and a second via 182 exposing the active layer 13, such as... Figure 8J and Figure 8K As shown.

[0123] Step 304 specifically includes the following steps:

[0124] 3041: A second photoresist layer 50 is formed on the passivation layer 18, and the second photoresist layer 50 is etched to form a first opening 501, a second opening 502, and a third opening 503 exposing the passivation layer 18, as shown. Figure 8J As shown. The material of the second photoresist layer 50 is positive photoresist. In the direction perpendicular to the plane of the substrate 10, the closed cross-sectional shape of the first opening 501, the closed cross-sectional shape of the second opening 502, and the closed cross-sectional shape of the third opening 503 are all trapezoidal.

[0125] 3042: Using the second photoresist layer 50 as a mask, the passivation layer 18 is etched to form a first via 181, a second via 182, and a third via 183 on the passivation layer 18. The first via 181 connects to the first opening 501, the second via 182 connects to the second opening 502, and both the first via 181 and the second via 182 expose the active layer 13. The third via 183 connects to the third opening 503, and the third via 183 penetrates the gate insulating layer 12 and exposes the first trace 191. Figure 8K As shown.

[0126] 3043: Peel off the second photoresist layer 50 to form as shown Figure 8L The structure shown.

[0127] 305: Conductive electrodes 14a and drain 15 are formed at intervals on the passivation layer 18, such as... Figure 8M and Figure 8N As shown.

[0128] First, a source / drain metal layer 14A is formed on the passivation layer 18 using a physical vapor deposition process. The source / drain metal layer 14A fills the first via 181, the second via 182, and the third via 183, as follows: Figure 8M As shown; next, the source / drain metal layer 14A is etched to form a conductive electrode 14a, a drain electrode 15, and a second trace portion 19a. The conductive electrode 14a is connected to the active layer 13 through a first via 181, the drain electrode 15 is connected to the active layer 13 through a second via 182, and the second trace portion 19a is connected to the first trace 191 through a third via 183, as shown. Figure 8N As shown.

[0129] 306: A transparent electrode 17 is formed on the drain electrode 15, such as Figure 8O As shown.

[0130] The transparent electrode 17 is formed sequentially using physical vapor deposition and photolithography. The material of the transparent electrode 17 can be indium tin oxide.

[0131] 307: Partial oxidation is performed on the conductive electrode 14a. The oxidized portion of the conductive electrode 14a forms a metal oxide barrier portion 16, and the unoxidized portion of the conductive electrode 14a forms the source electrode 14. The metal oxide barrier portion 16 covers the first source electrode portion 141 in the source electrode 14 and contacts the surface of the first source electrode portion 141, such as... Figure 8P As shown.

[0132] In this embodiment, the oxidation method for the conductive electrode 14a can be anodizing. Specifically, the anodizing method includes the following steps: placing the structure after the formation of the conductive electrode 14a in an electrolytic cell, wherein the electrolyte in the electrolytic cell is a mixture of ammonium tartrate, ethylene glycol, and water; and applying an electric current to the conductive electrode 14a to oxidize its surface. The degree of oxidation of the conductive electrode 14a is controlled by the voltage applied to the conductive electrode 14a and the current value of the conductive electrode 14a, i.e., controlling the thickness of the metal oxide barrier portion 16 formed after oxidation.

[0133] In this embodiment, the thickness of the metal oxide barrier portion 16 is one-quarter to one-half the thickness of the conductive electrode 14a. Within this range, while improving the water and oxygen barrier effect of the metal oxide barrier portion 16, good conductivity of the source electrode 14 can also be guaranteed. In some specific embodiments, the thickness of the metal oxide barrier portion 16 is one-quarter, one-third, or one-half the thickness of the conductive electrode 14a. In this embodiment, the thickness of the metal oxide barrier portion 16 is one-half the thickness of the conductive electrode 14a. Specifically, the thickness of the conductive electrode 14a can be 200 nm, the thickness of the metal oxide barrier portion 16 can be 100 nm, and in this case, the thickness of the source electrode 14 is also 100 nm.

[0134] It should be noted that while oxidizing the conductive electrode 14a, the second trace portion 19a is also partially oxidized. The oxidation method for the second trace portion 19a is the same as that for the conductive electrode 14a. After partial oxidation of the second trace portion 19a, the oxidized portion forms the protective portion 20, and the unoxidized portion forms the second trace 192. The protective portion 20 covers the second trace 192, and the second trace 192 and the first trace 191 constitute the power signal trace 19.

[0135] Thus, the fabrication method of the driving backplane 100 described in this embodiment is completed. In the fabrication method of the driving backplane 100 provided in this embodiment, photomasks are only used when fabricating the gate 11, active layer 13, passivation layer 18, drain 15, and transparent electrode 17. Moreover, the gate 11 and active layer 13 are fabricated using the same photomask. That is, this embodiment only requires four photomasks to complete the fabrication process of the driving backplane 100. Therefore, compared with the driving backplane 100 fabrication process in the prior art, this embodiment greatly reduces the number of photomasks used, thereby saving process costs.

[0136] Please refer to Figures 9A to 9D Example 4 of this application provides a method for fabricating a drive backplane 100. The method for fabricating the drive backplane 100 provided in Example 4 differs from that in Example 3 in that:

[0137] The first and second photoresist layers 50 are made of reversible photoresist. In steps 3041 and 3042, in the direction perpendicular to the plane of the substrate 10, the closed cross-sectional shapes of the first opening 501, the second opening 502, and the third opening 503 are all inverted trapezoids, as shown below. Figure 9A and Figure 9B As shown.

[0138] Second, step 3043 is omitted.

[0139] Third, step 305 specifically includes the following steps: First, a source / drain metal layer 14A is formed on the second photoresist layer 50 using a physical vapor deposition process. The source / drain metal layer 14A fills the first opening 501, the second opening 502, the third opening 503, the first via 181, the second via 182, and the third via 183, as shown below. Figure 9C As shown; next, the portion of the second photoresist layer 50 and the source / drain metal layer 14A located above the second photoresist layer 50 is stripped off. The portion of the source / drain metal layer 14A corresponding to the first opening 501 is formed as a conductive electrode 14a. The conductive electrode 14a is connected to the active layer 13 through the first via 181. The portion of the source / drain metal layer 14A corresponding to the second opening 502 is formed as a drain electrode 15. The drain electrode 15 is connected to the active layer 13 through the second via 182. The portion of the source / drain metal layer 14A corresponding to the third opening 503 is formed as a second trace portion 19a. The second trace portion 19a is connected to the first trace 191 through the third via 183, as shown. Figure 9D As shown.

[0140] In the fabrication method of the drive backplane 100 in this embodiment, since a photomask is not required when forming the conductive electrode 14a and the drain electrode 15, this embodiment can save one photomask, and thus the process of fabricating the drive backplane 100 can be completed by using three photomasks.

[0141] The foregoing has provided a detailed description of a driving backplane and its preparation method, as well as a display panel, provided by the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for preparing a drive backplate, characterized in that, Includes the following steps: Provide substrate; An active layer is formed on the substrate; Conductive electrodes and drain electrodes are formed at intervals on the active layer; A transparent electrode is formed on the drain electrode, and the transparent electrode is connected to the drain electrode. as well as The conductive electrode is partially oxidized, and the oxidized portion of the conductive electrode forms a metal oxide barrier portion, while the unoxidized portion of the conductive electrode forms a source electrode. The metal oxide barrier portion covers the source electrode and is in contact with the surface of the source electrode.

2. The method for preparing the drive backplate according to claim 1, characterized in that, The thickness of the metal oxide barrier is one-quarter to one-half the thickness of the conductive electrode.

3. The method for preparing the drive backplate according to claim 1, characterized in that, The step of forming spaced conductive electrodes and drain electrodes on the active layer includes: A passivation layer is formed on the active layer; A photoresist layer is formed on the passivation layer, and a first opening and a second opening are formed in the photoresist layer to expose the passivation layer; Using the photoresist layer as a mask, the passivation layer is etched to form a first via and a second via on the passivation layer that expose the active layer. The first via is connected to the first opening, and the second via is connected to the second opening. A source / drain metal layer is formed on the photoresist layer, and the source / drain metal layer fills the first opening, the first via, the second opening, and the second via; The portion of the photoresist layer and the portion of the source / drain metal layer located on the photoresist layer are stripped off. The portion of the source / drain metal layer corresponding to the first opening is formed as a conductive electrode. The conductive electrode is connected to the active layer through the first via. The portion of the source / drain metal layer corresponding to the second opening is formed as a drain electrode. The drain electrode is connected to the active layer through the second via.

4. The method for preparing the drive backplate according to claim 3, characterized in that, In a direction perpendicular to the plane of the substrate, the closed cross-sectional shape of the first opening and the closed cross-sectional shape of the second opening are both inverted trapezoids.

5. The method for preparing the drive backplate according to claim 1, characterized in that, The step of forming an active layer on the substrate includes: A gate metal layer, a gate insulating layer, and an active layer are sequentially formed on the substrate. The gate metal layer, the gate insulating layer, and the active layer on the entire surface are patterned using the same photomask to form the gate, the patterned gate insulating layer, and the patterned active layer, respectively.

6. A drive backplane, characterized in that, The drive backplate is prepared by the method described in any one of claims 1 to 5, wherein the drive backplate comprises: The substrate; The active layer is disposed on the substrate; The source and the drain are disposed on the active layer, and the source and the drain are respectively connected to the active layer; A gate is disposed on the substrate and located on the side of the active layer that is close to or far from the source electrode; The metal oxide barrier portion is disposed on the side of the source electrode away from the active layer, the metal oxide barrier portion covers the source electrode and is in contact with the surface of the source electrode; and The transparent electrode is disposed on the side of the drain electrode away from the active layer and is connected to the drain electrode.

7. The drive backplane according to claim 6, characterized in that, The source electrode includes a source electrode portion, and the metal oxide barrier portion is in contact with the source electrode portion. The metal element in the source electrode portion is the same as the metal element in the metal oxide barrier portion.

8. The drive backplane according to claim 6, characterized in that, The transparent electrode is in contact with the surface of the drain electrode away from the active layer.

9. The drive backplane according to claim 8, characterized in that, The gate is located on the side of the active layer away from the source electrode, and the driving backplane further includes a gate insulating layer disposed between the gate and the active layer; The drive backplane also includes a passivation layer disposed between the active layer and the source electrode. The passivation layer has a first via and a second via, both of which expose the active layer. The source electrode is connected to the active layer through the first via, and the drain electrode is connected to the active layer through the second via.

10. A display panel, characterized in that, The display panel includes a driving backplate as described in any one of claims 6 to 8 and a light-emitting structure disposed on the driving backplate.

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