Array substrate, manufacturing method thereof, and display panel

Abstract

An embodiment of the present application discloses an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes: a substrate, an active layer, a first metal layer, an insulating layer, and a second metal layer that are stacked. The active layer includes a source contact portion and a drain contact portion. A first connection hole is provided on the insulating layer between the second metal layer and the source contact portion, and a second connection hole is provided on the insulating layer between the second metal layer and the drain contact portion. Metal protection layers are provided between the insulating layer and the source contact portion and between the insulating layer and the drain contact portion. The orthographic projection of the metal protection layer in the direction perpendicular to the substrate at least covers the orthographic projections of the first connection hole and the second connection hole. The technical solution of the present application can use a conventional gas dry etching solution to etch the LTPS array substrate, resulting in a product with stable performance, a low risk factor during the etching process, and a low price, effectively reducing the production cost of the LTPS array substrate.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to an array substrate, a manufacturing method thereof, and a display panel. Background Art

[0002] Low Temperature Poly-silicon (LTPS) has the advantages of high mobility and good stability, and is widely used in small-size display devices.

[0003] Currently, conventional LTPS dielectric layer etching technologies usually adopt a high selectivity etching system, such as wet etching with hydrofluoric acid or plasma etching with octafluorocyclobutane. Among them, hydrofluoric acid has strong corrosiveness. As a strictly controlled chemical, its risk coefficient is high, while octafluorocyclobutane, as a special gas, is expensive, and the production cost is high. In the production process of display panels, conventional gas (CF 4 or NF 3 ) dry etching solutions have mature technologies and low costs, but they are prone to the problem of polysilicon over-etching during etching.

[0004] Therefore, there is an urgent need for an LTPS array substrate structure with stable performance and compatible with conventional gas dry etching solutions. Summary of the Invention

[0005] Embodiments of the present application provide an array substrate, a manufacturing method thereof, and a display panel. The LTPS array substrate can be etched by using a conventional gas (CF 4 or NF 3 ) dry etching solution. The obtained product has stable performance, low risk coefficient during the etching process, and low price, effectively reducing the production cost of the LTPS array substrate.

[0006] Embodiments of the present application provide an array substrate, including:

[0007] A substrate;

[0008] An active layer disposed on the substrate, the active layer including a channel portion, a source contact portion and a drain contact portion disposed on both sides of the channel portion and electrically connected to the channel portion;

[0009] An insulating layer disposed on the substrate and the active layer;

[0010] A first metal layer stacked with the insulating layer and corresponding to the channel portion;

[0011] A second metal layer is disposed above the insulating layer and corresponding to the source contact portion and the drain contact portion. A first connection hole is provided on the insulating layer between the second metal layer and the source contact portion, and a second connection hole is provided on the insulating layer between the second metal layer and the drain contact portion. The second metal layer is electrically connected to the source contact portion and the drain contact portion through the first connection hole and the second connection hole respectively;

[0012] Wherein, a metal protection layer is provided between the insulating layer and the source contact portion, and between the insulating layer and the drain contact portion. In the direction perpendicular to the substrate, the orthographic projection of the metal protection layer at least covers the orthographic projections of the first connection hole and the second connection hole.

[0013] Optionally, in the direction perpendicular to the substrate, the orthographic projection of the metal protection layer is located within the orthographic projections of the source contact portion and the drain contact portion.

[0014] Optionally, the active layer further includes a first connection portion disposed between the source contact portion and the channel portion and connecting the source contact portion and the channel portion, and a second connection portion disposed between the drain contact portion and the channel portion and connecting the drain contact portion and the channel portion;

[0015] Wherein, the materials of the source contact portion and the drain contact portion include amorphous silicon heavily doped with phosphine, and the materials of the first connection portion and the second connection portion include amorphous silicon lightly doped with phosphine.

[0016] Optionally, in the direction perpendicular to the substrate, the thickness of the first connection portion is greater than the thickness of the source contact portion, and the thickness of the second connection portion is greater than the thickness of the drain contact portion.

[0017] Optionally, a silicon-based insulating layer is provided on the metal protection layer, and a third connection hole and a fourth connection hole are provided on the silicon-based insulating layer. The third connection hole communicates with the first via hole, the fourth connection hole communicates with the second via hole, and the material of the silicon-based insulating layer is the same as the material of the channel portion.

[0018] Optionally, the materials of the source contact portion and the drain contact portion include amorphous silicon doped with phosphine or amorphous silicon doped with borane.

[0019] Optionally, the material of the metal protection layer includes any one of Mo, Ti and their alloys.

[0020] The present application also provides a method for manufacturing an array substrate, including the following steps:

[0021] Provide a substrate;

[0022] An active layer is formed on the substrate, and the active layer includes a channel portion, a source contact portion and a drain contact portion which are disposed on both sides of the channel portion and electrically connected to the channel portion;

[0023] A metal protection layer is formed on the source contact portion and the drain contact portion;

[0024] An insulating layer, a first metal layer and a second metal layer which are stacked are formed on the substrate, the active layer and the metal protection layer. The first metal layer is disposed corresponding to the channel portion. The second metal layer is disposed on the insulating layer and corresponds to the positions above the source contact portion and the drain contact portion. A first connection hole is provided on the insulating layer between the second metal layer and the source contact portion, and a second connection hole is provided on the insulating layer between the second metal layer and the drain contact portion. The second metal layer is electrically connected to the source contact portion and the drain contact portion respectively through the first connection hole and the second connection hole. In the direction perpendicular to the substrate, the positive projection of the metal protection layer at least covers the positive projections of the first connection hole and the second connection hole.

[0025] Optionally, the active layer further includes a first connection portion which is disposed between the source contact portion and the channel portion and connects the source contact portion and the channel portion, and a second connection portion which is disposed between the drain contact portion and the channel portion and connects the drain contact portion and the channel portion;

[0026] The steps of forming the active layer on the substrate, where the active layer includes a channel portion, a source contact portion and a drain contact portion which are disposed on both sides of the channel portion and electrically connected to the channel portion; and forming the metal protection layer on the source contact portion and the drain contact portion include:

[0027] A source contact portion, a source connection section connecting the source contact portion, a drain contact portion, and a drain connection section connecting the drain contact portion and located at a position close to the source contact portion are formed on the substrate;

[0028] A metal protection layer is formed on the source contact portion and the drain contact portion;

[0029] A source connection section two is formed on the source connection section one, a drain connection section two is formed on the drain connection section one, a channel portion precursor is formed on the substrate between the source connection section one and the drain connection section one, the source connection section one and the source connection section two are annealed to form the first connection portion, the drain connection section one and the drain connection section two are annealed to form the second connection portion, and the channel portion precursor is annealed to form the channel portion.

[0030] The present application also provides a display panel, including the array substrate described in any of the above embodiments.

[0031] The beneficial effects of the present invention at least include:

[0032] By providing a metal protection layer on the source contact portion and the drain contact portion, and in the direction perpendicular to the substrate, the orthographic projection of the metal protection layer at least covers the orthographic projections of the first connection hole and the second connection hole, so that during the process of forming the first connection hole and the second connection hole by conventional gas etching of the insulating layer, the problem of polysilicon over-etching will not occur, and the production of the LTPS array substrate does not require an additional high selectivity etching system, such as hydrofluoric acid wet etching or octafluorocyclobutane plasma etching, reducing the production cost and production risk coefficient of the LTPS array substrate. Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0034] Figure 1 It is a schematic structural diagram of an array substrate provided by an embodiment of the present application;

[0035] Figure 2 It is a schematic structural diagram of the metal protection layer in the structure of another array substrate provided by an embodiment of the present application;

[0036] Figure 3 It is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

[0037] Figure 4 It is a schematic structural diagram in a manufacturing method of an array substrate provided by an embodiment of the present application;

[0038] Figure 5 It is a schematic structural diagram in a manufacturing method of an array substrate provided by an embodiment of the present application;

[0039] Figure 6 It is a schematic structural diagram in a manufacturing method of an array substrate provided by an embodiment of the present application;

[0040] Figure 7 It is a schematic structural diagram in a manufacturing method of an array substrate provided by an embodiment of the present application;

[0041] Figure 8 It is a schematic structural diagram in a manufacturing method of an array substrate provided by an embodiment of the present application;

[0042] Figure 9 It is a schematic structural diagram in a method for manufacturing an array substrate provided by an embodiment of the present application;

[0043] Figure 10 It is a schematic structural diagram in a method for manufacturing an array substrate provided by an embodiment of the present application;

[0044] Figure 11 It is a schematic structural diagram in a method for manufacturing an array substrate provided by an embodiment of the present application;

[0045] Figure 12 It is a schematic structural diagram in a method for manufacturing an array substrate provided by an embodiment of the present application;

[0046] Figure 13 It is a flowchart of a method for manufacturing an array substrate provided by an embodiment of the present application;

[0047] Figure 14 It is a partial flowchart of a method for manufacturing another array substrate provided by an embodiment of the present application. Detailed implementation manners

[0048] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application.

[0049] An embodiment of the present application provides an array substrate, a method for manufacturing the same, and a display panel. The following will be described in detail respectively. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments. In addition, in the description of the present application, the term "including" means "including but not limited to". The terms first, second, third, etc. are only used as labels and do not impose numerical requirements or establish an order. The various embodiments of the present invention may exist in a range form; it should be understood that the description in a range form is only for convenience and brevity and should not be construed as a rigid limitation on the scope of the present invention; therefore, it should be considered that the described range description has specifically disclosed all possible sub-ranges and individual values within that range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and individual numbers within the range, such as 1, 2, 3, 4, 5, and 6, regardless of the range. In addition, whenever a numerical range is indicated herein, it means including any cited number (fraction or integer) within the indicated range.

[0050] An embodiment of the present application provides an array substrate 101, as Figure 1 and Figure 2 shown, including:

[0051] A substrate 10;

[0052] An active layer disposed on the substrate 10, the active layer including a channel portion 401, a source contact portion 201 and a drain contact portion 202 disposed on both sides of the channel portion 401 and electrically connected to the channel portion 401;

[0053] An insulating layer 50 disposed on the substrate 10 and the active layer;

[0054] A first metal layer 60 stacked with the insulating layer 50 and disposed corresponding to the channel portion 401;

[0055] A second metal layer 70 disposed above the insulating layer 50 and disposed corresponding to the source contact portion 201 and the drain contact portion 202. A first connection hole 503 is provided on the insulating layer 50 between the second metal layer 70 and the source contact portion 201, and a second connection hole 504 is provided on the insulating layer 50 between the second metal layer 70 and the drain contact portion 202. The second metal layer 70 passes through the first connection hole 503 and the second connection hole 504 respectively and is electrically connected to the source contact portion 201 and the drain contact portion 202;

[0056] Wherein, metal protection layers 30 are provided between the insulating layer 50 and the source contact portion 201 and between the insulating layer 50 and the drain contact portion 202. In the direction perpendicular to the substrate 10, the orthographic projection of the metal protection layer 30 at least covers the orthographic projections of the first connection hole 503 and the second connection hole 504.

[0057] It should be noted that the array substrate 101 in the present application includes a plurality of control devices, and the control devices may be thin film transistors (TFTs). An embodiment of the present application describes the film layer structure of one control device.

[0058] Specifically, the substrate 10 includes a substrate 101 and a buffer layer 102 disposed on the substrate 101. The substrate 101 includes a glass substrate 101, and the material of the buffer layer 102 includes but is not limited to at least one of SiOx, SiNx, SiNx / SiOx and SiNOx, and its thickness may be 1500 - 4000 angstroms.

[0059] Specifically, the active layer includes a channel portion 401, a source contact portion 201 and a drain contact portion 202 which are disposed on both sides of the channel portion 401 and electrically connected to the channel portion 401. The material of the channel portion 401 is different from that of the source contact portion 201 and the drain contact portion 202. The material of the channel portion 401 is low-temperature polycrystalline silicon, and the materials of the source contact portion 201 and the drain contact portion 202 are conductivized silicon materials. Among them, the conductivized silicon material can be a P-type hybrid material formed by doping with phosphine, or an N-type material formed by doping with borane, and its deposition thickness can be 400-1000 angstroms.

[0060] Specifically, as Figure 1 shown, the insulating layer 50 is disposed on the substrate 10, the active layer and the metal protection layer 30. The insulating layer 50 includes a gate insulating layer 501 and a dielectric layer 502. The gate insulating layer 501 is disposed on the substrate 10, the active layer and the metal protection layer 30. A first metal layer 60 is disposed on the gate insulating layer 501. The first metal layer 60 includes a gate. The dielectric layer 502 is disposed on the gate and the gate insulating layer 501. A second metal layer 70 is disposed on the dielectric layer 502. The second metal layer 70 includes a source electrode 701 and a drain electrode 702. In this embodiment, the case where the second metal layer 70 includes a source electrode 701 and a drain electrode 702 is taken as an example for description.

[0061] Specifically, the gate is disposed corresponding to the channel portion 401, the source electrode 701 is disposed corresponding to the source contact portion 201, and the drain electrode 702 is disposed corresponding to the drain contact portion 202.

[0062] It should be noted that in the embodiments of the present application, the gate is located above the channel portion 401, which is a top-gate structure. However, the setting manners of the source electrode 701, the drain electrode 702, a part of the insulating layer 50 and the structure of the active layer in the embodiments of the present application are also applicable to the bottom-gate structure. The present application does not elaborate on the array substrate 101 of the bottom-gate structure. Specifically, reference can be made to the array substrate 101 of the top-gate structure. The present application takes the top-gate structure as an example for description.

[0063] Specifically, the materials of the first metal layer 60 and the second metal layer 70 include but are not limited to one or more combinations of copper, silver, aluminum, steel, titanium and their alloys.

[0064] Specifically, the materials of the gate insulating layer 501 and the dielectric layer 502 include but are not limited to silicon dioxide.

[0065] Specifically, a first connection hole 503 is provided on the insulating layer 50 between the second metal layer 70 and the source contact portion 201, and a second connection hole 504 is provided on the insulating layer 50 between the second metal layer 70 and the drain contact portion 202. The second metal layer 70 passes through the first connection hole 503 and the second connection hole 504 respectively and is electrically connected to the source contact portion 201 and the drain contact portion 202. In this embodiment, the source 701 passes through the first connection hole 503 and is electrically connected to the source contact portion 201, and the drain 702 passes through the second connection hole 504 and is electrically connected to the drain contact portion 202 as an example for illustration.

[0066] It should be noted that in the production process of the conventional LTPS array substrate 101, a high-selectivity etching system is usually used to etch the insulating layer 50 to form vias corresponding to the source and drain contact portions 202 and the drain contact portion 202 (i.e., the first connection hole 503 and the second connection hole 504) to avoid the problem of polysilicon over-etching. However, the above high-selectivity etching system has the disadvantages of high risk coefficient and high cost, which limits the application of the LTPS array substrate 101 in the production of large-size display panels. In order to further reduce the production cost and improve the process stability, conventional gases are used for etching, and the technical solution of this embodiment is provided.

[0067] As Figure 1 , Figure 2 shown, by providing a metal protection layer 30 between the source contact portion 201 and the insulating layer 50 and between the drain contact portion 202 and the insulating layer 50, during the dry etching of the insulating layer 50 with conventional gases (CF 4 or NF 3 ), due to the barrier of the metal protection layer 30, the conventional gases (CF 4 or NF 3 ) will not etch the polysilicon material, effectively reducing the production cost of the LTPS array substrate 101 and improving the stability of the production of the LTPS array substrate 101.

[0068] Specifically, the material of the metal protection layer 30 can be a high-temperature resistant metal, specifically resistant to high temperatures above 1000 °C, to prevent the metal protection layer 30 from melting and causing other problems during subsequent production processes.

[0069] Specifically, the material of the metal protection layer 30 can specifically be one or a combination of Mo, Ti, or Mo / Ti. It can be formed by PVD deposition, and the deposition thickness can be 50 - 400 Å, specifically any one of 50 Å, 80 Å, 120 Å, 200 Å, 350 Å, 400 Å, and can be specifically selected according to the actual production situation.

[0070] Specifically, the function of the metal protection layer 30 is to prevent conventional gases (CF 4 or NF 3 ) from etching the polysilicon material. Therefore, in the direction perpendicular to the substrate 10, the area of the metal protection layer 30 covers at least the orthographic projections of the first connection hole 503 and the second connection hole 504.

[0071] It should be noted that in actual production, the vertical cross-sectional shapes of the first connection hole 503 and the second connection hole 504 are trapezoids inverted. Therefore, the orthographic projection of the first connection hole 503 refers to the orthographic projection of the opening at the end of the first connection hole 503 close to the source contact portion 201, and the orthographic projection of the second connection hole 504 refers to the orthographic projection of the opening at the end of the second connection hole 504 close to the drain contact portion 202.

[0072] Specifically, the orthographic projection of the metal protection layer 30 on the source contact portion 201 may coincide with the orthographic projection of the contact surface between the source contact portion 201 and the metal protection layer 30, as Figure 1 shown, or may be smaller than the orthographic projection of the source contact portion 201 (upper surface), as Figure 2 shown.

[0073] It can be understood that by providing the metal protection layer 30 on the source contact portion 201 and the drain contact portion 202, and in the direction perpendicular to the substrate 10, the orthographic projection of the metal protection layer 30 covers at least the orthographic projections of the first connection hole 503 and the second connection hole 504, so that during the process of etching the insulating layer 50 with conventional gases to form the first connection hole 503 and the second connection hole 504, the problem of over-etching of polysilicon does not occur, and the production of the LTPS array substrate 101 does not require the additional use of a high selectivity etching system, such as wet etching with hydrofluoric acid or plasma etching with octafluorocyclobutane, effectively reducing the production cost and production risk coefficient of the LTPS array substrate 101 and improving the stability of the device.

[0074] In one embodiment, as Figure 2 shown, in the direction perpendicular to the substrate 10, the orthographic projection of the metal protection layer 30 is located within the orthographic projections of the source contact portion 201 and the drain contact portion 202.

[0075] Specifically, the orthographic projection of the metal protection layer 30 on the source contact portion 201 is located on the upper surface of the source contact portion 201, and the orthographic projection of the metal protection layer 30 on the drain contact portion 202 is located on the upper surface of the drain contact portion 202.

[0076] In another example, the orthographic projection of the metal protection layer 30 is located within the orthographic projections of the source contact portion 201 and the drain contact portion 202.

[0077] It can be understood that through the above setting method, the usage amount of the material of the metal protection layer 30 can be reduced, and the production cost of the LTPS array substrate 101 can be lowered.

[0078] In one embodiment, as Figure 3 shown, the active layer further includes a first connection portion 402 disposed between the source contact portion 201 and the channel portion 401 and connecting the source contact portion 201 and the channel portion 401, and a second connection portion 403 disposed between the drain contact portion 202 and the channel portion 401 and connecting the drain contact portion 202 and the channel portion 401;

[0079] Wherein, the materials of the source contact portion 201 and the drain contact portion 202 include a phosphine-doped amorphous silicon layer 20, and the materials of the first connection portion 402 and the second connection portion 403 include lightly phosphine-doped amorphous silicon.

[0080] It should be noted that especially in the structure of a P-type control device, in order to further improve the stability of the thin-film transistor, improve the electric field distribution at the source-drain 702 connection end, reduce the electron migration phenomenon at the source-drain 702 connection end in the off state, thereby reducing the leakage current of the thin-film transistor and reducing the power loss, a lightly doped first connection portion 402 and a second connection portion 403 are respectively disposed between the source contact portion 201 and the drain contact portion 202 and the channel portion 401.

[0081] Specifically, the first connection portion 402 and the second connection portion 403 can be formed by the same process as the channel portion 401.

[0082] It can be understood that by setting the active layer of the P-type thin-film transistor to include a first connection portion 402 disposed between the source contact portion 201 and the channel portion 401 and connecting the source contact portion 201 and the channel portion 401, and a second connection portion 403 disposed between the drain contact portion 202 and the channel portion 401 and connecting the drain contact portion 202 and the channel portion 401, the electric field distribution at the connection ends of the source 701 and the drain 702 can be improved, the electron migration phenomenon at the connection ends of the source 701 and the drain 702 in the off state can be reduced, thereby reducing the device leakage current and reducing the power loss.

[0083] Continuing with the above embodiment, in the direction perpendicular to the substrate 10, the thickness of the first connection portion 402 is greater than the thickness of the source contact portion 201, and the thickness of the second connection portion 403 is greater than the thickness of the drain contact portion 202.

[0084] It should be noted that the conventional methods for forming the lightly doped first connection part 402 and the second connection part 403 include:

[0085] 1. Using the ion implantation method, the implementation method of which is different from that of this embodiment. The ion implantation scheme is mainly applied to the field of small-size LTPS display panels. In the field of large-size panels, it is difficult to implement this scheme due to cost and machine tool limitations;

[0086] 2. Using the gate coverage scheme, which will affect the reduction of device mobility.

[0087] In order to avoid forming the first connection part 402 and the second connection part 403 by additionally using the ion implantation method, this embodiment provides the following manufacturing process. As Figure 5 , Figure 7 , Figure 8 , Figure 9 and Figure 10 shown, in this embodiment, an amorphous silicon layer 20 doped with phosphine is first formed, and then through yellow photolithography and dry etching processes, a source contact part 201, a drain contact part 202, a source connection segment 4021 connecting the source contact part 201, and a drain connection segment 4031 connecting the drain contact part 202 and located near the source contact part 201 are formed. Among them, the distance between the side of the protective metal layer on the source contact part 201 close to the channel and the side of the source contact part 201 close to the channel is about 1 - 3 μm, and the distance between the side of the protective metal layer on the drain contact part 202 close to the channel and the side of the drain contact part 202 close to the channel is about 1 - 3 μm;

[0088] As Figure 9 shown, an amorphous silicon layer 40 is deposited on the source connection segment 4021 to form a source connection second segment 4022. Through blue laser annealing technology treatment, the phosphorus in the heavily doped source connection segment 4021 diffuses longitudinally and laterally into the amorphous silicon layer 40 (source connection second segment 4022) and crystallizes with it into lightly doped polycrystalline silicon, that is, the first connection part 402; an amorphous silicon layer 40 is deposited on the drain connection segment 4031 to form a drain connection second segment 4032. Through blue laser annealing technology treatment, the phosphorus in the heavily doped drain connection segment 4031 diffuses longitudinally and laterally into the amorphous silicon layer 40 (drain connection second segment 4032) and crystallizes with it into lightly doped polycrystalline silicon, that is, the second connection part 403.

[0089] Specifically, the source connection second segment 4022 and the drain connection second segment 4032 can be formed by the same manufacturing process.

[0090] It can be understood that the lightly doped structure (the first connecting portion 402 and the second connecting portion 403) is formed by means of stacking and diffusion, such that the thickness of the first connecting portion 402 is greater than the thickness of the source contact portion 201, and the thickness of the second connecting portion 403 is greater than the thickness of the drain contact portion 202, avoiding the formation of an LDD (light-dopping-drain) structure by means of ion implantation, enabling the fabrication of large-size LTPS display panels, and at the same time, the device has high stability.

[0091] Continuing from the above embodiments, as Figure 11 and Figure 12 shown, a silicon-based insulating layer 50 is provided on the metal protection layer 30, and a third connection hole 405 and a fourth connection hole 406 are provided on the silicon-based insulating layer 404. The third connection hole 405 communicates with the first via hole, the fourth connection hole 406 communicates with the second via hole, and the material of the silicon-based insulating layer 404 is the same as the material of the channel portion 401.

[0092] Specifically, the material of the silicon-based insulating layer 404 is the same as the material of the channel portion 401, both being low-temperature polycrystalline silicon.

[0093] Specifically, the silicon-based insulating layer 404 and the channel portion 401 are formed in the same process.

[0094] It can be understood that in the embodiments of the present application, by stacking and disposing an amorphous silicon layer 20 doped with phosphine and an amorphous silicon layer 40, and through blue laser annealing technology treatment, phosphorus in the heavily doped amorphous silicon layer that is not covered by the metal protection layer 30 diffuses longitudinally and laterally into the subsequently laminated amorphous silicon layer 40 to form a lightly doped structure. At the same time, the remaining amorphous silicon is transformed into low-temperature polycrystalline silicon to obtain the silicon-based insulating layer 404. By adopting the above technical solution, the etching precision requirement for the subsequently formed amorphous silicon layer 40 is significantly reduced, that is, the etching of the subsequently deposited amorphous silicon layer 40 can be performed outside the source contact portion 201 and the drain contact portion 202, as Figure 9 shown, its etching precision requirement is relatively low, production is convenient, the formed silicon-based insulating layer 404 will not affect the TFT device, and this structure also avoids the formation of an LDD structure by means of ion implantation, enabling the LTPS array substrate 101 to be applied to large-size flexible display panels.

[0095] In one embodiment, the materials of the source contact portion 201 and the drain contact portion 202 include amorphous silicon doped with phosphine or amorphous silicon doped with borane.

[0096] Specifically, the materials of the source contact portion 201 and the drain contact portion are conductive silicon-based materials.

[0097] Specifically, the thin film transistor formed of phosphine-doped amorphous silicon is a P-type thin film transistor, and the thin film transistor formed of borane-doped amorphous silicon is an N-type thin film transistor.

[0098] In one embodiment, the material of the metal protection layer 30 includes any one of Mo, Ti, and their alloys.

[0099] Specifically, metals Mo, Ti, and their alloys are all metal materials resistant to high temperatures above 1000 °C. Since some steps in the subsequent processes of the array substrate 101 need to be carried out in a high-temperature environment, therefore, setting the material of the metal protection layer 30 to include any one of Mo, Ti, and their alloys can effectively prevent the metal protection layer 30 from melting and failing in the subsequent processes, affecting other structures of the array substrate 101.

[0100] This application also provides a manufacturing method of an array substrate 101, as Figure 13 shown, including the following steps:

[0101] S1. Provide a substrate 10;

[0102] S2. Form an active layer on the substrate 10, where the active layer includes a channel portion 401, a source contact portion 201 and a drain contact portion 202 that are disposed on both sides of the channel portion 401 and electrically connected to the channel portion 401;

[0103] S3. Form a metal protection layer 30 on the source contact portion 201 and the drain contact portion 202;

[0104] S4. Form a stacked insulating layer 50, a first metal layer 60, and a second metal layer 70 on the substrate 10, the active layer, and the metal protection layer 30. The first metal layer 60 is disposed corresponding to the channel portion 401. The second metal layer 70 is disposed on the insulating layer 50, and the second metal layer 70 is disposed above the source contact portion 201 and the drain contact portion 202. A first connection hole 503 is provided on the insulating layer 50 between the second metal layer 70 and the source contact portion 201, and a second connection hole 504 is provided on the insulating layer 50 between the second metal layer 70 and the drain contact portion 202. The second metal layer 70 is electrically connected to the source contact portion 201 and the drain contact portion 202 respectively through the first connection hole 503 and the second connection hole 504. In the direction perpendicular to the substrate 10, the orthographic projection of the metal protection layer 30 at least covers the orthographic projections of the first connection hole 503 and the second connection hole 504.

[0105] Specifically, for the structure and material of the substrate 10, reference can be made to the embodiments of the above structure.

[0106] Specifically, the metal lamination of the metal protection layer 30 can adopt PVD method, and the metal layer patterning to form the metal protection layer 30 can adopt PHO (yellow light) process and wet etching process.

[0107] Specifically, the first metal layer 60 includes a plurality of gates, the second metal layer 70 includes a plurality of source electrodes 701 and a plurality of drain electrodes 702, and the first metal layer 60 and the second metal layer 70 are formed by PVD deposition of metal followed by PHO (yellow light) process and wet etching process.

[0108] Specifically, the thickness of the metal protection layer 30 is 50 to 400 angstroms.

[0109] Specifically, the first connection hole 503 and the second connection hole 504 are formed by using a conventional plasma etching gas system, such as CF 4 or NF 3 system dry etching process to etch the dielectric layer 502 (insulating layer 50) and the gate insulating layer 501 (insulating layer 50) in sequence, and in some embodiments, a polysilicon layer is also included, and etching is continued until reaching the metal protection layer 30 (MoTi), effectively preventing the source contact portion 201 and the drain contact portion 202 from being over-etched.

[0110] It can be understood that through the above preparation method, the production of the LTPS array substrate 101 structure does not require an additional high selectivity etching system, such as hydrofluoric acid wet etching or perfluorocyclobutane plasma etching, reducing the production cost and production risk coefficient of the LTPS array substrate 101.

[0111] In one embodiment, as Figure 14 shown, the active layer further includes a first connection portion 402 disposed between the source contact portion 201 and the channel portion 401 and connecting the source contact portion 201 and the channel portion 401, and a second connection portion 403 disposed between the drain contact portion 202 and the channel portion 401 and connecting the drain contact portion 202 and the channel portion 401;

[0112] The steps of forming the active layer on the substrate 10, the active layer including a channel portion 401, a source contact portion 201 and a drain contact portion 202 disposed on both sides of the channel portion 401 and electrically connected to the channel portion 401; and forming the metal protection layer 30 on the source contact portion 201 and the drain contact portion 202 include:

[0113] S21. Form a source contact portion 201, a source connection section 4021 connecting the source contact portion 201, a drain contact portion 202, and a drain connection section 4031 connecting the drain contact portion 202 and located near the source contact portion 201 on the substrate 10;

[0114] S3. Form a metal protective layer 30 on the source contact portion 201 and the drain contact portion 202.

[0115] S31. Form a second source connection segment 4022 on the first source connection segment 4021, form a second drain connection segment 4032 on the first drain connection segment 4031, form a channel portion 401 precursor on the substrate 10 between the first source connection segment 4021 and the first drain connection segment 4031, anneal the first source connection segment 4021 and the second source connection segment 4022 to form the first connection portion 402, anneal the first drain connection segment 4031 and the second drain connection segment 4032 to form the second connection portion 403, and anneal the channel portion 401 precursor to form the channel portion 401.

[0116] Specifically, the annealing process uses the blue laser annealing technology (BLDA, Blue Laser Diode Annealing).

[0117] Specifically, the distance between the side of the protective metal layer on the source contact portion 201 close to the channel and the side of the source contact portion 201 close to the channel is about 1 - 3 μm, and the distance between the side of the protective metal layer on the drain contact portion 202 close to the channel and the side of the drain contact portion 202 close to the channel is about 1 - 3 μm.

[0118] In a specific example, the manufacturing steps are as follows:

[0119] As Figure 4 shown, provide a substrate 10 including a substrate 101 layer and a buffer layer 102.

[0120] As Figure 5 shown, deposit a layer of phosphine-doped amorphous silicon layer 20 on the substrate 10, and laminate a metal layer on the phosphine-doped amorphous silicon layer 20.

[0121] As Figure 6 shown, pattern the metal layer using a yellow light process and a wet etching process to form a metal protective layer 30, and a photoresist PR is coated on the metal protective layer.

[0122] As Figure 7As shown, using a yellow light process and a dry etching process, a photoresist PR is coated on a section 4021 connected to the source electrode and a section 4031 connected to the drain electrode, and the amorphous silicon layer 20 doped with phosphine is patterned to form a source electrode contact portion 201, a section 4021 of the source electrode connecting the source electrode contact portion 201, a drain electrode contact portion 202, and a section 4031 of the drain electrode connecting the drain electrode contact portion 202 and located near the source electrode contact portion 201. The distance between the side of the protective metal layer on the source electrode contact portion 201 close to the channel and the side of the source electrode contact portion 201 close to the channel is about 1 - 3 μm, and the distance between the side of the protective metal layer on the drain electrode contact portion 202 close to the channel and the side of the drain electrode contact portion 202 close to the channel is about 1 - 3 μm;

[0123] As Figure 8 shown, an amorphous silicon layer 40 is deposited on the substrate 10, the metal protective layer 30, a section 4021 of the source electrode, and a section 4031 of the drain electrode;

[0124] As Figure 9 shown, using a yellow light process and a dry etching process, the amorphous silicon layer 40 is patterned to form a second section 4022 of the source electrode on the section 4021 of the source electrode and a second section 4032 of the drain electrode on the section 4031 of the drain electrode, and a precursor 401 of the channel portion on the substrate 10 between the section 4021 of the source electrode and the section 4031 of the drain electrode;

[0125] As Figure 10 shown, the precursor 401 of the channel portion (amorphous silicon layer 40) is crystallized into low-temperature polycrystalline silicon (channel portion 401) by using a blue laser annealing technique (BLDA, Blue Laser Diode Annealing). During the BLDA process, phosphorus in the section 4021 of the source electrode and the section 4031 of the drain electrode (the heavily doped and phosphine-doped amorphous silicon layer 20 not covered by the metal protective layer 30) diffuses longitudinally and laterally into the amorphous silicon layer 40 (the second section 4022 of the source electrode and the second section 4032 of the drain electrode) and crystallizes with it into low-doped polycrystalline silicon (the first connection portion 402 and the second connection portion 403). The laser annealing scanning direction is perpendicular to the channel scanning or parallel to the channel scanning.

[0126] As Figure 11 shown, a gate insulating layer 501 (insulating layer 50) and a gate and dielectric layer 502 (insulating layer 50) are sequentially deposited on the substrate 10, the active layer, and the metal protective layer 30. Using a conventional CF 4 or NF 3The system dry etching process sequentially etches the dielectric layer 502, the gate insulating layer 501, and the silicon-based insulating layer 404 (low-temperature polysilicon) until the metal protection layer 30 (MoTi) is etched to form a first connection hole 503 and a second connection hole 504. The first connection hole 503 is provided corresponding to the source contact portion 201, and the second connection hole 504 is provided corresponding to the drain contact portion 202.

[0127] As Figure 12 , a source electrode 701 and a drain electrode 702 are formed on the insulating layer 50. The source electrode 701 is electrically connected to the source contact portion 201 through the first connection hole 503, and the drain electrode 702 is electrically connected to the drain contact portion 202 through the second connection hole 504. A planarization layer 90 is formed on the drain electrode 702 and the drain electrode 702. A fifth connection hole is opened at a position of the planarization layer 90 corresponding to the source electrode 701. An ITO layer 80 is formed on the planarization layer 90 such that the ITO layer 80 is electrically connected to the source electrode 701 through a via hole provided on the planarization layer 90.

[0128] The present application further provides a display panel, including the array substrate 101 described in any one of the above embodiments.

[0129] Specifically, the display panel includes, but is not limited to, the following types: mobile phones, watches, bracelets, TVs, or other wearable display devices, as well as tablet computers, laptop computers, desktop monitors, TVs, smart glasses, smart watches, ATM machines, digital cameras, in-vehicle displays, medical displays, industrial control displays, e-books, electrophoretic display devices, game consoles, transparent displays, double-sided displays, naked-eye 3D displays, mirror display devices, transflective display devices, etc.

[0130] In summary, by providing the metal protection layer 30 on the source contact portion 201 and the drain contact portion 202, and in the direction perpendicular to the substrate 10, the positive projection of the metal protection layer 30 at least covers the positive projections of the first connection hole 503 and the second connection hole 504, so that in the process of etching the insulating layer 50 with a conventional gas to form the first connection hole 503 and the second connection hole 504, the problem of over-etching will not occur, and the production of the LTPS array substrate 101 structure does not require an additional high-selectivity etching system, such as hydrofluoric acid wet etching or octafluorocyclobutane plasma etching, reducing the production cost and production risk coefficient of the LTPS array substrate 101.

[0131] The above has introduced in detail an array substrate, a manufacturing method thereof, and a display panel provided by the embodiments of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. An array substrate, characterized in that, comprising: a substrate; an active layer disposed on the substrate, the active layer including a channel portion, a source contact portion and a drain contact portion disposed on both sides of the channel portion and electrically connected to the channel portion; an insulating layer disposed on the substrate and the active layer; a first metal layer stacked with the insulating layer and corresponding to the channel portion; a second metal layer disposed above the insulating layer and corresponding to the source contact portion and the drain contact portion, a first connection hole is provided on the insulating layer between the second metal layer and the source contact portion, and a second connection hole is provided on the insulating layer between the second metal layer and the drain contact portion, and the second metal layer is electrically connected to the source contact portion and the drain contact portion through the first connection hole and the second connection hole respectively; wherein, metal protection layers are provided between the insulating layer and the source contact portion and between the insulating layer and the drain contact portion, and in the direction perpendicular to the substrate, the positive projection of the metal protection layer at least covers the positive projections of the first connection hole and the second connection hole; a silicon-based insulating layer is provided on the metal protection layer, a third connection hole and a fourth connection hole are provided on the silicon-based insulating layer, the third connection hole is communicated with the first connection hole, the fourth connection hole is communicated with the second connection hole, and the material of the silicon-based insulating layer is the same as that of the channel portion, both are low-temperature polycrystalline silicon.

2. The array substrate according to claim 1, characterized in that, in the direction perpendicular to the substrate, the positive projection of the metal protection layer is located within the positive projections of the source contact portion and the drain contact portion.

3. The array substrate according to claim 2, characterized in that, the active layer further includes a first connection portion disposed between the source contact portion and the channel portion and connecting the source contact portion and the channel portion, and a second connection portion disposed between the drain contact portion and the channel portion and connecting the drain contact portion and the channel portion; wherein, the materials of the source contact portion and the drain contact portion include phosphine-doped amorphous silicon, and the materials of the first connection portion and the second connection portion include lightly phosphine-doped amorphous silicon.

4. The array substrate according to claim 3, characterized in that, in the direction perpendicular to the substrate, the thickness of the first connection portion is greater than the thickness of the source contact portion, and the thickness of the second connection portion is greater than the thickness of the drain contact portion.

5. The array substrate according to claim 1, characterized in that, the materials of the source contact portion and the drain contact portion include phosphine-doped amorphous silicon or borane-doped amorphous silicon.

6. The array substrate according to claim 1, characterized in that, the material of the metal protection layer includes any one of Mo, Ti and their alloys.

7. A manufacturing method of an array substrate, characterized in that, comprising the following steps: providing a substrate; forming an active layer on the substrate, the active layer including a channel portion, a source contact portion and a drain contact portion disposed on both sides of the channel portion and electrically connected to the channel portion; A metal protection layer and a silicon-based insulating layer are formed on the source contact portion and the drain contact portion. The material of the silicon-based insulating layer is the same as that of the channel portion, both being low-temperature polysilicon. An insulating layer, a first metal layer, and a second metal layer are formed in a stacked manner on the substrate, the active layer, and the metal protection layer. The first metal layer is disposed corresponding to the channel portion. The second metal layer is disposed on the insulating layer and corresponds to the positions above the source contact portion and the drain contact portion. A first connection hole is provided in the insulating layer between the second metal layer and the source contact portion, and a second connection hole is provided in the insulating layer between the second metal layer and the drain contact portion. A third connection hole and a fourth connection hole are provided in the silicon-based insulating layer. The third connection hole communicates with the first connection hole, and the fourth connection hole communicates with the second connection hole. The second metal layer is electrically connected to the source contact portion and the drain contact portion through the first connection hole and the second connection hole respectively. In the direction perpendicular to the substrate, the orthographic projection of the metal protection layer at least covers the orthographic projections of the first connection hole and the second connection hole.

8. The method for manufacturing an array substrate according to claim 7, characterized in that the active layer further includes a first connection portion disposed between the source contact portion and the channel portion and connecting the source contact portion and the channel portion, and a second connection portion disposed between the drain contact portion and the channel portion and connecting the drain contact portion and the channel portion; forming an active layer on the substrate, the active layer including a channel portion, a source contact portion and a drain contact portion disposed on both sides of the channel portion and electrically connected to the channel portion; The step of forming a metal protection layer on the source contact portion and the drain contact portion includes: forming a source contact portion, a first source connection section connecting the source contact portion, a drain contact portion, and a first drain connection section connecting the drain contact portion and located near the source contact portion on the substrate; forming a metal protection layer on the source contact portion and the drain contact portion; forming a second source connection section on the first source connection section, forming a second drain connection section on the first drain connection section, forming a channel portion precursor on the substrate between the first source connection section and the first drain connection section, annealing the first source connection section and the second source connection section to form the first connection portion, annealing the first drain connection section and the second drain connection section to form the second connection portion, and annealing the channel portion precursor to form the channel portion.

9. A display panel, characterized in that it includes the array substrate according to any one of claims 1 to 6.

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