All-around gate field-effect transistor based on diamond electrothermal regulation and its preparation method

Abstract

The present invention relates to a fully surrounding gate field effect transistor based on diamond electrothermal regulation and a preparation method thereof. The field effect transistor includes: a substrate; a buffer layer disposed on the substrate; a P-type diamond layer disposed on the buffer layer; an n-type Ga2O3 layer disposed on the P-type diamond layer, and the n-type Ga2O3 layer, the P-type diamond layer and a part of the buffer layer are stacked to form a cylindrical structure; an isolation layer, a gate metal layer and a protective layer are sequentially stacked from bottom to top on the buffer layer and are disposed on the side surface of the cylindrical structure from inside to outside; the top surface of the n-type Ga2O3 layer is higher than the top surface of the protective layer, and the top surfaces of the isolation layer and the gate metal layer are lower than the top surface of the protective layer, and the protective layer near the top part is in contact with the side surface of the n-type Ga2O3 layer; a source electrode is disposed on the n-type Ga2O3 layer and a part of the protective layer; a drain electrode is disposed on the buffer layer. The field effect transistor of the present invention can effectively suppress the short channel effect; the use of P-type diamond effectively avoids the problem of preparing P-type Ga2O3.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and particularly relates to a fully surrounding gate field effect transistor based on diamond electrothermal regulation and a preparation method thereof. Background Art

[0002] Ga2O3 has an ultra-wide bandgap (4.5 - 4.9 eV), a high critical breakdown field (~8 MV / cm), and a high Baliga figure of merit (BFOM). Therefore, Ga2O3 shows great potential in next-generation power devices. Due to the Baliga figure of merit of gallium oxide being as high as 3400, which is about 10 times that of SiC and 4 times that of GaN, when manufacturing gallium oxide field effect transistors with the same breakdown voltage, the on-resistance of the components is much lower than that of SiC and GaN, greatly reducing the on-state loss of the device and showing excellent power characteristics.

[0003] However, with the continuous advancement of Moore's law, the device size has been continuously reduced, and the gate's ability to control the channel has begun to decline. It is necessary to develop new materials or device structures to enhance the gate's ability to control the channel. Currently reported technologies include: high-k gate dielectrics and FinFETs. However, as the transistor size is further reduced from 45 nm, the gate length and equivalent oxide thickness approach the physical limit, and the planar MOSFETs prepared with high-k gate dielectrics can no longer meet the growing performance requirements. The gate of a FinFET covers three sides of the channel, while the gate of a planar MOSFET only covers one side of the channel. Therefore, compared with traditional planar MOSFETs, FinFETs have better channel control ability and effectively suppress the short-channel effect. However, with the continuous advancement of the process node, the size of the transistor has entered the nanometer scale, and it is necessary to increase the aspect ratio of the Fin structure to improve the device performance. However, due to the internal stress of the material, it is difficult for the Fin to maintain an upright state. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a fully surrounding gate field effect transistor based on diamond electrothermal regulation and a preparation method thereof. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0005] The present invention provides a fully surrounding gate field effect transistor based on diamond electrothermal regulation, including:

[0006] A substrate;

[0007] A buffer layer, disposed on the substrate;

[0008] A P-type diamond layer, disposed on the buffer layer;

[0009] An n-type Ga2O3 layer is disposed on the p-type diamond layer, and the n-type Ga2O3 layer, the p-type diamond layer, and a part of the buffer layer are stacked to form a cylindrical structure;

[0010] An isolation layer, a gate metal layer, and a protection layer are sequentially stacked from bottom to top on the buffer layer and are disposed around the side surface of the cylindrical structure from inside to outside;

[0011] The top surface of the n-type Ga2O3 layer is higher than the top surface of the protection layer, the top surfaces of the isolation layer and the gate metal layer are lower than the top surface of the protection layer, and the protection layer near the top portion is in contact with the side surface of the n-type Ga2O3 layer;

[0012] A source electrode is disposed on the n-type Ga2O3 layer and a part of the protection layer;

[0013] A drain electrode is disposed on the buffer layer that is not covered.

[0014] In an embodiment of the present invention, the substrate is a Ga2O3 substrate with a thickness of 300 - 650 μm, the doping ions are Si ions or Sn ions, and the doping concentration range is 1×10 18 ~6×10 19 cm -3 ; the buffer layer is an n-type Ga2O3 buffer layer with a thickness of 5 - 20 μm, the doping ions are Si ions or Sn ions, and the doping concentration range is 1×10 16 ~1×10 18 cm -3 .

[0015] In an embodiment of the present invention, the p-type diamond layer has a thickness of 300 - 600 nm, the doping ions are boron ions, and the doping concentration is 1×10 16 ~1×10 19 cm -3 .

[0016] In an embodiment of the present invention, the n-type Ga2O3 layer has a thickness of 400 - 1000 nm, and the doping concentration is 1×10 16 ~1×10 20 cm -3 .

[0017] In an embodiment of the present invention, the isolation layer is an Al2O3 isolation layer with a thickness of 5 - 30 nm.

[0018] In an embodiment of the present invention, the gate metal layer is a TiN layer with a thickness of 50 - 400 nm.

[0019] In one embodiment of the present invention, the protective layer is a SiN layer with a thickness of 100 - 500 nm.

[0020] In one embodiment of the present invention, the diameter of the cylindrical structure is 300 nm - 1000 nm.

[0021] The present invention provides a method for preparing a fully surrounding gate field effect transistor based on diamond electrothermal regulation, including:

[0022] Step 1: Obtain an epitaxial substrate, which includes a Ga2O3 substrate, an n-type Ga2O3 buffer layer, a P-type diamond layer, and an n-type doped Ga2O3 layer stacked in sequence from bottom to top;

[0023] Step 2: Use ICP etching to etch the n-type doped Ga2O3 layer, the P-type diamond layer, and part of the n-type Ga2O3 buffer layer to form a cylindrical structure;

[0024] Step 3: Use an ALD instrument to deposit an Al2O3 isolation layer on the device surface;

[0025] Step 4: Use a magnetron sputtering instrument to deposit a TiN gate metal layer on the Al2O3 isolation layer;

[0026] Step 5: Use a PECVD instrument to deposit a SiN layer on the TiN gate metal layer;

[0027] Step 6: Etch the SiN layer, the TiN gate metal layer, and the Al2O3 isolation layer at the top of the cylindrical structure to expose part of the n-type doped Ga2O3 layer;

[0028] Step 7: Use a PECVD instrument to deposit a SiN layer on the device surface;

[0029] Step 8: Use dry etching to etch the SiN layer at the top of the cylindrical structure and on the n-type Ga2O3 buffer layer to expose part of the n-type doped Ga2O3 layer and part of the n-type Ga2O3 buffer layer;

[0030] Step 9: Use an electron beam evaporation process to deposit a Ti / Al / Ni / Au stacked metal on the n-type doped Ga2O3 layer and the n-type Ga2O3 buffer layer;

[0031] Step 10: Perform ohmic annealing on the device to form source and drain electrodes.

[0032] In one embodiment of the present invention, in Step 2, the etched thickness of the n-type Ga2O3 buffer layer is 50 - 1000 nm, and the diameter of the cylindrical structure is 300 nm - 1000 nm.

[0033] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0034] 1. For the all-around gate field-effect transistor based on diamond electrothermal regulation of the present invention, its conductive channel is completely surrounded by the gate. Compared with the FinFET structure, it has a more excellent channel control ability and can effectively suppress the short-channel effect.

[0035] 2. For the all-around gate field-effect transistor based on diamond electrothermal regulation of the present invention, using P-type diamond as the P region can avoid the problem that it is difficult to prepare P-type Ga2O3.

[0036] The above description is only an overview of the technical solution of the present invention. In order to be able to more clearly understand the technical means of the present invention, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, the following specific embodiments are specifically given and described in detail in conjunction with the drawings as follows. Description of the Drawings

[0037] Figure 1 is a schematic cross-sectional structure diagram of an all-around gate field-effect transistor based on diamond electrothermal regulation provided by an embodiment of the present invention;

[0038] Figure 2 is a schematic diagram of a preparation method of an all-around gate field-effect transistor based on diamond electrothermal regulation provided by an embodiment of the present invention;

[0039] Figures 3a - 3j is a process flow chart of a preparation process of an all-around gate field-effect transistor based on diamond electrothermal regulation provided by an embodiment of the present invention. Detailed Embodiments

[0040] In order to further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the following provides a detailed description of an all-around gate field-effect transistor based on diamond electrothermal regulation and its preparation method according to the present invention in conjunction with the drawings and specific embodiments.

[0041] The foregoing and other technical contents, features and effects of the present invention can be clearly presented in the following detailed description in conjunction with the drawings. Through the description of the specific embodiments, a more in-depth and specific understanding of the technical means and effects adopted by the present invention to achieve the predetermined purpose can be obtained. However, the attached drawings are only for reference and illustration, and are not used to limit the technical solution of the present invention.

[0042] Example 1

[0043] Please refer to Figure 1 , Figure 1This is a schematic cross-sectional structure diagram of a fully-depleted surround-gate field-effect transistor based on diamond electrothermal regulation provided by an embodiment of the present invention. As shown in the figure, the fully-depleted surround-gate field-effect transistor based on diamond electrothermal regulation in this embodiment includes: a substrate 100, a buffer layer 101, a P-type diamond layer 102, an n-type Ga2O3 layer 103, an isolation layer 104, a gate metal layer 105, a protective layer 106, a source electrode 107, and a drain electrode 108.

[0044] Specifically, the buffer layer 101 is disposed on the substrate 100; the P-type diamond layer 102 is disposed on the buffer layer 101; the n-type Ga2O3 layer 103 is disposed on the P-type diamond layer 102.

[0045] In this embodiment, the n-type Ga2O3 layer 103, the P-type diamond layer 102, and a part of the buffer layer 101 are stacked to form a cylindrical structure.

[0046] Further, the isolation layer 104, the gate metal layer 105, and the protective layer 106 are sequentially stacked on the buffer layer 101 from bottom to top and are disposed around the side surface of the cylindrical structure from inside to outside.

[0047] In this embodiment, the top surface of the n-type Ga2O3 layer 103 is higher than the top surface of the protective layer 106, the top surfaces of the isolation layer 104 and the gate metal layer 105 are lower than the top surface of the protective layer 106, and the protective layer 106 near the top end is in contact with the side surface of the n-type Ga2O3 layer 103.

[0048] Further, the source electrode 107 is disposed on the n-type Ga2O3 layer 103 and a part of the protective layer 106; the drain electrode 108 is disposed on the buffer layer 101 that is not covered.

[0049] It should be noted that in this embodiment, the top surfaces of the isolation layer 104 and the gate metal layer 105 are lower than the top surface of the protective layer 106, and the protective layer 106 near the top end is in contact with the side surface of the n-type Ga2O3 layer 103, which can avoid device short circuit caused by the contact between the source electrode 107 and the gate metal layer 105.

[0050] Optionally, the substrate 100 is a Ga2O3 substrate with a thickness of 300 - 650 μm, the doping ion is Sn ion, and the doping concentration is 1×10 18 ~6×10 19 cm -3 ; the buffer layer 101 is an n-type Ga2O3 buffer layer with a thickness of 1 - 20 μm, the doping ion is Si ion or Sn ion, and the doping concentration is 1×10 16 ~1×10 18 cm -3 .

[0051] It should be noted that the substrate 100 can also be selected as other substrates such as a sapphire substrate.

[0052] Optionally, the thickness of the P-type diamond layer 102 is 300 - 600 nm, the doping ions are boron ions, and the doping concentration is 1×10 16 ~1×10 19 cm -3 .

[0053] In this embodiment, using P-type diamond as the P region can avoid the problem that P-type Ga2O3 is difficult to prepare.

[0054] Optionally, the thickness of the n-type Ga2O3 layer 103 is 400 - 1000 nm, the doping ions are Si ions or Sn ions, and the doping concentration is 1×10 16 ~1×10 20 cm -3 .

[0055] Optionally, the isolation layer 104 is an Al2O3 isolation layer with a thickness of 5 - 30 nm.

[0056] Optionally, the gate metal layer 105 is a TiN layer with a thickness of 50 - 400 nm. In this embodiment, the gate metal layer 105 serves as the gate of the field-effect transistor.

[0057] Optionally, the protective layer 106 is a SiN layer with a thickness of 100 - 500 nm.

[0058] Optionally, the diameter of the cylinder structure is 300 nm - 1000 nm.

[0059] For the all-around gate field-effect transistor based on diamond electrothermal regulation in this embodiment, the gate metal layer surrounds the side surface of the cylinder structure formed by stacking the n-type Ga2O3 layer, the P-type diamond layer, and part of the buffer layer to form an all-around gate structure, and its conductive channel is completely surrounded by the gate. Compared with the FinFET structure, it has better channel control ability and can effectively suppress the short-channel effect.

[0060] Embodiment 2

[0061] This embodiment provides a preparation method for an all-around gate field-effect transistor based on diamond electrothermal regulation, which is applicable to the all-around gate field-effect transistor based on diamond electrothermal regulation described in Embodiment 1. Please refer to Figure 2 , Figure 2 which is a schematic diagram of a preparation method for an all-around gate field-effect transistor based on diamond electrothermal regulation provided by an embodiment of the present invention. As shown in the figure, the preparation method of this embodiment includes:

[0062] Step 1: Obtain an epitaxial substrate, which includes a Ga2O3 substrate, an n-type Ga2O3 buffer layer, a P-type diamond layer, and an n-type doped Ga2O3 layer stacked in sequence from bottom to top;

[0063] Step 2: Use ICP etching to etch the n-type doped Ga2O3 layer, the P-type diamond layer, and a part of the n-type Ga2O3 buffer layer to form a cylindrical structure;

[0064] In this embodiment, the etching thickness of the n-type Ga2O3 buffer layer is 50 - 1000 nm, and the diameter of the cylindrical structure is 300 nm - 1000 nm.

[0065] Step 3: Use an ALD instrument to deposit an Al2O3 isolation layer on the device surface;

[0066] Step 4: Use a magnetron sputtering instrument to deposit a TiN gate metal layer on the Al2O3 isolation layer;

[0067] Step 5: Use a PECVD instrument to deposit a SiN layer on the TiN gate metal layer;

[0068] Step 6: Etch the SiN layer, the TiN gate metal layer, and the Al2O3 isolation layer at the top of the cylindrical structure to expose a part of the n-type doped Ga2O3 layer;

[0069] Step 7: Use a PECVD instrument to deposit a SiN layer on the device surface;

[0070] Step 8: Use dry etching to etch the SiN layer on the top of the cylindrical structure and the n-type Ga2O3 buffer layer to expose a part of the n-type doped Ga2O3 layer and a part of the n-type Ga2O3 buffer layer;

[0071] Step 9: Use an electron beam evaporation process to deposit a Ti / Al / Ni / Au stacked metal on the n-type doped Ga2O3 layer and the n-type Ga2O3 buffer layer;

[0072] Step 10: Perform ohmic annealing on the device to form source and drain electrodes.

[0073] Furthermore, the specific preparation process of the preparation method of the fully surrounding gate field effect transistor based on diamond electrothermal regulation in this embodiment will be described. Please refer to Figures 3a - 3j , Figures 3a - 3j which is a process flow chart of the preparation of a fully surrounding gate field effect transistor based on diamond electrothermal regulation provided by an embodiment of the present invention. As shown in the figure, the specific preparation process steps of this method include:

[0074] Step a: Obtain an epitaxial substrate and clean the substrate, as Figure 3a shown.

[0075] In this embodiment, the epitaxial substrate includes a Ga2O3 substrate 300 with a thickness of 300 - 650 μm, an n-type Ga2O3 buffer layer 301 with a thickness of 1 - 20 μm, a p-type diamond layer 302 with a thickness of 300 - 600 nm, and an n-type doped Ga2O3 layer 303 with a thickness of 400 - 1000 nm, which are stacked in sequence from bottom to top. Among them, the doping ions of the Ga2O3 substrate 300 are Si ions or Sn ions, and the doping concentration range is 1×10 18 ~6×10 19 cm -3 ; the doping ions of the n-type Ga2O3 buffer layer 301 are Si ions or Sn ions, and the doping concentration range is 1×10 16 ~1×10 18 cm -3 ; the doping ions of the n-type doped Ga2O3 layer 303 are Si ions or Sn ions, and the doping concentration is 1×10 16 ~1×10 20 cm -3 ; the doping ions of the p-type diamond layer 302 are boron ions, and the doping concentration is 1×10 16 ~1×10 19 cm -3 .

[0076] Step b: Etch to form a cylindrical structure, as shown in Figure 3b .

[0077] Specifically, spin-coat photoresist on the surface of the epitaxial substrate, and use the ICP etching method to first etch the 400 - 1000 nm n-type doped Ga2O3 layer 303. Among them, the upper electrode power is 250 - 300 W, the lower electrode power is 40 - 80 W, the chamber pressure is 10 mTorr, the gas flow rate is 30 - 60 sccm of Cl2, and the chuck temperature is 20°C.

[0078] Further, use the ICP etching method to etch the 300 - 600 nm p-type diamond layer 302. Among them, the upper electrode power is 250 - 300 W, the lower electrode power is 40 - 80 W, the chamber pressure is 10 mTorr, the gas flow rate is 30 - 60 sccm of O2, and the chuck temperature is 20°C.

[0079] Further, use the ICP etching method to etch the 50 - 1000 nm n-type Ga2O3 buffer layer 301. Among them, the upper electrode power is 250 - 300 W, the lower electrode power is 40 - 80 W, the chamber pressure is 10 mTorr, the gas flow rate is 30 - 60 sccm of Cl2, and the chuck temperature is 20°C.

[0080] Step c: Clean and perform surface damage repair treatment on the etched device.

[0081] Specifically, the photoresist is removed by using acetone, stripping solution, acetone, and isopropanol. In this embodiment, ultrasonic treatment with acetone solution is carried out for 5 min, water bath treatment with stripping solution at 60 °C is carried out for 10 min, ultrasonic treatment with acetone is carried out for 5 min, ultrasonic treatment with isopropanol is carried out for 5 min, rinsing with pure water is carried out for 2 min, and then drying with nitrogen is carried out.

[0082] Furthermore, wet processing is used to repair the damage on the device surface. In this embodiment, wet processing is carried out using a TMAH solution, where the concentration of the TMAH solution is 5-20%, the temperature of the wet processing is 80 °C, and the processing time is 10-30 min.

[0083] Step d: Deposit an Al2O3 isolation layer 304 on the device surface, as Figure 3c and 3d shown.

[0084] Specifically, use an ALD instrument to deposit Al2O3 on the device surface, with a deposition thickness of 5-30 nm, and then perform pattern etching to form the Al2O3 isolation layer 304.

[0085] Step e: Deposit a TiN gate metal layer 305 on the Al2O3 isolation layer 304, as Figure 3e shown.

[0086] Specifically, use a magnetron sputtering instrument to perform selective area deposition of the TiN gate metal layer 305, with a deposition thickness of 50-400 nm.

[0087] Step f: Deposit a SiN layer on the TiN gate metal layer, as Figure 3f shown.

[0088] Specifically, use a PECVD instrument to perform selective area deposition of the SiN layer, with a deposition thickness of 30-60 nm.

[0089] Step g: Etch the SiN layer, TiN gate metal layer 305, and Al2O3 isolation layer 304 at the top of the cylindrical structure to expose a part of the n-type doped Ga2O3 layer 303, as Figure 3g shown.

[0090] Specifically, after spin-coating photoresist on the device, exposure is carried out, and the photolithography pattern is circular with a diameter of 300 nm - 1000 nm.

[0091] Furthermore, a dry etching process is used to etch off the SiN layer. The etching machine is from Northern Microelectronics, and F-based etching is used, where CF4 = 20-30 sccm, O2 = 5-10 sccm, the pressure = 5 mTorr, the upper electrode power = 60-100 W, and the lower electrode power = 10-20 W.

[0092] Further, after the ashing process, the TiN gate metal layer 305 and the Al2O3 isolation layer 304 are etched away by a wet etching process. Specifically, the wet etching process uses an SC_1 solution (NH4OH:H2O2:H2O), with a water bath at 70 °C and an etching time of 3 - 10 min.

[0093] Step h: Perform a second deposition of the SiN layer on the device surface. The SiN layer deposited this time forms a SiN protection layer 306 with the SiN layer deposited in step f, as Figure 3h shown.

[0094] In this embodiment, the deposition thickness of the SiN layer is 100 - 500 nm.

[0095] Step i: Etch the SiN protection layer 306 on the top of the cylindrical structure and on the n-type Ga2O3 buffer layer 301 to expose a part of the n-type doped Ga2O3 layer 303 and a part of the n-type Ga2O3 buffer layer 301, as Figure 3i shown.

[0096] Specifically, spin coat a photoresist on the device surface. The photoresist selected is EPI621, and the spin coating process is: spin coat at a low speed of 500 r / min for 5 sec and at a high speed of 3000 r / min for 30 sec.

[0097] Further, use a dry etching process to etch away the excess SiN protection layer 306 and expose the source contact area and the drain contact area. In this embodiment, the etching machine used is from Northern Microelectronics, with F-based etching. Among them, CF4 = 20 - 30 sccm, O2 = 5 - 10 sccm, the pressure = 5 mTorr, the upper electrode power = 60 - 100 W, and the lower electrode power = 10 - 20 W.

[0098] Step j: Deposit a metal in the source contact area and the drain contact area to form a source 307 and a drain 308, as Figure 3j shown.

[0099] Specifically, use an electron beam evaporation process to deposit a Ti / Au or Ti / Al / Ni / Au laminated metal on the n-type doped Ga2O3 layer 303 and the n-type Ga2O3 buffer layer 301; the deposition thickness of the Ti / Au laminated metal is 20 - 40 / 100 - 400 nm, and the deposition thickness of the Ti / Al / Ni / Au laminated metal is 20 - 40 / 50 - 200 / 20 - 200 / 20 - 200 nm;

[0100] Further, perform an ohmic annealing on the device to form a source 307 and a drain 308, where the annealing temperature is 750 - 1000 °C and the annealing time is 50 - 80 sec.

[0101] It should be noted that in this text, the terms "include", "comprise" or any other variants are intended to cover non-exclusive inclusion, so that an article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed. Without more limitations, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the article or device including the said element. Similar words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The orientation or positional relationship indicated by "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation on the present invention.

[0102] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A fully-depleted surround-gate field-effect transistor based on diamond electrothermal regulation, characterized in that Comprising: A substrate; A buffer layer disposed on the substrate; A P-type diamond layer disposed on the buffer layer; An n-type Ga2O3 layer disposed on the P-type diamond layer, and the n-type Ga2O3 layer, the P-type diamond layer and a part of the buffer layer are stacked to form a cylindrical structure; An isolation layer, a gate metal layer and a protective layer are sequentially stacked from bottom to top on the buffer layer, and are arranged on the side surface of the cylindrical structure from inside to outside; The top surface of the n-type Ga2O3 layer is higher than the top surface of the protective layer, the top surfaces of the isolation layer and the gate metal layer are lower than the top surface of the protective layer, and the protective layer near the top part is in contact with the side surface of the n-type Ga2O3 layer; A source electrode disposed on the n-type Ga2O3 layer and a part of the protective layer; A drain electrode disposed on the buffer layer not covered.

2. The all-around gate field effect transistor based on diamond electrothermal regulation according to claim 1, wherein The substrate is a Ga2O3 substrate with a thickness of 300 - 650 μm. The doping ions are Si ions or Sn ions, and the doping concentration ranges from 1×10 18 to 6×10 19 cm -3 ; The buffer layer is an n-type Ga2O3 buffer layer with a thickness of 5 - 20 μm. The doping ions are Si ions or Sn ions, and the doping concentration ranges from 1×10 16 to 1×10 18 cm -3 .

3. The all-around gate field-effect transistor based on diamond electrothermal regulation according to claim 1, wherein The thickness of the P-type diamond layer is 300 - 600 nm, the doping ion is boron ion, and the doping concentration is 1×10 16 ~1×10 19 cm -3 .

4. The all-around gate field effect transistor based on diamond electrothermal regulation according to claim 1, wherein The thickness of the n-type Ga2O3 layer is 400 to 1000 nm, and the doping concentration is 1×10 16 ~1×10 20 cm -3 .

5. The all-around gate field effect transistor based on diamond electrothermal regulation according to claim 1, characterized in that The isolation layer is an Al2O3 isolation layer with a thickness of 5 - 30 nm.

6. The all-around gate field-effect transistor based on diamond electrothermal regulation according to claim 1, characterized in that The gate metal layer is a TiN layer with a thickness of 50 - 400 nm.

7. The all-around gate field-effect transistor based on diamond electrothermal regulation according to claim 1, wherein The protective layer is a SiN layer with a thickness of 100 - 500 nm.

8. The all-around gate field-effect transistor based on diamond electrothermal regulation according to claim 1, wherein The diameter of the cylindrical structure is 300 nm - 1000 nm.

9. A preparation method of a fully depleted surrounding gate field effect transistor based on diamond electrothermal regulation, characterized in that, Comprising: Step 1: Obtain an epitaxial substrate, which includes a Ga2O3 substrate, an n-type Ga2O3 buffer layer, a P-type diamond layer, and an n-type doped Ga2O3 layer stacked from bottom to top in sequence; Step 2: Use ICP etching method to etch the n-type doped Ga2O3 layer, the P-type diamond layer and a part of the n-type Ga2O3 buffer layer to form a cylindrical structure; Step 3: Use an ALD instrument to deposit an Al2O3 isolation layer on the device surface; Step 4: Use a magnetron sputtering instrument to deposit a TiN gate metal layer on the Al2O3 isolation layer; Step 5: Use a PECVD instrument to deposit a SiN layer on the TiN gate metal layer; Step 6: Etch the SiN layer, the TiN gate metal layer and the Al2O3 isolation layer at the top of the cylindrical structure to expose a part of the n-type doped Ga2O3 layer; Step 7: Use a PECVD instrument to deposit a SiN layer on the device surface; Step 8: Use dry etching to etch the SiN layer at the top of the cylindrical structure and on the n-type Ga2O3 buffer layer to expose a part of the n-type doped Ga2O3 layer and a part of the n-type Ga2O3 buffer layer; Step 9: Adopt an electron beam evaporation process to deposit a Ti / Al / Ni / Au stacked metal on the n-type doped Ga2O3 layer and the n-type Ga2O3 buffer layer; Step 10: Perform ohmic annealing on the device to form a source electrode and a drain electrode.

10. The manufacturing method of the all-around gate field-effect transistor based on diamond electrothermal regulation according to claim 9, characterized in that In the step 2, the etching thickness of the n-type Ga2O3 buffer layer is 50 - 1000 nm, and the diameter of the cylindrical structure is 300 nm - 1000 nm.

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