Method for preparing array substrate, array substrate, and display panel

Abstract

The present application discloses a method for preparing an array substrate, an array substrate, and a display panel. The method comprises the following steps: providing a substrate; forming a gate on the substrate; forming a gate insulating layer on the gate; forming an oxide semiconductor layer on the gate insulating layer, the oxide semiconductor layer including a channel; forming a channel protection layer on the oxide semiconductor layer, the channel protection layer covering the channel, the material of the channel protection layer including a metal; forming a source electrode and a drain electrode on the oxide semiconductor layer, the source electrode and the drain electrode being located on opposite sides of the channel protection layer; oxidizing the channel protection layer to form a water-soluble oxide layer; and introducing water vapor into the water-soluble oxide layer to remove the water-soluble oxide layer. The present application improves the stability of thin-film transistors while achieving a miniaturized design of thin-film transistors.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a method for preparing an array substrate, an array substrate, and a display panel. Background Art

[0002] Because oxide thin-film transistors are sensitive to hydrogen, when hydrogen is injected into the channel of an oxide thin-film transistor, it can cause the device's threshold voltage to significantly deviate negatively or even cause a short circuit. Specifically, for liquid crystal display panels, when the threshold voltage of the thin-film transistor in the gate drive circuit deviates negatively, it can cause device leakage, resulting in poor functionality of the gate drive circuit; when the threshold voltage of the thin-film transistor within the panel deviates negatively, it can cause display anomalies, such as pixels that are always on. Therefore, preventing hydrogen injection into the channel of the oxide thin-film transistor, and thus preventing the threshold voltage of the oxide thin-film transistor from deviating negatively, is crucial for the application of oxide semiconductors.

[0003] In existing array substrates, an etch-stop layer is typically placed on the surface of the channel to prevent hydrogen from injecting into the thin-film transistor channel and affecting the thin-film transistor's electrical stability. This creates an etch-stop thin-film transistor. However, the etch-stop layer increases the size of the thin-film transistor, hindering its miniaturization. Summary of the Invention

[0004] The embodiments of the present application provide a method for manufacturing an array substrate, an array substrate, and a display panel, so as to achieve a miniaturized design of thin film transistors while improving the stability of thin film transistors.

[0005] The present invention provides a method for preparing an array substrate, which includes the following steps:

[0006] providing a substrate;

[0007] forming a gate on the substrate;

[0008] forming a gate insulating layer on the gate;

[0009] forming an oxide semiconductor layer on the gate insulating layer, wherein the oxide semiconductor layer includes a channel;

[0010] forming a channel protection layer on the oxide semiconductor layer, wherein the channel protection layer covers the channel, and a material of the channel protection layer includes metal;

[0011] forming a source electrode and a drain electrode on the oxide semiconductor layer, wherein the source electrode and the drain electrode are located on opposite sides of the channel protection layer;

[0012] performing an oxidation treatment on the channel protection layer so as to form the channel protection layer into a water-soluble oxide layer; and

[0013] Water vapor is introduced into the water-soluble oxide layer to remove the water-soluble oxide layer.

[0014] Optionally, in some embodiments of the present application, the oxide semiconductor layer further includes a source contact and a drain contact, wherein the source contact and the drain contact are located on opposite sides of the channel, and the step of forming the source and the drain on the oxide semiconductor layer includes:

[0015] forming a source-drain metal layer on the oxide semiconductor layer, wherein the source-drain metal layer covers the channel protection layer, the source contact portion, and the drain contact portion;

[0016] The source-drain metal layer is patterned to form a source connected to the source contact portion and a drain connected to the drain contact portion.

[0017] Optionally, in some embodiments of the present application, the orthographic projection of the source on the plane where the substrate is located and the orthographic projection of the drain on the plane where the substrate is located are both located outside the orthographic projection of the channel protection layer on the plane where the substrate is located.

[0018] Optionally, in some embodiments of the present application, the step of introducing water vapor into the water-soluble oxide layer includes: introducing water vapor into the water-soluble oxide layer within a temperature range of 30°C-60°C.

[0019] Optionally, in some embodiments of the present application, the thickness of the water-soluble oxide layer is 1 / 10-1 / 5 of the thickness of the source electrode.

[0020] Optionally, in some embodiments of the present application, the thickness of the water-soluble oxide layer is 300 angstroms to 500 angstroms, and the thickness of the source electrode and the drain electrode is 2000 angstroms to 4000 angstroms.

[0021] Optionally, in some embodiments of the present application, the material of the channel protection layer is molybdenum, and the material of the water-soluble oxide layer is molybdenum oxide.

[0022] Optionally, in some embodiments of the present application, after the step of introducing water vapor into the water-soluble oxide layer, the method further includes: annealing the channel in an oxygen atmosphere.

[0023] An embodiment of the present application provides an array substrate, which is prepared by the method for preparing an array substrate described in any of the aforementioned embodiments.

[0024] An embodiment of the present application further provides a display panel, which includes the array substrate as described in the above embodiment.

[0025] In the preparation method of the array substrate provided in the present application, a channel protection layer is pre-formed on the channel of the oxide semiconductor layer. During the formation of the source and drain electrodes, due to the blocking and protective effect of the channel protection layer, hydrogen present in the system will not be injected into the channel, thereby avoiding the influence of hydrogen on the channel; after the source and drain electrodes are formed, since the channel protection layer is formed into an easily removable water-soluble oxide layer through oxidation treatment, the water-soluble oxide layer can be removed by passing water vapor into the water-soluble oxide layer, thereby reducing the size of the thin film transistor, and further improving the stability of the thin film transistor while enabling the miniaturization design of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. The drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 Schematic diagram of the process of preparing the array substrate provided in an embodiment of the present application.

[0028] Figures 2A to 2I yes Figure 1 The structure diagram of each step in the preparation method of the array substrate shown is obtained in sequence.

[0029] Figure 3 It is a structural schematic diagram of the array substrate provided in this application.

[0030] Figure 4 It is a structural schematic diagram of the display panel provided in this application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0032] The present application provides a method for manufacturing an array substrate, an array substrate, and a display panel, which are described in detail below.

[0033] Please refer to Figure 1 The present application provides a method for preparing an array substrate, which comprises the following steps:

[0034] 101: providing a substrate;

[0035] 102: forming a gate on a substrate;

[0036] 103: forming a gate insulating layer on the gate;

[0037] 104: forming an oxide semiconductor layer on the gate insulating layer, wherein the oxide semiconductor layer includes a channel;

[0038] 105: forming a channel protection layer on the oxide semiconductor layer, where the channel protection layer covers the channel, and the material of the channel protection layer includes metal;

[0039] 106: forming a source electrode and a drain electrode on the oxide semiconductor layer, wherein the source electrode and the drain electrode are located on opposite sides of the channel protection layer;

[0040] 107: performing oxidation treatment on the channel protection layer to form the channel protection layer into a water-soluble oxide layer; and

[0041] 108: Water vapor is introduced into the water-soluble oxide layer to remove the water-soluble oxide layer.

[0042] Therefore, in the preparation method of the array substrate provided in the present application, a channel protection layer is formed in advance on the channel of the oxide semiconductor layer. During the formation of the source and drain electrodes, due to the blocking and protective effect of the channel protection layer, the hydrogen present in the system will not be injected into the channel, thereby avoiding the influence of hydrogen on the channel; after the source and drain electrodes are formed, since the channel protection layer is formed into an easily removable water-soluble oxide layer through oxidation treatment, the water-soluble oxide layer can be removed by passing water vapor into the water-soluble oxide layer, thereby reducing the size of the thin film transistor, and further improving the stability of the thin film transistor while realizing the miniaturization design of the thin film transistor.

[0043] The following describes in detail the method for preparing the array substrate provided in this application through specific examples.

[0044] 101: Provide a substrate 11, such as Figure 2A shown.

[0045] The substrate 11 may be a rigid substrate, such as a glass substrate; or, the substrate 11 may be a flexible substrate, such as a polyimide substrate. The present application does not specifically limit the material of the substrate 11.

[0046] 102: Form a gate 12 on the substrate 11, such as Figure 2Bshown.

[0047] Specifically, physical vapor deposition and photolithography are sequentially used to form the gate 12. The gate 12 may be made of one or more of copper, aluminum, molybdenum, and titanium, or an alloy of at least two of the above materials.

[0048] 103: Form a gate insulating layer 13 on the gate 12, such as Figure 2C shown.

[0049] Specifically, the gate insulating layer 13 is formed using a chemical vapor deposition process. The material of the gate insulating layer 13 may include one or more of silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the gate insulating layer 13 is silicon oxide. The thickness of the gate insulating layer 13 is 1000 angstroms to 2000 angstroms.

[0050] 104: forming an oxide semiconductor layer 14 on the gate insulating layer 13, wherein the oxide semiconductor layer 14 includes a channel 141, such as Figure 2D shown.

[0051] Specifically, the oxide semiconductor layer 14 is formed using a physical vapor deposition process and a photolithography process. The material of the oxide semiconductor layer 14 includes one or more of IGZO, IGZTO, IGTO, IZTO, ITO, and IZO. In this embodiment, the material of the oxide semiconductor layer 14 is IGZO. The thickness of the oxide semiconductor layer 14 is 200 angstroms to 450 angstroms.

[0052] In this embodiment, the oxide semiconductor layer 14 further includes a source contact portion 142 and a drain contact portion 143 . The source contact portion 142 and the drain contact portion 143 are located on opposite sides of the channel 141 .

[0053] 105: forming a channel protection layer 151 on the oxide semiconductor layer 14, the channel protection layer 151 covers the channel 141, and the material of the channel protection layer 151 includes metal, such as Figure 2E shown.

[0054] Specifically, the channel protection layer 151 is formed using a physical vapor deposition process and a photolithography process. In this embodiment, the material of the channel protection layer 151 is molybdenum. Because molybdenum can prevent hydrogen from being injected into the channel 141 and can isolate water vapor, it can provide good protection for the channel protection layer 151. The channel protection layer 151 completely covers the channel 141 to maximize the barrier protection effect of the channel protection layer 151.

[0055] 106 : forming a source electrode 16 and a drain electrode 17 on the oxide semiconductor layer 14 . The source electrode 16 and the drain electrode 17 are located on opposite sides of the channel protection layer 151 .

[0056] Specifically, step 106 includes:

[0057] 1061: forming a source-drain metal layer 161 on the oxide semiconductor layer 14, the source-drain metal layer 161 covers the channel protection layer 151, the source contact portion 142 and the drain contact portion 143, as shown in FIG. Figure 2F shown.

[0058] Specifically, the source / drain metal layer 161 is formed by physical vapor deposition. The material of the source / drain metal layer 161 may include one or more of copper, aluminum, molybdenum and titanium, or an alloy of at least two of the above materials.

[0059] 1062: Patterning the source-drain metal layer 161 to form a source 16 connected to the source contact portion 142 and a drain 17 connected to the drain contact portion 143, as shown in FIG. Figure 2G shown.

[0060] Specifically, the source / drain metal layer 161 is patterned using a photolithography process. The photolithography process includes exposure, development, and etching. During the etching process of the source / drain metal layer 161, due to the blocking and protective effect of the channel protection layer 151, hydrogen in the system where the source / drain metal layer 161 is etched will not be injected into the channel 141, thereby preventing the influence of hydrogen on the channel 141. In addition, because the molybdenum used in the channel protection layer 151 can isolate external water vapor, the channel protection layer 151 can also prevent external water vapor from invading the channel 141.

[0061] In this embodiment, the orthographic projections of the source 16 and the drain 17 on the plane of the substrate 11 are both located outside the orthographic projection of the channel protection layer 151 on the plane of the substrate 11 .

[0062] 107: Oxidizing the channel protection layer 151 to form the channel protection layer 151 into a water-soluble oxide layer 15, such as Figure 2H shown.

[0063] Specifically, since molybdenum oxide is soluble in water, oxygen is introduced into the channel protection layer 151 to oxidize the channel protection layer 151, thereby forming a water-soluble oxide layer 15. The water-soluble oxide layer 15 is made of easily removable molybdenum oxide.

[0064] In this embodiment, the thickness of the water-soluble oxide layer 15 is 1 / 10-1 / 5 of the thickness of the source electrode 16. Because the water-soluble oxide layer 15 is located between the source electrode 16 and the drain electrode 17, this arrangement prevents the formation of residual water-soluble oxide on the contact surfaces between the water-soluble oxide layer 15 and the source electrode 16, and on the contact surfaces between the water-soluble oxide layer 15 and the drain electrode 17, during the subsequent removal of the water-soluble oxide layer 15, thereby preventing the conductive properties of the source electrode 16 and the drain electrode 17 from being affected. In some specific embodiments, the thickness of the water-soluble oxide layer 15 is 1 / 10, 1 / 9, 1 / 8, 1 / 7, 1 / 6, or 1 / 5 of the thickness of the source electrode 16.

[0065] In this embodiment, the thickness of the water-soluble oxide layer 15 is 1 / 6 of the thickness of the source electrode 16. Within this range, the subsequent removal of the water-soluble oxide layer 15 can completely avoid affecting the source electrode 16 and the drain electrode 17. The thickness of the water-soluble oxide layer 15 is 300-500 angstroms, and the thickness of the source electrode 16 and the drain electrode 17 are the same, both 2000-4000 angstroms. In this embodiment, the thickness of the water-soluble oxide layer 15 can be 500 angstroms, and the thickness of the source electrode 16 can be 3000 angstroms.

[0066] 108: Water vapor is introduced into the water-soluble oxide layer 15 to remove the water-soluble oxide layer 15, such as Figure 2I shown.

[0067] Specifically, after water vapor is introduced into the water-soluble oxide layer 15, the water-soluble oxide in the water-soluble oxide layer 15 volatilizes and is then removed from the oxide semiconductor layer 14. While water vapor is introduced into the water-soluble oxide layer 15, bombardment is performed in an oxygen atmosphere to improve the removal efficiency of the water-soluble oxide layer 15 and prevent residue.

[0068] In this embodiment, water vapor is introduced into the water-soluble oxide layer 15 at a temperature within a range of 30° C. to 60° C. In some embodiments, the temperature may be set to 30° C., 35° C., 40° C., 45° C., 50° C., 55° C., or 60° C. In this embodiment, water vapor is introduced into the water-soluble oxide layer 15 at a temperature of 40° C. to improve the volatilization efficiency of the water-soluble oxide, thereby further preventing the water-soluble oxide from remaining.

[0069] Furthermore, since the orthographic projection of the source electrode 16 on the plane where the substrate 11 is located and the orthographic projection of the drain electrode 17 on the plane where the substrate 11 is located are both located outside the orthographic projection of the channel protection layer 151 on the plane where the substrate 11 is located, when the water-soluble oxide layer 15 is removed, it will not affect the source electrode 16 and the drain electrode 17.

[0070] In this embodiment, after step 108, the process further includes: performing an annealing treatment on the channel 141 in an oxygen atmosphere to repair defects within the channel 141. In the oxygen atmosphere, oxygen is used to compensate for defects within the channel 141, thereby preventing electrons in the channel 141 from being trapped and causing a decrease in the current in the channel 141, thereby improving the electrical performance of the device. After the above steps, the gate 12, the gate insulating layer 13, the oxide semiconductor layer 14, the source 16, and the drain 17 form the thin film transistor 10A.

[0071] Therefore, in the preparation method of the array substrate 10 provided in this embodiment, since a channel protection layer 151 is pre-formed on the channel 141 of the oxide semiconductor layer 14, during the formation of the source electrode 16 and the drain electrode 17, due to the blocking and protective effect of the channel protection layer 151, the hydrogen present in the system will not be injected into the channel 141, thereby avoiding the influence of hydrogen on the channel 141, thereby improving the stability of the thin film transistor 10A; after the source electrode 16 and the drain electrode 17 are formed, since the channel protection layer 151 is formed into an easily removable water-soluble oxide layer 15 through oxidation treatment, the water-soluble oxide layer 15 can be removed by passing water vapor into the water-soluble oxide layer 15, thereby reducing the size of the thin film transistor 10A, and further improving the stability of the thin film transistor 10A while realizing a miniaturized design of the thin film transistor 10A.

[0072] It should be noted that when the array substrate 10 of this embodiment is applied to a liquid crystal display panel, the preparation method of the array substrate 10 also includes the steps of sequentially forming a first passivation layer, an organic insulating layer, a common electrode layer, a second passivation layer and a pixel electrode layer on the thin film transistor 10A. The relevant preparation methods are all existing technologies and will not be repeated here.

[0073] Please refer to Figure 3 The present embodiment further provides an array substrate 30. The array substrate 30 includes a substrate 11 and a thin film transistor 10A disposed on the substrate 11. The thin film transistor 10A includes a gate electrode 12, a gate insulating layer 13, an oxide semiconductor layer 14, a source electrode 16, and a drain electrode 17 disposed in sequence. It should be noted that the thin film transistor 10A in this embodiment may be the thin film transistor 10A prepared in the method for preparing the array substrate 10 described in the previous embodiment. The relevant preparation method can refer to the description of the previous embodiment and will not be repeated here.

[0074] Furthermore, in this embodiment, the array substrate 30 may further include a first passivation layer 18, an organic insulating layer 19, a common electrode layer 20, a second passivation layer 21, and a pixel electrode layer 22 stacked on the source electrode 16 and the drain electrode 17. The pixel electrode layer 22 includes a pixel electrode 221, which is connected to the drain electrode 17 through a via (not shown).

[0075] Furthermore, the present application also provides a display panel. The display panel may be a liquid crystal display panel, an organic light emitting diode display panel, a mini light emitting diode display panel or a micro light emitting diode display panel. Figure 4 As shown, taking the display panel as a liquid crystal display panel 100 as an example, the liquid crystal display panel 100 includes an array substrate 30 and a color filter substrate 40 that are arranged opposite to each other, and a liquid crystal layer 50 disposed between the array substrate 30 and the color filter substrate 40. The structure of the array substrate 30 is the same as that of the array substrate 30 described in the previous embodiment. For details, please refer to the description of the previous embodiment and will not be repeated here.

[0076] The above is a detailed introduction to a method for preparing an array substrate, an array substrate, and a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for preparing an array substrate, characterized in that: The following steps are involved: providing a substrate; forming a gate on the substrate; forming a gate insulating layer on the gate; forming an oxide semiconductor layer on the gate insulating layer, wherein the oxide semiconductor layer includes a channel; forming a channel protection layer on the oxide semiconductor layer, wherein the channel protection layer covers the channel, and a material of the channel protection layer includes metal; forming a source electrode and a drain electrode on the oxide semiconductor layer, wherein the source electrode and the drain electrode are located on opposite sides of the channel protection layer; performing an oxidation treatment on the channel protection layer so as to form the channel protection layer into a water-soluble oxide layer; and Water vapor is introduced into the water-soluble oxide layer to remove the water-soluble oxide layer.

2. The method for preparing an array substrate according to claim 1, wherein: The oxide semiconductor layer further includes a source contact portion and a drain contact portion, wherein the source contact portion and the drain contact portion are located on opposite sides of the channel. The step of forming the source and the drain on the oxide semiconductor layer includes: forming a source-drain metal layer on the oxide semiconductor layer, wherein the source-drain metal layer covers the channel protection layer, the source contact portion, and the drain contact portion; The source-drain metal layer is patterned to form a source connected to the source contact portion and a drain connected to the drain contact portion.

3. The method for preparing an array substrate according to claim 2, wherein: The orthographic projection of the source electrode on the plane where the substrate is located and the orthographic projection of the drain electrode on the plane where the substrate is located are both located outside the orthographic projection of the channel protection layer on the plane where the substrate is located.

4. The method for preparing an array substrate according to claim 1, wherein: The step of introducing water vapor into the water-soluble oxide layer comprises: introducing water vapor into the water-soluble oxide layer at a temperature range of 30° C. to 60° C.

5. The method for preparing an array substrate according to claim 4, wherein: The thickness of the water-soluble oxide layer is 1 / 10-1 / 5 of the thickness of the source electrode.

6. The method for preparing an array substrate according to claim 5, wherein: The thickness of the water-soluble oxide layer is 300 angstroms to 500 angstroms, and the thickness of the source electrode and the drain electrode is 2000 angstroms to 4000 angstroms.

7. The method for preparing an array substrate according to claim 1, wherein: The material of the channel protection layer is molybdenum, and the material of the water-soluble oxide layer is molybdenum oxide.

8. The method for preparing an array substrate according to claim 1, wherein: After the step of introducing water vapor into the water-soluble oxide layer, the method further includes: performing annealing treatment on the channel in an oxygen atmosphere.

9. An array substrate, characterized in that: The array substrate is prepared by the method for preparing an array substrate according to any one of claims 1 to 8.

10. A display panel, characterized in that: The display panel includes the array substrate according to claim 9.

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