Low capacitance TVS device structure and manufacturing method

Abstract

The present invention discloses a low capacitance TVS structure, comprising a low capacitance diode D1 and a low breakdown voltage TVS diode D2, wherein the low capacitance diode D1 is formed on a wafer; the P+ region in the low capacitance diode D1 is formed on the front of the wafer; the N-type doped polysilicon column in the low breakdown voltage TVS diode D2 is arranged in the wafer; the N-type doped polysilicon column is penetrated through the back of the wafer by wafer back grinding and dry etching; a heavily doped P+ type Ge layer or a P+ type Si layer is evaporated or sputtered on the back of the wafer; the polysilicon column in the low breakdown voltage TVS diode D2 extends to the heavily doped P+ type Ge layer or the P+ type Si layer prepared by evaporation or sputtering; and the wafer is a high resistance N-type single crystal. The present invention also discloses a method for manufacturing the low capacitance TVS structure. The present invention uses a high resistance single crystal to replace a high resistance epitaxial wafer, completely eliminating the difficult epitaxial problem.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device preparation, and in particular to a low-capacitance TVS device structure and a preparation method thereof. Background Art

[0002] Transient Voltage Suppressor (TVS) is a circuit protection device used to protect sensitive circuit components from transient high-voltage spike pulses. TVS is a diode-type protection device. When the input voltage is higher than the avalanche breakdown point, it can quickly change the impedance value between the two ends from high impedance to low impedance, thereby shunting excess current and clamping the voltage at both ends to a predetermined value. Like all voltage clamps, after the transient high-voltage spike, TVS will automatically return to a high-impedance state.

[0003] In order to improve the discharge capability of TVS, deep trench technology was introduced into the manufacturing process of TVS. Through deep trench etching and filling with doped polysilicon, the junction area of ​​PN junction was increased, thereby improving the discharge capability of the device. At the same time, the introduction of high-resistance epitaxial technology makes the capacitance of the device much smaller than that of ordinary TVS, which is very suitable for data interface circuits.

[0004] The device structure and equivalent circuit diagram of the existing low capacitance deep trench TVS can be found in Figure 1 and Figure 2 In the existing low-capacitance deep trench TVS structure, a TVS diode D2 is formed between the N+ doped polysilicon in the deep trench and the P+ substrate; in addition, a PN junction D1 is formed between the P-type doped region and the high-resistance (low-concentration doped) N-type epitaxial layer, and the barrier capacitance of this PN junction D1 is extremely small; by connecting this PN junction D1 and the TVS diode D2 in series, the overall capacitance of the device is very small, thereby improving the working speed of the IO interface.

[0005] The existing low-capacitance TVS is composed of a low-capacitance diode D1 and a low-breakdown voltage TVS diode D2. Among them, the low-breakdown voltage TVS diode D2 is a PN junction between the N+ type doped polysilicon and the P+ type heavily doped substrate in the deep trench, and this deep trench needs to penetrate the N-type high-resistance epitaxial layer / N+ type buffer layer; and the low-capacitance diode D1 is a PIN diode formed between the high-resistance N-type epitaxial layer grown on this P+ type heavily doped substrate and the P-type doped region. It is extremely difficult to grow a high-resistance N-type epitaxial layer on a heavily doped P+ type substrate. In order to suppress the out-diffusion / self-doping effect of heavily doped P-type impurities during the epitaxial process, back sealing and / or N+ type buffer layer methods are currently used, but the process is still very difficult to achieve. Summary of the invention

[0006] One of the technical problems to be solved by the present invention is to provide a new low-capacitance TVS structure for the above-mentioned problems existing in the existing low-capacitance TVS, using a high-resistance single crystal wafer to replace the high-resistance epitaxial wafer, and completely eliminating the difficult epitaxial problem.

[0007] The second technical problem to be solved by the present invention is to provide a method for manufacturing the above-mentioned new low-capacitance TVS structure.

[0008] In order to achieve the above-mentioned purpose of the invention, the low-capacitance TVS structure of the present invention includes a low-capacitance diode D1 and a low-breakdown voltage TVS diode D2, characterized in that the low-capacitance diode D1 is formed on a wafer; the P+ region in the low-capacitance diode D1 is formed on the front side of the wafer; the N-type doped polysilicon column in the low-breakdown voltage TVS diode D2 is arranged in the wafer; the N-type doped polysilicon column penetrates through the back side of the wafer by means of wafer back grinding and dry etching; a heavily doped P+ type Ge layer or a P+ type Si layer is evaporated or sputtered on the back side of the wafer; the polysilicon column in the low-breakdown voltage TVS diode D2 extends to the heavily doped P+ type Ge layer or the P+ type Si layer prepared by evaporation or sputtering; and the wafer is a high-resistance N-type single crystal.

[0009] In a preferred embodiment of the present invention, metal bumps are prepared on the bonding pads of the low-capacitance diode D1 and the bonding pads of the low-breakdown voltage TVS diode D2 on the front side of the wafer.

[0010] In a preferred embodiment of the present invention, the front side of the wafer is covered with an epoxy resin molding layer; the front side of the metal bump exposes the epoxy resin molding layer.

[0011] The method for manufacturing the low capacitance TVS structure of the present invention comprises the following steps:

[0012] Step 1: Prepare a wafer, wherein the wafer is a high-resistance N-type single crystal wafer;

[0013] Step 2: Oxidize the front side of the wafer to form an oxide layer; photolithography is used to determine the position of the groove and etch the corresponding oxide layer, and then a groove is etched in the wafer; the groove corresponds to the position of the N-type doped polysilicon column in the low breakdown voltage TVS diode D2; the bottom of each groove does not penetrate the back side of the wafer;

[0014] Step 3: Depositing a SiO2 layer at the bottom of each trench;

[0015] Step 4: depositing N-type doped polysilicon on the surface of the oxide layer and allowing the N-type doped polysilicon to completely fill each trench;

[0016] Step 5: Etching away the N-type doped polysilicon on the surface of the wafer, so that the N-type doped polysilicon is completely embedded in the groove to form an N-type doped polysilicon column with an oxide layer at the bottom;

[0017] Step 6: forming a P+ region of the low capacitance diode D1 at a position of the surface oxide layer corresponding to the low capacitance diode D1, and forming the low capacitance diode D1 between the P+ region and the wafer;

[0018] Step 7: Opening contact holes on the oxide layer on the front side of the wafer and evaporating or sputtering metal Al to form a metal Al layer; performing photolithography and etching on the metal Al layer to prepare two bonding pads of the device; one of the bonding pads is connected to the N-type doped polysilicon column of the low breakdown voltage TVS diode D2, and the other bonding pad is connected to the P+ type region of the low capacitance diode D1;

[0019] Step 8: Making a metal bump of the low breakdown voltage TVS diode D2 on the pressure welding point of the low breakdown voltage TVS diode D2; making a metal bump of the low capacitance diode D1 on the pressure welding point of the low capacitance diode D1;

[0020] Step 9: Covering the surface of the wafer with a layer of epoxy resin molding layer, wherein the epoxy resin molding layer completely covers the metal bumps on the pressure welding point of the low breakdown voltage TVS diode D2 and the metal bumps on the pressure welding point of the low capacitance diode D1; then grinding the epoxy resin molding layer so that the front side of the metal bumps on the pressure welding point of the low breakdown voltage TVS diode D2 and the front side of the metal bumps on the pressure welding point of the low capacitance diode D1 are exposed from the epoxy resin molding layer;

[0021] Step 10: Grinding and dry etching the back side of the wafer to expose the N-type doped polysilicon column;

[0022] Step 11, remove the oxide layer at the bottom of the groove, and then form a heavily doped P+ type Ge layer or a P+ type Si layer on the back side of the wafer formed in step 10 by evaporation or sputtering, and form a low breakdown voltage TVS diode D2 between the heavily doped P+ type Ge layer or the P+ type Si layer and the polysilicon column.

[0023] In a preferred embodiment of the present invention, in step 10, the back side of the wafer is ground and dry-etched to expose the N-type doped polysilicon column, and the specific steps are:

[0024] Step 10a, grinding the back side of the wafer, wherein the oxide layer at the bottom of the groove does not expose the back side of the wafer after grinding;

[0025] Step 10b: etching the back side of the wafer formed in step 10a to expose the oxide layer at the bottom of the trench; continuing silicon etching with the oxide layer at the bottom of the trench as a shielding layer to expose the N-type doped polysilicon column.

[0026] In a preferred embodiment of the present invention, in step 11, a heavily doped P+ type Ge layer or a P+ type Si layer is formed on the back side of the wafer formed in step 10 by an evaporation method or a sputtering method. Specifically, a heavily doped P+ type Ge layer or a P+ type Si layer is deposited on the back side of the wafer formed in step 10 by an evaporation method or a sputtering method.

[0027] The present invention adopts a high-resistance N-type single crystal to replace the high-resistance epitaxial wafer in the prior art, completely eliminating the difficult epitaxy problem. Metal bumps are respectively arranged on the pressure welding point of the low-capacitance diode D1 and the pressure welding point of the low-breakdown voltage TVS diode D2; the surface of the wafer is covered with an epoxy resin plastic sealing layer and the resin layer is grinded to expose the metal bumps on the pressure welding point of the low-capacitance diode D1 and the metal bumps on the pressure welding point of the low-breakdown voltage TVS diode D2; the low-voltage TVS diode adopts a PN junction between an N+ type polysilicon column and an evaporated or sputtered heavily doped P+ type Ge layer or a P+ type Si layer, rather than a traditional PN junction between an N+ type polysilicon column and a P+ type substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a structural schematic diagram of an existing low-capacitance deep-trench TVS.

[0029] Figure 2 Schematic diagram of the equivalent circuit of the existing low-capacitance deep-trench TVS.

[0030] Figure 3 This is a schematic diagram of the structure of the high-resistance N-type single crystal in step 1 of the present invention.

[0031] Figure 4 It is a schematic diagram of step 2 of the present invention.

[0032] Figure 5 Schematic diagram of step 3 of the present invention.

[0033] Figure 6 It is a schematic diagram of step 4 of the present invention.

[0034] Figure 7 This is a schematic diagram of step 5 of the present invention.

[0035] Figure 8 This is a schematic diagram of step 6 of the present invention.

[0036] Fig. 9 This is a schematic diagram of step 7 of the present invention.

[0037] Fig.10It is a schematic diagram of step 8 of the present invention.

[0038] Fig.11 It is a schematic diagram of step 9 of the present invention.

[0039] Fig.12 Schematic diagram of step 10 of the present invention.

[0040] Fig.13 It is a schematic diagram of step 11 of the present invention.

[0041] Fig.14 and Fig.15 It is a schematic diagram of the low capacitance TVS structure of the present invention. DETAILED DESCRIPTION

[0042] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments.

[0043] The method for manufacturing a low capacitance TVS structure of the present invention comprises the following steps:

[0044] Step 1: See Figure 3 , prepare a high-resistance N-type single crystal wafer 1;

[0045] Step 2: See Figure 4 , oxidize the front side of the high-resistance N-type single crystal 1 to form an oxide layer 2; determine the position of the groove 3 by photolithography and etch the corresponding oxide layer 2, and then etch the groove 3 in the high-resistance N-type single crystal 1; the groove 3 corresponds to the position of the N-type doped polysilicon column in the low breakdown voltage TVS diode D2; the bottom of each groove 3 does not penetrate the back side 4 of the high-resistance N-type single crystal 1;

[0046] Step 3: See Figure 5 , depositing a SiO2 layer 5 at the bottom of each trench 3;

[0047] Step 4: See Figure 6 , depositing N-type doped polysilicon 7 on the surface 6 of the oxide layer 2 and making the N-type doped polysilicon 7 completely fill each trench 3;

[0048] Step 5: See Figure 7 , etching away the N-type doped polysilicon 7 on the surface 6 of the high-resistance N-type single crystal wafer 1, so that the N-type doped polysilicon 7 is completely embedded in the groove 3, forming an N-type doped polysilicon column 8 with an oxide layer 5 at the bottom;

[0049] Step 6: See Figure 8 , a P+ region 10 of the low capacitance diode D1 is formed at a position of the oxide layer 2 on the surface of the wafer 1 corresponding to the low capacitance diode D1, and a low capacitance diode D1 is formed between the P+ region 10 and the high resistance N-type single crystal wafer 1;

[0050] Step 7: See Fig. 9, opening contact holes 15 and 17 on the oxide layer 2 on the front side of the wafer 1, evaporating or sputtering metal Al to form a metal Al layer, performing photolithography and etching on the metal Al layer, and preparing two bonding pads 13 and 14 of the device; one of the bonding pads 13 is connected to the N-type doped polysilicon 8 of the low breakdown voltage TVS diode D2, and the other bonding pad 14 is connected to the P+ type region 10 of the low capacitance diode D1;

[0051] Step 8: See Fig.10 , a metal bump 19 of the low breakdown voltage TVS diode D2 is made on the pressure welding point 13 of the low breakdown voltage TVS diode D2; a metal bump 20 of the low capacitance diode D1 is made on the pressure welding point 14 of the low capacitance diode D1;

[0052] Step 9: See Fig.11 , covering the surface of the wafer with a layer of epoxy resin molding layer 21, the epoxy resin molding layer 21 completely covers the metal bumps 19 on the pressure welding point 13 of the low breakdown voltage TVS diode D2 and the metal bumps 20 on the pressure welding point 14 of the low capacitance diode D1; then grinding the epoxy resin molding layer 21, so that the upper surfaces of the metal bumps 19 on the pressure welding point 13 of the low breakdown voltage TVS diode D2 and the metal bumps 20 on the pressure welding point 14 of the low capacitance diode D1 are exposed from the epoxy resin molding layer;

[0053] Step 10: See Fig.12 , grinding the back side 4 of the high-resistance N-type single crystal 1, after which the oxide layer 3 at the bottom of the groove 3 must not be exposed from the back side 4 of the high-resistance N-type single crystal 1;

[0054] Step 11: See Fig.13 , performing dry silicon etching on the back side 4 of the high-resistance N-type single crystal 1 formed in step 10 to expose the oxide layer 3 at the bottom of the trench 3; continuing silicon etching with the oxide layer 3 at the bottom of the trench 3 as a shielding layer to expose the N-type doped polysilicon column 8;

[0055] Step 12, see Fig.14 and Fig.15 , remove the oxide layer 3 at the bottom of the groove 3, and then evaporate or sputter a heavily doped P+ type Ge layer or P+ type Si layer 26 on the back side 4 of the high resistance N-type single crystal 1 formed in step 11, and form a low breakdown voltage TVS diode D2 between the heavily doped P+ type Ge layer or P+ type Si layer 26 and the polysilicon column 8.

Claims

1. A method for manufacturing a low capacitance TVS structure, characterized in that: The steps include: Step 1: Prepare a wafer, wherein the wafer is a high-resistance N-type single crystal wafer; Step 2: Oxidize the front side of the wafer to form an oxide layer; photolithography determines the location of the groove and etches the corresponding oxide layer, and then etches a groove in the wafer; this groove corresponds to the location of the N-type doped polysilicon column in the low breakdown voltage TVS diode D2; The bottom of each groove does not penetrate the back side of the wafer; Step 3: Depositing a SiO2 layer at the bottom of each trench; Step 4: depositing N-type doped polysilicon on the surface of the oxide layer and allowing the N-type doped polysilicon to completely fill each trench; Step 5: Etching away the N-type doped polysilicon on the surface of the wafer, so that the N-type doped polysilicon is completely embedded in the groove to form an N-type doped polysilicon column with an oxide layer at the bottom; Step 6: forming a P+ region of the low capacitance diode D1 at a position of the oxide layer corresponding to the low capacitance diode D1, and forming the low capacitance diode D1 between the P+ region and the wafer; Step 7: Opening contact holes on the oxide layer on the front side of the wafer and evaporating or sputtering metal Al to form a metal Al layer; performing photolithography and etching on the metal Al layer to prepare two bonding pads of the device; one of the bonding pads is connected to the N-type doped polysilicon column of the low breakdown voltage TVS diode D2, and the other bonding pad is connected to the P+ type region of the low capacitance diode D1; Step 8: Making a metal bump of the low breakdown voltage TVS diode D2 on the pressure welding point of the low breakdown voltage TVS diode D2; making a metal bump of the low capacitance diode D1 on the pressure welding point of the low capacitance diode D1; Step 9: Covering the surface of the wafer with a layer of epoxy resin molding layer, wherein the epoxy resin molding layer completely covers the metal bumps on the pressure welding point of the low breakdown voltage TVS diode D2 and the metal bumps on the pressure welding point of the low capacitance diode D1; then grinding the epoxy resin molding layer so that the front side of the metal bumps on the pressure welding point of the low breakdown voltage TVS diode D2 and the front side of the metal bumps on the pressure welding point of the low capacitance diode D1 are exposed from the epoxy resin molding layer; Step 10: Grinding and dry etching the back side of the wafer to expose the N-type doped polysilicon column; Step 11, remove the oxide layer at the bottom of the groove, and then form a heavily doped P+ type Ge layer or a P+ type Si layer on the back side of the wafer formed in step 10 by evaporation or sputtering, and form a low breakdown voltage TVS diode D2 between the heavily doped P+ type Ge layer or the P+ type Si layer and the polysilicon column.

2. The method for manufacturing a low capacitance TVS structure according to claim 1, wherein: In step 10, the back side of the wafer is ground and dry-etched to expose the N-type doped polysilicon column. The specific steps are: Step 10a, grinding the back side of the wafer, wherein the oxide layer at the bottom of the groove does not expose the back side of the wafer after grinding; Step 10b: etching the back side of the wafer formed in step 10a to expose the oxide layer at the bottom of the trench; continuing silicon etching with the oxide layer at the bottom of the trench as a shielding layer to expose the N-type doped polysilicon column.

3. The method for manufacturing a low capacitance TVS structure according to claim 1, wherein: In step 11, a heavily doped P+ type Ge layer or a P+ type Si layer is formed on the back side of the wafer formed in step 10 by evaporation or sputtering. Specifically, a heavily doped P+ type Ge layer or a P+ type Si layer is deposited on the back side of the wafer formed in step 10 by evaporation or sputtering.

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