A method for preparing GaP surface-treated ITO structure LED

Abstract

The present invention relates to the field of LED technology, and more specifically, to a method for preparing an ITO-structured LED with a GaP surface treatment. The method comprises the following specific steps: growing LED epitaxial material; etching a SiO2 mask and GaP; surface treatment of the GaP window layer; deposition of an ITO thin film; preparation of a P electrode; preparation of an N electrode; and cutting to obtain the desired chip. The method utilizes argon plasma bombardment to treat the thinned GaP material surface, effectively reducing the P-type doping concentration of the thin surface layer. The surface layer is then etched into a rough interface, increasing contact resistance at that location, improving the lateral current expansion capability, and enhancing light extraction efficiency.

Description

Technical Field

[0001] The invention relates to the technical field of LEDs, and in particular to a method for preparing an ITO structure LED with a GaP surface treated thereon. Background Art

[0002] Light-emitting diodes (LEDs) are recognized as a new generation of green light sources, boasting advantages such as high luminous efficacy, low energy consumption, long life, high reliability, high safety, and environmental friendliness. Currently, LEDs are widely used in high-efficiency solid-state lighting applications such as display screens, automotive lighting, backlights, traffic lights, and landscape lighting. LEDs fabricated from the quaternary AlGaInP material can emit light in wavelengths covering red, orange, yellow, and yellow-green. The industry generally uses ITO (indium tin oxide) thin films, with their high transmittance and excellent conductivity, as transparent electrode materials to enhance the brightness of AlGaInP-based LED chips.

[0003] In the typical LED chip growth process, a thin film of ITO is deposited on the GaP layer of the epitaxial wafer, followed by the vapor deposition of metal electrodes as conductive pads. However, since the metal electrodes completely block light, if too much current is concentrated directly below the electrodes, the light extraction efficiency of the entire LED will be very low, and the brightness will also be affected. The industry generally achieves the goal of improving light extraction efficiency by etching and thinning the GaP material below the metal electrodes, but the current spread and light brightness are still not ideal. Therefore, solving the current spread problem of ITO structure LED chips is very critical. Summary of the Invention

[0004] In response to the shortcomings of the existing technology, the present invention provides a method for preparing an ITO structure LED with a GaP surface treatment. The preparation method of the present invention uses argon plasma bombardment treatment on the GaP surface below the electrode, which can effectively reduce the P-type doping concentration of the thin layer on the GaP surface, thereby increasing the contact resistance below the electrode, helping to guide the lateral expansion of the current and improve the light extraction efficiency.

[0005] The first object of the present invention is to provide a method for preparing an ITO structure LED with a GaP surface treatment, comprising the following specific steps:

[0006] S1. Growth of LED epitaxial materials: On the GaAs substrate, a GaAs buffer layer, an N-type confinement layer, an N-face space layer, a multi-quantum well active layer, a P-face space layer, a P-type confinement layer, a P-type transition layer, and a GaP window layer are grown in sequence.

[0007] S2, SiO2 mask and GaP etching: depositing SiO2 as a mask on the GaP surface of the GaP window layer, then patterning it through photolithography, and etching the SiO2 and GaP at the corresponding position directly below the preset P electrode with an etching solution;

[0008] S3. Surface treatment of the GaP window layer: Place the wafer in an ICP (inductively coupled plasma) etcher, bombard the GaP material at the corresponding position directly below the preset P electrode with argon plasma, rinse with deionized water, and then soak in an etching solution to remove the surface SiO2;

[0009] S4, ITO thin film deposition: using PECVD (plasma enhanced chemical vapor deposition) technology, deposit an ITO thin film on the surface of the GaP window layer treated in S3;

[0010] S5. Preparation of P electrode: Use photolithography patterning technology to coat negative photoresist on the surface of ITO film, bake, expose and develop, then place the wafer into electron beam evaporation equipment to evaporate P electrode;

[0011] S6. Preparation of N electrode: After thinning the GaAs substrate using grinding and polishing techniques, the wafer is placed in an electron beam evaporation device to evaporate the N electrode;

[0012] S7. Cutting: Use a grinding wheel or laser to cut and separate the prepared wafer along four sides to obtain the required chips.

[0013] Argon plasma bombardment, a purely physical etching surface treatment method, can knock out phosphorus from the thin layer on the GaP surface, creating a large number of Group V vacancies. These serve as donor impurities for Group III and V semiconductors, achieving surface modification. After thinning the GaP window layer, the present invention utilizes ICP equipment to bombard the thinned GaP material surface with argon plasma, depositing an ITO transparent conductive film, and then evaporating a P electrode. This effectively reduces the P-type doping concentration of the thin surface layer, thereby increasing the contact resistance beneath the electrode. This prevents current from concentrating beneath the light-shielding metal electrode, helping to guide the current's lateral expansion and improving light extraction efficiency.

[0014] Furthermore, in the above technical solution S3, the working pressure of the ICP is 0.5Pa~1Pa, the upper electrode power is 280W~320W, the lower electrode power is 100W~120W, the argon flow rate is 100sccm~1000sccm, and the etching time is 8min~10min.

[0015] Furthermore, in the above technical solution S3, the thickness of the GaP window layer after surface treatment is reduced to 100 nm to 200 nm.

[0016] Furthermore, in the above technical solution S2, the etching solution is a mixture of iodic acid, hydrochloric acid and deionized water in a volume ratio of 1:3:100.

[0017] Furthermore, in the above technical solution S4, the thickness of the deposited ITO film is 200nm to 300nm.

[0018] Furthermore, in the above technical solution, the material of the P electrode is one or more combinations of Au, Zn, Pt, Al, and Ti.

[0019] Furthermore, in the above technical solution, the materials of the N-type confinement layer and the P-type confinement layer are both AlInP; the materials of the N-face space layer, the P-face space layer and the P-type transition layer are all AlGaInP.

[0020] The second object of the present invention is to provide an ITO structure LED chip manufactured by the above-mentioned preparation method.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] 1. After thinning the GaP window layer, the present invention utilizes ICP technology and uses argon plasma bombardment to treat the surface of the thinned GaP material, thereby bombarding phosphorus elements from the surface of the GaP window layer, generating a large number of Group V element vacancies. This not only reduces the P-type doping concentration of the surface thin layer, but also etches the surface layer into a rough interface, thereby increasing the contact resistance at this position, thereby improving the lateral expansion capability of the current and the light extraction efficiency.

[0023] 2. The preparation method of the present invention is basically consistent with the existing process, without adding any additional complicated process. It can improve the light extraction efficiency of LED chips on the basis of existing technology, has high repeatability, and is of great significance for mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Schematic diagram of the epitaxial material structure of an ITO structure LED chip;

[0025] Figure 2 This is a schematic diagram of the typical ITO structure LED chip structure in the industry;

[0026] Figure 3 This is a schematic diagram of the structure of the ITO structure LED chip with GaP surface treatment according to the present invention;

[0027] Figure 4 The following are test charts of wavelength and brightness of typical ITO structure LED chips in the industry, where a is the brightness test chart and b is the wavelength test chart;

[0028] Figure 5 This is a test chart of the wavelength and brightness of the ITO structure LED chip prepared by the present invention, wherein a is the brightness test chart and b is the wavelength test chart.

[0029] Description of the numbers in the schematic diagram:

[0030] 1. GaAs substrate; 2. GaAs buffer layer; 3. N-type confinement layer; 4. N-side space layer; 5. Multi-quantum well active layer; 6. P-side space layer; 7. P-type confinement layer; 8. P-type transition layer; 9. GaP window layer; 10. ITO thin film; 11. P-type electrode; 12. N-type electrode. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is in no way intended to limit the present application and its application or use. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0032] In the description of this application, it should be understood that the use of words such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Unless otherwise stated, the above words have no special meaning and therefore cannot be understood as limiting the scope of protection of this application.

[0033] In the description of this application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "horizontal, vertical, vertical, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of this application; the directional words "inside and outside" refer to the inside and outside relative to the outline of each component itself.

[0034] See also Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the shape, quantity and proportion of each component can be changed at will, and the component layout may also be more complicated.

[0035] At present, the typical preparation method of ITO structure LED chip in the industry mainly includes the following steps:

[0036] 1. Preparation of epitaxial material structure

[0037] Schematic diagram of epitaxial material structure of ITO structure LED chip Figure 1 As shown, using the technology and equipment of metal organic chemical vapor deposition (MOCVD), an ITO structure LED chip epitaxial material is grown on a GaAs substrate 1, which includes, from bottom to top, a GaAs buffer layer 2, an N-type confinement layer 3, an N-face space layer 4, a multi-quantum well active layer 5, a P-face space layer 6, a P-type confinement layer 7, a P-type transition layer 8, and a GaP window layer 9.

[0038] 2. ITO structure LED chip preparation process:

[0039] (1) Cleaning the surface of the epitaxial structure using an organic cleaning agent;

[0040] (2) depositing SiO2 as a mask on the GaP surface of the GaP window layer 9, and then etching the SiO2 and GaP materials at the corresponding position directly below the preset P electrode through photolithography patterning;

[0041] (3) removing the SiO2 mask by solution etching, and then depositing an ITO film 10 transparent conductive film on the surface of the wafer;

[0042] (4) Through photolithography patterning, a negative photoresist for electrode stripping is first coated on the wafer surface, and then the P electrode 11 is evaporated;

[0043] (5) Using metal stripping technology, remove the metal electrode above the photoresist, then remove the photoresist and clean it with deionized water;

[0044] (6) Grinding, thinning, and polishing the substrate on the back of the wafer, and then evaporating the N electrode 12 on the substrate surface;

[0045] (7) Using laser or grinding wheel to cut and separate the chip along the four sides of the chip, the schematic diagram of the prepared ITO structure LED chip structure is as follows Figure 2 shown.

[0046] However, the typical ITO structure LED chip in the industry, although the etching and thinning of the GaP window layer material under the P electrode can play a certain positive role in current expansion, still has obvious disadvantages: even if the GaP window layer material is thinned, the doping concentration of the GaP window layer under the P electrode is still high, generally reaching 1×10 18 cm -3 ~5×10 18 cm -3 , there will still be a lot of current gathered under the electrode to emit light, affecting the current expansion and light extraction efficiency.

[0047] To further solve the problems existing in the prior art, the present invention uses a corrosive solution to thin the GaP window layer, then uses ICP equipment to bombard the thinned GaP material surface with argon plasma, then deposits an ITO transparent conductive film, and finally evaporates the P electrode. Without adding any additional cumbersome process, the light extraction efficiency of the LED chip can be improved on the basis of the existing technology, with high repeatability and application in mass production.

[0048] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0049] The embodiment of the present invention provides a method for preparing an ITO structure LED with a GaP surface treatment, comprising the following specific steps:

[0050] S1. Growth of ITO structure LED epitaxial material: The schematic diagram of its epitaxial material structure is as follows Figure 1 As shown, from bottom to top, it includes: GaAs substrate 1, GaAs buffer layer 2, N-type confinement layer 3, N-face space layer 4, multi-quantum well active layer 5, P-face space layer 6, P-type confinement layer 7, P-type transition layer 8, and GaP window layer 9;

[0051] Specifically, MOCVD technology is used for preparation. The metal organic source materials used include trimethylgallium, trimethylaluminum, trimethylindium, bismuth magnesium, and carbon tetrachloride. The Group V element source materials used include arsine, phosphine, and silane. The above source materials are carried into the reaction chamber by a carrier gas. In a low-pressure environment with a growth temperature of 600°C to 800°C, the above epitaxial materials are grown layer by layer. The specific composition and doping concentration of each individual epitaxial layer are regulated by the corresponding flow rate and growth temperature.

[0052] S2, SiO2 mask and GaP etching: SiO2 is deposited as a mask on the GaP surface of the GaP window layer, and then patterned by photolithography to etch the SiO2 and GaP at positions corresponding to the positions directly below the preset P electrode;

[0053] Specifically, the surface of the epitaxial structure is cleaned using an organic cleaning solution;

[0054] Using PECVD technology to deposit SiO2 thin film on the surface of GaP window layer, followed by photolithography patterning, coating with positive photoresist, exposure and development;

[0055] Prepare GaP etching solution with iodic acid: hydrochloric acid: deionized water = 1:3:100. Soak the wafer in the etching solution for 5-6 minutes, then rinse with deionized water for 10 minutes and spin dry.

[0056] Use a stripping solution to remove the residual photoresist on the surface of the SiO2 mask.

[0057] S3. Surface treatment of the GaP window layer: Place the wafer in an ICP etcher and perform argon plasma bombardment on the GaP material at the corresponding position directly below the preset P electrode. Rinse with deionized water and then soak in a corrosion solution to remove the surface SiO2.

[0058] Specifically, the wafer is placed in an ICP etcher with the following working conditions: working pressure of 0.5 Pa to 1 Pa, upper electrode power of 280 W to 320 W, lower electrode power of 100 W to 120 W, argon flow rate of 100 sccm to 1000 sccm, and etching time of 8 min to 10 min;

[0059] After surface treatment, rinse with deionized water for 10 minutes, then use a corrosion solution of hydrofluoric acid: deionized water = 1:10 to soak and clean the surface to remove SiO2 for 10 minutes, then rinse with deionized water for 10 minutes and dry it with a dryer.

[0060] S4, ITO thin film deposition: Using PECVD technology, deposit ITO thin film on the surface of the GaP window layer processed in S3;

[0061] Specifically, the thickness of the deposited ITO film is 200nm to 300nm;

[0062] S5. Preparation of P electrode: Use photolithography patterning technology to coat negative photoresist on the surface of ITO film, bake, expose and develop, then place the wafer into electron beam evaporation equipment to evaporate P electrode;

[0063] Specifically, a negative photoresist is coated on the surface of the ITO film using a photolithography patterning technique, and then baked, exposed, and developed;

[0064] Place the wafer into the electron beam evaporation equipment and set the chamber vacuum to 1×10 -4 Pa, bake at 120℃ for 20min, then cool to 80℃ to evaporate P electrode metal. The evaporated P electrode material is one or more combination structures of Au, Zn, Pt, Al, and Ti;

[0065] Use a metal stripping machine to remove the metal other than the P electrode;

[0066] Soak the wafer in a degumming solution to remove residual photoresist, then rinse with deionized water for 10 minutes and spin dry in a spin dryer;

[0067] S6. Preparation of N electrode: After thinning the GaAs substrate using grinding and polishing techniques, the wafer is placed in an electron beam evaporation device to evaporate the N electrode;

[0068] Specifically, the GaAs substrate is thinned using grinding and polishing techniques;

[0069] Place the wafer into the electron beam evaporation equipment and set the chamber vacuum to 1×10 -4 Pa, baked at 120℃ for 20min, and maintained at 120℃ to evaporate the N electrode metal. The evaporated N electrode material is a Ni / Au / Ge / Au stacked metal combination.

[0070] S7, cutting: cutting and separating the prepared wafer along the four sides by using a grinding wheel or laser to obtain the ITO structure LED chip with GaP surface treatment of the present invention, the structural diagram of which is shown in FIG. Figure 3 shown.

[0071] Based on all the above embodiments of the present invention, another embodiment of the present invention further provides an ITO structure LED chip, such as Figure 3 As shown, the ITO structure LED chip includes, from bottom to top, an N electrode 12, a GaAs substrate 1, a GaAs buffer layer 2, an N-type confinement layer 3, an N-face space layer 4, a multi-quantum well active layer 5, a P-face space layer 6, a P-type confinement layer 7, a P-type transition layer 8, a GaP window layer 9, an ITO film 10, and a P electrode 11;

[0072] The GaP surface of the GaP window layer at the corresponding position directly below the P electrode is firstly subjected to argon plasma bombardment treatment, and then an ITO film is deposited, and then the P electrode is prepared by evaporation.

[0073] Specifically, the GaP surface treatment uses an inductively coupled plasma (ICP) etcher. The etching gas is argon, which is ionized into an argon plasma in the ICP equipment and physically etches the GaP surface. This solution can create Group V element vacancies in the GaP surface layer and simultaneously etch the surface into a rough interface, increasing the contact resistance at that location and improving the lateral expansion capability of the current.

[0074] The typical ITO structure LED chip in the industry and the ITO structure LED chip with GaP surface treatment prepared by the present invention were placed in the LED wafer spot tester for wavelength and brightness testing. The results are as follows: Figure 4 and Figure 5 The chip size is 106μm×106μm, the test current is 20mA, and the test equipment is an LED chip spot tester.

[0075] from Figure 4 The test results show that the typical ITO structure LED chip in the industry has a wavelength of 621-622nm and a brightness of 135-145mcd. Figure 5Test results show that the ITO-structured LED chip produced using the present invention emits light at a wavelength of 621-622 nm, with a brightness primarily distributed between 165 and 175 mcd. Comparing the data reveals that the LED chip of the present invention is approximately 20% brighter than a typical TIO-structured LED chip.

[0076] Finally, it should be emphasized that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing an ITO structure LED with GaP surface treatment, characterized in that: The specific steps include: S1. Growth of LED epitaxial materials: On the GaAs substrate, a GaAs buffer layer, an N-type confinement layer, an N-face space layer, a multi-quantum well active layer, a P-face space layer, a P-type confinement layer, a P-type transition layer, and a GaP window layer are grown in sequence. S2, SiO2 mask and GaP etching: depositing SiO2 as a mask on the GaP surface of the GaP window layer, then patterning it through photolithography, and etching the SiO2 and GaP at the corresponding position directly below the preset P electrode with an etching solution; S3. Surface treatment of the GaP window layer: Place the wafer into an ICP etcher, and perform argon plasma bombardment on the GaP material at the corresponding position directly below the preset P electrode to bombard out the phosphorus element in the thin layer on the surface of the GaP, generate a large number of Group V element vacancies, and reduce the P-type doping concentration. After that, rinse with deionized water and then soak with a corrosion solution to remove the surface SiO2; the working pressure of the ICP is 0.5Pa~1Pa, the upper electrode power is 280W~320W, the lower electrode power is 100W~120W, the argon flow rate is 100sccm~1000sccm, and the etching time is 8min~10min; rinse with deionized water for 10min, and then use a corrosion solution with a volume ratio of hydrofluoric acid:deionized water of 1:10 to soak and clean the surface to remove SiO2 for 10min, then rinse with deionized water for 10min, and dry with a spin dryer; S4, ITO thin film deposition: Using PECVD technology, deposit ITO thin film on the surface of the GaP window layer processed in S3; S5. Preparation of P electrode: Use photolithography patterning technology to coat negative photoresist on the surface of ITO film, bake, expose and develop, then place the wafer into electron beam evaporation equipment to evaporate P electrode; S6. Preparation of N electrode: After thinning the GaAs substrate using grinding and polishing techniques, the wafer is placed in an electron beam evaporation device to evaporate the N electrode; S7. Cutting: Use a grinding wheel or laser to cut and separate the prepared wafer along four sides to obtain the required chips.

2. The method for preparing a GaP surface treated ITO structure LED according to claim 1, characterized in that: In S3, the GaP window layer is thinned to a thickness of 100 nm to 200 nm after surface treatment.

3. The method for preparing a GaP surface-treated ITO structure LED according to claim 1, characterized in that: In S2, the etching solution is a mixture of iodic acid, hydrochloric acid and deionized water in a volume ratio of 1:3:

100.

4. The method for preparing a GaP surface treated ITO structure LED according to claim 1, characterized in that: In S4, the thickness of the deposited ITO film is 200 nm to 300 nm.

5. The method for preparing a GaP surface treated ITO structure LED according to claim 1, characterized in that: The material of the P electrode is one or more combinations of Au, Zn, Pt, Al, and Ti.

6. The method for preparing a GaP surface treated ITO structure LED according to claim 1, characterized in that: The material of the N electrode is a Ni / Au / Ge / Au stacked metal combination.

7. The method for preparing a GaP surface treated ITO structure LED according to claim 1, characterized in that: The materials of the N-type confinement layer and the P-type confinement layer are both AlInP; the materials of the N-face space layer, the P-face space layer and the P-type transition layer are all AlGaInP.

8. An ITO structure LED chip prepared by the preparation method according to any one of claims 1 to 7.

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