Trigger and reset circuit and method for composite signal priority readout

Abstract

The present invention discloses a trigger and reset circuit and method for composite signal priority reading, belonging to the technical field of sensor chips. The present invention sets an amplification module, a comparison module, a detection module and a priority reading module in the trigger and reset circuit for composite signal priority reading, wherein the amplification module is used to receive an input current signal and amplify the current signal to obtain an amplified current signal; the comparison module is used to receive the amplified current signal and compare the amplified current signal to output a pulse signal; the detection module is used to perform time measurement and energy measurement according to the pulse signal and generate a trigger signal according to the pulse signal; the priority reading module is used to receive the trigger signal and read the address information according to the trigger signal, and read the time information and energy information according to the trigger signal, so that the address information, time information and energy information can be read out at the same time, and multiple information can be read quickly.

Description

Technical Field

[0001] The present invention relates to the technical field of sensor chips, and in particular to a trigger and reset circuit and method for composite signal priority readout. Background Art

[0002] Priority readout is widely used in the readout of pixel chip hit information of the vertex detector of high-energy physics experiments. It uses an event-driven priority readout method to improve the readout speed of the pixel chip and reduce the dead time of the pixel chip. Usually, the pixel detector chip using event-driven priority readout realizes digitization in the pixel, and the high level output represents that the pixel is a hit pixel. The priority readout circuit is triggered by edge detection to read the hit information of the pixel, and the priority readout circuit sends a reset signal to reset the logic circuit in the pixel to facilitate the reception of the next hit signal.

[0003] The trigger signal of the traditional priority readout is the leading edge of the comparator output signal, which can only read address information and a single type of information. Summary of the invention

[0004] The main purpose of the present invention is to provide a trigger and reset circuit and method for composite signal priority reading, aiming to solve the technical problem that the prior art priority reading can only read address information and read single information.

[0005] To achieve the above object, the present invention provides a trigger and reset circuit for composite signal priority reading, the trigger and reset circuit for composite signal priority reading comprising: an amplification module, a comparison module, a detection module and a priority reading module connected in sequence;

[0006] The amplification module is used to receive an input current signal and amplify the current signal to obtain an amplified current signal;

[0007] The comparison module is used to receive the amplified current signal, compare the amplified current signal, and output a pulse signal;

[0008] The detection module is used to perform time measurement and energy measurement according to the pulse signal, and generate a trigger signal according to the pulse signal;

[0009] The priority reading module is used to receive the trigger signal, read the address information according to the trigger signal, and read the time information and energy information according to the trigger signal.

[0010] Optionally, the detection module includes: a trailing edge detection circuit, a leading edge detection circuit and a time-amplitude conversion circuit; the input ends of the trailing edge detection circuit, the leading edge detection circuit and the time-amplitude conversion circuit are respectively connected to the output end of the comparison module, and the output ends of the trailing edge detection circuit, the leading edge detection circuit and the time-amplitude conversion circuit are respectively connected to the priority reading module;

[0011] The trailing edge detection circuit is used to receive the pulse signal and generate a trigger signal to the priority reading module according to the pulse signal;

[0012] The leading edge detection circuit is used to receive the pulse signal and perform time measurement according to the pulse signal;

[0013] The time-amplitude conversion circuit is used to receive the pulse signal and perform energy measurement according to the pulse signal.

[0014] Optionally, the trigger and reset circuit for composite signal priority readout further includes: a reset fan-out and pulse width extension module, the input end of the reset fan-out and pulse width extension module is connected to the priority reading module, and the output end of the reset fan-out and pulse width extension module is connected to the time amplitude conversion circuit;

[0015] The priority reading module is further used to generate an initial reset signal after reading the address information, the time information and the energy information;

[0016] The reset fan-out and pulse width extension module is used to generate a first reset signal, a second reset signal and a third reset signal according to the initial reset signal, and perform period extension through the first reset signal, the second reset signal and the third reset signal;

[0017] The reset fan-out and pulse width expansion module is also used to send the first reset signal to the time amplitude conversion circuit, and send the second reset signal and the third reset signal to the trailing edge detection circuit, so as to reset the time amplitude conversion circuit and the trailing edge detection circuit.

[0018] Optionally, the trailing edge detection circuit comprises: a first trigger, a second trigger and a latch connected in sequence;

[0019] The first trigger is triggered by a falling edge, and the second trigger is triggered by a rising edge;

[0020] The data input terminal of the first trigger is connected to the power supply voltage, the clock input terminal of the first trigger is connected to the output terminal of the comparison module, and the output terminal of the first trigger is connected to the data input terminal of the second trigger;

[0021] The clock input terminal of the second trigger is connected to the system clock output terminal, the output terminal of the second trigger is connected to the input terminal of the latch, and the reset port of the first trigger and the reset port of the second trigger are respectively connected to the output terminal of the reset fan-out and pulse width expansion module;

[0022] The output end of the latch is connected to the input end of the priority reading module.

[0023] Optionally, the latch includes: a first transmission gate, a second transmission gate, a first inverter, a second inverter and a third inverter;

[0024] The input end of the first transmission gate is connected to the output end of the second trigger, the control end of the first transmission gate is connected to the control signal input end, and the output end of the first transmission gate is respectively connected to the input end of the second transmission gate and the input end of the first inverter;

[0025] The output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter and the output end of the second transmission gate are respectively connected to the input end of the priority reading module;

[0026] The input end of the third inverter is connected to the control signal input end, and the output end of the third inverter is connected to the control end of the second transmission gate.

[0027] Optionally, the first transmission gate includes: a first MOS transistor and a second MOS transistor, the second transmission gate includes: a third MOS transistor and a fourth MOS transistor, and the control signal input terminal is used to access a third reset signal;

[0028] The gate of the first MOS tube is connected to the control signal input terminal, the drain of the first MOS tube and the drain of the second MOS tube are respectively connected to the output terminal of the second trigger, the source of the first MOS tube and the source of the second MOS tube are respectively connected to the input terminal of the first inverter and the drain of the third MOS tube and the drain of the fourth MOS tube, and the gate of the second MOS tube is connected to the output terminal of the third inverter;

[0029] The input end of the third inverter is connected to the control signal input end, the gate of the third MOS tube is connected to the output end of the third inverter, the source of the third MOS tube, the source of the fourth MOS tube and the output end of the second inverter are respectively connected to the input end of the priority reading module, and the gate of the fourth MOS tube is connected to the control signal input end.

[0030] Optionally, the reset fan-out and pulse width expansion module comprises: a reset fan-out circuit and a reset pulse width expansion circuit, the input end of the reset fan-out circuit and the input end of the reset pulse width expansion circuit are respectively connected to the output end of the priority reading module, and the output end of the reset fan-out circuit is respectively connected to the input end of the time amplitude conversion circuit and the input end of the trailing edge detection circuit;

[0031] The reset fan-out circuit is used to receive the initial reset signal transmitted by the priority reading module, and generate a first reset signal, a second reset signal and a third reset signal according to the initial reset signal, and send the first reset signal to the time amplitude conversion circuit, and send the second reset signal and the third reset signal to the trailing edge detection circuit, so that the time amplitude conversion circuit and the trailing edge detection circuit perform circuit reset;

[0032] The reset pulse width extension circuit is used to generate a target reset signal according to the initial reset signal, so as to perform clock cycle extension on the pulse width of the initial reset signal.

[0033] Optionally, the reset fan-out circuit includes: a third trigger, a fourth inverter, a first NOR gate, a first OR gate and a second OR gate;

[0034] The data input terminal of the third trigger is connected to the power supply voltage, the initial reset terminal of the third trigger is connected to the output terminal of the priority reading module, the output terminal of the third trigger is connected to the input terminal of the first NOR gate, and the output terminal of the first NOR gate is connected to the input terminal of the trailing edge detection circuit;

[0035] The input end of the fourth inverter is connected to the global reset signal input end, and the output end of the fourth inverter is respectively connected to the input end of the first NOR gate, the input end of the first OR gate, and the input end of the second OR gate;

[0036] The input end of the first OR gate is also connected to the output end of the priority reading module, the output end of the first OR gate is connected to the input end of the trailing edge detection circuit, and the output end of the second OR gate is connected to the input end of the time amplitude conversion circuit.

[0037] Optionally, the reset pulse width extension circuit includes: a fourth trigger, a fifth trigger, a sixth trigger, a fifth inverter and a first AND gate;

[0038] The data input terminal of the fourth trigger is connected to the power supply voltage, the initial reset terminal of the fourth trigger is connected to the output terminal of the priority reading module, and the output terminal of the fourth trigger is respectively connected to the input terminal of the second OR gate and the data input terminal of the fifth trigger;

[0039] The clock input terminal of the fifth flip-flop is connected to the system clock output terminal, the output terminal of the fifth flip-flop is connected to the data input terminal of the sixth flip-flop, the clock input terminal of the sixth flip-flop is connected to the system clock output terminal, the target reset terminal of the sixth flip-flop is connected to the global reset signal input terminal, and the output terminal of the sixth flip-flop is connected to the input terminal of the fifth inverter;

[0040] The output end of the fifth inverter is connected to the input end of the first AND gate, the input end of the first AND gate is also connected to the global reset signal input end, and the output end of the first AND gate is respectively connected to the target reset end of the third trigger, the target reset end of the fourth trigger, and the target reset end of the fifth trigger.

[0041] In addition, to achieve the above-mentioned purpose, the present invention further proposes a pixel detector, which includes the trigger and reset circuit for composite signal priority readout as described above.

[0042] In addition, to achieve the above-mentioned purpose, the present invention also provides a triggering and resetting method for composite signal priority reading, the triggering and resetting method for composite signal priority reading is applied to the triggering and resetting circuit for composite signal priority reading described above, the circuit comprises: an amplification module, a comparison module, a detection module and a priority reading module connected in sequence, the method comprises the following steps:

[0043] The amplifying module receives an input current signal and amplifies the current signal to obtain an amplified current signal;

[0044] The comparison module receives the amplified current signal, compares the amplified current signal, and outputs a pulse signal;

[0045] The detection module performs time measurement and energy measurement according to the pulse signal to obtain time information and energy information, and generates a trigger signal according to the pulse signal;

[0046] The priority reading module receives the trigger signal, reads the address information according to the trigger signal, and reads the time information and the energy information according to the trigger signal.

[0047] The present invention sets an amplification module, a comparison module, a detection module and a priority reading module in a trigger and reset circuit for composite signal priority reading. The amplification module is used to receive an input current signal and amplify the current signal to obtain an amplified current signal; the comparison module is used to receive the amplified current signal, compare the amplified current signal and output a pulse signal; the detection module is used to perform time measurement and energy measurement according to the pulse signal and generate a trigger signal according to the pulse signal; the priority reading module is used to receive the trigger signal and read the address information according to the trigger signal, and read the time information and energy information according to the trigger signal. The address information, time information and energy information can be read simultaneously, and a variety of information can be read quickly. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a block diagram of the traditional priority readout and its trigger and reset structure;

[0049] Figure 2 A schematic diagram of the structure of a first embodiment of a trigger and reset circuit for composite signal priority reading according to the present invention;

[0050] Figure 3 A schematic diagram of the structure of a second embodiment of a trigger and reset circuit for composite signal priority reading according to the present invention;

[0051] Figure 4 A schematic diagram of the structure of a third embodiment of a trigger and reset circuit for composite signal priority reading according to the present invention;

[0052] Figure 5 A schematic diagram of the structure of a fourth embodiment of a trigger and reset circuit for composite signal priority readout according to the present invention;

[0053] Figure 6 A timing diagram of a trailing edge detection circuit in an embodiment of a trigger and reset circuit for composite signal priority readout of the present invention;

[0054] Figure 7 A schematic diagram of the structure of a fifth embodiment of a trigger and reset circuit for composite signal priority readout according to the present invention;

[0055] Figure 8 It is a timing diagram of reset fan-out and pulse width expansion module in one embodiment of the trigger and reset circuit for composite signal priority readout of the present invention;

[0056] Fig. 9 FIG. 1 is a flow chart of a first embodiment of a trigger and reset method for composite signal priority reading according to the present invention.

[0057] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings.

[0058] Description of Figure Numbers:

[0059] DETAILED DESCRIPTION

[0060] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0061] The traditional priority readout and its trigger and reset structure diagram is as follows Figure 1 As shown, the charge-sensitive preamplifier amplifies the detector response current and then enters the comparator. The comparator outputs a pulse signal that generates a STATE trigger signal through the leading edge detection circuit. If the pixel priority is the highest among the hit pixels, the priority readout generates a SYNC signal, which generates a RST reset signal after reset decoding. The leading edge detection module is reset at the falling edge of the RST reset signal, and the address bus is latched at the falling edge of the SYNC signal, that is, the pixel position information. The traditional priority readout trigger signal is the leading edge of the comparator output signal, which can only read address information, and the type of information read is single.

[0062] Reference Figure 2 , Figure 2 Schematic diagram of the structure of the first embodiment of the trigger and reset circuit for composite signal priority readout of the present invention.

[0063] In this embodiment, the trigger and reset circuit for composite signal priority reading includes: an amplification module 1, a comparison module 2, a detection module 3 and a priority reading module 4 connected in sequence; the amplification module 1 is used to receive an input current signal and amplify the current signal to obtain an amplified current signal.

[0064] It should be noted that the input end of the amplification module 1 is connected to the pixel detector, receives the current signal input by the pixel detector, and amplifies the input current signal to obtain an amplified current signal. The amplification module 1 includes a charge-sensitive preamplifier, which amplifies the current input by the detector. The output end of the amplification module 1 is connected to the input end of the comparison module 2, and the amplification module 1 transmits the amplified current signal to the comparison module 2.

[0065] In this embodiment, the comparison module 2 is used to receive the amplified current signal, compare the amplified current signal, and output a pulse signal.

[0066] It should be understood that the comparison module 2 includes a comparator, which may be a voltage comparator or other comparator capable of comparing the amplified current signal, and this embodiment does not limit this. The positive input terminal of the comparison module 2 is connected to the output terminal of the amplification module 1 to receive the amplified current signal, and the reverse input terminal of the comparison module 2 is connected to the power supply voltage. The comparison module 2 compares the amplified current signal and outputs a pulse signal, and the pulse signal refers to the COMPOUT pulse signal.

[0067] The detection module 3 is used to perform time measurement and energy measurement according to the pulse signal, and generate a trigger signal according to the pulse signal; the priority reading module 4 is used to receive the trigger signal, read the address information according to the trigger signal, and read the time information and energy information according to the trigger signal.

[0068] It should be noted that the detection module 3 is used to receive the pulse signal output by the comparison module 2, and to generate a trigger signal according to the pulse signal and to perform time measurement and energy measurement according to the pulse signal. The detection module 3 includes leading edge detection, trailing edge detection and time amplitude conversion, etc., which are not limited in this embodiment. The trailing edge detection in the detection module 3 transmits the trigger signal to the priority reading module 4. After receiving the trigger signal, the priority reading module 4 reads the time information and energy information in the detection module 3. After receiving the trigger signal, the priority module 4 generates a SYNC (synchronization) signal, and generates a RST (RESET) signal after reset decoding. The detection module 3 is reset at the falling edge of the RST reset signal, and the address bus is latched at the falling edge of the SYNC signal to read the address information of the pixel. The address information, time information and energy information can be read according to the pulse signal at the same time.

[0069] This embodiment sets an amplification module, a comparison module, a detection module and a priority reading module in a trigger and reset circuit for composite signal priority reading. The amplification module is used to receive an input current signal and amplify the current signal to obtain an amplified current signal; the comparison module is used to receive the amplified current signal, compare the amplified current signal and output a pulse signal; the detection module is used to perform time measurement and energy measurement according to the pulse signal and generate a trigger signal according to the pulse signal; the priority reading module is used to receive the trigger signal and read the address information according to the trigger signal, and read the time information and energy information according to the trigger signal. The address information, time information and energy information can be read simultaneously, and multiple information can be read quickly.

[0070] Reference Figure 3 , Figure 3 Schematic diagram of the structure of the second embodiment of the trigger and reset circuit for composite signal priority reading of the present invention.

[0071] Based on the above-mentioned first embodiment, in this embodiment, the detection module 3 includes: a trailing edge detection circuit 30, a leading edge detection circuit 31 and a time-amplitude conversion circuit 32; the input ends of the trailing edge detection circuit 30, the leading edge detection circuit 31 and the time-amplitude conversion circuit 32 are respectively connected to the output end of the comparison module 2, and the output ends of the trailing edge detection circuit 30, the leading edge detection circuit 31 and the time-amplitude conversion circuit 32 are respectively connected to the priority reading module 4.

[0072] It should be noted that the input end of the trailing edge detection circuit 30, the input end of the leading edge detection circuit 31, and the input end of the time amplitude conversion circuit 32 are respectively connected to the comparator in the comparison module 2 to receive the pulse signal output by the comparator. The output end of the trailing edge detection circuit 30 and the time amplitude conversion circuit are respectively connected to the priority reading module 4. The detection module 3 also includes a time measurement circuit 33. The output end of the leading edge detection circuit 31 is connected to the time measurement circuit 33. The leading edge detection circuit 31 is used to receive the pulse signal and perform time measurement according to the pulse signal. The leading edge detection circuit 31 receives the pulse signal output by the comparator in the comparison module 2. The pulse signal starts the time measurement through the leading edge detection circuit 31 and generates a measurement signal to the time measurement circuit 33. The time measurement circuit 33 and the leading edge detection circuit 31 are also respectively connected to the system clock to receive the CLK (clock) clock signal output by the system clock, and the time is measured through the time measurement circuit 33.

[0073] In this embodiment, the trailing edge detection circuit 30 is used to receive the pulse signal and generate a trigger signal to the priority reading module 4 based on the pulse signal, and the time amplitude conversion circuit 32 is used to receive the pulse signal and perform energy measurement based on the pulse signal.

[0074] It should be noted that the input end of the time-amplitude conversion circuit 32 is connected to the comparator in the comparison module 2, and the comparator outputs a pulse signal to the time-amplitude conversion circuit 32. The time-amplitude conversion circuit 32 receives the pulse signal, and the pulse signal width is measured by the time-amplitude conversion circuit 32 to realize energy measurement. The trailing edge detection circuit 30 transmits the trigger signal to the priority reading module 4. When the priority reading module 4 receives the trigger signal, it triggers the reading of time information, energy information and address information.

[0075] In this embodiment, a trailing edge detection circuit, a leading edge detection circuit and a time-amplitude conversion circuit are arranged in the detection module; the input ends of the trailing edge detection circuit, the leading edge detection circuit and the time-amplitude conversion circuit are respectively connected to the output end of the comparison module, and the output ends of the trailing edge detection circuit, the leading edge detection circuit and the time-amplitude conversion circuit are respectively connected to the priority reading module; the trailing edge detection circuit is used to receive the pulse signal and generate a trigger signal to the priority reading module according to the pulse signal; the leading edge detection circuit is used to receive the pulse signal and perform time measurement according to the pulse signal; the time-amplitude conversion circuit is used to receive the pulse signal and perform energy measurement according to the pulse signal. Because the trailing edge detection circuit, the leading edge detection circuit and the time-amplitude conversion circuit are arranged in the detection module, the technical problem that the existing priority readout can only read address information is overcome, and the time information, energy information and address information can be detected by the trailing edge detection circuit, the leading edge detection circuit and the time-amplitude conversion circuit. The priority reading module can read the time information, energy information and address information at the same time, and can quickly read multiple information.

[0076] Reference Figure 4 , Figure 4 Schematic diagram of the structure of the third embodiment of the trigger and reset circuit for composite signal priority reading of the present invention.

[0077] Based on the above-mentioned first and second embodiments, in this embodiment, the trigger and reset circuit for composite signal priority reading also includes: a reset fan-out and pulse width expansion module 5, the input end of the reset fan-out and pulse width expansion module 5 is connected to the priority reading module 4, and the output end of the reset fan-out and pulse width expansion module 5 is connected to the time amplitude conversion circuit 32; the priority reading module 4 is also used to generate an initial reset signal after reading the address information, the time information and the energy information.

[0078] The trigger signal of the traditional priority readout is the leading edge of the comparator output signal. The readout reset signal can only reset the digital circuit and only lasts for half a clock cycle, and cannot reset the analog circuit.

[0079] It should be noted that the input end of the reset fan-out and pulse width expansion module 5 is connected to the priority reading module 4, and the input end of the reset fan-out and pulse width expansion module 5 is also connected to the system clock to receive the CLK signal of the system clock. The output end of the reset fan-out and pulse width expansion module 5 is connected to the time amplitude conversion circuit 32, and the output end of the reset fan-out and pulse width expansion module 5 is also respectively connected to the time measurement circuit 33, the leading edge detection circuit 31, and the trailing edge detection circuit 30.

[0080] In this embodiment, after reading the address information, the time information and the energy information, the priority reading module 4 generates an initial reset signal RST, and the initial reset signal RST includes a first reset signal, a second reset signal and a third reset signal.

[0081] In a specific implementation, the reset fan-out and pulse width expansion module 5 is used to generate a first reset signal, a second reset signal and a third reset signal according to the initial reset signal, and to perform period expansion through the first reset signal, the second reset signal and the third reset signal; the reset fan-out and pulse width expansion module 5 is also used to send the first reset signal to the time amplitude conversion circuit 32, and send the second reset signal and the third reset signal to the trailing edge detection circuit 30, so that the time amplitude conversion circuit 32 and the trailing edge detection circuit 30 perform circuit reset.

[0082] It should be noted that the reset fan-out and pulse width expansion module 5 is used to analyze the initial reset signal to obtain the first reset signal, the second reset signal and the third reset signal. The clock cycle is expanded by the first reset signal, the second reset signal and the third reset signal. The reset fan-out and pulse width expansion module 5 is also used to send the first reset signal to the time amplitude conversion circuit 32, and send the second reset signal and the third reset signal to the trailing edge detection circuit 30, so that the time amplitude conversion circuit 32 and the trailing edge detection circuit 30 perform analog circuit and digital circuit reset.

[0083] Furthermore, the reset fan-out and pulse width expansion module 5 includes: a reset fan-out circuit 50 and a reset pulse width expansion circuit 51, the input end of the reset fan-out circuit 50 and the input end of the reset pulse width expansion circuit 51 are respectively connected to the output end of the priority reading module 4, and the output end of the reset fan-out circuit 50 is respectively connected to the input end of the time amplitude conversion circuit 32 and the input end of the trailing edge detection circuit 30; the reset fan-out circuit 50 is used to receive the initial reset signal transmitted by the priority reading module 4, and generate a first reset signal, a second reset signal and a third reset signal according to the initial reset signal, and send the first reset signal to the time amplitude conversion circuit 32, and send the second reset signal and the third reset signal to the trailing edge detection circuit 30, so that the time amplitude conversion circuit 32 and the trailing edge detection circuit 30 perform circuit reset; the reset pulse width expansion circuit 51 is used to generate a target reset signal according to the initial reset signal to perform clock cycle expansion on the pulse width of the initial reset signal.

[0084] It should be noted that the target reset signal refers to the final reset signal, and the pulse width of the initial reset signal can be extended by the target reset signal for a clock cycle, and the output end of the reset pulse width extension circuit 51 is also connected to the input end of the reset fan-out circuit 50. The first reset signal, the second reset signal, and the third reset signal can be low-level signals or high-level signals, and the target reset signal can be a low-level signal or a high-level signal.

[0085] In this embodiment, a reset fan-out and pulse width expansion module is further provided in the trigger and reset circuit of the composite signal priority readout, wherein the input end of the reset fan-out and pulse width expansion module is connected to the priority reading module, and the output end of the reset fan-out and pulse width expansion module is connected to the time amplitude conversion module; the priority reading module is further used to generate an initial reset signal after reading the address information, the time information and the energy information; the reset fan-out and pulse width expansion module is used to generate a first reset signal, a second reset signal and a third reset signal according to the initial reset signal, and generate a first reset signal, a second reset signal and a third reset signal through the first reset signal, the second reset signal and the third composite signal. The reset fan-out and pulse width expansion module is also used to send the first reset signal to the time amplitude conversion circuit, and send the second reset signal and the third reset signal to the trailing edge detection circuit, so that the time amplitude conversion circuit and the trailing edge detection circuit perform circuit resets. The priority reading module sends an initial reset signal after reading the time information, energy information and address information, and sends the initial reset signal to the reset fan-out and pulse width expansion module to reset the analog circuit. At the same time, the reset signal is fanned out to reset multiple digital circuits. The digital circuit and the analog circuit can be reset and the clock cycle can be extended.

[0086] Reference Figure 5 , Figure 5 Schematic diagram of the structure of the fourth embodiment of the trigger and reset circuit for composite signal priority readout of the present invention.

[0087] Based on the above-mentioned first, second and third embodiments, the trailing edge detection circuit 30 in this embodiment includes: a first trigger A1, a second trigger A2 and a latch S connected in sequence; the first trigger A1 adopts a falling edge trigger, and the second trigger A2 adopts a rising edge trigger; the data input end of the first trigger A1 is connected to the power supply voltage, the clock input end of the first trigger A1 is connected to the output end of the comparison module 2, and the output end of the first trigger A1 is connected to the data input end of the second trigger A2; the clock input end of the second trigger A2 is connected to the system clock output end, the output end of the second trigger A2 is connected to the input end of the latch S, the reset port of the first trigger A1 and the reset port of the second trigger A2 are respectively connected to the output end of the reset fan-out and pulse width expansion module 5; the output end of the latch S is connected to the input end of the priority reading module 4.

[0088] It should be understood that the power supply voltage includes a first power supply input terminal VDD, the first trigger A1 is triggered by a falling edge, the second trigger A2 is triggered by a rising edge, the first trigger A1 includes a data input terminal, a clock input terminal, a reset port and an output terminal, the data input terminal of the first trigger A1 is represented by the first port, the clock input terminal is represented by the second port, the reset port is represented by the third port, and the output terminal is represented by the fourth port. The first port of the first trigger A1 is connected to the first power supply input terminal VDD, the second port of the first trigger A1 is connected to the output terminal of the comparison module 2, and the third port of the first trigger A1 is connected to the output terminal of the reset fan-out and pulse width expansion module 5, for receiving the second reset signal. The fourth port of the first trigger A1 is connected to the data input terminal of the second trigger A2. The second trigger A2 includes a data input terminal, a clock input terminal, a reset port and an output terminal. The data input terminal of the second trigger A2 is represented by the first port, the clock input terminal of the second trigger A2 is represented by the second port, the reset port of the second trigger A2 is represented by the third port, and the output terminal of the second trigger A2 is represented by the fourth port. The second port of the second trigger A2 is connected to the system clock output terminal 6 for receiving the CLK signal output by the system clock output terminal 6. The third port of the second trigger A2 is connected to the output terminal of the reset fan-out and pulse width expansion module 5 for receiving the second reset signal. The fourth port of the second trigger A2 is connected to the input terminal of the latch S.

[0089] In this embodiment, the latch S includes: a first transmission gate S1, a second transmission gate S2, a first inverter N1, a second inverter N2 and a third inverter N3; the input end of the first transmission gate S1 is connected to the output end of the second trigger A2, the control end of the first transmission gate S1 is connected to the control signal input end 7, and the output end of the first transmission gate S1 is respectively connected to the input end of the second transmission gate S2 and the input end of the first inverter N1; the output end of the first inverter N1 is connected to the input end of the second inverter N2, the output end of the second inverter N2 and the output end of the second transmission gate S2 are respectively connected to the input end of the priority reading module 4; the input end of the third inverter N3 is connected to the control signal input end 7, and the output end of the third inverter N3 is connected to the control end of the second transmission gate S2.

[0090] In a specific implementation, the first transmission gate S1 and the second transmission gate S2 are respectively composed of an N-type transistor and a P-type transistor. The transistors may be triodes or MOS transistors, which is not limited in this embodiment.

[0091] Further, the first transmission gate S1 includes: a first MOS tube M1 and a second MOS tube M2, the second transmission gate S2 includes: a third MOS tube M3 and a fourth MOS tube M4, the control signal input terminal 7 is used to access the third reset signal; the gate of the first MOS tube M1 is connected to the control signal input terminal 7, the drain of the first MOS tube M1 and the drain of the second MOS tube M2 are respectively connected to the output terminal of the second trigger A2, the source of the first MOS tube M1 and the source of the second MOS tube M2 are respectively connected to the input terminal of the first inverter N1 and the The drain of the third MOS tube M3 is connected to the drain of the fourth MOS tube M4, and the gate of the second MOS tube M2 is connected to the output end of the third inverter N3; the input end of the third inverter N3 is connected to the control signal input end 7, the gate of the third MOS tube M3 is connected to the output end of the third inverter N3, the source of the third MOS tube M3, the source of the fourth MOS tube M4 and the output end of the second inverter N2 are respectively connected to the input end of the priority reading module 4, and the gate of the fourth MOS tube M4 is connected to the control signal input end 7.

[0092] The first transmission gate S1 includes a first MOS tube M1, which is an N-type MOS tube. The gate of the first MOS tube M1 is connected to the control signal input terminal 7. The control signal input terminal 7 is used to access the third reset signal. The third reset signal can be a high-level control signal or a low-level control signal. The first MOS tube M1 is controlled to be turned on or off by the third reset signal. The second MOS tube M2 is a P-type MOS tube. The gate of the second MOS tube M2 is connected to the output terminal of the third inverter N3. The input terminal of the third inverter N3 is connected to the control signal input terminal 7 to receive the third reset signal output by the control signal input terminal 7. signal, and outputs a first control signal, the first control signal can be a low-level control signal or a high-level control signal, the control signal levels of the third reset signal and the first control signal are different, the gate of the second MOS tube M2 is connected to the output end of the third inverter N3, the on-off of the second MOS tube M2 is controlled by the first control signal, the drain of the first MOS tube M1 and the drain of the second MOS tube M2 are both connected to the fourth port of the second trigger A2, the source of the first MOS tube M1 and the source of the second MOS tube M2 are respectively connected to the input end of the first inverter N1, the drain of the third MOS tube M3 and the drain of the fourth MOS tube M4.

[0093] In a specific implementation, the gate of the third MOS tube M3 is connected to the output end of the third inverter N3, the gate of the fourth MOS tube M4 is connected to the control signal input end 7, the third MOS tube M3 is an N-type MOS tube, the fourth MOS tube M4 is a P-type MOS tube, the source of the third MOS tube M3 and the source of the fourth MOS tube M4 are respectively connected to the output end of the second inverter N2, the output end of the first inverter N1 is connected to the input end of the second inverter N2. The input end of the third inverter N3 is connected to the control signal input end 7, and the output end of the third inverter N3 outputs the first control signal to control the on and off of the second MOS tube M2 and the third MOS tube M3. The third reset signal and the first control signal are in an inverse relationship. When the third reset signal is at a low level and the first control signal is at a high level, the first MOS tube M1 and the second MOS tube M2 are turned on, the third MOS tube M3 and the fourth MOS tube M4 are turned off, and the output end of the second inverter N2 generates a STATE trigger signal through the first inverter N1 and the second inverter N2. The trigger signal enters the priority reading module 4, triggering the priority reading module 4 to read the time information, energy information and address information. The third port of the first inverter N1 and the third port of the second inverter N2 are both connected to the output end of the priority reading module 4 to receive the second reset signal. The timing of the trailing edge detection circuit 30 is as follows: Figure 6As shown, CLK is the clock signal, RSTNINT is the second reset signal, COMPOUT is the pulse signal, QINT is the signal output from the output end of the first trigger A1, Q is the signal output from the output end of the second trigger A2, RSTINTREG is the third reset signal, RSTNINTREG is the first control signal, STATE is the trigger signal, and the RSTNINT second reset signal resets the trailing edge detection circuit 30 after power-on to ensure that the outputs of the first trigger A1 and the second trigger A2 are both low level. After the falling edge of the COMPOUT pulse signal arrives, the first trigger A1 outputs a high level QINT signal, and when the next clock rising edge arrives, the second trigger A2 outputs a high level Q signal, and the high level Q signal is maintained for half a After the clock cycle, the RSTNINT second reset signal generates a low level signal, resets the first trigger A1 and the second trigger A2, and makes the Q signal output by the second trigger A2 a low level signal. At the same time, the first MOS tube M1 and the second MOS tube M2 are disconnected, the third MOS tube M3 and the fourth MOS tube M4 are turned on, and the STATE trigger signal maintains a high level. At the next adjacent clock rising edge, the first MOS tube M1 and the second MOS tube M2 are turned on, the third MOS tube M3 and the fourth MOS tube M4 are disconnected, and the STATE trigger signal becomes a low level. The RSTNINT second reset signal maintains 2.5 clock cycles to ensure that the time amplitude conversion circuit 32 is completely reset to the baseline before receiving the next hit signal, thereby ensuring the accuracy of the time amplitude conversion result read each time.

[0094] In this embodiment, a first trigger, a second trigger and a latch are sequentially connected in a trailing edge detection circuit; the first trigger is triggered by a falling edge, and the second trigger is triggered by a rising edge; the data input terminal of the first trigger is connected to the power supply voltage, the clock input terminal of the first trigger is connected to the output terminal of the comparison module, and the output terminal of the first trigger is connected to the data input terminal of the second trigger; the clock input terminal of the second trigger is connected to the system clock output terminal, the output terminal of the second trigger is connected to the input terminal of the latch, the reset port of the first trigger and the reset port of the second trigger are respectively connected to the output terminal of the reset fan-out and pulse width expansion module; the output terminal of the latch is connected to the input terminal of the priority reading module, and a trigger signal can be quickly generated through the latch, and the time amplitude conversion circuit can only receive the next hit signal after it is completely reset according to the latch control, thereby improving the accuracy of the reading time amplitude conversion result.

[0095] Reference Figure 7 , Figure 7 Schematic diagram of the structure of the fifth embodiment of the trigger and reset circuit for composite signal priority readout of the present invention.

[0096] Based on the above-mentioned first, third and fourth embodiments, the reset fan-out circuit 50 in this embodiment includes: a third trigger A3, a fourth inverter N4, a first NOR gate NOR, a first OR gate OR1 and a second OR gate OR2; the data input terminal of the third trigger A3 is connected to the power supply voltage, the initial reset terminal of the third trigger A3 is connected to the output terminal of the priority reading module 4, the output terminal of the third trigger A3 is connected to the input terminal of the first NOR gate NOR, and the output terminal of the first NOR gate NOR is connected to the input terminal of the trailing edge detection circuit 30; the input terminal of the fourth inverter N4 is connected to the global reset signal input terminal 8, and the output terminal of the fourth inverter N4 is respectively connected to the input terminal of the first NOR gate NOR, the input terminal of the first OR gate OR1 and the input terminal of the second OR gate OR2; the input terminal of the first OR gate OR1 is also connected to the output terminal of the priority reading module 4, the output terminal of the first OR gate OR1 is connected to the input terminal of the trailing edge detection circuit 30, and the output terminal of the second OR gate OR2 is connected to the input terminal of the time amplitude conversion circuit 32.

[0097] It should be noted that the power supply voltage includes a first power supply input terminal VDD, an initial reset terminal of the third trigger A3 is used to access an initial reset signal RST, a priority reading module 4 outputs an RST initial reset signal to the third trigger A3, a data input terminal of the third trigger A3 is represented by port 1, an initial reset terminal of the third trigger A3 is represented by port 2, an output terminal of the third trigger A3 is represented by port 3, an output terminal of the third trigger A3 is connected to an input terminal of the first NOR gate NOR, and the RST initial reset signal is transmitted to the first NOR gate NOR, an input terminal of the first NOR gate NOR is also connected to an output terminal of the fourth inverter N4, an input terminal of the fourth inverter N4 is connected to a global reset signal input terminal 8, a global reset signal GRSTN is input to the global reset signal input terminal 8, a global reset signal GRSTN is transmitted to the fourth inverter N4 through the global reset signal input terminal 8, and a GRST reset signal is output to the first NOR gate NOR through the fourth inverter N4, and the first NOR gate NOR generates a RSTNINT second reset signal after receiving the RST initial reset signal and the GRST reset signal.

[0098] In a specific implementation, the input end of the first OR gate OR1 is connected to the output end of the priority reading module 4 and the output end of the fourth inverter N4 respectively, the first OR gate OR1 receives the RST initial reset signal and the GRST reset signal, and generates the RSTINTREG third reset signal through the RST initial reset signal and the GRST reset signal. The second reset signal and the third reset signal are transmitted to the trailing edge detection circuit 30, the input end of the second OR gate OR2 is connected to the output end of the fourth inverter N4, receives the GRST reset signal output by the fourth inverter N4, and generates the first reset signal according to the GRST reset signal, and transmits the first reset signal to the time amplitude conversion circuit 32.

[0099] In this embodiment, the reset pulse width extension circuit 51 includes: a fourth trigger A4, a fifth trigger A5, a sixth trigger A6, a fifth inverter N5 and a first AND gate AND; the data input terminal of the fourth trigger A4 is connected to the power supply voltage, the initial reset terminal of the fourth trigger A4 is connected to the output terminal of the priority reading module 4, the output terminal of the fourth trigger A4 is respectively connected to the input terminal of the second OR gate OR2 and the data input terminal of the fifth trigger A5; the clock input terminal of the fifth trigger A5 is connected to the system clock output terminal 6, and the output terminal of the fifth trigger A5 is connected to the data input terminal of the sixth trigger A6. The clock input terminal of the sixth flip-flop A6 is connected to the system clock output terminal 6, the target reset terminal of the sixth flip-flop A6 is connected to the global reset signal input terminal 8, and the output terminal of the sixth flip-flop A6 is connected to the input terminal of the fifth inverter N5; the output terminal of the fifth inverter N5 is connected to the input terminal of the first AND gate AND, the input terminal of the first AND gate AND is also connected to the global reset signal input terminal 8, and the output terminal of the first AND gate AND is respectively connected to the target reset terminal of the third flip-flop A3, the target reset terminal of the fourth flip-flop A4, and the target reset terminal of the fifth flip-flop A5.

[0100] The data input terminal of the fourth trigger A4 is connected to the first power input terminal VDD of the power supply voltage, the initial reset terminal of the fourth trigger A4 is used to access the initial reset signal RST reset signal, the priority reading module 4 outputs the RST initial reset signal to the fourth trigger A4, the data input terminal of the fourth trigger A4 is represented by the first port, the initial reset terminal of the fourth trigger A4 is represented by the second port, the output terminal of the fourth trigger A4 is represented by the third port, the output terminal of the third port of the fourth trigger A4 is also connected to the input terminal of the second OR gate OR2, the third port of the fourth trigger A4 is connected to the data input terminal of the fifth trigger A5, the clock input terminal of the fifth trigger A5 is connected to the system clock output terminal 6 for receiving the CLK clock signal, the data input terminal of the fifth trigger A5 is represented by the first port, the clock input terminal of the fifth trigger A5 is represented by the second port, and the output terminal of the fifth trigger A5 is represented by the third port.

[0101] In this embodiment, the output end of the fifth flip-flop A5 is connected to the data input end of the sixth flip-flop A6, the clock input end of the sixth flip-flop A6 is connected to the system clock output end 6 for receiving the CLK clock signal, the target reset end of the sixth flip-flop A6 is connected to the global reset signal input end 8, the output end of the sixth flip-flop is connected to the input end of the fifth inverter N5, the data input end of the sixth flip-flop A6 is represented by the first port, the clock input end of the sixth flip-flop A6 is represented by the second port, the output end of the sixth flip-flop A6 is represented by the third port, the target reset end of the sixth flip-flop A6 is represented by the fourth port, the output end of the fifth inverter N5 is connected to the input end of the first AND gate AND, and the input end of the first AND gate AND is also connected to the global reset signal input end 8.

[0102] The third trigger A3, the fourth trigger A4 and the fifth trigger A5 all include a target reset terminal, and the target reset terminals of the third trigger A3, the fourth trigger A4 and the fifth trigger A5 are represented by the fourth port, and the target reset terminals of the third trigger A3, the fourth trigger A4 and the fifth trigger A5 are respectively connected to the output terminal of the first AND gate AND, and output the target reset signal RN. The third trigger A3, the fourth inverter N4, the first NOR gate NOR, the first OR gate OR1 and the second OR gate OR2 are used to realize the generation of three first reset signals, second reset signals and third reset signals with different phases and pulse widths from one reset signal, the RST initial reset signal or the GRSTN global reset signal. The reset pulse width extension circuit 51 is composed of the fourth trigger A4, the fifth trigger A5, the sixth trigger A6, the fifth inverter N5 and the first AND gate AND, and realizes the expansion of the reset signal pulse width from 0.5 clock cycles to multiple clock cycles, so that the analog circuit has a long enough time to reset to the reference voltage.

[0103] like Figure 8 As shown, Figure 8 This is the timing diagram of the reset fan-out and pulse width expansion module in this embodiment. Figure 8 In the figure, CLK is the clock signal, GRSTN is the global reset signal, RST is the initial reset signal, RN is the target reset signal, RSTINT is the first reset signal, RSTNINT is the second reset signal, and RSTINTREG is the third reset signal. The global reset signal GRSTN is valid at low level, and initialization is realized after power-on. The priority reading module 4 generates the RST initial reset signal and sends it to the reset fan-out and pulse width expansion module 5. The rising edge of the RST initial reset signal triggers the third trigger A3, so that the second reset signal RSTNINT becomes low level, and the third reset signal RSTINTREG becomes high level. The falling edge of the RST initial reset signal triggers the fourth trigger A4, so that the second reset signal RSTNINT becomes high, and at the same time, the third reset signal RSTINTREG becomes low. After two clock cycles, the target reset signal RN becomes low, so that the second reset signal RSTNINT becomes high, and at the same time, the first reset signal RSTINT becomes low. The first reset signal RSTINT maintains two clock cycles for resetting the time amplitude conversion circuit 32 to ensure that the analog circuit has enough time to reset to the reference voltage. The second reset signal RSTNINT and the third reset signal RSTINTREG reset the trailing edge detection circuit 30. The second reset signal RSTNINT maintains 2.5 clock cycles to ensure that the next hit information can be received only after the analog circuit is reset, thereby realizing the simultaneous reset of the digital circuit and the analog circuit.

[0104] In this embodiment, a third trigger A3, a fourth inverter N4, a first NOR gate NOR, a first OR gate OR1 and a second OR gate OR2 are arranged in the reset fan-out circuit; the data input terminal of the third trigger A3 is connected to the power supply voltage, the initial reset terminal of the third trigger A3 is connected to the output terminal of the priority reading module 4, the output terminal of the third trigger A3 is connected to the input terminal of the first NOR gate NOR, the output terminal of the first NOR gate NOR is connected to the input terminal of the time amplitude conversion circuit 32; the input terminal of the fourth inverter N4 is connected to the global reset signal The output end of the fourth inverter N4 is respectively connected to the input end of the first NOR gate NOR, the input end of the first OR gate OR1 and the input end of the second OR gate OR2; the input end of the first OR gate OR1 is also connected to the output end of the priority reading module 4, the output end of the first OR gate OR1 and the output end of the second OR gate OR2 are respectively connected to the input end of the trailing edge detection circuit 30, and the reset fan-out circuit can be used to generate three reset signals with different phases from one reset signal, so that the pulse width of the reset signal can be quickly expanded.

[0105] The embodiment of the present invention provides a triggering and resetting method for composite signal priority reading, referring to Fig. 9 , Fig. 9 The flowchart of the first embodiment of the trigger and reset method for composite signal priority reading of the present invention is shown in FIG. The method is applied to the trigger and reset circuit for composite signal priority reading described above, and the circuit includes: an amplification module, a comparison module, a detection module and a priority reading module connected in sequence.

[0106] In this embodiment, the triggering and resetting method for composite signal priority reading includes the following steps:

[0107] Step S10: the amplifying module receives the input current signal and amplifies the current signal to obtain an amplified current signal.

[0108] It should be noted that the amplification module receives the current signal input by the pixel detector and amplifies the input current signal to obtain an amplified current signal. The amplification module includes a charge-sensitive preamplifier, which amplifies the current input by the detector. The output end of the amplification module is connected to the input end of the comparison module, and the amplification module transmits the amplified current signal to the comparison module.

[0109] Step S20: the comparison module receives the amplified current signal, compares the amplified current signal, and outputs a pulse signal.

[0110] It should be understood that the comparison module includes a comparator, which may be a voltage comparator or other comparator that can compare the amplified current signal, and this embodiment does not limit this. The positive input terminal of the comparison module is connected to the output terminal of the amplification module to receive the amplified current signal, and the reverse input terminal of the comparison module is connected to the power supply voltage. The comparison module compares the amplified current signal and outputs a pulse signal, and the pulse signal refers to the COMPOUT pulse signal.

[0111] Step S30: the detection module performs time measurement and energy measurement according to the pulse signal to obtain time information and energy information, and generates a trigger signal according to the pulse signal.

[0112] Step S40: the priority reading module receives the trigger signal, reads the address information according to the trigger signal, and reads the time information and the energy information according to the trigger signal.

[0113] It should be noted that the detection module is used to receive the pulse signal output by the comparison module, and to generate a trigger signal according to the pulse signal and to perform time measurement and energy measurement according to the pulse signal. The detection module includes leading edge detection, trailing edge detection and time amplitude conversion, etc. This embodiment does not limit this. The trailing edge detection in the detection module transmits the trigger signal to the priority reading module. After receiving the trigger signal, the priority reading module reads the time information and energy information in the detection module. After receiving the trigger signal, the priority module generates a SYNC (synchronization) signal, and generates a RST (RESET) signal after reset decoding. The detection module is reset at the falling edge of the RST reset signal, and the address bus is latched at the falling edge of the SYNC signal to read the address information of the pixel. The address information, time information and energy information can be read according to the pulse signal at the same time.

[0114] This embodiment sets an amplification module, a comparison module, a detection module and a priority reading module in a trigger and reset circuit for composite signal priority reading. The amplification module is used to receive an input current signal and amplify the current signal to obtain an amplified current signal; the comparison module is used to receive the amplified current signal, compare the amplified current signal and output a pulse signal; the detection module is used to perform time measurement and energy measurement according to the pulse signal and generate a trigger signal according to the pulse signal; the priority reading module is used to receive the trigger signal and read the address information according to the trigger signal, and read the time information and energy information according to the trigger signal. The address information, time information and energy information can be read simultaneously, and multiple information can be read quickly.

[0115] In addition, to achieve the above purpose, the present invention also proposes a pixel detector, which includes a trigger and reset circuit for composite signal priority readout as described above. Since the pixel detector adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0116] It should be understood that the above is only an example and does not constitute any limitation on the technical solution of the present invention. In specific applications, technicians in this field can make settings as needed, and the present invention does not limit this.

[0117] It should be noted that the workflow described above is merely illustrative and does not limit the scope of protection of the present invention. In practical applications, technicians in this field can select part or all of them according to actual needs to achieve the purpose of the present embodiment, and no limitation is made here.

[0118] In addition, for technical details not fully described in this embodiment, reference may be made to the triggering and resetting method for composite signal priority reading provided in any embodiment of the present invention, and will not be repeated here.

[0119] In addition, it should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0120] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0121] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory (ROM) / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0122] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A trigger and reset circuit for composite signal priority readout, characterized in that: The trigger and reset circuit for composite signal priority reading includes: an amplification module, a comparison module, a detection module and a priority reading module connected in sequence; The amplification module is used to receive an input current signal and amplify the current signal to obtain an amplified current signal; The comparison module is used to receive the amplified current signal, compare the amplified current signal, and output a pulse signal; The detection module is used to perform time measurement and energy measurement according to the pulse signal, and generate a trigger signal according to the pulse signal; The priority reading module is used to receive the trigger signal, read the address information according to the trigger signal, and read the time information and energy information according to the trigger signal; The detection module comprises: a trailing edge detection circuit, a leading edge detection circuit and a time-amplitude conversion circuit; the input ends of the trailing edge detection circuit, the leading edge detection circuit and the time-amplitude conversion circuit are respectively connected to the output end of the comparison module, and the output ends of the trailing edge detection circuit, the leading edge detection circuit and the time-amplitude conversion circuit are respectively connected to the priority reading module; The trailing edge detection circuit is used to receive the pulse signal and generate a trigger signal to the priority reading module according to the pulse signal; The leading edge detection circuit is used to receive the pulse signal and perform time measurement according to the pulse signal; The time amplitude conversion circuit is used to receive the pulse signal and perform energy measurement according to the pulse signal; The trigger and reset circuit for composite signal priority reading further includes: a reset fan-out and pulse width extension module, the input end of the reset fan-out and pulse width extension module is connected to the priority reading module, and the output end of the reset fan-out and pulse width extension module is connected to the time amplitude conversion circuit; The priority reading module is further used to generate an initial reset signal after reading the address information, the time information and the energy information; The reset fan-out and pulse width extension module is used to generate a first reset signal, a second reset signal and a third reset signal according to the initial reset signal, and perform period extension through the first reset signal, the second reset signal and the third reset signal; The reset fan-out and pulse width expansion module is also used to send the first reset signal to the time amplitude conversion circuit, and send the second reset signal and the third reset signal to the trailing edge detection circuit, so as to reset the time amplitude conversion circuit and the trailing edge detection circuit.

2. The trigger and reset circuit for composite signal priority reading as claimed in claim 1, characterized in that: The trailing edge detection circuit comprises: a first trigger, a second trigger and a latch connected in sequence; The first trigger is triggered by a falling edge, and the second trigger is triggered by a rising edge; The data input terminal of the first trigger is connected to the power supply voltage, the clock input terminal of the first trigger is connected to the output terminal of the comparison module, and the output terminal of the first trigger is connected to the data input terminal of the second trigger; The clock input terminal of the second trigger is connected to the system clock output terminal, the output terminal of the second trigger is connected to the input terminal of the latch, and the reset port of the first trigger and the reset port of the second trigger are respectively connected to the output terminal of the reset fan-out and pulse width expansion module; The output end of the latch is connected to the input end of the priority reading module.

3. The trigger and reset circuit for composite signal priority reading as claimed in claim 2, characterized in that: The latch comprises: a first transmission gate, a second transmission gate, a first inverter, a second inverter and a third inverter; The input end of the first transmission gate is connected to the output end of the second trigger, the control end of the first transmission gate is connected to the control signal input end, and the output end of the first transmission gate is respectively connected to the input end of the second transmission gate and the input end of the first inverter; The output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter and the output end of the second transmission gate are respectively connected to the input end of the priority reading module; The input end of the third inverter is connected to the control signal input end, and the output end of the third inverter is connected to the control end of the second transmission gate.

4. The trigger and reset circuit for composite signal priority reading as claimed in claim 3, characterized in that: The first transmission gate includes: a first MOS transistor and a second MOS transistor, the second transmission gate includes: a third MOS transistor and a fourth MOS transistor, and the control signal input terminal is used to access a third reset signal; The gate of the first MOS tube is connected to the control signal input terminal, the drain of the first MOS tube and the drain of the second MOS tube are respectively connected to the output terminal of the second trigger, the source of the first MOS tube and the source of the second MOS tube are respectively connected to the input terminal of the first inverter and the drain of the third MOS tube and the drain of the fourth MOS tube, and the gate of the second MOS tube is connected to the output terminal of the third inverter; The input end of the third inverter is connected to the control signal input end, the gate of the third MOS tube is connected to the output end of the third inverter, the source of the third MOS tube, the source of the fourth MOS tube and the output end of the second inverter are respectively connected to the input end of the priority reading module, and the gate of the fourth MOS tube is connected to the control signal input end.

5. The trigger and reset circuit for composite signal priority reading as claimed in claim 1, characterized in that: The reset fan-out and pulse width expansion module comprises: a reset fan-out circuit and a reset pulse width expansion circuit, the input end of the reset fan-out circuit and the input end of the reset pulse width expansion circuit are respectively connected to the output end of the priority reading module, and the output end of the reset fan-out circuit is respectively connected to the input end of the time amplitude conversion circuit and the input end of the trailing edge detection circuit; The reset fan-out circuit is used to receive the initial reset signal transmitted by the priority reading module, and generate a first reset signal, a second reset signal and a third reset signal according to the initial reset signal, and send the first reset signal to the time amplitude conversion circuit, and send the second reset signal and the third reset signal to the trailing edge detection circuit, so that the time amplitude conversion circuit and the trailing edge detection circuit perform circuit reset; The reset pulse width extension circuit is used to generate a target reset signal according to the initial reset signal, so as to perform clock cycle extension on the pulse width of the initial reset signal.

6. The trigger and reset circuit for composite signal priority reading as claimed in claim 5, characterized in that: The reset fan-out circuit comprises: a third trigger, a fourth inverter, a first NOR gate, a first OR gate and a second OR gate; The data input terminal of the third trigger is connected to the power supply voltage, the initial reset terminal of the third trigger is connected to the output terminal of the priority reading module, the output terminal of the third trigger is connected to the input terminal of the first NOR gate, and the output terminal of the first NOR gate is connected to the input terminal of the trailing edge detection circuit; The input end of the fourth inverter is connected to the global reset signal input end, and the output end of the fourth inverter is respectively connected to the input end of the first NOR gate, the input end of the first OR gate, and the input end of the second OR gate; The input end of the first OR gate is also connected to the output end of the priority reading module, the output end of the first OR gate is connected to the input end of the trailing edge detection circuit, and the output end of the second OR gate is connected to the input end of the time amplitude conversion circuit.

7. The trigger and reset circuit for composite signal priority reading as claimed in claim 6, characterized in that: The reset pulse width extension circuit comprises: a fourth trigger, a fifth trigger, a sixth trigger, a fifth inverter and a first AND gate; The data input terminal of the fourth trigger is connected to the power supply voltage, the initial reset terminal of the fourth trigger is connected to the output terminal of the priority reading module, and the output terminal of the fourth trigger is respectively connected to the input terminal of the second OR gate and the data input terminal of the fifth trigger; The clock input terminal of the fifth flip-flop is connected to the system clock output terminal, the output terminal of the fifth flip-flop is connected to the data input terminal of the sixth flip-flop, the clock input terminal of the sixth flip-flop is connected to the system clock output terminal, the target reset terminal of the sixth flip-flop is connected to the global reset signal input terminal, and the output terminal of the sixth flip-flop is connected to the input terminal of the fifth inverter; The output end of the fifth inverter is connected to the input end of the first AND gate, the input end of the first AND gate is also connected to the global reset signal input end, and the output end of the first AND gate is respectively connected to the target reset end of the third trigger, the target reset end of the fourth trigger, and the target reset end of the fifth trigger.

8. A trigger and reset method for composite signal priority readout, characterized in that: The triggering and resetting method for composite signal priority reading is applied to the triggering and resetting circuit for composite signal priority reading described in any one of claims 1 to 7, the circuit comprising: an amplification module, a comparison module, a detection module and a priority reading module connected in sequence, the method comprising: The amplifying module receives an input current signal and amplifies the current signal to obtain an amplified current signal; The comparison module receives the amplified current signal, compares the amplified current signal, and outputs a pulse signal; The detection module performs time measurement and energy measurement according to the pulse signal to obtain time information and energy information, and generates a trigger signal according to the pulse signal; The priority reading module receives the trigger signal, reads the address information according to the trigger signal, and reads the time information and the energy information according to the trigger signal; The detection module comprises: a trailing edge detection circuit, a leading edge detection circuit and a time-amplitude conversion circuit; the input ends of the trailing edge detection circuit, the leading edge detection circuit and the time-amplitude conversion circuit are respectively connected to the output end of the comparison module, and the output ends of the trailing edge detection circuit, the leading edge detection circuit and the time-amplitude conversion circuit are respectively connected to the priority reading module; The step of the detection module performing time measurement and energy measurement according to the pulse signal comprises: The trailing edge detection circuit receives the pulse signal and generates a trigger signal to the priority reading module according to the pulse signal; The leading edge detection circuit receives the pulse signal and performs time measurement according to the pulse signal; The time-amplitude conversion circuit receives the pulse signal and performs energy measurement according to the pulse signal; The trigger and reset circuit for composite signal priority reading further includes: a reset fan-out and pulse width extension module, the input end of the reset fan-out and pulse width extension module is connected to the priority reading module, and the output end of the reset fan-out and pulse width extension module is connected to the time amplitude conversion circuit; The method further comprises: The priority reading module generates an initial reset signal after reading the address information, the time information and the energy information; The reset fan-out and pulse width extension module generates a first reset signal, a second reset signal and a third reset signal according to the initial reset signal, and performs cycle extension through the first reset signal, the second reset signal and the third reset signal; The reset fan-out and pulse width expansion module sends the first reset signal to the time amplitude conversion circuit, and sends the second reset signal and the third reset signal to the trailing edge detection circuit to reset the time amplitude conversion circuit and the trailing edge detection circuit.

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