A low-noise millimeter-wave fractional frequency synthesizer phase-locked loop structure

Abstract

The invention belongs to the field of digital-analog hybrid circuits, and specifically provides a low-noise millimeter-wave fractional frequency synthesizer phase-locked loop structure, which is used to overcome the problem that in a traditional phase-locked loop structure based on a time error amplifier (TA), the TA has a small dynamic range and large nonlinearity, which deteriorates the quantization noise within the phase-locked loop band and generates fractional frequency spurious. On the basis of the traditional structure, the invention also includes: a coarse digital time converter (CDTC), a fine digital time converter (FDTC) and a digital time converter pre-distortion calibration circuit; by inserting the coarse digital time converter and the fine digital time converter before and after the time error amplifier respectively, the variance of the input phase difference of the time error amplifier is reduced to improve the linearity of the time error amplifier, and the quantization noise generated by the fractional frequency division is suppressed at the same time; by adopting a threshold merit DTC adaptive pre-distortion, the spurious is reduced while maintaining the second-order shaping of the quantization noise of the DTC.

Description

Technical Field

[0001] The invention belongs to the field of digital-analog hybrid circuits, relates to a phase-locked loop structure, and specifically provides a low-noise millimeter-wave fractional frequency synthesizer phase-locked loop structure based on a time error amplifier and a digital-to-time converter. Background Art

[0002] With the advent of 5G communication technology, wireless communication systems have increasingly higher requirements for the noise performance of clock sources, and low-noise phase-locked loops are a prerequisite for various applications. In addition, in order to ensure that the frequency can be finely adjusted within a certain range, the phase-locked loop needs to support fractional frequency division.

[0003] The noise of a phase-locked loop is usually composed of the in-band noise and out-band noise of the phase-locked loop. The two are in a balance relationship. When a larger bandwidth is used, the contribution of the in-band noise to the output noise of the phase-locked loop will increase, while the contribution of the out-band noise to the output noise of the phase-locked loop will decrease. Since the phase-locked loop based on the time error amplifier (TA) can well suppress the noise of the charge pump (CP) (the main in-band noise contributor in integer mode), if the quantization noise of the fractional frequency division (another major in-band noise contributor in fractional mode) can be well suppressed, a larger bandwidth can be used to suppress the noise of the voltage controlled oscillator (VCO) (the main contributor to out-band noise); however, the traditional method of implementing fractional frequency division based on the Delta-Sigma Modulator (DSM) divider has a much higher in-band quantization noise than TA. In addition, the inherent small dynamic range of TA and the large nonlinearity limit make the fractional frequency division based on the DSM divider produce large quantization noise and fractional spurious. Summary of the invention

[0004] The purpose of the present invention is to provide a low-noise millimeter-wave fractional frequency synthesizer phase-locked loop structure based on a time error amplifier and a digital-to-time converter (Digital-to-Time Converter, DTC), so as to overcome the problem that in a traditional phase-locked loop structure based on a time error amplifier (TA), the TA has a small dynamic range and a large nonlinearity, which deteriorates the quantization noise within the phase-locked loop band and generates fractional frequency spurious. The present invention reduces the variance of the input phase difference of the time error amplifier by inserting a coarse digital time converter (Coarse DTC, CDTC) and a fine digital time converter (Fine DTC, FDTC) before and after the time error amplifier (TA), so as to improve the linearity of the time error amplifier and suppress the quantization noise generated by the fractional frequency division.

[0005] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0006] A low-noise millimeter-wave fractional frequency synthesizer phase-locked loop structure, comprising: a phase frequency detector (PFD), a time error amplifier (TA), a charge pump (CP), a loop filter (LF), a voltage-controlled oscillator (VCO), a frequency divider, and a DSM module, characterized in that the phase-locked loop structure also includes: a coarse digital time converter (CDTC), a fine digital time converter (FDTC) and a digital time converter pre-distortion calibration circuit, wherein the input end of the coarse digital time converter is connected to the output end of the frequency divider, and the output end is connected to the frequency division input end of the phase frequency detector, and the fine digital time converter (FDTC) is connected between the time error amplifier and the charge pump; the digital time converter pre-distortion calibration circuit includes: a first DTC pre-distortion calibration module, a second DTC pre-distortion calibration module and a Bang-Bang phase detector (BBPD), and the output signal of the phase frequency detector is Connected to the input of the Bang-Bang phase detector, the Bang-Bang phase detector extracts The phase error information is connected to the first DTC pre-distortion calibration module and the second DTC pre-distortion calibration module. The first DTC pre-distortion calibration module generates a CDTC control signal and is connected to the control end of the coarse digital-to-time converter. The second DTC pre-distortion calibration module generates a FDTC control signal and is connected to the control end of the fine digital-to-time converter.

[0007] Furthermore, in the phase-locked loop structure, the input signal f in The output signal of the coarse digital time converter is connected to the frequency division input terminal of the phase detector, and the output signal of the phase detector is connected to the crystal oscillator signal input terminal of the phase detector. Connect to the input of the time error amplifier and generate the output signal through the time error amplifier Connected to the input of the thin digital time converter, the thin digital time converter generates an output signal And connected to the input of the charge pump, the charge pump generates an output current signal and converts it into a voltage signal V through a loop filter tune , voltage signal V tune Connected to the control terminal of the voltage controlled oscillator, the voltage controlled oscillator generates an output signal f out ; At the same time, the output signal f out The feedback signal is connected to the input of the frequency divider, and the frequency divider generates a divided signal f div Connected to the input of the coarse digital-to-time converter and the frequency-divided signal f div As the clock drives the DSM module, the DSM module generates phase residual information accordingly. Control signal Ndiv They are respectively connected to the phase residual input terminal of the first DTC pre-distortion calibration module and the control terminal of the frequency divider.

[0008] Further, the first DTC pre-distortion calibration module includes: a first DTC pre-distortion module and a first DTC calibration module; wherein the first DTC pre-distortion module includes: a first lookup table, a first threshold calculation module, a first comparator and a first priority encoder, wherein the first lookup table stores the delay data of each control word corresponding to the coarse digital time converter, the first threshold calculation module calculates the average value of each adjacent delay data in the first lookup table and outputs the calculation result, and the phase residual information output by the DSM module is converted into the phase residual information. The output of the first threshold calculation module is compared with each output of the first threshold calculation module, and the comparison result is input to the first priority encoder, and the first priority encoder selects the phase residual information closest to the phase residual information in the lookup table. Delay data D clut , and the delayed data D clut The corresponding control word is used as the CDTC control signal and output; at the same time, the phase residual information Subtract the delayed data D clut The phase residual output D of the first DTC predistortion calibration module cdtc , and connected to the phase residual input terminal of the second DTC pre-distortion calibration module.

[0009] Further, the second DTC predistortion calibration module includes: a second DTC predistortion module and a second DTC calibration module; wherein the second DTC predistortion module includes: a second lookup table, a second threshold calculation module, a second comparator and a second priority encoder, wherein the second lookup table stores the delay data of each control word of the corresponding fine digital time converter, the second threshold calculation module calculates the average value of each adjacent delay data in the second lookup table and outputs the calculation result, and the phase residual output D of the first DTC predistortion calibration module is cdtc and the current residual R dsm Add to get the value to be compared D c , D c The output of the second threshold calculation module is compared with each output of the second threshold calculation module, and the comparison result is input to the second priority encoder, and the second priority encoder selects the closest to the comparison value D in the lookup table. c Delay data D flut , and delay data D flut The corresponding control word is used as the FDTC control signal and output; at the same time, the comparison value D c With delayed data D flut Subtract the phase residual R of the next cycle dsm ; Phase residual output D cdtc With delayed data D flutSubtract the phase residual output D of the second DTC pre-distortion calibration module fdtc , and connected to the second DTC calibration module and the first DTC calibration module.

[0010] Furthermore, the second DTC calibration module and the first DTC calibration module adopt the same structure, specifically: the phase residual output D of the second DTC pre-distortion calibration module is fdtc The sign bit of the bang-bang phase detector is compared with the output of the bang-bang phase detector. When the two are different, the second lookup table and the first lookup table are updated: when the bang-bang phase detector output is 1, the delay data D in the second lookup table is increased according to the preset step size. flut and the delay data D in the first lookup table clut When the Bang-Bang phase detector output is 0, the delay data D in the second lookup table is reduced according to the preset step length. flut and the delay data D in the first lookup table clut .

[0011] The beneficial effects of the present invention are:

[0012] The present invention provides a low-noise millimeter-wave fractional frequency synthesizer phase-locked loop structure, which has the following advantages:

[0013] 1) DTC is used to directly realize digital phase control in the phase domain, and the quantization error residual of DSM is compensated in the phase domain. At the same time, the compensation of quantization error also reduces the input phase jitter of TA, so that TA can be designed with higher gain, thereby reducing the in-band noise of the phase-locked loop; finally, the present invention can achieve a quantization noise of less than -170dBc / Hz;

[0014] 2) Using threshold merit DTC adaptive pre-distortion to reduce spurious while maintaining the first-order shaping of DTC quantization noise;

[0015] 3) Using two-stage DTC can reduce the thermal noise and power consumption of DTC. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the phase-locked loop structure of the low-noise millimeter-wave frequency synthesizer in the present invention.

[0017] Figure 2 It is a structural schematic diagram of the first DTC pre-distortion calibration module in the present invention.

[0018] Figure 3 It is a structural schematic diagram of the second DTC pre-distortion calibration module in the present invention.

[0019] Figure 4 It is a structural schematic diagram of the DTC calibration module in the present invention.

[0020] Figure 5 The figure is a schematic diagram of the convergence process of the DTC calibration module in the embodiment of the present invention.

[0021] Figure 6 : is the quantization noise of the DSM in the embodiment of the present invention (after DTC noise elimination) and the phase noise contribution of the comparative example (MESH 1-1) at the reference. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical scheme and technical effect of the present invention clearer and more complete, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0023] This embodiment provides a low-noise millimeter-wave fractional frequency synthesizer phase-locked loop structure based on a time error amplifier and a digital-to-time converter, such as Figure 1 As shown, where f in is the input crystal signal, f out The output signal is a frequency-multiplied output signal of a phase-locked loop; specifically, it includes: a phase frequency detector (PFD), a time error amplifier (TA), a charge pump (CP), a loop filter (LF), a voltage controlled oscillator (VCO), a frequency divider, a Delta-Sigma Modulator (DSM) module, a coarse digital time converter (CDTC), a fine digital time converter (FDTC) and a digital time converter (DTC) pre-distortion calibration circuit, wherein the digital time converter (DTC) pre-distortion calibration circuit includes: a first DTC pre-distortion calibration module, a second DTC pre-distortion calibration module and a Bang-Bang phase detector (BBPD);

[0024] Input signal f in Connected to the crystal oscillator signal input terminal of the PFD, the output signal of the CDTC is connected to the frequency division input terminal of the PFD, and the output signal of the PFD is connected to the crystal oscillator signal input terminal of the PFD. Connect to the input of TA and generate output signal through TA Connect to the input of FDTC, FDTC generates output signal Connected to the input of CP, CP generates an output current signal and converts it into a voltage signal V through LF tune , voltage signal V tune Connected to the control terminal of VCO, VCO generates output signal f out ; At the same time, the output signal f outThe feedback signal is connected to the input of the frequency divider, and the frequency divider generates a divided signal f div Connected to the input of CDTC; the frequency division signal f div As the clock drives the DSM module, the DSM module generates phase residual information accordingly. Control signal N div The output signal is connected to the phase residual input terminal of the first DTC pre-distortion calibration module and the control terminal of the frequency divider to realize the fractional frequency division function; Connected to the input of BBPD, BBPD extracts The phase error information is connected to the first DTC pre-distortion calibration module and the second DTC pre-distortion calibration module, the first DTC pre-distortion calibration module generates a CDTC control signal and is connected to the control end of CDTC, the second DTC pre-distortion calibration module generates an FDTC control signal and is connected to the control end of FDTC; in this embodiment, CDTC has a 5-bit numerical control range, covering a 115ps interval; FDTC has a 5-bit numerical control range, covering a 120ps numerical control interval.

[0025] Further, the first DTC pre-distortion calibration module includes: a first DTC pre-distortion module and a first DTC calibration module; the first DTC pre-distortion module is as follows: Figure 2 As shown, it includes: a first lookup table, a first threshold calculation module, a first comparator and a first priority encoder, wherein the first lookup table stores the delay data of each control word corresponding to the CDTC (32 in this embodiment), the first threshold calculation module (an adder array in this embodiment) calculates the average value of each adjacent delay data in the first lookup table: F(a,b)=(a+b) / / 2, and outputs the calculation result, the phase residual information The output of the first threshold calculation module is compared with each output of the first threshold calculation module, and the comparison result is input to the first priority encoder, and the first priority encoder selects the phase residual information closest to the phase residual information in the lookup table. Delay data D clut , and delay data D clut The corresponding control word is used as the CDTC control signal and output; at the same time, the phase residual information Subtract the delayed data D clut The phase residual output D of the first DTC predistortion calibration module cdtc , and connected to the phase residual input terminal of the second DTC pre-distortion calibration module;

[0026] The second DTC pre-distortion calibration module includes: a second DTC pre-distortion module and a second DTC calibration module; the second DTC pre-distortion module is as follows Figure 3As shown, it includes: a second lookup table, a second threshold calculation module, a second comparator and a second priority encoder, wherein the second lookup table stores the delay data of each control word corresponding to the FDTC (32 in this embodiment), the second threshold calculation module (an adder array in this embodiment) calculates the average value of each adjacent delay data in the second lookup table and outputs the calculation result, and the phase residual output D cdtc and the current residual R dsm Add to get the value to be compared D c , D c The output of the second threshold calculation module is compared with each output of the second threshold calculation module, and the comparison result is input to the second priority encoder, and the second priority encoder selects the closest to the comparison value D in the lookup table. c Delay data D flut , and delay data D flut The corresponding control word is used as the FDTC control signal and output; at the same time, the comparison value D c With delayed data D flut Subtract the phase residual R of the next cycle dsm ; Phase residual output D cdtc With delayed data D flut Subtract the phase residual output D of the second DTC pre-distortion calibration module fdtc , and connected to the second DTC calibration module and the first DTC calibration module;

[0027] The second DTC calibration module has the same structure as the first DTC calibration module. Figure 4 As shown, specifically: Phase residual output D fdtc The sign bit of the DTC pre-distortion module is compared with the output of the BBPD. When the two are different, the lookup table of the DTC pre-distortion module is updated: when the BBPD output is 1, the delay data D in the lookup table is increased according to the preset step size. flut With delayed data D clut When the BBPD output is 0, the delay data D in the lookup table is reduced according to the preset step size. flut With delayed data D clut ; When the two are the same, there is no need to update the lookup table.

[0028] From the calibration principle, when the delay data in the lookup table in the current cycle is small, the threshold calculation module will also generate a smaller threshold, so that the actual delay of DTC (CDTC and FDTC) will be higher, and BBPD will have a higher probability of outputting 1. Therefore, the corresponding delay data in the lookup table is increased to complete the calibration process; Figure 5 The figure shows the convergence process of the DTC calibration module. For the convenience of display, the first of the 32 delay data is taken. The convergence process of the remaining registers is expected to be similar. It can be seen from the figure that the calibration value can be well converged within 10ms.

[0029] In this embodiment, a conventional MASH1-1 circuit (with 1% output nonlinearity) is used as a comparative example. The quantization noise modulation order of this embodiment and the comparative example is the same (2nd order); Figure 6 The figure shows the comparison of quantization noise between the comparative example and the embodiment. The noise of the comparative example will be greater than -150dBc / Hz at 1MHz; the phase noise performance of the embodiment can achieve less than -180dBc / Hz at 1MHz; it can be seen that the in-band quantization noise of the present invention can be much smaller than the noise contribution of the TA and the crystal oscillator.

[0030] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A low-noise millimeter-wave fractional frequency synthesizer phase-locked loop structure, comprising: A phase frequency detector (PFD), a time error amplifier (TA), a charge pump (CP), a loop filter (LF), a voltage controlled oscillator (VCO), a frequency divider, and a DSM module, characterized in that the phase-locked loop structure also includes: a coarse digital time converter (CDTC), a fine digital time converter (FDTC) and a digital time converter pre-distortion calibration circuit, wherein the input end of the coarse digital time converter is connected to the output end of the frequency divider, and the output end is connected to the frequency division input end of the phase frequency detector, and the fine digital time converter (FDTC) is connected between the time error amplifier and the charge pump; the digital time converter pre-distortion calibration circuit includes: a first DTC pre-distortion calibration module, a second DTC pre-distortion calibration module and a Bang-Bang phase detector (BBPD), and the output signal of the fine digital time converter Connected to the input of the Bang-Bang phase detector, the Bang-Bang phase detector extracts The phase error information is connected to the first DTC predistortion calibration module and the second DTC predistortion calibration module, the first DTC predistortion calibration module generates a CDTC control signal and is connected to the control end of the coarse digital-to-time converter, the second DTC predistortion calibration module generates an FDTC control signal and is connected to the control end of the fine digital-to-time converter; the DSM module is connected to the divider and the first DTC predistortion calibration module, and the first DTC predistortion calibration module is connected to the second DTC predistortion calibration module.

2. The low-noise millimeter-wave fractional frequency synthesizer phase-locked loop structure according to claim 1, characterized in that: In the phase-locked loop structure, the input signal f in The output signal of the coarse digital time converter is connected to the frequency division input terminal of the phase detector, and the output signal of the phase detector is connected to the crystal oscillator signal input terminal of the phase detector. Connect to the input of the time error amplifier and generate the output signal through the time error amplifier Connected to the input of the thin digital time converter, the thin digital time converter generates an output signal And connected to the input of the charge pump, the charge pump generates an output current signal and converts it into a voltage signal V through a loop filter tune , voltage signal V tune Connected to the control terminal of the voltage controlled oscillator, the voltage controlled oscillator generates an output signal f out ; At the same time, the output signal f out The feedback signal is connected to the input of the frequency divider, and the frequency divider generates a divided signal f div Connected to the input of the coarse digital-to-time converter and the frequency-divided signal f div As the clock drives the DSM module, the DSM module generates phase residual information accordingly. Control signal N div They are respectively connected to the phase residual input terminal of the first DTC pre-distortion calibration module and the control terminal of the frequency divider.

3. The low-noise millimeter-wave fractional frequency synthesizer phase-locked loop structure according to claim 1, characterized in that: The first DTC predistortion calibration module includes: a first DTC predistortion module and a first DTC calibration module; wherein the first DTC predistortion module includes: a first lookup table, a first threshold calculation module, a first comparator and a first priority encoder, wherein the first lookup table stores the delay data of each control word corresponding to the coarse digital time converter, the first threshold calculation module calculates the average value of each adjacent delay data in the first lookup table and outputs the calculation result, and the phase residual information output by the DSM module is converted into the phase residual information. The output of the first threshold calculation module is compared with each output of the first threshold calculation module, and the comparison result is input to the first priority encoder, and the first priority encoder selects the phase residual information closest to the phase residual information in the lookup table. Delay data D clut , and the delayed data D clut The corresponding control word is used as the CDTC control signal and output; at the same time, the phase residual information Subtract the delayed data D clut As the phase residual output D of the first DTC pre-distortion calibration module cdtc .

4. The low-noise millimeter-wave fractional frequency synthesizer phase-locked loop structure according to claim 1, characterized in that: The second DTC predistortion calibration module includes: a second DTC predistortion module and a second DTC calibration module; wherein the second DTC predistortion module includes: a second lookup table, a second threshold calculation module, a second comparator and a second priority encoder, wherein the second lookup table stores the delay data of each control word of the corresponding fine digital time converter, the second threshold calculation module calculates the average value of each adjacent delay data in the second lookup table and outputs the calculation result, and the phase residual output D of the first DTC predistortion calibration module is cdtc and the current residual R dsm Add to get the value to be compared D c , D c The output of the second threshold calculation module is compared with each output of the second threshold calculation module, and the comparison result is input to the second priority encoder, and the second priority encoder selects the closest to the comparison value D in the lookup table. c Delay data D flut , and delay data D flut The corresponding control word is used as the FDTC control signal and output; at the same time, the comparison value D c With delayed data D flut Subtract the phase residual R of the next cycle dsm ; Phase residual output D cdtc With delayed data D flut Subtract the phase residual output D of the second DTC pre-distortion calibration module fdtc .

5. The low-noise millimeter-wave fractional frequency synthesizer phase-locked loop structure according to claim 3, characterized in that: The first DTC calibration module is specifically: the phase residual output D of the second DTC pre-distortion calibration module is fdtc The sign bit of is compared with the output of the Bang-Bang phase detector. When the two are different, the first lookup table is updated: when the output of the Bang-Bang phase detector is 1, the delay data D in the first lookup table is increased according to the preset step size. clut When the Bang-Bang phase detector output is 0, the delay data D in the first lookup table is reduced according to the preset step length. clut .

6. The low-noise millimeter-wave fractional frequency synthesizer phase-locked loop structure according to claim 4, characterized in that: The second DTC calibration module is specifically: the phase residual output D of the second DTC pre-distortion calibration module is fdtc The sign bit of the bang-bang phase detector is compared with the output of the bang-bang phase detector. When the two are different, the second lookup table is updated: when the bang-bang phase detector output is 1, the delay data D in the second lookup table is increased according to the preset step size. flut When the Bang-Bang phase detector output is 0, the delay data D in the second lookup table is reduced according to the preset step length. flut .

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