3D NAND memory and methods of forming the same

Abstract

A method for forming a 3D NAND memory, a storage structure and a polysilicon layer on the storage structure are formed in a channel via, the surface of the polysilicon layer is lower than the top surface of the dielectric layer, then a first metal silicide layer and a via contact metal layer on the first metal silicide layer are formed on the surface of the polysilicon layer; the sacrificial layer is replaced with a control gate structure; a first via exposing part of the surface of the well region on one side of the stack structure and a plurality of second vias exposing the surface of the corresponding step structure are formed in the dielectric layer; a second metal silicide layer is formed on the surface of the well region at the bottom of the first via; a first contact plug is formed in the first via, and a second contact plug is formed in the second via.

Description

[0001] Cross Reference to Related Applications

[0002] The present disclosure is based on and claims priority to Chinese Patent Application No. 202011117206.4, filed on October 19, 2020, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to a 3D NAND memory and a forming method thereof. BACKGROUND

[0004] NAND flash is a better storage device than hard disk drive, and has been widely used in electronic products as people pursue low power consumption, light weight and good performance of non-volatile storage products. At present, the planar structure of NAND flash has reached the limit of practical expansion. In order to further improve the storage capacity and reduce the storage cost per bit, a 3D structure of NAND memory is proposed.

[0005] In related technologies, when a first metal silicide layer is formed on a channel hole, a void is easily formed at a conductive plug of the channel hole, thereby causing the contact resistance to become large. SUMMARY

[0006] The present disclosure provides a forming method of a 3D NAND memory, comprising:

[0007] A semiconductor substrate is provided, which has a well region therein, and a stack structure of alternating layers of a sacrificial layer and an isolation layer is formed on the well region of the semiconductor substrate, and the end of the stack structure has a step structure;

[0008] A dielectric layer covering the semiconductor substrate and the stack structure is formed;

[0009] A plurality of channel through holes penetrating the thickness of the stack structure are formed in the dielectric layer and the stack structure;

[0010] A storage structure and a polysilicon layer located on the storage structure are formed in the channel through hole, and the surface of the polysilicon layer is lower than the top surface of the dielectric layer;

[0011] A first metal silicide layer and a via contact metal layer located on the first metal silicide layer are formed on the surface of the polysilicon layer;

[0012] The sacrificial layer is replaced by a control gate structure;

[0013] forming a first via hole exposing a part of the surface of the well region on the side of the stack structure and a plurality of second via holes exposing the surface of the corresponding step structure;

[0014] forming a second metal silicide layer on the surface of the well region at the bottom of the first via hole;

[0015] forming a first contact plug connected with the second metal silicide layer in the first via hole and a second contact plug connected with the surface of the corresponding step structure in the second via hole.

[0016] Optionally, the forming process of the first metal silicide layer and the via hole contact metal layer is: forming a first metal layer on the surface of the dielectric layer and in the channel via hole on the polysilicon layer; annealing the first metal layer to make the first metal layer react with a part of the polysilicon layer on the storage structure and form a first metal silicide layer on the surface of the polysilicon layer, the surface of the first metal silicide layer being lower than the top surface of the dielectric layer; removing the unreacted first metal layer to form a via hole contact metal layer on the surface of the first metal silicide layer, the surface of the via hole contact metal layer being flush with the top surface of the dielectric layer.

[0017] Optionally, the material of the first metal silicide layer is one of nickel silicide, cobalt silicide, tantalum silicide, titanium silicide or a combination thereof.

[0018] Optionally, the forming process of the control gate structure is: forming a hard mask layer on the stack structure; forming a gate separation groove in the hard mask layer and the stack structure; removing the sacrificial layer along the gate separation groove; forming a control gate structure at the position where the sacrificial layer is removed; and forming an array common source in the gate separation groove.

[0019] Optionally, it further includes: forming a bit line connected with the via hole contact metal layer in the hard mask layer, the size of the bit line being smaller than that of the via hole contact metal layer.

[0020] Optionally, the forming process of the second metal silicide layer, the first contact plug, the second contact plug and the bit line comprises: etching the hard mask layer and the dielectric layer to form a first via exposing a part of the surface of the well region on one side of the stack structure, a plurality of second vias exposing the surface of the corresponding step structure, and a third via exposing a part of the surface of the via contact metal layer in the hard mask layer, the size of the third via being smaller than the size of the via contact metal layer; forming a second metal layer in the first via and on the surface of the hard mask layer; performing annealing to make the second metal layer react with the silicon in the well region to form a second metal silicide layer on the surface of the well region; removing the unreacted second metal layer; filling a metal layer in the first via, the second via and the third via to form a first contact plug connected with the second metal silicide layer in the first via, a second contact plug connected with the surface of the corresponding step structure in the second via, and a bit line connected with the via contact metal layer in the third via.

[0021] Optionally, the material of the second metal silicide layer is one of nickel silicide, cobalt silicide, tantalum silicide and titanium silicide, or a combination thereof.

[0022] Optionally, the memory structure comprises a charge storage layer on the surface of the channel via sidewall and a channel layer on the sidewall of the charge storage layer.

[0023] Optionally, the charge storage layer comprises a blocking layer on the surface of the channel via sidewall, a charge trapping layer on the sidewall of the blocking layer, and a tunneling layer on the sidewall of the charge trapping layer.

[0024] Optionally, the control gate structure comprises a gate dielectric layer and a gate electrode on the gate dielectric layer.

[0025] Further, the forming process of the second metal silicide layer, the first contact plug, the second contact plug and the bit line includes: etching the hard mask layer and the dielectric layer to form a first via exposing a part of the surface of the well region on one side of the stack structure and a plurality of second vias exposing the surface of the corresponding step structure, and a third via exposing a part of the surface of the via contact metal layer in the hard mask layer, the size of the third via being smaller than the size of the via contact metal layer; forming a second metal layer in the first via and on the surface of the hard mask layer; performing annealing to make the second metal layer react with the silicon in the well region to form a second metal silicide layer on the surface of the well region; removing the unreacted second metal layer; filling a metal layer in the first via, the second via and the third via, forming a first contact plug connected with the second metal silicide layer in the first via, a second contact plug connected with the surface of the corresponding step structure in the second via, and a bit line connected with the via contact metal layer in the third via. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figures 1A-1D A cross-sectional structure schematic diagram of a forming process of a 3D NAND memory.

[0027] Figures 2-10 A cross-sectional structure schematic diagram of a forming process of a 3D NAND memory provided by some embodiments of the present disclosure. DETAILED DESCRIPTION

[0028] As described in the background, the thickness of the first metal silicide layer formed in the related art is difficult to meet the performance requirements.

[0029] Figures 1A-1D A cross-sectional structure schematic diagram of a forming process of a 3D NAND memory. Referring to Figure 1A , a semiconductor structure is provided, which includes: a semiconductor substrate 10 having a well region 20 therein; a stack structure 12 having a sacrificial layer 13 and an isolation layer 14 alternately stacked on the semiconductor substrate 10, the stack structure 12 having a step structure 21 at one end; a first dielectric layer 15 covering the stack structure 12 and the semiconductor substrate 10 on one side of the stack structure 12; a channel via penetrating through the first dielectric layer 15 and the stack structure 12, a channel structure 18 located in the channel via and a polysilicon layer 19 located in the channel via remaining on the channel structure 18. The channel structure 18 includes a charge storage layer 17 located on the surface of the side wall of the channel via and a channel layer 16 located on the surface of the charge storage layer 17.

[0030] Referring to Figure 1BA mask layer 22 is formed on the stack structure 12; a gate line slite (GLS) 23 is formed in the mask layer 22 and the stack structure 12; a dielectric material layer (e.g., an oxide sidewall) is formed in the gate line slite 23; the sacrificial layer is removed along the gate line slite 23; and a control gate structure 131 is formed at the position where the sacrificial layer is removed. An array common source (ACS) 24 is formed in the gate line slite 23 (e.g., in the gate line slite 23 formed in the oxide sidewall).

[0031] Reference Figure 1C A first via hole exposing a part of the surface of the well region 20 on one side of the stack structure 12 and a plurality of second via holes exposing the surface of the corresponding step structure 21 are formed in the mask layer 22 and the first dielectric layer 15 by a first photolithography process, and a bit line contact via hole exposing the polysilicon layer 19 is formed in the mask layer 22. A first metal silicide layer 26 and a second metal silicide layer 25 are respectively formed in the bit line contact via hole and the first via hole. Since a lower contact resistance is required when the first contact plug 27 is connected to the well region, more metal needs to be deposited to form a thicker second metal silicide layer 25 when forming the second metal silicide layer 25. However, the inventors of the present disclosure have noticed in research that in the related art, when the first metal silicide layer is formed on the channel hole, a void is easily formed at the conductive plug of the channel hole, thereby causing the contact resistance to become larger, resulting in a smaller overall channel current and degradation of the low-temperature characteristics of the device.

[0032] A metal layer material is filled in the remaining gate line slite on the first via hole, the second via hole, the bit line contact via hole, and the array common source 24 to form a first contact plug 27, a second contact plug 30, a bit line contact plug 28, and a fourth contact plug 29. Since the bit line contact via hole and the first via hole are formed in the same step, the diameter of the bit line contact via hole can be different from the diameter of the polysilicon layer 19, for example, the diameter of the bit line contact via hole and the bit line contact plug 28 is smaller than the diameter of the polysilicon layer 19.

[0033] Reference Figure 1DA second dielectric layer 31 is formed on the mask layer 22, and a fourth via hole exposing the bit line contact plug 28 is formed in the second dielectric layer 31 by a second photolithography process. In order to reduce the diameter of the bit line contact structure formed in the fourth via hole, for example, to be smaller than the diameter of the channel via hole or the first metal silicide layer, the diameter of the fourth via hole formed is smaller than the diameter of the bit line contact via hole, and a conductive material is filled in the fourth via hole to form a bit line contact structure 32, and the diameter of the finally formed bit line contact structure 32 is smaller than the diameter of the channel via hole or the first metal silicide layer. The bit line contact structure 32 is in conductive contact with the first metal silicide layer 26 through the bit line contact plug 28.

[0034] The inventors of the present disclosure found through research that the thickness of the first metal silicide layer formed in the related art is too thick and does not meet the performance requirements. Further research found that the existing first metal silicide layer and the second metal silicide layer are formed in the same process step. However, since the first contact plug needs to have a low contact resistance when connected to the well region, a large amount of metal needs to be deposited to form a thick second metal silicide layer when the second metal silicide layer is formed. Compared to the hole depth of the first via hole, the hole depth of the bit line contact via hole on the channel structure is shallower. If the same amount of metal is deposited in the same process step, the thickness of the first metal silicide layer formed by annealing in the bit line contact via hole with a shallower hole depth will be thicker, that is, the thickness of the first metal silicide layer formed in the bit line contact via hole with a shallower hole depth is greater than the thickness of the second metal silicide layer formed in the first via hole with a deeper hole depth. Thus, a void is easily formed at the conductive plug of the channel hole, thereby causing the contact resistance to become large, and further causing the overall channel current to be too small and the low-temperature characteristics of the device to degrade.

[0035] In addition, in order to make the size of the bit line contact structure smaller than the size of the channel via hole or the first metal silicide layer, an additional photolithography process is needed to form the bit line contact structure with a size smaller than the size of the channel via hole or the first metal silicide layer, which increases the cost. For example, the photolithography process for forming the bit line contact structure is not compatible with the photolithography process for forming the first metal silicide layer and the second metal silicide layer.

[0036] For example, the disclosure provides a forming method of a 3D NAND memory, forming a storage structure and a polysilicon layer on the storage structure in a channel via, the surface of the polysilicon layer being lower than the top surface of the dielectric layer, then forming a first metal silicide layer on the surface of the polysilicon layer and a via contact metal layer on the first metal silicide layer; replacing the sacrificial layer with a control gate structure; forming a first via in the dielectric layer to expose a portion of the surface of the well region on one side of the stack structure and a plurality of second vias to expose the surface of the corresponding step structure; forming a second metal silicide layer on the surface of the well region at the bottom of the first via; forming a first contact plug connected with the second metal silicide layer in the first via, and forming a second contact plug connected with the surface of the corresponding step structure in the second via. The step of forming the first metal silicide layer and the subsequent step of forming the second metal silicide are not performed in the same step, so that when the first metal silicide is formed, the thickness of the formed first metal silicide layer can be adjusted independently, so that the thickness of the first metal silicide layer is not limited by the process of forming the second metal silicide layer, so that the thickness of the formed first metal silicide layer meets the performance requirements, so as to reduce the probability of holes in the first metal silicide layer and the probability of increased contact resistance and reduced yield.

[0037] To make the above-mentioned purposes, features and advantages of the disclosure more obvious and easy to understand, the specific embodiments of the disclosure will be described in detail below in combination with the drawings. In the detailed description of the embodiments of the disclosure, the schematic diagram will be partially enlarged without general proportion for convenience of description, and the schematic diagram is only an example, which should not limit the protection scope of the disclosure here. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in actual manufacture.

[0038] Figures 2-10 The cross-sectional structure schematic diagram of the forming process of the 3D NAND memory provided by some embodiments of the disclosure.

[0039] It should be noted that the forming method of the 3D NAND memory described in the disclosure is not limited to forming a 3D NAND memory, but can also be used to form a 3D Re-RAM memory, a 3D PCM memory and other three-dimensional non-volatile memories.

[0040] Reference Figure 2, and a semiconductor layer is provided. For example, the semiconductor layer can be a semiconductor substrate 100, and for the convenience of description, the semiconductor layer is described as the semiconductor substrate 100 in the following, but embodiments of the present disclosure are not limited thereto. For example, the semiconductor substrate 100 has a well region 110, and a stack structure 111 of alternating layers of a sacrificial layer 103 and an isolation layer 104 is formed on the well region 110 of the semiconductor substrate, and the stack structure 111 has a step structure 11 at an end thereof; a dielectric layer 105 covering the semiconductor substrate 100 and the stack structure 111 is formed; a plurality of channel through holes penetrating the thickness of the stack structure are formed in the dielectric layer 105 and the stack structure 111; a storage structure 108 and a polysilicon layer 111 on the storage structure 108 are formed in the channel through holes. In some examples, a channel structure is arranged in each channel through hole, and the channel through hole and the channel structure constitute a channel hole, and the storage structure 108 is the channel structure.

[0041] For example, the material of the semiconductor layer (the semiconductor substrate 100) can include (for example, can be) any one or any combination of monocrystalline silicon (Si), monocrystalline germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), polycrystalline silicon; can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or can also be other materials, such as gallium arsenide and other group III-V compounds. For example, the material of the semiconductor substrate 100 is monocrystalline silicon (Si).

[0042] The semiconductor substrate 100 has a well region 110. The well region 110 can be a P-type well region. For example, the well region 110 can be an N-type well region.

[0043] The stack structure 111 includes a plurality of alternating layers of a sacrificial layer 103 and an isolation layer 104 (for example, an electrically isolated layer, an insulating layer), the sacrificial layer 103 is removed to form a cavity in the subsequent process, and then a control gate structure (Word line) is formed at the position where the sacrificial layer 103 is removed. The isolation layer 104 serves as electrical isolation between different layers of control gates, and between control gates and other devices (conductive contacts, channel holes, etc.). In some embodiments, the sacrificial layer can include a dielectric material, a semiconductor material, or a conductive material. The isolation layer can include an electrically isolated material, an insulating material, or a dielectric material.

[0044] The alternating layer stack of the sacrificial layer 103 and the isolation layer 104 includes that the sacrificial layer 103 and the isolation layer 104 are arranged alternately. In an embodiment, the alternating layer stack of the sacrificial layer 103 and the isolation layer 104 can be that after forming a layer of the sacrificial layer 103, a layer of the isolation layer 104 is formed on the surface of the sacrificial layer 103, and then the steps of forming the sacrificial layer 103 and the isolation layer 104 on the sacrificial layer 103 are performed in turn. For example, the bottom layer of the stack structure 111 is a layer of the sacrificial layer 103, and the top layer is a layer of the isolation layer 104. The bottom layer of the stack structure 111 and the semiconductor substrate 100 further form the buffer oxide layer 101.

[0045] In an embodiment, the stack structure 111 and the semiconductor substrate 100 further form the buffer oxide layer 101.

[0046] The number of layers of the stack structure 111 (the number of double-layer stack structures of the sacrificial layer 103 and the isolation layer 104 in the stack structure 111) is determined according to the number of the storage units to be formed in the vertical direction. The number of layers of the stack structure 111 can be 8, 32, 64, etc. The more the number of layers of the stack structure 111, the higher the integration. In the embodiment, only the number of layers of the stack structure 111 being 6 is taken as an example for description.

[0047] The materials of the sacrificial layer 103 and the isolation layer 104 are different. When the sacrificial layer 103 is removed subsequently, the sacrificial layer 103 has a high etching selectivity with respect to the isolation layer 104, so that the etching amount of the isolation layer 104 is small or negligible when the sacrificial layer 103 is removed, thereby ensuring the flatness of the isolation layer 104.

[0048] The material of the isolation layer 104 can be one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon nitride, and the material of the sacrificial layer 103 can be one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, amorphous silicon, amorphous carbon, and polycrystalline silicon. In the embodiment, the material of the isolation layer 104 is silicon oxide, and the material of the sacrificial layer 103 is silicon nitride. The isolation layer 104 and the sacrificial layer 103 are formed by a chemical vapor deposition process.

[0049] In an embodiment, the bottom layer of the sacrificial layer 103 in the stack structure 111 can be used as a bottom selective gate sacrificial layer. Subsequently, a bottom selective gate (BSG) can be formed at the position where the bottom selective gate sacrificial layer is removed. The top layer of the sacrificial layer 103 in the stack structure 111 can be used as a top selective gate sacrificial layer. Subsequently, a top selective gate (TSG) can be formed at the position where the top selective gate sacrificial layer is removed.

[0050] In an embodiment, one end of the stack structure 111 has a stepped structure 11, which includes several steps gradually raised in a stepped manner.

[0051] The top surface of the dielectric layer 105 is higher than the top surface of the stack structure 111, and the material of the dielectric layer 105 is silicon oxide. For example, the forming process of the dielectric layer 105 can be plasma enhanced chemical vapor deposition, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, high density plasma chemical vapor deposition, or atomic layer chemical vapor deposition.

[0052] In an embodiment, after forming the channel through holes in the dielectric layer 105 and the stack structure 111, the semiconductor substrate 100 exposed at the bottom of the channel through holes is etched to form a recess in the semiconductor substrate 100. A semiconductor epitaxial layer is formed in the recess by selective epitaxy, for example, the surface of the semiconductor epitaxial layer is lower than the surface of the bottommost isolation layer 104 and higher than the surface of the semiconductor substrate 100. The material of the semiconductor epitaxial layer is silicon, germanium, or silicon germanium. The storage structure 108 is formed on the semiconductor epitaxial layer, and the surface of the storage structure 108 is lower than the surface of the dielectric layer 105. A polysilicon layer 109 is formed on the storage structure 108 to fill the remaining channel through holes, for example, the surface of the polysilicon layer 109 is flush with the surface of the dielectric layer 105. The channel structure is arranged in each channel through hole, and the channel through hole and the channel structure form a channel hole. Here, the storage structure 108 is the channel structure.

[0053] The storage structure 108 includes a charge storage layer 107 on the sidewall surface of the channel through hole and a channel layer 106 on the surface of the charge storage layer 107. In some embodiments, the charge storage layer 107 can be a charge storage functional layer, which includes a charge blocking layer, a charge trapping layer, and a tunneling layer stacked. The forming method of the charge storage functional layer includes: forming a charge blocking layer on the sidewall surface of the channel through hole; forming a charge trapping layer on the surface of the charge blocking layer; and forming a tunneling layer on the surface of the charge trapping layer. The materials of the charge blocking layer and the tunneling layer can be the same, for example, the materials of the charge blocking layer and the tunneling layer are silicon oxide layers, and the material of the charge trapping layer is a silicon nitride layer.

[0054] In an embodiment, the charge storage layer 107 includes a blocking layer on the sidewall surface of the channel through hole, a charge trapping layer on the sidewall surface of the blocking layer, and a tunneling layer on the sidewall surface of the charge trapping layer. The materials of the blocking layer and the tunneling layer are silicon oxide, the material of the charge trapping layer is silicon nitride, and the material of the channel layer 106 is polysilicon.

[0055] Reference Figure 3etching back the polysilicon layer 109 so that the surface of the remaining polysilicon layer 109 is lower than the surface of the dielectric layer 105.

[0056] The etching back of the polysilicon layer can be performed by a wet etching process or an isotropic plasma etching process. In some embodiments, the polysilicon layer can be etched back by an etching process so that the surface of the remaining polysilicon layer 109 is lower than the surface of the dielectric layer 105, thereby forming a recess at the polysilicon layer of the channel via. During the etching back of the polysilicon layer, the etching material selected has a higher etching rate for the polysilicon layer than for the dielectric layer 105. In this case, the dielectric layer 105 and the charge storage functional layer (tunneling layer) of the channel structure can act as an etching stop layer for etching the polysilicon layer, thereby eliminating the need for an additional mask layer for etching the polysilicon layer. This can reduce the number of mask plates required for the process. The first metal silicide layer and the via contact metal layer can then be formed in the recess. Here, the via contact metal layer can be a bit line contact plug.

[0057] The etching back of the polysilicon layer 109 can be performed at a location for subsequent formation of the first metal silicide layer and the via contact metal layer on the first metal silicide layer. In embodiments of the present disclosure, the first metal silicide layer and the via contact metal layer (bit line contact plug) are formed in the channel via. For example, the diameter of the via contact metal layer is equal to the diameter of the polysilicon layer 109. For example, the diameter of the via contact metal layer is equal to the diameter of the first metal silicide layer.

[0058] Referring to Figure 4 and Figure 5 , the first metal silicide layer 112 (see Figure 4 ) and the via contact metal layer 113 (see Figure 5 ) are formed on the surface of the polysilicon layer 109.

[0059] In an embodiment, the first metal silicide layer 112 and the via contact metal layer 113 are formed by: forming a first metal layer (not shown in the figures) on the surface of the dielectric layer 105 and in the channel via on the polysilicon layer 109; annealing the first metal layer so that the first metal layer reacts with part of the polysilicon layer 109 on the storage structure, thereby forming the first metal silicide layer 112 on the surface of the polysilicon layer 109, and the surface of the first metal silicide layer 112 is lower than the top surface of the dielectric layer 105; and removing the unreacted first metal layer, thereby forming the via contact metal layer 113 on the surface of the first metal silicide layer 112, and the surface of the via contact metal layer 113 is flush with the top surface of the dielectric layer 105. In some embodiments, the material of the via contact metal layer is different from the material of the first metal layer.

[0060] The material of the first metal layer is one or more of nickel, cobalt, tantalum, and titanium. The first metal layer is formed by sputtering, and the thickness of the first metal layer is less than the radius of the channel via.

[0061] The annealing includes a first annealing and a second annealing, and the temperature of the second annealing is higher than that of the first annealing. In an embodiment, the first annealing is dip annealing, the annealing temperature is 220-320 degrees Celsius, the annealing time is 30-90 seconds, and the second annealing is millisecond annealing, the annealing temperature is 700-950 degrees Celsius, and the annealing time is 0.25-20 milliseconds.

[0062] The removing of the unreacted first metal layer can be performed by a wet etching process.

[0063] The material of the formed first metal silicide layer 112 is one or a combination of nickel silicide, cobalt silicide, tantalum silicide, and titanium silicide. In some embodiments of the present disclosure, the step of forming the first metal silicide layer 112 is not performed in the same step as the step of subsequently forming the second metal silicide, so that the thickness of the first metal silicide layer 112 can be adjusted by adjusting the thickness of the first metal layer alone, so that the thickness of the first metal silicide layer is not limited by the process of forming the second metal silicide layer, and the thickness of the formed first metal silicide layer 112 meets the performance requirements. In an embodiment, the thickness of the first metal layer is 7-50 nm, and the thickness of the first metal silicide layer 112 is 7-50 nm.

[0064] For example, the process of forming the via contact metal layer 113 includes: forming a metal layer on the dielectric layer 105 and the first metal silicide layer 112; and planarizing to remove the metal layer above the surface of the dielectric layer 105, and forming the via contact metal layer 113 on the first metal silicide layer 112. The via contact metal layer 113 is subsequently used to connect with the bit line, and when the second metal silicide layer is subsequently formed, the second metal layer can be isolated from the first metal silicide layer 112, so that the thickness of the formed first metal silicide layer 112 is prevented from changing, and the via contact metal layer 113 can also be used as an etching stop layer when a third via is subsequently formed in the hard mask layer. In some embodiments, the via contact metal layer 113 is a bit line contact plug. The subsequently formed bit line connection structure is in conductive contact with the first metal silicide layer through the bit line contact plug. In the embodiments of the present disclosure, the bit line contact plug is formed in the channel via, and there is no need to use an additional mask layer to form the bit line contact plug.

[0065] For example, the material of the via contact metal layer 113 can be tungsten.

[0066] ReferenceFigure 6 The sacrificial layer is replaced by a control gate structure 123.

[0067] In one embodiment, the control gate structure 123 is formed by forming a hard mask layer 114 on the stack structure 111, forming a gate trench 115 in the hard mask layer 114 and the stack structure 111, removing the sacrificial layer along the gate trench 115, and forming a control gate structure 113 at the location where the sacrificial layer is removed.

[0068] In some examples, after the gate trench 115 is formed, the method further includes removing the hard mask layer 114 and forming a second dielectric layer on the dielectric layer 105. For example, the second dielectric layer is located at the same location as the hard mask layer 114 in Figures 6-10 In view of the fact that the second dielectric layer is located at the same location as the hard mask layer 114 in Figures 6-10 In view of the fact that the second dielectric layer is located at the same location as the hard mask layer 114 in Figures 6-10 In view of the fact that the second dielectric layer is located at the same location as the hard mask layer 114 in

[0069] For example, the hard mask layer 114 can be a single layer or a multi-layer stack structure. For example, the material of the hard mask layer 114 is one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0070] The removal of the sacrificial layer employs a wet etching process. In one embodiment, the bottommost layer of the sacrificial layer (bottom selective gate sacrificial layer) in the stack structure is removed to form a bottom selective gate (BSG) 122 at the corresponding location, and the topmost layer of the sacrificial layer (top selective gate sacrificial layer) in the stack structure is removed to form a top selective gate (TSG) 124 at the corresponding location. The bottom selective gate sacrificial layer and the top selective gate sacrificial layer are removed at the same time as the other sacrificial layers, and the bottom selective gate 122 and the top selective gate 124 are formed at the same time as the control gate structure 133.

[0071] The control gate structure 103 includes a gate dielectric layer and a gate electrode on the gate dielectric layer. In an embodiment, the control gate structure 103 can be a high-K dielectric layer and a metal gate on the surface of the high-K dielectric layer, and the material of the metal gate can be one or more of W, Al, Cu, Ti, Ag, Au, Pt, Ni. The material of the high-K dielectric layer can be HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO. In other embodiments, the control gate structure 103 can include a silicon oxide dielectric layer and a polysilicon gate on the dielectric layer.

[0072] Referring to Figure 7 , the array common source 116 is formed in the gate line slite 115 (refer to Figure 6 ).

[0073] Before the array common source 116 is formed, an isolation side wall is formed on the sidewall of the gate line slite 115. The isolation side wall includes an electrically isolated layer (e.g., a dielectric layer) deposited on the sidewall of the gate line slite 115. For example, the array common source 116 includes a conductive layer of a conductive material such as titanium nitride, W, Co, Cu, Al, doped silicon, or silicide, and the electrically isolated layer can be a layer of an insulating material such as a silicon oxide layer.

[0074] In some embodiments of the present disclosure, the surface of the array common source 116 is lower than the surface of the hard mask layer 114, and the material of the array common source 116 is a polysilicon layer.

[0075] Referring to Figure 8 , a patterned photoresist layer 130 is formed on the hard mask layer 114; the hard mask layer 114 and the dielectric layer 105 are etched with the patterned photoresist layer 130 as a mask, to form a first via 117 exposing part of the surface of the well region 110 on one side of the stack structure 111, a plurality of second vias 118 exposing the surface of the corresponding step structure 11, and a third via 119 exposing part of the surface of the via contact metal layer 113 in the hard mask layer 114, the size of the third via 119 being smaller than the size of the via contact metal layer 113.

[0076] The first contact plug connected with the well region 110 is formed in the first via hole 117, the second contact plug connected with the step structure 11 is formed in the second via hole 118, and the bit line contact structure is formed in the third via hole 119 and connected with the via contact metal layer 113. The thickness of the via contact metal layer (bit line contact plug) is less than the thickness of the bit line contact structure.

[0077] The size of the third via hole 119 is less than the size of the via contact metal layer 113 (or the channel via hole), and the diameter of the corresponding subsequently formed bit line contact structure is less than the diameter of the via contact metal layer 113 (or the channel via hole), so that the diameter of the formed bit line contact structure can be smaller. In an embodiment, the diameter of the third via hole 119 can be 1 / 4-2 / 3 of the diameter of the via contact metal layer 113 (or the channel via hole).

[0078] For example, the etching of the hard mask layer 114 and the dielectric layer 105 can adopt an anisotropic dry etching process, such as an anisotropic plasma etching process. Here, the materials of the hard mask layer and the dielectric layer are the same.

[0079] In some embodiments of the present disclosure, since the first metal silicide layer 112 is formed first and the second metal silicide layer is formed later, the thickness of the first metal silicide layer 112 can be controlled independently to meet the performance requirements. For example, when forming the first metal silicide layer 112, there is no need to form a mask layer (the position of the first metal silicide layer 112 is directly defined by the channel via hole), and the formation of the second metal silicide layer as well as the first contact plug, the second contact plug and the bit line contact structure only needs to form a photoetch process once, and through one photoetch process, a bit line contact structure with a smaller diameter can be formed, thereby saving costs.

[0080] In some embodiments of the present disclosure, since the first metal silicide layer 112 is formed first and the second metal silicide layer is formed later, the thickness of the first metal silicide layer 112 can be controlled independently. For example, the thickness of the first metal silicide layer and the thickness of the second metal silicide layer can also be made consistent.

[0081] In some embodiments of the present disclosure, since the first metal silicide layer 112 is formed first and the second metal silicide layer is formed later, not only can the thickness of the first metal silicide layer 112 be controlled individually to meet performance requirements, but also when the first via hole 117 and the third via hole 119 are formed through the hard mask layer 114, since the first metal silicide layer 112 has already been formed, the size of the third via hole 119 will not affect the size of the first metal silicide layer, so that the size of the third via hole 119 can be set to be smaller than the size of the via contact metal layer 113 (or the channel via hole) at this time, and thus the bit line connection structure with a size smaller than the via contact metal layer 113 (or the channel via hole) can be formed through the hard mask layer 114 of the second metal silicide layer. Therefore, the first contact plug, the second contact plug and the bit line connection structure are formed only once through the formation of the second metal silicide layer and a photoetching process, and the bit line with a smaller size can be formed through the photoetching process once, thereby saving costs.

[0082] In the method of forming the first metal silicide layer and the second metal silicide layer in the same process step in the related art, a photoetching process is used when the first metal silicide layer and the second metal silicide layer are formed, and only the bit line contact plug can be formed in the photoetching process, and a photoetching process is further needed to form the bit line connection structure with a size smaller than the bit line contact plug. In the embodiments of the present disclosure, since the first metal silicide layer and the bit line contact plug in contact with the first metal silicide layer have been formed before the photoetching process of the second metal silicide layer, the third via hole 119 with a size smaller than the first metal silicide layer or the bit line contact plug can be formed in the photoetching process of the second metal silicide layer, and the bit line connection structure can be formed through the third via hole 119. In other words, compared with the related art, the first metal silicide layer and the via contact metal layer (i.e. the bit line contact plug) can be formed only through the Recess process in the embodiments of the present disclosure, without using a mask layer, and the bit line connection structure can be formed only through a photoetching process once.

[0083] Reference Figure 9 The second metal silicide layer 120 is formed on the surface of the well region at the bottom of the first via hole 117.

[0084] In an embodiment, the process of forming the second metal silicide layer 120 includes: forming a second metal layer in the first via hole 117 and on the surface of the hard mask layer 105; performing annealing to make the second metal layer react with silicon in the well region to form the second metal silicide layer 120 on the surface of the well region; and removing the unreacted second metal layer. It should be noted that when the second metal layer is deposited in the first via hole 117, the second metal layer is also present on the surface of the hard mask layer 105.

[0085] The material of the second metal layer is one or more of nickel, cobalt, tantalum, and titanium. The forming process of the second metal layer is sputtering.

[0086] The annealing includes a first annealing and a second annealing, the second annealing is performed at a higher temperature than the first annealing. In one embodiment, the first annealing is dip annealing, the annealing temperature is 220-320 degrees Celsius, the annealing time is 30-90 seconds, and the second annealing is millisecond annealing, the annealing temperature is 700-950 degrees Celsius, and the annealing time is 0.25-20 milliseconds.

[0087] The removing of the unreacted second metal layer can be performed by a wet etching process.

[0088] The material of the formed second metal silicide layer 112 is one or a combination of nickel silicide, cobalt silicide, tantalum silicide, and titanium silicide.

[0089] Reference Figure 10 A first contact plug 125 connected with the second metal silicide layer 120 is formed in the first via, a second contact plug 126 connected with the surface of the corresponding step structure 11 is formed in the second via, and a bit line contact 127 connected with the via contact metal layer 113 is formed in the third via.

[0090] The first contact plug 125, the second contact plug 126, and the bit line contact 127 are formed in the same step. Before the formation of the first contact plug 125, the second contact plug 126, and the bit line contact 127, the patterned photoresist layer 130 is removed to expose the remaining gate trench on the array common source 116. The fourth contact plug 128 is formed in the remaining gate trench on the array common source 116 at the same time when the first contact plug 125, the second contact plug 126, and the bit line contact 127 are formed. The fourth contact plug can be used to electrically lead out the array common source, and thus the fourth contact plug can be referred to as a source contact plug.

[0091] In some embodiments, the first contact plug 125, the second contact plug 126, the bit line connection structure 127 and the fourth contact plug 128 are formed by: forming a metal layer filling the first via hole, the second via hole, the third via hole, the remaining gate isolation groove on the array common source 116 and covering the surface of the hard mask layer 114, the material of the metal layer can be tungsten; a planarization process (such as a chemical mechanical polishing process) is used to remove the metal layer above the surface of the hard mask layer 114, thereby forming the first contact plug 125 in the first via hole, the second contact plug 126 in the second via hole, the bit line connection structure 127 in the third via hole, and the fourth contact plug 128 in the remaining gate isolation groove on the array common source 116.

[0092] For example, compared with the method in the related art in which the first metal silicide layer and the second metal silicide layer are formed in the same process step, in the method for forming the 3D NAND memory provided in the present disclosure, the first metal silicide layer 112 is formed before the formation of the first via hole 117 and the third via hole 119, so that the diameter of the third via hole (bit line connection structure) can be controlled through the photolithography process for forming the first via hole. With the increasing integration of memory, the size of the memory cell becomes smaller and smaller, and the diameter of the bit line connection structure can be controlled through the method provided in the embodiments of the present disclosure, in other words, the diameter of the bit line connection structure can be freely controlled through the method provided in the embodiments of the present disclosure, so that the diameter of the bit line connection structure can adapt to the smaller and smaller memory cell.

[0093] Further, compared with the related art in which two photolithography processes are required, i.e., a mask layer and a second dielectric layer are formed to form the bit line contact plug (located in the mask layer) and the bit line connection structure (located in the second dielectric layer), in the present disclosure, only one photolithography process is required, i.e., only a hard mask layer is formed to form the bit line contact plug (located in the channel via hole) and the bit line connection structure (located in the hard mask layer or the second dielectric layer). Therefore, the longitudinal height of the 3D NAND memory finally formed in the related art (refer to Figure 1D ) is greater than the longitudinal height of the 3D NAND memory finally formed in the present disclosure (refer to Figure 10 ). In other words, through the method for forming the 3D NAND memory provided in the present disclosure, the longitudinal size of the device can be reduced.

[0094] The embodiment of the present disclosure further provides a memory, comprising: a semiconductor layer, a stack structure located on the semiconductor layer, and a medium layer covering the semiconductor layer and the stack structure; a channel hole penetrating through the stack structure, the channel hole comprising a channel structure, a polysilicon layer, a first metal silicide layer, and a via contact metal layer located on the first metal silicide layer; a second metal silicide layer and a first contact plug formed in the medium layer, the second metal silicide layer being located on the semiconductor layer, and the first contact plug being located on the second metal silicide layer; wherein the via contact metal layer is a bit line contact plug.

[0095] In some embodiments, the diameter of the via contact metal layer is equal to the diameter of the polysilicon layer.

[0096] In some embodiments, further comprising: a second medium layer located on the medium layer; a bit line connection structure located in the second medium layer, the bit line connection structure being located on the via contact metal layer; and the diameter of the bit line connection structure is smaller than the diameter of the channel hole.

[0097] In some embodiments, the thickness of the via contact metal layer is smaller than the thickness of the bit line connection structure.

[0098] In some embodiments, the diameter of the bit line connection structure is smaller than the diameter of the first contact plug.

[0099] In some embodiments, the end of the stack structure has a step structure; further comprising: a second contact plug located in the medium layer, the second contact plug being connected with a corresponding step structure surface; and the diameter of the second contact plug is greater than the diameter of the bit line connection structure.

[0100] In some embodiments, further comprising: an array common source located in the stack structure and a fourth contact plug, the array common source being located on the semiconductor layer, and the fourth contact plug being located on the array common source.

[0101] The embodiment of the present disclosure further provides a memory system, comprising: the memory as described above; and a memory controller coupled with the memory.

[0102] In some embodiments, the memory can be a 3D NAND memory.

[0103] Specifically, the storage system can be an electronic computer, a smart phone, a smart television, a smart set-top box, a smart router, an electronic digital camera, an SSD, etc. with a memory. The storage system of the present disclosure usually also includes a controller, an input / output device, a display device, etc. The memory is used to store files or data and is called by the controller. Specifically, the storage controller can write data into the memory, i.e. the memory provided by the present disclosure, and also can read data from the memory, i.e. the memory provided by the present disclosure. The input / output device is used to input instructions or output signals, and the display device visualizes the signals to realize various functions of the storage system.

[0104] It should be noted that the above description of the memory and the storage system is similar to the description of the above-mentioned 3D NAND memory formation method embodiment, has similar beneficial effects as the 3D NAND memory formation method embodiment, and therefore is not described in detail. For technical details not disclosed in the memory and the storage system of the present embodiment, please refer to the description of the 3D NAND memory formation method in the present embodiment.

[0105] The above is only the preferred embodiment of the present disclosure, and it should be noted that those skilled in the art can make several improvements and refinements without departing from the principles of the present disclosure, and these improvements and refinements should also be considered within the protection scope of the present disclosure.

Claims

1. A method for forming a 3D NAND memory, wherein, include: A semiconductor structure is provided, the semiconductor structure comprising a semiconductor substrate, a stacked structure located on the semiconductor substrate, and a dielectric layer covering the semiconductor substrate and the stacked structure; A plurality of through-holes penetrating the stacked structure are formed in the dielectric layer and the stacked structure; A channel structure is formed within the channel via, and a polysilicon layer, a first metal silicide layer on the polysilicon layer, and a via contact metal layer on the first metal silicide layer are sequentially formed within the channel via and on the channel structure. After forming the first metal silicide layer, a first via is formed in the dielectric layer to expose the semiconductor substrate; A second metal silicide layer is formed at the bottom of the first through hole, and a first contact plug connected to the second metal silicide layer is formed in the first through hole.

2. The method for forming a 3D NAND memory as described in claim 1, wherein, The formation process of the first metal silicide layer and the via contact metal layer is as follows: a first metal layer is formed on the surface of the dielectric layer and in the via on the polysilicon layer; the first metal layer is annealed to react with a portion of the polysilicon layer on the channel structure, forming a first metal silicide layer on the surface of the polysilicon layer, wherein the surface of the first metal silicide layer is lower than the top surface of the dielectric layer; the unreacted first metal layer is removed, and a via contact metal layer is formed on the surface of the first metal silicide layer, wherein the surface of the via contact metal layer is flush with the top surface of the dielectric layer.

3. The method for forming a 3D NAND memory as described in claim 2, wherein, The material of the first metal silicide layer is one or a combination of nickel silicide, cobalt silicide, tantalum silicide, and titanium silicide.

4. The method for forming a 3D NAND memory as described in any one of claims 1 to 3, wherein, The stacked structure includes alternating layers of sacrificial layers and isolation layers; After forming the via contact metal layer, the method further includes: replacing the sacrificial layer with a control gate structure.

5. The method for forming a 3D NAND memory as described in claim 4, wherein, The process of forming the control gate structure is as follows: forming a hard mask layer on the stacked structure; forming a gate slot in the hard mask layer and the stacked structure; The sacrificial layer is removed along the gate trench; A control gate structure is formed at the location where the sacrificial layer is removed; An array of common sources is formed in the gate spacer.

6. The method for forming a 3D NAND memory as described in claim 5, wherein, The material of the hard mask layer is the same as the material of the dielectric layer.

7. The method for forming a 3D NAND memory as described in claim 5, wherein, Also includes: A bitline connection structure is formed in the hard mask layer to connect with the via contact metal layer, and the size of the bitline connection structure is smaller than the size of the via contact metal layer.

8. The method for forming a 3D NAND memory as described in claim 7, wherein, The stacked structure has a stepped structure at its ends; While forming the first through hole in the dielectric layer, the method also includes forming a plurality of second through holes in the dielectric layer that expose the corresponding stepped structure surface.

9. The method for forming a 3D NAND memory as described in claim 8, wherein, Also includes: A second contact plug is formed in the second through hole to connect with the corresponding stepped structure surface.

10. The method for forming a 3D NAND memory as described in claim 9, wherein, The formation process of the second metal silicide layer, the first contact plug, the second contact plug, and the bit line connection structure includes: etching the hard mask layer and the dielectric layer; forming a first via on the semiconductor substrate exposing one side of the stacked structure and a plurality of second vias exposing the corresponding stepped structure surfaces in the hard mask layer and the dielectric layer; forming a third via on the hard mask layer exposing a portion of the via contact metal layer surface, wherein the size of the third via is smaller than the size of the channel via; forming a second metal layer in the first via and on the surface of the hard mask layer; annealing to react the second metal layer with silicon in the semiconductor substrate to form a second metal silicide layer on the surface of the semiconductor substrate; removing the unreacted second metal layer; filling the first via, the second via, and the third via with metal layers; forming a first contact plug connected to the second metal silicide layer in the first via; forming a second contact plug connected to the corresponding stepped structure surface in the second via; and forming a bit line connection structure connected to the via contact metal layer in the third via.

11. The method for forming a 3D NAND memory as described in claim 7, wherein, The second metal silicide layer material is one or a combination of nickel silicide, cobalt silicide, tantalum silicide, and titanium silicide.

12. The method of forming a 3D NAND memory as described in any one of claims 1 to 11, wherein, The channel structure includes a charge storage layer on the sidewall surface of the channel via and a channel layer on the sidewall surface of the charge storage layer; and / or, the charge storage layer includes a barrier layer on the sidewall surface of the channel via, a charge trapping layer on the sidewall surface of the barrier layer and a tunneling layer on the sidewall surface of the charge trapping layer. And / or, the control gate structure includes a gate dielectric layer and a gate electrode located on the gate dielectric layer; and / or, the via contact metal layer is a bit line contact plug.

13. The method for forming a 3D NAND memory as described in claim 1, wherein, The first contact plug does not overlap with the orthographic projection of the stacked structure onto the semiconductor substrate.

14. A memory, wherein, include: A semiconductor layer, a stacked structure on the semiconductor layer, and a dielectric layer covering the semiconductor layer and the stacked structure; A channel hole is formed through the stacked structure, the channel hole including a channel structure, a polysilicon layer, a first metal silicide layer and a via contact metal layer located on the first metal silicide layer; A second metal silicide layer and a first contact plug are formed within the dielectric layer, wherein the second metal silicide layer is located on the semiconductor layer and the first contact plug is located on the second metal silicide layer; The through-hole contact metal layer is a bit line contact plug.

15. The memory of claim 14, wherein, The diameter of the through-hole contact metal layer is equal to the diameter of the polycrystalline silicon layer.

16. The memory of claim 15, wherein, It also includes: a second dielectric layer located on the dielectric layer; a bit line connection structure located within the second dielectric layer, the bit line connection structure being located on the via contact metal layer; the diameter of the bit line connection structure being smaller than the diameter of the channel via.

17. The memory of claim 16, wherein, The thickness of the through-hole contact metal layer is less than the thickness of the bit line connection structure.

18. The memory of claim 16, wherein, The diameter of the bit line connection structure is smaller than the diameter of the first contact plug.

19. The memory of claim 16, wherein, The stacked structure has a stepped structure at its end; it also includes a second contact plug located within the dielectric layer, the second contact plug being connected to the corresponding stepped structure surface; the diameter of the second contact plug is larger than the diameter of the bit line connection structure.

20. The memory of claim 19, wherein, It also includes: an array common source electrode and a fourth contact plug located in the stacked structure, wherein the array common source electrode is located on the semiconductor layer and the fourth contact plug is located on the array common source electrode.

21. A storage system, comprising: One or more memories as described in any one of claims 14 to 20; And a storage controller, which is coupled to the memory.

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