Error cleaning method, device and computer equipment applicable to heterogeneous redundancy

Abstract

The present application relates to an error cleaning method, device, computer device, storage medium, and computer program product applicable to heterogeneous redundancy. The method includes: obtaining the register bank of each central processing unit among a plurality of central processing units, where each central processing unit adopts a different instruction set architecture; obtaining a preset program and its corresponding assembly file; the assembly file includes the operation processes of each central processing unit on its own registers; determining the first central processing unit that runs into an error; determining the corresponding assembly sub-file of the second central processing unit that runs correctly from the assembly file; obtaining the correspondence between the register bank of the second central processing unit and the register bank of the first central processing unit, and obtaining the reference value of each register in the first central processing unit after executing the preset program according to the assembly sub-file and the correspondence; updating the values of the registers in the first central processing unit based on the reference values. This method can improve the error cleaning efficiency and accuracy of the heterogeneous redundancy system.

Description

Technical Field

[0001] This application relates to the technical field of data cleaning, and particularly to an error cleaning method, device, computer device, storage medium, and computer program product applicable to heterogeneous redundancy. Background Art

[0002] A heterogeneous redundancy system mainly consists of components such as a heterogeneous CPU (Central Processing Unit) system, a mimicry scheduling unit, a bus, and peripherals. Among them, the heterogeneous CPU system is generally composed of CPUs with three different instruction set architectures. When the mimicry scheduler adjudicates the output results of the heterogeneous CPUs and finds that the three are inconsistent, it is necessary to identify the faulty CPU and perform error cleaning on it.

[0003] In traditional technologies, for a mimicry system composed of heterogeneous CPUs, checkpoints are usually inserted into the software program. When the program executes to each checkpoint, the outputs of each CPU are judged. When it is found that a CPU is running incorrectly, the cleaning function is completed by loading the register information from the previous checkpoint of the CPU, and the program from the previous checkpoint to this checkpoint needs to be re-executed.

[0004] However, the number of checkpoints inserted in the software is limited. Assuming that the time interval between each checkpoint is T, then after cleaning, the CPU needs to re-execute all the instructions before the cycle T, which has a greater impact on the cleaning and running efficiency of the system. Summary of the Invention

[0005] Based on this, it is necessary to provide an error cleaning method, device, computer device, computer-readable storage medium, and computer program product applicable to heterogeneous redundancy for the above technical problems.

[0006] In a first aspect, this application provides an error cleaning method applicable to heterogeneous redundancy. The method includes:

[0007] Obtain the register bank of each central processing unit among multiple central processing units, and each central processing unit adopts a different instruction set architecture;

[0008] Obtain a preset program and the assembly file corresponding to the preset program; the assembly file includes different operation processes of central processing units with different instruction set architectures on their own registers;

[0009] Determine a first central processing unit that runs incorrectly from among the multiple central processing units;

[0010] Determine the assembly sub-file corresponding to a second central processing unit that runs correctly from the assembly file;

[0011] Obtain the correspondence between the register bank of the second central processing unit and the register bank of the first central processing unit, and obtain the reference value of each register participating in the execution of the preset program in the first central processing unit after the execution of the preset program according to the assembly sub-file and the correspondence;

[0012] Update the values in the registers of the first central processing unit based on the reference values.

[0013] In one embodiment, updating the values in the registers of the first central processing unit based on the reference values includes:

[0014] Obtain the initial values of multiple registers of the first central processing unit before the execution of the preset program;

[0015] Determine the types of each register in the first central processing unit based on the initial values and reference values of the registers;

[0016] Update the values of the registers based on the types of the registers and the reference values.

[0017] In one embodiment, determining the types of each register in the first central processing unit based on the initial values and reference values of the registers includes:

[0018] When the initial value of the register is the same as the reference value, the register is a first type of register;

[0019] When the initial value of the register is different from the reference value, the register is a second type of register.

[0020] In one embodiment, updating the values of the registers based on the types of the registers and the reference values includes:

[0021] When the register is a first type of register, load according to the initial value of the register;

[0022] When the register is a second type of register, use the reference value as the value of the register.

[0023] In one embodiment, when the register is a second type of register, it further includes:

[0024] When the second type of register calls a subroutine in the preset program through an instruction, the hardware automatically saves the subroutine return address in a preset cache register.

[0025] In one embodiment, after updating the values in the registers of the first central processing unit based on the reference values, it further includes:

[0026] Obtain the subroutine return address in the preset cache register, and continue to execute the preset program based on the subroutine return address.

[0027] Second aspect, the present application also provides an error cleaning device applicable to heterogeneous redundancy. The device includes:

[0028] A register bank acquisition module, configured to acquire the register bank of each central processing unit among multiple central processing units, and each central processing unit adopts a different instruction set architecture;

[0029] An assembly file acquisition module, configured to acquire a preset program and an assembly file corresponding to the preset program; the assembly file includes different operation processes of central processing units with different instruction set architectures on their own registers;

[0030] An error central processing unit determination module, configured to determine a first central processing unit that runs with errors from among multiple central processing units;

[0031] An assembly sub-file acquisition module, configured to determine an assembly sub-file corresponding to a second central processing unit that runs correctly from the assembly file;

[0032] A reference value acquisition module, configured to obtain the correspondence between the register bank of the second central processing unit and the register bank of the first central processing unit, and obtain the reference value of each register participating in the execution of the preset program in the first central processing unit after the execution of the preset program according to the assembly sub-file and the correspondence;

[0033] An update module, configured to update the values in the registers of the first central processing unit based on the reference values.

[0034] Third aspect, the present application also provides a computer device. The computer device includes a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, the steps of the method described in any one of the above embodiments are implemented.

[0035] Fourth aspect, the present application also provides a computer-readable storage medium for a computer device. The computer-readable storage medium for a computer device stores a computer program, and when the computer program is executed by a processor, the steps of the method described in any one of the above embodiments are implemented.

[0036] Fifth aspect, the present application also provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the steps of the method described in any one of the above embodiments are implemented.

[0037] The above error cleaning method, device, computer device, storage medium and computer program product applicable to heterogeneous redundancy first obtains the register banks of each central processing unit among multiple central processing units, and each central processing unit adopts a different instruction set architecture; then obtains a preset program and the corresponding assembly file; the assembly file includes the different operation processes of the central processing units with different instruction set architectures on their own registers. Then, a first central processing unit that runs into an error is determined from the multiple central processing units; an assembly sub-file corresponding to a second central processing unit that runs correctly is determined from the assembly file, and the values of the registers in the second central processing unit that runs correctly can be obtained. Further, the correspondence relationship between the register bank of the second central processing unit and the register bank of the first central processing unit is obtained, and based on the assembly sub-file and the correspondence relationship, the reference values of each register in the first central processing unit that participates in executing the preset program after executing the preset program are obtained, and then the values in the registers of the first central processing unit are updated based on the reference values. Obtaining the reference values of the registers of the first central processing unit based on the values of the registers of the second central processing unit that runs correctly can enable the first central processing unit to continue executing subsequent programs after the register values are updated, without the need to re-execute all programs, and can improve the update efficiency and accuracy of the register values of the first central processing unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 FIG. is an application environment diagram of an error cleaning method applicable to heterogeneous redundancy in an embodiment;

[0039] Figure 2 FIG. is a flowchart of an error cleaning method applicable to heterogeneous redundancy in an embodiment;

[0040] Figure 3 FIG. is a schematic diagram of a preset program in an embodiment;

[0041] Figure 4 FIG. is a structural block diagram of an error cleaning device applicable to heterogeneous redundancy in an embodiment;

[0042] Figure 5 FIG. is an internal structure diagram of a computer device in an embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0044] The error cleaning method applicable to heterogeneous redundancy provided by the embodiments of the present application can be implemented on the server or the terminal alone, or can be applied to a system including the terminal and the server, and is implemented through the interaction between the terminal and the server.

[0045] The error cleaning method applicable to heterogeneous redundancy provided by the embodiments of the present application can be applied to an application environment as Figure 1 shown. Among them, the terminal 102 communicates with the server 104 through a network. The data storage system can store the data that the server 104 needs to process. The data storage system can be integrated on the server 104, or placed on the cloud or other network servers. The server 104 can provide an error cleaning environment for the terminal 102. The server 104 communicates and interacts with the terminal 102, so as to enter the error cleaning environment, obtain the register banks of each central processing unit among multiple central processing units, and each central processing unit adopts a different instruction set architecture. Then, the server 104 obtains a preset program and the assembly file corresponding to the preset program; the assembly file includes the different operation processes of the central processing units with different instruction set architectures on their own registers. Further, the server 104 determines a first central processing unit that runs into an error from multiple central processing units; determines an assembly sub-file corresponding to a second central processing unit that runs correctly from the assembly file; obtains the correspondence between the register bank of the second central processing unit and the register bank of the first central processing unit, and obtains the reference value of each register participating in the execution of the preset program in the first central processing unit after the execution of the preset program according to the assembly sub-file and the correspondence. Finally, the server 104 updates the values in the registers of the first central processing unit based on the reference values.

[0046] The heterogeneous redundancy system mainly consists of components such as a heterogeneous CPU system, a mimicry scheduling unit, a bus, and peripherals. Among them, the system of the terminal 102 is equivalent to the peripheral of the heterogeneous redundancy system, and the server 104 is equivalent to the heterogeneous CPU system.

[0047] In one embodiment, as Figure 2 shown, an error cleaning method applicable to heterogeneous redundancy is provided. Taking the implementation of this method on the server side as an example, it includes the following steps 202 to step 212.

[0048] Step 202, obtain the register bank of each central processing unit among multiple central processing units, and each central processing unit adopts a different instruction set architecture.

[0049] In this embodiment, the heterogeneous CPU system can be composed of CPUs with three different instruction set architectures.

[0050] In this embodiment, the register bank of the central processing unit is an array composed of multiple registers in the central processing unit, and is usually implemented by a fast static random access memory (SRAM). This kind of RAM has dedicated read ports and write ports, and can access different registers in multiple paths concurrently.

[0051] Step 204: Obtain a preset program and the assembly file corresponding to the preset program; the assembly file includes the different operation processes of the central processing unit (CPU) with different instruction set architectures for its own registers.

[0052] In this embodiment, the assembly file includes multiple assembly sub-files, respectively corresponding to the different operation processes of the central processing unit with each instruction set architecture for its own registers.

[0053] In this embodiment, the server can respectively compile the preset program based on the compilation tools corresponding to each instruction set architecture to respectively obtain the assembly sub-files corresponding to each instruction set architecture.

[0054] Step 206: Determine, from multiple central processing units, a first central processing unit that runs with errors.

[0055] In this embodiment, the server makes a judgment on the output results of multiple central processing units through the mimicry scheduling unit. When the output results of multiple central processing units are inconsistent, the central processing unit with errors can be determined through the multi-mode judgment method. For example, when a heterogeneous CPU adopts three central processing units with different instruction set architectures and one of the results of the three central processing units is different from the other two, the central processing unit whose result is inconsistent with the results of the other central processing units can be determined as the first central processing unit that runs with errors.

[0056] In another embodiment, when a heterogeneous CPU adopts more than three central processing units with different instruction set architectures, the mode of the results of multiple central processing units can be used as the correct result, and the central processing unit whose result is different from the correct result among the results of multiple central processing units can be used as the first central processing unit that runs with errors.

[0057] Step 208: Determine, from the assembly file, the assembly sub-file corresponding to the second central processing unit that runs correctly.

[0058] In this embodiment, among the multiple central processing units of the heterogeneous CPU, the central processing units different from the first central processing unit are the central processing units that run correctly. The server can select one of the multiple central processing units that run correctly as the second central processing unit and query the assembly sub-file corresponding to the second central processing unit based on the assembly file.

[0059] Step 210: Obtain the corresponding relationship between the register bank of the second central processing unit and the register bank of the first central processing unit, and obtain the reference values of each register participating in the execution of the preset program in the first central processing unit after the execution of the preset program according to the assembly sub-file and the corresponding relationship.

[0060] In this embodiment, the preset program may include, but is not limited to: the entire main program, a subroutine in the main program.

[0061] In this embodiment, the server may obtain the values of each register involved in executing a preset program in the second central processing unit after the execution of the preset program based on the assembly sub-file corresponding to the second central processing unit. Further, the server may obtain the reference values of each register involved in executing the preset program in the first central processing unit after the execution of the preset program based on the correspondence between the register bank of the second central processing unit and the register bank of the first central processing unit, as well as the values of each register involved in executing the preset program in the second central processing unit after the execution of the preset program.

[0062] In this embodiment, the correspondence between the register bank of the second central processing unit and the register bank of the first central processing unit refers to the correspondence of the register values of the register bank of the first central processing unit and the register bank of the second central processing unit respectively after the execution of the same preset program. For example, after the execution of the same loop, the result after the loop is stored in register 1 in the first central processing unit, and the result after the loop is stored in register 2 in the second central processing unit. Then, the server may obtain the reference value of register 1 in the first central processing unit after the execution of the preset program based on the value of register 2 in the second central processing unit after the execution of the preset program.

[0063] Step 212: Update the values in the registers of the first central processing unit based on the reference values.

[0064] In this embodiment, the server may update the values of each register involved in executing the preset program in the first central processing unit based on the reference values, so that the values in the registers of the first central processing unit are updated to the values after the normal execution of the preset program, and the subsequent programs can be continued to be executed.

[0065] In the above error cleaning method applicable to heterogeneous redundancy, first, the register bank of each central processing unit (CPU) among multiple CPUs is obtained, and different instruction set architectures are adopted by each CPU; then, a preset program and the corresponding assembly file are obtained; the assembly file includes different operation processes of the CPUs with different instruction set architectures on their own registers. Then, the first CPU that runs into an error is determined from the multiple CPUs; the assembly sub-file corresponding to the second CPU that runs correctly is determined from the assembly file, and the values of the registers in the second CPU that runs correctly can be obtained. Further, the corresponding relationship between the register bank of the second CPU and the register bank of the first CPU is obtained, and based on the assembly sub-file and the corresponding relationship, the reference values of each register in the first CPU that participates in executing the preset program after the execution of the preset program are obtained, and then the values in the registers of the first CPU are updated based on the reference values. Obtaining the reference values of the registers of the first CPU based on the values of the registers of the second CPU that runs correctly can enable the first CPU to continue executing the subsequent program after the register values are updated, without the need to re-execute all programs, and can improve the update efficiency and accuracy of the register values of the first CPU.

[0066] In one embodiment, updating the values in the registers of the first CPU based on the reference values may include: obtaining the initial values of multiple registers of the first CPU before executing the preset program; determining the types of each register in the first CPU based on the initial values and the reference values of the registers; and updating the values of the registers based on the types of the registers and the reference values.

[0067] In this embodiment, the server can observe the changes in the register values of the first CPU after executing the preset program. After executing the preset program, the values of multiple registers of the first CPU may or may not change. The server can determine the types of each register in the first CPU based on the initial values and the reference values of the registers.

[0068] In one embodiment, determining the types of each register in the first CPU based on the initial values and the reference values of the registers may include: when the initial value of the register is the same as the reference value, the register is a first type of register; when the initial value of the register is different from the reference value, the register is a second type of register.

[0069] In this embodiment, when the register is a second type of register, the server can use the reference value as the value of the register and perform assignment update on the value of the register.

[0070] In this embodiment, when the register is a first type of register, the server does not need to perform assignment update on the value of the first type of register and can load it according to the initial value of the register.

[0071] In one embodiment, when the register is a second type of register, it may further include: when the second type of register invokes a subroutine in a preset program through an instruction, the hardware automatically saves the subroutine return address in a preset cache register.

[0072] In this embodiment, there is at least one preset cache register in each central processing unit of the instruction set architecture for saving the subroutine address.

[0073] In one embodiment, after updating the value in the register of the first central processing unit based on a reference value, it may further include: obtaining the subroutine return address in the preset cache register and continuing to execute the preset program based on the subroutine return address.

[0074] In this embodiment, the server can read the preset cache register to obtain the subroutine return address. Further, after the server updates the register value of the first central processing unit, the server can make the program execution address of the central processing unit point to the subroutine return address by reading the subroutine return address, so as to achieve the purpose of making the first central processing unit work properly again without restarting the preset program.

[0075] In one embodiment, take a heterogeneous CPU system with three instruction sets of arm (Acorn RISC Machine), risc-v (RISC-V instruction set architecture), and mips (MIPS architecture) as an example. To illustrate how to load and assign values between the registers of CPUs with different instruction set architectures.

[0076] In this embodiment, as Figure 3 shown, take a C program of loop addition as an example for illustration. Compile this C program into an assembly file respectively using the gcc (GNU Compiler Collection) compilation tools of arm, risc-v, and mips, as shown in Table 1 below.

[0077] Table 1 Assembly File Table

[0078]

[0079]

[0080] In this embodiment, for the ARM processor, the register file contains 13 general-purpose registers r0 - r12, as well as the SP stack pointer, LR link register, and PC program counter, for a total of 16 registers. For the RISC-V processor, the register file contains the x0 zero register, x1 dynamic return address (ra), x2 stack pointer (sp), x3 global pointer (gp), x4 thread pointer (tp), x8 stack frame pointer register (s0 / fp), and 16 general-purpose registers x5 - x7 and x9 - x31, for a total of 32 registers. For the MIPS processor, the register file contains the $0 zero register, 27 general-purpose registers $1 - $27, and $28 is the gp global pointer, $29 is the sp stack pointer, $30 is the fp stack frame pointer register, and $31 is the ra dynamic return address, for a total of 32 registers.

[0081] Generally speaking, the stored content in the general-purpose registers can be exchanged between CPUs with different instruction set architectures, but the content of the special registers still needs to be obtained from its own CPU.

[0082] In this embodiment, when the CPU with the ARM instruction set architecture malfunctions, the server can select a CPU with the MIPS or RISC-V instruction set architecture as the second central processing unit, and the second central processing unit loads the register values into the ARM.

[0083] In this embodiment, it can be seen from the assembly sub-file corresponding to the CPU with the ARM instruction set architecture in the assembly file that after the CPU with the ARM instruction set architecture finishes executing a loop addition process, the registers (the first type of registers) whose initial values are the same as the reference values are sp and r7, and the server can load the registers sp and r7 according to their initial values respectively.

[0084] In this embodiment, it can be seen from the assembly sub-file corresponding to the CPU with the ARM instruction set architecture in the assembly file that after the CPU with the ARM instruction set architecture finishes executing a loop addition process, the registers (the second type of registers) whose initial values are different from the reference values are r0, r2, and r3. Therefore, the server needs to update the values of these three registers. Further, the server can obtain the reference values of the above three registers (r0 = 0, r3 = 0, r2 = $3) based on the assembly sub-file corresponding to the CPU with the ARM instruction set architecture in the assembly file, and update the values of the registers with the reference values of the registers.

[0085] In this embodiment, the server may use the link register lr in the CPU with the ARM instruction set architecture as the preset cache register. As shown in the assembly sub-file corresponding to the CPU with the ARM instruction set architecture in the assembly file, when the second type of register calls a subroutine through the bl or blx instruction, the hardware automatically saves the subroutine return address in the lr register (preset cache register). That is to say, as long as the second type of register has not jumped into other subroutines after executing the program, the lr register should hold the return address of the previous subroutine.

[0086] In another embodiment, when the CPU with the RISC-V instruction set architecture encounters an error, the server may select a CPU with the MIPS or ARM instruction set architecture as the second central processing unit, and the second central processing unit loads the register values into the RISC-V.

[0087] In this embodiment, as can be seen from the assembly sub-file corresponding to the CPU with the RISC-V instruction set architecture in the assembly file, after the CPU with the RISC-V instruction set architecture finishes executing a loop addition process, the registers (the first type of registers) with the initial value and the reference value being the same are sp and s0 (fp), and the server may load the registers sp and s0 (fp) respectively according to their initial values.

[0088] In this embodiment, as can be seen from the assembly sub-file corresponding to the CPU with the RISC-V instruction set architecture in the assembly file, after the CPU with the RISC-V instruction set architecture finishes executing a loop addition process, the registers (the second type of registers) with the initial value and the reference value being different are a0, a5, and a4. Therefore, the server needs to assign and update these three registers. Further, the server may obtain the reference values of the above three registers (a0 = 0x0, a5 = 0x0, a4 = r2) based on the assembly sub-file corresponding to the CPU with the RISC-V instruction set architecture in the assembly file, and update the values of the registers with the reference values of the registers.

[0089] In this embodiment, the server may use the x1 dynamic return address (ra) in the CPU with the RISC-V instruction set architecture as the preset cache register. As shown in the assembly sub-file corresponding to the CPU with the RISC-V instruction set architecture in the assembly file, when the second type of register calls a subroutine, the hardware automatically saves the subroutine return address in the x1 dynamic return address (ra) (preset cache register). That is to say, as long as the second type of register has not jumped into other subroutines after executing the program, the x1 dynamic return address (ra) register should hold the return address of the previous subroutine.

[0090] In another embodiment, when the CPU of the MIPS instruction set architecture malfunctions, the server can select a CPU of the RISC-V or ARM instruction set architecture as the second central processing unit, and the second central processing unit loads the register values into MIPS.

[0091] In this embodiment, it can be known from the assembly sub-file corresponding to the CPU of the MIPS instruction set architecture in the assembly file that after the CPU of the MIPS instruction set architecture finishes executing a loop addition process, the registers (the first type of registers) whose initial values are the same as the reference values are $sp and $fp, and the server can load the registers $sp and $fp according to their initial values respectively.

[0092] In this embodiment, it can be known from the assembly sub-file corresponding to the CPU of the MIPS instruction set architecture in the assembly file that after the CPU of the MIPS instruction set architecture finishes executing a loop addition process, the registers (the second type of registers) whose initial values are different from the reference values are $2 and $3. Therefore, the server needs to update the values of these two registers. Further, the server can obtain the reference values of the above two registers ($2 = 0, $3 = a4) based on the assembly sub-file corresponding to the CPU of the MIPS instruction set architecture in the assembly file, and update the values of the registers with the reference values of the registers.

[0093] In this embodiment, the server can use $31 in the CPU of the MIPS instruction set architecture as a preset cache register. As shown in the assembly sub-file corresponding to the CPU of the MIPS instruction set architecture in the assembly file, when the second type of register calls a subroutine, the hardware automatically saves the subroutine return address in $31 (the preset cache register). That is to say, as long as the second type of register has not jumped into other subroutines after executing the program, the value saved in $31 should be the return address of the previous subroutine.

[0094] In this embodiment, this method only observes the register changes caused by a section of loop addition C code as Figure 3 shown, and by reassigning the registers, the purpose of not restarting the program and enabling the CPU to resume normal operation is achieved.

[0095] In another embodiment, the server can read the preset cache register to obtain the subroutine return address.

[0096] In this embodiment, the subroutine return address can be a numerical value, a character, etc., and its representation form is the same as the data in the PC program counter. For example, when the preset program is 10 lines of code and an error occurs when the first central processing unit executes to the 6th line of code, the data in the pc program counter may be 6 (the data in the pc program counter will also be incorrect when the program runs wild). Suppose the subroutine return address is 6 at this time. Then, after the server updates the register value in the first central processing unit, it assigns the subroutine return address in the preset cache register to the pc program counter, so that the first central processing unit can continue to execute the subsequent program after the register value is updated, without having to execute all the programs again.

[0097] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are shown in sequence according to the arrows, these steps do not necessarily have to be executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages do not necessarily have to be executed at the same time, but can be executed at different times. The execution order of these steps or stages does not necessarily have to be sequential, but can be executed alternately or alternately with at least a part of other steps or steps in other steps.

[0098] Based on the same inventive concept, an embodiment of the present application further provides an error cleaning device for heterogeneous redundancy that is used to implement the above-mentioned error cleaning method for heterogeneous redundancy. The implementation solution provided by this device to solve the problem is similar to the implementation solution described in the above method. Therefore, the specific limitations in one or more embodiments of the error cleaning device for heterogeneous redundancy provided below can refer to the limitations on the error cleaning method for heterogeneous redundancy in the above text, and will not be repeated here.

[0099] In one embodiment, as Figure 4 shown, an error cleaning device for heterogeneous redundancy is provided, including: a register bank acquisition module 402, an assembly file acquisition module 404, an error central processing unit determination module 406, an assembly sub-file acquisition module 408, a reference value acquisition module 410, and an update module 412.

[0100] Among them, the register bank acquisition module 402 is used to acquire the register bank of each central processing unit in multiple central processing units, and each central processing unit adopts a different instruction set architecture.

[0101] An assembly file acquisition module 404 is configured to acquire a preset program and an assembly file corresponding to the preset program; the assembly file includes different operation processes of a central processing unit (CPU) with different instruction set architectures on its own registers.

[0102] An error CPU determination module 406 is configured to determine, from multiple CPUs, a first CPU that runs with errors.

[0103] An assembly sub-file acquisition module 408 is configured to determine, from the assembly file, an assembly sub-file corresponding to a second CPU that runs correctly.

[0104] A reference value acquisition module 410 is configured to acquire a corresponding relationship between the register bank of the second CPU and the register bank of the first CPU, and obtain, according to the assembly sub-file and the corresponding relationship, reference values of each register in the first CPU that participates in executing the preset program after the preset program is executed.

[0105] An update module 412 is configured to update values in the registers of the first CPU based on the reference values.

[0106] In one embodiment, the update module 412 may include:

[0107] An initial value acquisition sub-module is configured to acquire initial values of multiple registers of the first CPU before the preset program is executed.

[0108] A register type determination sub-module is configured to determine types of respective registers in the first CPU based on the initial values and the reference values of the registers.

[0109] A register value update sub-module is configured to update values of the registers based on the types and the reference values of the registers.

[0110] In one embodiment, the register type determination sub-module may include:

[0111] A first determination unit is configured to determine that a register is a first type of register when the initial value of the register is the same as the reference value.

[0112] A second determination unit is configured to determine that a register is a second type of register when the initial value of the register is different from the reference value.

[0113] In one embodiment, the register value update sub-module may include:

[0114] A first update unit is configured to load according to the initial value of the register when the register is a first type of register.

[0115] A second update unit is configured to use the reference value as the value of the register when the register is a second type of register.

[0116] In one embodiment, when the register is a second type of register, the second update unit may further include:

[0117] An address cache subunit, configured to automatically save the subroutine return address in a preset cache register by hardware when the second type of register calls a subroutine in a preset program through an instruction.

[0118] In one embodiment, the above device may further include:

[0119] A continue execution module, configured to obtain the subroutine return address in the preset cache register and continue to execute the preset program based on the subroutine return address.

[0120] Each module in the above error cleaning device applicable to heterogeneous redundancy can be implemented in whole or in part by software, hardware, and their combination. Each of the above modules can be embedded in the processor in the computer device in hardware form or be independent of it, or be stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to each of the above modules.

[0121] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in Figure 5 The figure shows. The computer device includes a processor, a memory, and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data such as subroutine return addresses, initial values of registers of the first central processing unit, reference values, etc. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it implements an error cleaning method applicable to heterogeneous redundancy.

[0122] Those skilled in the art can understand that Figure 5 The structure shown in the figure is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0123] In one embodiment, a computer device is provided, including a memory and a processor. A computer program is stored in the memory. When the processor executes the computer program, the following steps are implemented: obtaining the register heap of each central processing unit (CPU) among multiple CPUs, where each CPU adopts a different instruction set architecture; obtaining a preset program and an assembly file corresponding to the preset program; the assembly file includes different operation processes of CPUs with different instruction set architectures on their own registers; determining a first CPU that runs with errors from among the multiple CPUs; determining an assembly sub-file corresponding to a second CPU that runs correctly from the assembly file; obtaining the correspondence between the register heap of the second CPU and the register heap of the first CPU, and obtaining the reference value of each register participating in the execution of the preset program in the first CPU after the execution of the preset program according to the assembly sub-file and the correspondence; updating the values in the registers of the first CPU based on the reference value.

[0124] In one of the embodiments, when the processor executes the computer program, the step of updating the values in the registers of the first CPU based on the reference value may include: obtaining the initial values of multiple registers of the first CPU before the execution of the preset program; determining the type of each register in the first CPU based on the initial value and the reference value of the register; updating the value of the register based on the type of the register and the reference value.

[0125] In one of the embodiments, when the processor executes the computer program, the step of determining the type of each register in the first CPU based on the initial value and the reference value of the register may include: when the initial value of the register is the same as the reference value, the register is a first type of register; when the initial value of the register is different from the reference value, the register is a second type of register.

[0126] In one of the embodiments, when the processor executes the computer program, the step of updating the value of the register based on the type of the register and the reference value may include: when the register is a first type of register, loading according to the initial value of the register; when the register is a second type of register, using the reference value as the value of the register.

[0127] In one of the embodiments, when the processor executes the computer program and the register is a second type of register, it may further include: when the second type of register calls a subroutine in the preset program through an instruction, the hardware automatically saves the subroutine return address in a preset cache register.

[0128] In one of the embodiments, after the processor executes the computer program and updates the values in the registers of the first CPU based on the reference value, it may further include: obtaining the subroutine return address in the preset cache register and continuing to execute the preset program based on the subroutine return address.

[0129] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: obtaining the register banks of each central processing unit (CPU) among multiple CPUs, where each CPU adopts a different instruction set architecture; obtaining a preset program and an assembly file corresponding to the preset program; the assembly file includes different operation processes of CPUs with different instruction set architectures on their own registers; determining a first CPU that runs with errors from among the multiple CPUs; determining an assembly sub-file corresponding to a second CPU that runs correctly from the assembly file; obtaining the correspondence between the register bank of the second CPU and the register bank of the first CPU, and obtaining the reference values of each register participating in the execution of the preset program in the first CPU after the execution of the preset program according to the assembly sub-file and the correspondence; updating the values in the registers of the first CPU based on the reference values.

[0130] In one of the embodiments, when the computer program is executed by a processor, updating the values in the registers of the first CPU based on the reference values may include: obtaining the initial values of multiple registers of the first CPU before executing the preset program; determining the types of each register in the first CPU based on the initial values of the registers and the reference values; updating the values of the registers based on the types of the registers and the reference values.

[0131] In one of the embodiments, when the computer program is executed by a processor, determining the types of each register in the first CPU based on the initial values of the registers and the reference values may include: when the initial value of a register is the same as the reference value, the register is a first type of register; when the initial value of a register is different from the reference value, the register is a second type of register.

[0132] In one of the embodiments, when the computer program is executed by a processor, updating the values of the registers based on the types of the registers and the reference values may include: when the register is a first type of register, loading according to the initial value of the register; when the register is a second type of register, using the reference value as the value of the register.

[0133] In one of the embodiments, when the computer program is executed by a processor and when the register is a second type of register, it may further include: when the second type of register calls a subroutine in the preset program through an instruction, the hardware automatically saves the subroutine return address in a preset cache register.

[0134] In one of the embodiments, after updating the values in the registers of the first CPU based on the reference values when the computer program is executed by a processor, it may further include: obtaining the subroutine return address in the preset cache register and continuing to execute the preset program based on the subroutine return address.

[0135] In one embodiment, a computer program product is provided, including a computer program, which when executed by a processor implements the following steps: obtaining the register banks of each central processing unit (CPU) among a plurality of CPUs, where each CPU adopts a different instruction set architecture; obtaining a preset program and an assembly file corresponding to the preset program; the assembly file includes different operation processes of the CPUs with different instruction set architectures on their own registers; determining a first CPU that runs with errors from among the plurality of CPUs; determining an assembly sub-file corresponding to a second CPU that runs correctly from the assembly file; obtaining the correspondence between the register bank of the second CPU and the register bank of the first CPU, and obtaining the reference values of each register in the first CPU that participates in executing the preset program after the execution of the preset program according to the assembly sub-file and the correspondence; updating the values in the registers of the first CPU based on the reference values.

[0136] In one of the embodiments, when the computer program is executed by a processor, updating the values in the registers of the first CPU based on the reference values may include: obtaining the initial values of a plurality of registers of the first CPU before executing the preset program; determining the types of the respective registers in the first CPU based on the initial values of the registers and the reference values; and updating the values of the registers based on the types of the registers and the reference values.

[0137] In one of the embodiments, when the computer program is executed by a processor, determining the types of the respective registers in the first CPU based on the initial values of the registers and the reference values may include: when the initial value of a register is the same as the reference value, the register is a first type of register; when the initial value of a register is different from the reference value, the register is a second type of register.

[0138] In one of the embodiments, when the computer program is executed by a processor, updating the values of the registers based on the types of the registers and the reference values may include: when the register is a first type of register, loading according to the initial value of the register; when the register is a second type of register, using the reference value as the value of the register.

[0139] In one of the embodiments, when the computer program is executed by a processor, when the register is a second type of register, it may further include: when the second type of register calls a subroutine in the preset program through an instruction, the hardware automatically saves the subroutine return address in a preset cache register.

[0140] In one of the embodiments, after the computer program, when executed by a processor, updates the value in the register of the first central processing unit based on a reference value, it may further include: obtaining a subroutine return address in a preset cache register and continuing to execute a preset program based on the subroutine return address.

[0141] Those of ordinary skill in the art can understand that all or part of the processes of implementing the methods in the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it may include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium provided in the various embodiments of the present application may include at least one of non-volatile and volatile memories. Non-volatile memories may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memories may include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the various embodiments of the present application may include at least one of relational databases and non-relational databases. Non-relational databases may include distributed databases based on blockchain, etc., without limitation. The processors involved in the various embodiments of the present application may be general-purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., without limitation.

[0142] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0143] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. An error cleaning method applicable to heterogeneous redundancy, characterized in that The method includes: Obtaining the register heap of each central processing unit (CPU) among multiple CPUs, where each CPU adopts a different instruction set architecture; Obtaining a preset program and the assembly file corresponding to the preset program; the assembly file includes different operation processes of CPUs with different instruction set architectures on their own registers; Determining a first CPU that runs with errors from the multiple CPUs; Determining an assembly sub-file corresponding to a second CPU that runs correctly from the assembly file; Obtaining the correspondence between the register heap of the second CPU and the register heap of the first CPU, and obtaining the reference value of each register that participates in executing the preset program in the first CPU after the preset program is executed according to the assembly sub-file, the correspondence, and the value of each register that participates in executing the preset program in the second CPU after the preset program is executed; Updating the values in the registers of the first CPU based on the reference value.

2. The method according to claim 1, wherein The updating the values in the registers of the first CPU based on the reference value includes: Obtaining the initial values of multiple registers of the first CPU before executing the preset program; Determining the types of each register in the first CPU based on the initial values of the registers and the reference value; Updating the values of the registers based on the types of the registers and the reference value.

3. The method according to claim 2, characterized in that, The determining the types of each register in the first CPU based on the initial values of the registers and the reference value includes: When the initial value of the register is the same as the reference value, the register is a first type of register; When the initial value of the register is different from the reference value, the register is a second type of register.

4. The method according to claim 3, characterized in that The updating the values of the registers based on the types of the registers and the reference value includes: When the register is a first type of register, loading according to the initial value of the register; When the register is a second type of register, using the reference value as the value of the register.

5. The method according to claim 4, characterized in that, When the register is a second type of register, it further includes: When the second type of register calls a subroutine in the preset program through an instruction, the hardware automatically saves the subroutine return address in a preset cache register.

6. The method according to claim 5, characterized in that, After updating the values in the registers of the first CPU based on the reference value, it further includes: Obtaining the subroutine return address in the preset cache register and continuing to execute the preset program based on the subroutine return address.

7. An error cleaning device applicable to heterogeneous redundancy, characterized in that, The device includes: A register heap obtaining module, configured to obtain the register heap of each central processing unit (CPU) among multiple CPUs, where each CPU adopts a different instruction set architecture; An assembly file obtaining module, configured to obtain a preset program and the assembly file corresponding to the preset program; the assembly file includes different operation processes of CPUs with different instruction set architectures on their own registers; An error CPU determining module, configured to determine a first CPU that runs with errors from the multiple CPUs; An assembly sub-file acquisition module, configured to determine, from the assembly file, the assembly sub-file corresponding to the second central processing unit that runs correctly; A reference value acquisition module, configured to obtain the correspondence between the register bank of the second central processing unit and the register bank of the first central processing unit, and obtain, according to the assembly sub-file, the correspondence, and the values of each register participating in the execution of the preset program in the second central processing unit after the execution of the preset program, the reference values of each register participating in the execution of the preset program in the first central processing unit after the execution of the preset program; An update module, configured to update the values in the registers of the first central processing unit based on the reference values.

8. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product comprising a computer program, characterized in that, When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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