A termination regulator for DDR memory with high transient response

Abstract

The application discloses a terminal regulator for DDR memory with high transient response, which comprises V REF A generating circuit adopts a driving buffer; two error amplifiers ampA and ampB are commonly connected at the negative end of V SENSE The positive end of V SENSE is a bus terminal voltage V TT A feedback input end; a transient enhancement stage is used for monitoring the change of an output voltage; when a larger current is generated at the output end and causes the change of the bus terminal voltage V TT , the feedback circuit monitors the change and instantaneously feeds back the change to a transient enhancement module; the transient enhancement module improves the driving capacity of an output tube to inhibit the generation of transient overshoot; and an output stage adopts a push-pull output structure, and the gate voltages of a power tube MP and a power tube MN are connected with the output ends of the two error amplifiers respectively. The application adopts a double-loop design; the first loop is the basis for keeping the circuit to work stably, and the second loop is a transient enhancement loop, which improves the transient response capacity of the circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to a terminal adjuster, in particular to a terminal adjuster for DDR memory with high transient response. BACKGROUND

[0002] Memory is one of the three components of a computer, and its technology has gone through the stages of DRAM, SDRAM, and DDR SDRAM. In order to solve the access speed problem of CPU, JEDEC (Institute of Electrical and Electronics Engineers) specially developed the interface protocol SSTL (Strobe Signal Transistor Logic) for high-speed memory. DDR memory, also known as "Double Data Rate Synchronous Dynamic Random Access Memory", is developed on the basis of SDRAM (Synchronous Dynamic Random Access Memory). Compared with single data rate, DDR technology realizes two read / write operations in one clock cycle, i.e., one read / write operation is performed at the rising edge and the falling edge of the clock, respectively.

[0003] As shown in Figure 1 , a DDR SDRAM system usually requires three power supplies, namely power supply voltage VDDQ, bus terminal power supply VTT (with sink and source functions), and reference voltage VREF. In DDR memory, the chipset output buffer adopts a push-pull structure, and the DDR memory receiving end adopts a differential comparator structure, and RS and RT are matching resistors.

[0004] The bus terminal voltage VTT and the reference voltage VREF are both 0.5*VDDQ and can accurately follow VDDQ. If the chipset output buffer control signal is at low potential, the current flows from VDDQ to VTT; if the chipset output buffer control signal is at high potential, the current flows from VTT to GND. By combining the chipset output buffer control signal with the differential comparator of the DDR memory receiving end, the DDR read / write operation is realized.

[0005] Currently, there are relatively few studies in the field of DDR memory terminal adjuster research at home and abroad. Among them, the known technical literature is as follows:

[0006] US Patent No. US 11,287,839 B2 discloses a dual-loop LDO voltage regulator, and the circuit principle is shown in Figure 2 . The voltage regulator includes a current mirror, which generates a VOUT voltage through a mirror current and resistors R1 and R2. At the same time, the VOUT voltage is divided by resistors R1 and R2, and the divided Vdiv is amplified by an error amplifier to control the opening state of MN3, thereby maintaining the stability of the entire closed loop.

[0007] The drawback of this circuit is its limited driving capability. Stable driving can be provided by adjusting the mirror ratio of the current mirror.

[0008] US Patent No. 10,234,883 B1 discloses a dual-loop adaptive LDO voltage regulator, the circuit principle of which is as follows: Figure 3 As shown, this circuit contains a voltage loop and a current loop, with the current loop coupled to the output via a source follower. Because the current is mirrored, the MP3 transistor struggles to adapt to drastic current changes and provide the required current when the load varies significantly.

[0009] US Patent No. 10,860,045 B1 discloses a high-voltage shared push-pull buffer circuit, the circuit principle of which is as follows: Figure 4 As shown, this circuit consists of an input stage, a buffer stage, and an output stage. The output stage is a push-pull output, capable of carrying and releasing current. Since the output stage is controlled by Vy and Vx respectively, with the voltage at Vy provided by M8, M12, M7, M11, and M10, the Vout voltage can easily be pulled low when the load changes drastically because M9 cannot provide sufficient drive current.

[0010] An article titled "A Low-Voltage DDR Termination Regulator Chip" was published in the 2020 S01 issue of Environmental Technology. Figure 5 This is a diagram of the DDR termination regulator architecture. The DDR termination regulator consists of a buffer, an error amplifier, a current amplifier, and high-side and low-side power transistors. System stability is provided by an external capacitor Cout, which has a large capacitance value and can stabilize the output VTT. Simulation results show that when the output drive varies within the range of -3A to 3A, the VTT output changes by approximately ±12mV.

[0011] An article titled "An LDO Chip Design for DDR Memory Drivers" was published in Volume 18, Issue 4 of the journal *Electronics & Packaging* in 2018. The article proposes an LDO chip applicable to DDR memory drivers. The circuit diagram is shown below. Figure 6 As shown in the diagram, this circuit employs a relatively novel frequency compensation method by adding a resistor between the gate and source of the MNP1 power transistor, and connecting a resistor from the gate of the MNP2 power transistor to ground. Simulation results show that when the current varies from -1.5A to 1.5A, the transient response overshoot is 63mV. Summary of the Invention

[0012] The purpose of this invention is to provide a terminal regulator for DDR memory with high transient response.

[0013] The technical solution of this invention is:

[0014] A terminal regulator for DDR memory with high transient response, wherein the DDR memory requires three power supplies, namely the main power supply voltage V DDQ Bus terminal voltage V TT and reference voltage V REF ,

[0015] The terminal adjuster is characterized in that it comprises:

[0016] V REF Generation circuit: includes a drive buffer; power supply voltage V DDQ After voltage division by resistors R1 and R2, the reference voltage V for the output DDR memory is generated by the drive buffer. REF ;

[0017] Error amplifier group: includes two error amplifiers ampA and ampB; the positive terminals of the two error amplifiers are connected to the voltage divider node V1 of resistors R1 and R2; the negative terminals of the two error amplifiers are connected to V... SENSE End, V SENSE The terminal is the bus termination voltage V. TT Feedback input terminal;

[0018] Transient enhancement stage: Includes feedback circuit and transient enhancement circuit, used to monitor changes in output voltage. When a large instantaneous current is generated at the output terminal, causing a change in the bus termination voltage V... TT When a change occurs, the feedback circuit detects the change and instantly feeds it back to the transient enhancement module. The transient enhancement module suppresses the generation of transient overshoot by increasing the driving capability of the output transistor.

[0019] The output stage adopts a push-pull output structure consisting of a PMOS power transistor MP and an NMOS power transistor MN. The gate voltages of power transistors MP and MN are respectively connected to the output terminals of two error amplifiers.

[0020] Preferably, the two error amplifiers ampA and ampB are P-input folded common-source cascode operational amplifiers; the input stage of ampA consists of MP0 and MP1, and the input stage of ampB consists of MP2 and MP3. After being amplified by the common-source cascode amplifier, the input stages are output to the control power transistors MP and MN, respectively.

[0021] Preferably, the operational amplifier bias currents of both error amplifiers ampA and ampB adopt a cascode structure; NMOS power transistors MN3, MN4, MN7, and MN8 provide the bias current for the operation of the operational amplifiers; NMOS power transistors MN1 and MN2, together with PMOS power transistors MP0 and MP1, form the common-source common-gate input stage of ampA, and NMOS power transistors MN5 and MN6, together with PMOS power transistors MP2 and MP3, form the common-source common-gate input stage of ampB; PMOS power transistors MP8, MP9, MP10, and MP11 form a low-voltage common-source common-gate current mirror, converting the double-ended output of ampA into a single-ended output; PMOS power transistors MP12, MP13, MP14, and MP15 form a low-voltage common-source common-gate current mirror, converting the double-ended output of ampB into a single-ended output; the devices in the main path operate in the subthreshold region, and the other devices in the operational amplifier operate in the saturation region.

[0022] Preferably, the transient enhancement circuit of the transient enhancement stage includes transient enhancement transistors, which are composed of PMOS power transistors MP20 and MP21 and NMOS power transistors MN20 and MN21; wherein the drain terminals of MP20 and MN20 are connected to the gate terminal VP1 of the power transistor MP, and the drain terminals of MP21 and MN21 are connected to the gate terminal VN1 of the power transistor MN; the source terminals of MP20 and MP21 share the same power supply as the power transistors, and the source terminals of MN20 and MN21 are respectively grounded;

[0023] The error amplifier uses a dual-input, single-output design. Its two input terminals are connected to VTT and V1 respectively, and the output terminal VCTL is connected to the gate terminals of the transient enhancement transistors MP20, MP21, MN20, and MN21.

[0024] Preferably, the error amplifier is one of the following: a single-stage operational amplifier, a multi-stage operational amplifier, a sleeve-type operational amplifier, a folded cascode operational amplifier, a common-source amplifier, or an integrator.

[0025] Preferably, the transient enhancement circuit is in the form of an inverter-like circuit or a bias module that can control the gate.

[0026] Preferably, the error amplifier that makes up the terminal adjuster has a fully symmetrical architecture.

[0027] The advantages of this invention are:

[0028] 1. The DDR memory terminal regulator of the present invention adopts a dual-loop design. The first loop is the basis for the circuit to maintain stable operation, and the second loop is a transient enhancement loop to improve the transient response capability of the circuit. The loop stability of the system is determined by the main loop, and the stability of the main loop is determined by the external capacitor. When the main loop is unstable, the system will oscillate.

[0029] 2. To ensure the accuracy of the bias current mirroring, the bias current of the operational amplifier adopts a cascode structure. To ensure that the circuit can operate normally under low voltage conditions, the devices in the main path operate in the subthreshold region, while the other devices in the operational amplifier operate in the saturation region.

[0030] 3. The transient enhancement circuit of this invention consists of a feedback circuit and a transient enhancement circuit. It monitors changes in the output voltage. When a large instantaneous current is generated at the output terminal, causing a change in the VTT output voltage, the feedback circuit detects this change and instantly feeds it back to the transient enhancement module. The transient enhancement module suppresses transient overshoot by increasing the driving capability of the output transistor. When the load current changes rapidly, the output terminal of the DDR memory termination regulator will absorb or output current as needed to ensure that the change in the DDR bus termination voltage remains within a small range. Attached Figure Description

[0031] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0032] Figure 1 This is a schematic diagram of the basic power management structure of the SSTL interface for DDR memory in the existing technology.

[0033] Figure 2 This is a schematic diagram of a dual-loop LDO voltage regulator in the prior art.

[0034] Figure 3 This is a schematic diagram of a dual-loop adaptive LDO voltage regulator in the prior art.

[0035] Figure 4 This is a schematic diagram of a push-pull buffer circuit used in existing high-voltage applications.

[0036] Figure 5 This is a schematic diagram of a low-voltage DDR terminal regulator chip in the existing technology.

[0037] Figure 6 This is a schematic diagram of an LDO chip suitable for DDR memory driving in the existing technology.

[0038] Figure 7 This is a block diagram of the high transient response DDR memory terminal regulator of the present invention;

[0039] Figure 8 This is a schematic diagram of one implementation of the DDR memory terminal adjuster of the present invention;

[0040] Figure 9 This is a schematic diagram of the implementation of the drive enhancement circuit for the DDR memory terminal regulator of the present invention;

[0041] Figure 10This is the transient response diagram of the original DDR memory's termination regulator;

[0042] Figure 11 This is a transient response diagram of the DDR memory terminal adjuster of the present invention. Detailed Implementation

[0043] As one of the three major components of a computer, memory typically requires three power supplies: the power supply voltage VDDQ, the bus terminal power supply VTT (which has sink and source functions), and the reference voltage VREF. In DDR memory, the chipset output buffer uses a push-pull structure, the DDR memory receiver uses a differential comparator structure, and RS and RT are matching resistors.

[0044] This invention discloses a terminal regulator for DDR memory with high transient response, the principle block diagram of which is shown below. Figure 7 As shown.

[0045] This invention mainly consists of a VREF generation circuit, an error amplifier, a transient enhancement module, and a drive output stage, wherein VTT and VSENSE are connected together by external leads.

[0046] VREF generation circuit: mainly generates the reference voltage used by DDR memory. It is generated by dividing the VDDQ voltage through resistors R1 and R2 and then outputting it through the drive buffer.

[0047] Error Amplifier: The error amplifier used in this invention consists of two completely symmetrical error amplifiers. Their positive input terminals are connected to V1, which is obtained by voltage division of VDDQ through resistors R1 and R2. Their negative input terminals are connected to VSENSE, which is the feedback input terminal for VTT.

[0048] Transient enhancement stage: The transient enhancement stage mainly consists of a feedback circuit and a transient enhancement circuit. Its function is to monitor changes in the output voltage. When a large instantaneous current is generated at the output terminal, causing a change in the VTT output voltage, the feedback circuit detects the change and instantly feeds it back to the transient enhancement module. The transient enhancement module suppresses the generation of transient overshoot by increasing the driving capability of the output transistor.

[0049] Output stage: The output stage mainly consists of a PMOS power transistor and an NMOS power transistor.

[0050] Figure 8This is one implementation of a termination regulator for DDR memory. The circuit consists of two fully symmetrical folded cascode op-amps. The inputs of the two folded cascode op-amps are connected together, with one end connected to V1 and the other end connected to the VSENSE feedback input. Since the DDR linear regulator designed in this paper needs to be applied to SDRAM, DDR, DDR2, DDR3, and DDR4, and the chip operating voltage is relatively low, a P-input folded cascode op-amp is used, which can meet the low input voltage requirement while providing high voltage gain.

[0051] VDDQ is divided by resistors and then input to the positive terminals of error amplifiers ampA and ampB via V1. The input stage of ampA consists of MP0 and MP1, and the input stage of ampB consists of MP2 and MP3. After amplification by a common-source cascode amplifier, the input stages are output to the control power transistors MP and MN, respectively. The output stage is a push-pull output. When the load is pulling current, the upper transistor MP is active and the lower transistor MN is off. When the load is sinking current, the lower transistor MN is active and the upper transistor MP is off. To ensure the accuracy of the bias current mirror, the bias currents of the op-amps all adopt a cascode structure. MN3, MN4, MN7, and MN8 provide the bias current for the op-amp operation. MN1, MN2, MP0, and MP1 form the common-source cascode input stage of ampA, and MN5, MN6, MP2, and MP3 form the common-source cascode input stage of ampB. MP8, MP9, MP10, and MP11 constitute a low-voltage common-source cascode current mirror, converting the two-ended output of ampA into a single-ended output. MP12, MP13, MP14, and MP15 form a low-voltage cascode current mirror, converting the dual-ended output of ampB to a single-ended output. To ensure the circuit functions correctly under low voltage conditions, the components in the main path operate in the subthreshold region, while the other components in the op-amp operate in the saturation region.

[0052] At this time, the output resistances of the op-amps at VP1 and VPN1 are respectively

[0053] R eqP1 =[(g mn2 +g mbn2 )×r on2 ×(r op0 / / r on4 )] / / [(g mp11 +g mbp11 )×r op11 ×r op9 (1)

[0054] R eqN1 =[(g mn6 +g mbn6 )×r on6 ×(r op2 / / ron8 )] / / [(g mp15 +g mbp15 )×r op15 ×r op13 (2)

[0055] Because the voltage regulator needs to provide a large current, the power transistors MP and MN are typically large, resulting in large parasitic capacitances. Therefore, the circuit has poles.

[0056]

[0057] In the formula, CCP is the capacitance to ground at VP1, and CCN is the capacitance to ground at VN1.

[0058] Since this voltage regulator is used in a DDR environment, it needs to have sink and source functions. At the same time, since the inflow or outflow current must meet the range of -1.5A to 1.5A, the equivalent resistance of the output terminal of the voltage regulator changes drastically. As a result, the zero and pole points of the circuit will change significantly, causing problems with the stability of the system.

[0059] When the load is light, the system output impedance RO is...

[0060]

[0061] The capacitor seen at the output terminal is:

[0062] C eq =C L +C GDP +C GDN (5)

[0063] Therefore, the output stage has a pole:

[0064]

[0065] When the load is light, the dominant pole of the circuit is at ω. p2 .

[0066] When the load is heavy, R is needed to absorb or discharge a larger current. o It becomes extremely low, therefore the principal pole becomes ω. pp1 or ω pN1 Changes in the dominant pole can sometimes lead to system stability issues.

[0067] Therefore, in order to improve the system's stability and fast response capability, a large capacitor needs to be added at the output end to reduce the impact of the lower output impedance.

[0068] However, simply adding capacitors can improve circuit stability and reduce the impact of load on the system, but due to issues such as its driving capability, the output of the circuit still varies greatly with the load.

[0069] The transient enhancement module designed in this invention is in Figure 8 The specific implementation method in is as follows Figure 9 As shown.

[0070] The error amplifier employs a simple dual-input, single-output implementation. Its two input terminals are connected to VTT and V1, respectively, and its output terminal VCTL is connected to the gate terminals of transient enhancement transistors MP20, MP21, MN20, and MN21. (Dual-input, single-output error amplifiers can be implemented in various ways, such as sleeve-type, folded cascode type, or even simple source follower types.)

[0071] The transient enhancement transistor consists of MP20, MP21, MN20, and MN21. Its key feature is that the drain terminals of MP20 and MN20 are connected to the gate terminal VP1 of the power transistor MP, and the drain terminals of MP21 and MN21 are connected to the gate terminal VN1 of the power transistor MN. The sources of MP20 and MP21 share a common power supply with the power transistors, while the sources of MN20 and MN21 are grounded.

[0072] When the load current changes rapidly, the output of the DDR memory termination regulator will sink (absorb) or source (output) current as needed to ensure that the change in the DDR bus termination voltage is within a small range.

[0073] Figure 10 The figure shows the transient response of the VTT output voltage of the original DDR memory terminal regulator in the range of load current from -1.5A to 1.5A. As can be seen from the figure, although the circuit uses a large capacitor to stabilize the loop, an overshoot of 33mV peak-to-peak value still occurs during the current transient phase. At the same time, the VTT output voltage also changes with the load current.

[0074] Figure 11 The figure shows the transient response of the VTT output voltage using the DDR memory terminal regulator of this invention within a load current range of -1.5A to 1.5A. As can be seen from the figure, by adding a new feedback loop to the original output loop, the system stability and transient response are significantly improved. When the load current varies within the range of -1.5A to 1.5A, the peak-to-peak overshoot is only 16.4μV, a reduction of 2000 times. This greatly improves the transient response capability of the circuit.

[0075] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All modifications made according to the spirit and essence of the main technical solution of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A termination regulator for a DDR memory having a high transient response, the DDR memory requiring three power supply sources, a main power voltage V DDQ , a bus termination voltage V TT , and a reference voltage V REF , characterized by The terminal regulator comprises: V REF Circuit for generating: including a driving buffer; power voltage V DDQ Reference voltage V for DDR memory generated by driving buffer after voltage division by resistors R1 and R2 REF ; Error amplifier group: including two error amplifiers ampA and ampB; the positive terminals of the two error amplifiers are connected to the voltage division node V1 of resistors R1 and R2; the negative terminals of the two error amplifiers are connected to the bus terminal voltage V SENSE . SENSE . TT Feedback input terminal Transient enhancement stage: including feedback circuit and transient enhancement circuit, for monitoring the change of output voltage, when the output terminal produces a larger instantaneous current resulting in bus terminal voltage V TT When the change occurs, the feedback circuit monitors the change and instantaneously feeds back to the transient enhancement module, which suppresses the generation of transient overshoot by improving the driving capacity of the output tube; The output stage adopts a push-pull output structure composed of a PMOS power transistor MP and an NMOS power transistor MN, and the gate voltages of the power transistor MP and the power transistor MN are connected with two error amplifiers respectively; The transient enhancement circuit of the transient enhancement stage comprises a transient enhancement transistor composed of a PMOS power transistor MP20, a PMOS power transistor MP21, an NMOS power transistor MN20 and an NMOS power transistor MN21; wherein the drain of the PMOS power transistor MP20 and the drain of the NMOS power transistor MN20 are connected with the gate of the power transistor MP, the drain of the PMOS power transistor MP21 and the drain of the NMOS power transistor MN21 are connected with the gate of the power transistor MN; the source of the PMOS power transistor MP20 and the source of the PMOS power transistor MP21 are connected with the common power supply of the power transistor, and the source of the NMOS power transistor MN20 and the source of the NMOS power transistor MN21 are connected with the ground respectively; The error amplifier adopts double-end input and single-end output, two input ends of which are connected with V TT and V1 respectively, and the output end VCTL is connected with the gate end of MP20, MP21, MN20 and MN21 of the transient enhancement tube. The feedback circuit of the transient enhancement stage is a double-ended input and single-ended output of the error amplifier, and is composed of PMOS power tubes MP30, MP31, MP32 and NMOS power tubes MN31, MN32; wherein the gate ends of MP31 and MP32 are respectively connected to V1 and V TT , the drain ends of MP31 and MP32 are respectively connected to the drain ends of MN31 and MN32, the source ends of MN31 and MN32 are respectively connected to the ground, the gate ends of MN31 and MN32 are commonly connected, the source ends of MP31 and MP32 are commonly connected to the drain end of MP30, the source end of MP30 is simultaneously connected to the substrate ends of MP31 and MP32 and a working voltage supply end V IN ; and the commonly connected point of the drain ends of MP32 and MN32 is used as an output end VCTL. The feedback circuit of the transient enhancement stage is a double-ended input and single-ended output of the error amplifier, and is composed of PMOS power tubes MP30, MP31, MP32 and NMOS power tubes MN31, MN32; wherein the gate ends of MP31 and MP32 are respectively connected to V1 and V TT , the drain ends of MP31 and MP32 are respectively connected to the drain ends of MN31 and MN32, the source ends of MN31 and MN32 are respectively connected to the ground, the gate ends of MN31 and MN32 are commonly connected, the source ends of MP31 and MP32 are commonly connected to the drain end of MP30, the source end of MP30 is simultaneously connected to the substrate ends of MP31 and MP32 and a working voltage supply end V IN ; and the commonly connected point of the drain 2. The termination regulator for DDR memory with high transient response according to claim 1, wherein, The two error amplifiers ampA and ampB adopt a P-input folded common-source common-gate operational amplifier; the input stage of the ampA is composed of MP0 and MP1, and the input stage of the ampB is composed of MP2 and MP3, and the input stage is amplified by the common-source common-gate amplifier and then output to the control power transistor MP and MN respectively.

3. The termination regulator for DDR memory with high transient response according to claim 2, characterized in that, The operational amplifier bias currents of the two error amplifiers ampA and ampB adopt a cascode structure; the NMOS power transistors MN3, MN4, MN7 and MN8 provide the bias current for the operational amplifier; the NMOS power transistors MN1 and MN2 and the PMOS power transistors MP0 and MP1 constitute the common-source common-gate input stage of the ampA, the NMOS power transistors MN5 and MN6 and the PMOS power transistors MP2 and MP3 constitute the common-source common-gate input stage of the ampB; the PMOS power transistors MP8, MP9, MP10 and MP11 constitute a low-voltage common-source common-gate current mirror to convert the double-end output of the ampA into a single-end output; the PMOS power transistors MP12, MP13, MP14 and MP15 constitute a low-voltage common-source common-gate current mirror to convert the double-end output of the ampB into a single-end output; the devices on the main path work in the sub-threshold region, and the other devices in the operational amplifier work in the saturation region.

4. The termination regulator for DDR memory with high transient response according to claim 3, wherein, The error amplifier is one of a single-stage operational amplifier, a multi-stage operational amplifier, a sleeve type operational amplifier, a folded common-source common-gate type operational amplifier, a common-source stage amplifier and an integrator.

5. The termination regulator for DDR memory with high transient response according to claim 4, wherein, The transient enhancement circuit is a kind of inverter or a bias module capable of playing a control gate function.

6. The termination regulator for DDR memory with high transient response according to claim 4, wherein, The error amplifier of the terminal regulator is a full-symmetrical architecture.

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