Method for verifying error correction circuit of static random access memory

Abstract

A method for verifying an error correction (ECC) circuit of a static random access memory includes passing original data through an error correction encoding procedure to output first data; obtaining second data according to an error embedding mask; performing a bit operation on the first data and the second data to obtain third data; writing the third data into a test target area in the static memory to become fourth data; reading the fourth data from the test target area; inputting the fourth data into an error correction decoding procedure to output fifth data and error information; and obtaining a verification result according to the fifth data, the original data, the error information, and the second data.

Description

Technical Field

[0001] A method and electronic device for processing verification data, particularly relating to a method for verifying an error correction circuit (ECC) for SRAM. Background Technology

[0002] With the rapid development of integrated circuit manufacturing processes, more electronic components can be accommodated within the same unit area. The same applies to Static Random-Access Memory (SRAM). High-capacity SRAM has a greater number of storage components per unit area, meaning a higher storage density. When writing to a particular storage component, adjacent components are more susceptible to the electrical or magnetic forces exerted during the write, making the data stored in those adjacent components prone to errors.

[0003] Generally, bit errors in SRAM can be verified using an error checking and correcting (ECC) mechanism. As the storage density of SRAM increases, the probability of bit errors also rises, making the proper functioning of the ECC mechanism even more crucial. Summary of the Invention

[0004] In view of this, according to some embodiments, the present invention provides a method for verifying SRAM and ECC errors, used to verify whether there are bit errors in the SRAM and whether the ECC circuit is operating correctly.

[0005] In some embodiments, the method for verifying SRAM and ECC errors includes the following steps: passing the original data through an error correction encoding program to output first data; passing the original data through an error correction encoding program to output first data; obtaining second data based on an error mask; performing bitwise operations on the first data and the second data to obtain third data; writing the third data to a test target area in static memory to become fourth data; reading the fourth data from the test target area; inputting the fourth data into an error correction decoding program to output fifth data and error information; and obtaining a verification result based on the fifth data, the original data, the error information, and the second data. This embodiment allows for the specification of bit error checks in a specific area or all areas of the SRAM and confirms whether the correction function of the ECC circuit is operating normally.

[0006] In some embodiments, the step of passing the original data through an error correction coding procedure to output first data includes: modulating the original data having an original bit length into first data having an operand bit length.

[0007] In some embodiments, the step of obtaining second data based on the error mask includes: setting the bit length of the error mask according to the operation bit length; selecting at least one error bit in the error mask; and writing the error data into the at least one error bit to obtain the second data.

[0008] In some embodiments, the step of obtaining the second data based on the misplacement mask further includes: repeatedly selecting other bits as at least one misplacement bit in the misplacement mask until all specific bits of the misplacement mask have been selected.

[0009] In some embodiments, the step of repeatedly selecting other bits as at least one misplaced bit in the misplaced mask includes: randomly selecting other bits in the misplaced mask that have not been selected before to obtain a new at least one misplaced bit.

[0010] In some embodiments, the step of writing third data into a test target area in static memory to become fourth data includes: selecting an address segment from the test target area, the address segment having a bit length equal to the bit length of the third data; and writing the third data into the address segment to become fourth data.

[0011] In some embodiments, the step of writing the third data into a test target area in a static memory to become the fourth data includes: obtaining the start address and end address of the static memory; using the start address to the end address as the test target area, wherein the bit length of the test target area is greater than or equal to the bit length of the third data.

[0012] In some embodiments, the step of writing the third data into a test target area in a static memory to become the fourth data further includes: selecting an address segment from the test target area, wherein the bit length of the address segment is the same as the bit length of the third data; and writing the third data into the address segment to become the fourth data.

[0013] In some embodiments, the step of writing third data into an address segment to become fourth data includes: repeatedly selecting another address segment at a different location in the test target area until all specific addresses in the test target area have been selected.

[0014] In some embodiments, the step of repeatedly selecting another address segment at a different location in the test target area includes obtaining another address segment by starting from the address segment and offsetting by a second incremental distance.

[0015] In some embodiments, the step of repeatedly selecting another address segment at a different location within the test target area includes: randomly selecting another address segment from the test target area that has not been selected before.

[0016] In some embodiments, bitwise operations are selected from mutual exclusion operations or distinct mutual exclusion operations.

[0017] According to some embodiments, the verification method for the static random access memory (SRAM) error correction circuit can check for bit errors in a specified area or all areas, and also verify whether the error correction circuit of the ECC circuit is operating correctly. In some embodiments, this verification method can perform synchronous or batch checks, which can save checking time and reduce hardware setup costs compared to traditional time-sharing checks. Attached Figure Description

[0018] To make the above and other objects, features, advantages and embodiments of this application more apparent and understandable, the accompanying drawings are described below:

[0019] Figure 1 This is a schematic diagram of the system architecture according to an embodiment of the present invention;

[0020] Figure 2A This is a schematic flowchart illustrating a verification method for the error correction circuit of a static random access memory (SRAM) according to one embodiment.

[0021] Figure 2B This is a schematic diagram illustrating the generation of various data in one embodiment;

[0022] Figure 3 This is a schematic diagram of a misplaced mask and misplaced placement in one embodiment;

[0023] Figure 4 This is a schematic diagram of the process for obtaining second data according to one embodiment;

[0024] Figure 5A This is a schematic diagram illustrating the operation process of selecting misaligned burial sites according to one embodiment;

[0025] Figure 5B This is a schematic diagram illustrating the single-buried misalignment and displacement processing in different configuration rounds of one embodiment.

[0026] Figure 5C This is a schematic diagram illustrating the handling of multiple misalignments and displacements in different configuration rounds of an embodiment.

[0027] Figure 5D This is a schematic diagram of the process for selecting a new location for burying faulty bits, as shown in one embodiment.

[0028] Figure 6A This is a schematic diagram of the process for selecting a test target area in one embodiment;

[0029] Figure 6B This is a schematic diagram of the test target area and starting address in one embodiment;

[0030] Figure 6C This is a schematic diagram of the process for selecting a test target area in one embodiment;

[0031] Figure 7A This is a schematic diagram of the address segment selection process in one embodiment;

[0032] Figure 7B This is a schematic diagram of the address segments for different operating rounds in one embodiment;

[0033] Figure 8A This is a schematic diagram of the address range and embedded misalignment of the operation round and setting round in one embodiment;

[0034] Figure 8B This is a schematic diagram of the address segments and embedded misalignments of an operation round and a setting round in one embodiment;

[0035] Figure 8C This is a schematic diagram of the address segments and embedded misalignments of an operation round and a setting round in one embodiment;

[0036] Figure 8D This is a schematic diagram of the address segment and embedded misalignment of another operation round and setting round in one embodiment;

[0037] Figure 8E This is a schematic diagram of the address segment and embedded misalignment for another operation round and another setting round in one embodiment;

[0038] Figure 8F This is a schematic diagram of the address segment and embedded misalignment for another operation round and another setting round in one embodiment. Detailed Implementation

[0039] The term "coupled" as used in this article can also refer to "electrical coupling," and the term "connection" can also refer to "electrical connection." "Coupled" and "connection" can also refer to the cooperation or interaction of two or more components.

[0040] Please refer to Figure 1 The diagram shown illustrates a system architecture according to an embodiment of the present invention. The static random access memory 100 of this embodiment includes memory cells 110, an error checking and correcting (ECC) circuit 120, and a checking circuit 130. The static random access memory 100 (or memory cell 110) can be verified by external devices or by the static random access memory 100 itself. A memory cell 110 is a single memory chip or a collection of multiple memory chips. The storage space of a memory cell 110 is determined by the number of memory chips. Each memory cell 110 has a memory space 111. The memory space 111 includes a test target area 112, which is used to verify whether a bit error exists in the memory cell 110 to which it belongs. The method for selecting the test target area 112 will be described later.

[0041] ECC circuit 120 is coupled to memory cell 110. ECC circuit 120 receives raw data and outputs the first data. Generally, ECC algorithms can be broadly classified into block code and convolution code error correction algorithms. Block code ECC algorithms include Gray code, BCH code (Bose–Chaudhuri–Hocquenghem codes), multidimensional parity-check code, and Hamming code, but are not limited to these. Convolutional codes include the Viterbi algorithm. ECC circuit 120 can use either block code or convolutional code ECC error correction algorithms. ECC circuit 120 can be used to execute error correction coding and error correction decoding procedures. Besides the aforementioned ECC algorithms, the error correction coding and decoding procedures can also use other algorithms capable of detecting and correcting errors. Error correction coding procedure 121 and error correction decoding procedure 122 generally employ the same ECC error correction algorithm.

[0042] The verification circuit 130 is coupled to the memory cell 110 and the ECC circuit 120. When the static random access memory 100 is in test mode, the verification circuit 130 can verify bit errors in the memory cell 110 and verify the operation of the ECC circuit 120. The verification circuit 130 can perform relevant verification processing on the memory cell 110 and the ECC circuit 120 based on the raw data. Please cooperate with... Figure 2A and Figure 2B The document describes a verification method for an SRAM error correction circuit according to an embodiment, including a flowchart and a diagram illustrating the generation of data within the verification method. The verification method for the SRAM error correction circuit includes the following steps:

[0043] Step S210: The original data is processed by an error correction coding procedure to output the first data;

[0044] Step S220: Obtain the second data based on the misplaced mask;

[0045] Step S230: Perform bitwise operations on the first data and the second data to obtain the third data;

[0046] Step S240: Write the third data to the test target area in the storage unit;

[0047] Step S250: Read the fourth data from the test target area;

[0048] Step S260: The fourth data is processed by an error correction decoding program to output the fifth data and error information; and

[0049] Step S270: Obtain the verification result based on the fifth data, the original data, the error message, and the second data.

[0050] First, the checking circuit 130 determines whether the static random access memory 100 is in test mode. If the static random access memory 100 is in test mode, the checking circuit 130 generates raw data. The checking circuit 130 can generate a set of raw data through random computation. The type of random algorithm can be, but is not limited to, the Monte Carlo method, the linear congruential generator (LCG), or the middle-square method. Generally, the bit length of the raw data is not limited, but it must be at least two bits. The checking circuit 130 sends the raw data to the ECC circuit 120, so that the ECC circuit 120 can input the raw data into the error correction encoding program 121 to output the first data. Figure 2B As shown.

[0051] The bit length of the first data is the operand length. Generally, the operand length can be equal to the original bit length of the original data. However, in some embodiments, the ECC circuit 120 can modulate the length of the original data according to the requirements of the error correction coding program 121. The error correction coding program 121 modulates the original bit length of the original data to the operand length of the first data. Figure 2B In the text box, the dashed text box represents the action / program executed after the target object is input.

[0052] For example, if the original data has an original bit length of 8 bits and its content is "1010 1010", when the original data is input into the error correction encoding program 121, the error correction encoding program 121 can output the first data "01011 1010 1010" with a length of 13 bits (i.e., the length of the operation bits).

[0053] Next, the inspection circuit 130 obtains the second data based on the error mask 113. The length of the error mask 113 corresponds to the length of the operands. Please refer to the diagram. Figure 3 As shown. Taking the bit length of the operation mentioned in the previous paragraph as an example, the error mask 113 corresponds to a length of 13 bits. Figure 3 The error mask 113 shown is composed of "0" and "1", where "0" represents a bit position where no data is written and "1" represents a bit position where data can be written, also known as error mask 114. The number of error masks 114 is greater than or equal to one. Figure 3The error location 114 is marked with a gray dashed box. The inspection circuit 130 can perform a bitwise operation between any data and the error mask 113 to obtain the second data. Alternatively, the inspection circuit 130 can write an erroneous data into the error location 114 and directly treat the modified error mask 113 as the second data. Or, multiple erroneous data can be written separately to their corresponding error locations, making the modified error mask 113 the second data. In this case, the inspection circuit 130 also records the position of the error location 114 within the second data.

[0054] Generally, the misplacement mask 113 may include at least one misplacement position 114, and multiple misplacement positions 114 may not necessarily be adjacent. In this embodiment, a single check of the ECC circuit 120 is used as an example. In other embodiments, the position of the misplacement position 114 may be adjusted in different check rounds, and the operation mode of multiple rounds will be described later.

[0055] The inspection circuit 130 performs a bit operation on the first data and the second data to obtain the third data. In some embodiments, the bit operation is selected from the exclusive-OR (XOR) operation. Continuing with the previous example, if the first data is "01011 1010 1010" and the second data is "00000 0000 0001", the inspection circuit 130 performs an XOR operation on the first data and the second data to obtain the third data "01011 1010 1011". The inspection circuit 130 writes the third data into the test target area 112 of the storage unit 110. To distinguish the data before and after writing to the test target area 112, the third data after being written to the test target area 112 is referred to as the fourth data. Figure 2B As shown.

[0056] The inspection circuit 130 reads the fourth data from the test target area 112. The inspection circuit 130 drives the ECC circuit 120 to perform an error correction decoding program 122 on the fourth data, which outputs the fifth data and error information. The error information includes "unit error" and "multiple bit error". The inspection circuit 130 obtains the verification result based on the fifth data, the original data, the error information, and the second data. The verification result records whether the ECC circuit 120 is operating normally; it may also include the ECC error correction result and the bit count error result. The inspection circuit 130 can obtain the ECC error correction result based on the fifth data and the original data. The inspection circuit 130 can obtain the bit count error result based on the error information and the second data.

[0057] In the previous example, the error mask 113 is "00000 0000 0001". Therefore, the inspection circuit 130 will write error data at the error location 114 to generate the second data "00000 0000 0001". If the third data written to the test target area 112 is "01011 1010 1011", the fourth data read from the test target area 112 is "01011 1010 1011". The ECC circuit 120 performs an error correction decoding procedure 122 on the fourth data and obtains the fifth data "1010 1010" and error information (e.g., unit error or multiple bit error). In some embodiments, information about unit errors and information about multiple bit errors can be represented in the following ways: (1) by two independent bits, one bit of which is used to represent unit error information, for example, a value of 0 indicates no unit error and a value of 1 indicates a unit error; the other bit is used to represent multiple bit errors, for example, a value of 0 indicates no multiple bit error and a value of 1 indicates multiple bit errors. Or (2) by two associated bits, for example, a value of 00 indicates no bit error, 01 indicates a unit error, and 11 indicates multiple bit errors, but not limited to this.

[0058] The inspection circuit 130 compares the fifth data with the original data and obtains the ECC error correction result. If the fifth data is the same as the original data, the ECC error correction result is "correction correct," indicating that the ECC circuit 120's bit correction function is normal. The inspection circuit 130 compares the second data with the error information and obtains the bit error counting result. Since only one erroneous data is added to the error mask 113, the inspection circuit 130 can detect at least one error. If the bit error counting result is "unit error," it indicates that the ECC circuit 120's error bit checking function is normal. Therefore, the verification result can be recorded as "ECC circuit 120 is operating normally." Moreover, the bits in other locations in the test target area 112 can also be accessed normally.

[0059] Furthermore, if the bit error result is "unit error" and the fifth data differs from the original data, it indicates that the ECC circuit 120 has malfunctioned. The inspection circuit 130 will output a verification result of "ECC circuit 120 malfunction".

[0060] If the bit error result is "multiple bit errors", it means that the ECC circuit 120 is malfunctioning or there are other bit errors in the test target area 112 (because the error mask 113 only adds one erroneous data). Therefore, in the case of "multiple bit errors", regardless of whether the fifth data is the same as the original data, the inspection circuit 130 will output the verification result of "ECC circuit 120 malfunctioning".

[0061] In some embodiments, the inspection circuit 130 can adjust the position of the misplaced bit 114 according to the bit length of the misplaced mask 113 and the set round. Please cooperate. Figure 4 This is a schematic diagram of a process for obtaining second data according to some embodiments, and the process further includes the following steps:

[0062] Step S221: Set the bit length of the error mask according to the operation bit length;

[0063] Step S222: Select at least one misplaced position in the misplacement mask;

[0064] Step S223: Write the erroneous data to at least one misaligned position to obtain the second data; and

[0065] Step S224: Repeatedly select other bits as at least one misplaced bit in the misplaced mask until all specific bits of the misplaced mask have been selected.

[0066] First, the inspection circuit 130 determines the bit length of the error mask 113 based on the bit length of the first data, ensuring that the bit length of the first data matches that of the error mask 113. In other words, the bit lengths of the first data and the second data are also consistent. The inspection circuit 130 selects at least one error-burying bit 114 of a specific bit length from the error mask 113. Therefore, each setting of the error-burying bit 114 is referred to as a setting round. After each setting round, the inspection circuit 130 can generate a new set of second data. In other words, the inspection circuit 130 can generate a corresponding number of second data sets based on the number of setting rounds.

[0067] For example, if the error mask 113 is 13 bits long, the inspection circuit 130 selects one bit as the error-hiding bit 114. Therefore, the inspection circuit 130 will perform 13 rounds of setting the error-hiding bit 114 and obtain 13 sets of second data (including the aforementioned). Figure 3 (Second data in the embodiment). The checking circuit 130 generates corresponding third data based on the obtained second data.

[0068] In some embodiments, the inspection circuit 130 can select the buried misalignment 114 to obtain the second data in the following manner, please refer to Figure 5A As shown. Figure 5A This is a schematic diagram of the operation process for selecting misaligned burial sites according to an embodiment, which includes the following steps:

[0069] Step S511: Select the displacement direction of the misalignment;

[0070] Step S512: Check the circuit to obtain a new at least one misplaced position by starting from at least one buried misplaced position and offsetting by a first incremental distance; and

[0071] Step S513: Repeat the offsetting of the misplacement until each specific position in the misplacement mask is considered as a misplacement at least once.

[0072] The inspection circuit 130 selects the displacement direction of the misplaced bit 114, which can include left shift or right shift. After the setting round ends, the inspection circuit 130 will use the current misplaced bit 114 as the starting point and move it by a first incrementing distance. The bit position obtained after moving the first incrementing distance is the new position of the misplaced bit 114. In the next setting round, the inspection circuit 130 will perform the aforementioned verification with the new misplaced bit 114. Basically, the minimum movement distance of the first incrementing distance is 1 bit.

[0073] Please refer to Figure 5B The diagram illustrates the handling of a single misplacement and displacement in different configuration rounds according to one embodiment. If the number of misplacements 114 is one, and the first increment distance is one position, the displacement direction is right displacement (indicated by a black arrow). Figure 5B The above shows the positions of the misplacement mask 113 and misplacement position 114 when setting round (X). Figure 5B Below are the positions of the error mask 113 and the error bit 114 when setting round (X+1), where X represents the round number. When the specific position in the aforementioned error mask is all the positions in the error mask 113, the checking circuit 130 will repeat the right shift of the error bit 114 until the error bit 114 has been traversed through all the bits in the error mask 113 (i.e., all the bits in the error mask 113 have been used as the error bit 114 at least once). If the error bit 114 reaches the boundary of the error mask 113 (e.g., the right boundary of the 13th bit) during the shift, the error bit 114 will move into the error mask 113 from the other boundary of the error mask 113 (e.g., the left boundary of the 1st bit), so that the error bit 114 forms a cyclic movement in the error mask 113.

[0074] Similarly, the left displacement of the misplaced position 114 is handled in the same way, and will not be described again. In some embodiments, for multiple misplaced positions 114, the displacement method is based on the principle of non-repeating positions. In other words, the misplaced positions 114 in setting round (Y) and setting round (Y+1) can be completely non-repeating. Please refer to [reference needed]. Figure 5C As shown, Y represents the number of rounds to be set. The inspection circuit 130 can use the error mask 113 itself as the second data, or it can perform an exclusive operation between the error mask 113 and other data to obtain the second data. For ease of explanation, the error mask 113 will be directly regarded as the second data below.

[0075] In some embodiments, the inspection circuit 130 may also select the location of the new buried misalignment 114 to obtain the second data in the following manner: Please refer to [reference needed]. Figure 5D As shown. The process for selecting a new location for the misalignment 114 according to some embodiments includes the following steps:

[0076] Step S521: Check the circuit to randomly select other bits in the misplaced mask that have not been selected before to obtain at least one new misplaced bit; and

[0077] Step S522: Repeat the random selection of misplacement until each specific position in the misplacement mask is considered as a misplacement at least once.

[0078] The inspection circuit 130 selects the misplaced bit 114 from the misplaced mask 113 using a random selection algorithm. The inspection circuit 130 randomly selects bits from the misplaced mask 113 that have not been used as the misplaced bit 114. At the end of a setup round, the inspection circuit 130 may randomly select any bit from the remaining bits as the new position for the misplaced bit 114. At the start of the next setup round, the inspection circuit 130 will verify using the new misplaced bit 114. When a specific position in the aforementioned misplaced mask 113 is one of all positions in the misplaced mask 113, the inspection circuit 130 records the misplaced bit 114 and its position set in each setup round until all bits in the misplaced mask 113 have been used as the misplaced bit 114 at least once. Alternatively, at the beginning of a new setup round, the inspection circuit 130 may randomly select a new misplaced bit 114 from the remaining bits.

[0079] In some embodiments, the inspection circuit 130 can select the test target area 112 in the storage unit 110 in the following manner. Please refer to... Figure 6A and Figure 6B The figures shown are a flowchart illustrating the selection of a test target area according to one embodiment and a diagram illustrating the test target area and the starting address, respectively. The process for selecting the test target area 112 according to one embodiment includes the following steps:

[0080] Step S611: Select a memory address from the memory cell; and

[0081] Step S612: Use the memory address as the starting address of the test target area, and the bit length of the test target area is the same as the bit length of the third data.

[0082] The inspection circuit 130 randomly selects any memory address in the storage cell 110 and obtains the test target area 112 based on the bit length of the fault mask 113 and the selected memory address. Figure 6BThe dark gray area is designated as the test target area 112, and the arrow indicates the starting address of the memory address of the test target area 112. The inspection circuit 130 performs ECC circuit 120 and related verification processing on the test target area 112. For example, if the error mask 113 is 13 bits long, when the inspection circuit 130 selects memory location "0X0010F000", the range of the test target area 112 is "0X0010F000" to "0X0010F00D".

[0083] In some embodiments, the inspection circuit 130 can select different ranges of test target areas 112. Please refer to... Figure 6C This is a schematic diagram of the process for selecting a test target area according to one embodiment. The process for selecting the test target area 112 according to one embodiment includes the following steps:

[0084] Step S621: Check the circuit to obtain the start and end addresses of the memory cell; and

[0085] Step S622: Set the space from the start address to the end address as the test target area.

[0086] The inspection circuit 130 selects a start address and an end address from the memory cell 110, and considers the memory segment between the start address and the end address as the test target area 112. The length of the test target area 112 depends on the bit length of the error mask 113. In other words, the length of the test target area 112 is greater than the bit length of the error mask 113. The inspection circuit 130 can set the test target area 112 to the entire memory space 111 of the memory cell 110 under test.

[0087] In some embodiments, the location within the test target area 112 where the third data is written is determined. After the inspection circuit 130 determines the range of the test target area 112, the inspection circuit 130 selects an address segment 115 within the test target area 112. The bit length of the address segment 115 is equal to the operand length (also the length of the third data). The inspection circuit 130 writes the third data into the selected address segment 115, thus making the third data the fourth data.

[0088] In some embodiments, the checking circuit 130 may select address segments 115 at different locations in different operating rounds. An operating round is the process by which the checking circuit 130 verifies each address segment 115. In another operating round, the checking circuit 130 selects another address segment 115 from the test target area 112. The checking circuit 130 repeats this process of selecting another address segment 115 at a different location in the test target area 112 until a specific location (e.g., all locations) in the test target area 112 has been written.

[0089] In some embodiments, the inspection circuit 130 can select the address segment 115 from the test target area 112 in the following manner. Please refer to... Figure 7A . Figure 7A This is a schematic diagram of an address segment selection process according to one embodiment. The process for selecting address segment 115 according to one embodiment includes the following steps:

[0090] Step S711: Select the displacement direction of the address segment; and

[0091] Step S712: Obtain another address segment by starting from the address segment and offsetting by a second incremental distance; and

[0092] Step S713: Repeat selecting another address segment in the test target area until a specific location in the test target area has been written.

[0093] The checking circuit 130 selects the displacement direction of address segment 115, which can be either left or right displacement. Before the end of the operating round, the checking circuit 130 uses the current address segment 115 as a starting point and offsets it by a second incremental distance according to the displacement direction to obtain another address segment 115. The second incremental distance is determined based on the bit length of address segment 115 to ensure that address segments 115 from previous and subsequent rounds do not overlap. At the start of the next operating round, the checking circuit 130 performs the write processing for the new operating round based on the new address segment 115.

[0094] Please refer to Figure 7B As shown, in Figure 7B The top section represents the operating round (Y). Figure 7B Below is the operation round (Y+1), used to indicate the previous and next operation rounds. Test target area 112 is a diagonal block from the upper left to the lower right, and address segment 115 is a diagonal block from the upper right to the lower left. The direction of the black solid arrow indicates the displacement direction. If the inspection circuit 130 selects a left displacement, and the second increment distance is 1 operand length, in operation round (Y+1), the inspection circuit 130 will move address segment 115 to the left, as follows: Figure 7B As indicated by the white arrow in the diagram. Check the processing of the repeated address segment 115 offset in circuit 130 until all positions in the test target area 112 have been traversed.

[0095] In some embodiments, the checking circuit 130 selects a new address segment 115 in a random manner. Essentially, the checking circuit 130 selects a new address segment 115 from memory locations in the test target area 112 that have not been selected before. After each operating round, the checking circuit 130 records the selected address segments 115. The checking circuit 130 repeats the random selection of address segments 115 until all locations in the test target area 112 have been traversed.

[0096] The inspection circuit 130 can form a nested loop through different operation rounds and setting rounds, and can verify each bit of the test target area 112 and address segment 115. Please refer to... Figures 8A to 8F As shown, in Figures 8A to 8F The middle section represents the SRAM memory space 111. The test target area 112 is an example of a diagonal block from the upper left to the lower right, the address segment 115 is an example of a diagonal block from the upper right to the lower left, and the grid area represents the embedded error 114. Generally, the value written to the address segment 115 is the third data, not the embedded error mask 113 itself. However, to clearly illustrate the operating sequence, the value of the embedded error mask 113, including the embedded error 114, is used as an example of the third data for explanation.

[0097] exist Figure 8A The table above records the current round number of the operation round (A) and the setting round (B) of the inspection circuit 130. To clearly represent the operation of each operation round and setting round, Ax is defined as an operation round where x is the round number of the operation round, and By is a setting round where y is the round number of the setting round. Figure 8A For example, the inspection circuit 130 checks the operation round (A1) and the setting round (B1). For simplicity, the rounds (Ax, By) mentioned below refer to the combined operation round and the setting round.

[0098] In the setup round (B1), the initial position of the embedded misalignment bit 114 is the littleendian region of address segment 115, and there is a one-bit interval between two embedded misalignment bits 114. Figure 8A The black arrow in the diagram indicates the left offset direction of the misplaced bit 114, and the first increment distance is 1 bit. This means that the misplaced bit 114 moves from the low bit area to the high bit area (big endian). In the setting round (B1), the checking circuit 130 outputs the verification result corresponding to that round (A1, B1).

[0099] Figure 8B When setting round (B2), the offset bit 114 is embedded at a new position in address segment 115. During setting round (B2), the checking circuit 130 outputs the verification result corresponding to round (A1, B2). The checking circuit 130 repeats the offset and setting of the offset bit 114 in address segment 115 and obtains the verification result for each setting round (By). Assume the total number of setting rounds By is m, and the total number of operating rounds Ay is n. Figure 8C After m rounds of setting, the inspection circuit 130 will traverse all positions in the address segment 115.

[0100] Figure 8D and Figure 8E The diagrams illustrate the positions of the misplaced bit 114 in different operation rounds (A2) for address segment 115. In rounds (A2, B1), address segment 115 is shifted left by one operand length (i.e., the aforementioned second incrementing distance), and the misplaced bit 114 is set in the lower-order region of address segment 115. In rounds (A2, B2), the misplaced bit 114 is shifted left by the first incrementing distance, as shown below. Figure 8E As shown. The inspection circuit 130 repeats the offset processing of the buried misalignment 114 until all bits in the address segment 115 are traversed, and then offsets the address segment 115 to the next position. After round (A2, Bm) ends, the inspection circuit 130 shifts the address segment 115 to the left to the next position.

[0101] Please refer to Figure 8F The diagram shows the locations of address segment 115 and embedded bit 114 during the operation round (An) and setup round (Bm). Upon completion of the operation round (An) and setup round (Bm), the inspection circuit 130 obtains the verification results (number of m*n) of each bit in the test target area 112 and the ECC circuit 120. Therefore, the inspection circuit 130 can confirm the bit error locations of the SRAM and whether the ECC circuit 120 is functioning correctly based on the verification results.

[0102] The present invention provides a method for verifying SRAM and ECC errors. The static random access memory (SRAM) can perform bit error checks on a specified area or all areas of the SRAM, and simultaneously verify the correct operation of the ECC circuit. Because the present invention's method for verifying SRAM and ECC errors can perform synchronous and batch checks, it saves checking time and hardware costs compared to traditional time-sharing checks.

[0103] Explanation of reference numerals in the attached figures:

[0104] 100: Static Random Access Memory

[0105] 110: Storage unit

[0106] 111: Memory Space

[0107] 112: Test target area

[0108] 113: Misplaced Mask

[0109] 114: Misplaced

[0110] 115: Address Range

[0111] 120: ECC circuit

[0112] 121: Error Correction Coding Program

[0113] 122: Error Correction Decoding Program

[0114] 130: Check the circuit

[0115] S210~S270: Procedure Flow

[0116] S221~S223: Procedure Flow

[0117] S511~S513: Procedure Flow

[0118] S521~S522: Procedure Flow

[0119] S611~S612: Procedure Flow

[0120] S621~S622: Procedure Flow

[0121] S711~S713: Procedure Flow

Claims

1. A verification method for the error correction circuit of a static random access memory, comprising: A raw data is processed by an error correction coding program to output a first data; A second set of data is obtained based on a misplaced mask; Perform a bitwise operation between the first data and the second data to obtain a third data; The third data is written into a test target area of ​​a static memory to become a fourth data; Read the fourth data from the test target area; The fourth data is input into an error correction decoding program to output a fifth data and an error message; as well as Based on the fifth data, the original data, the error message, and the second data, a verification result is obtained. The step of passing the original data through the error correction coding procedure to output the first data includes: modulating the original data having an original bit length into the first data having an operand bit length. The step of obtaining the second data based on the error mask includes: The length of one bit of the error mask is set according to the length of the operation bit; Select at least one misplacement in the misplacement mask; and An erroneous data is written into the at least one embedded misalignment to obtain the second data.

2. The verification method for the error correction circuit of the static random access memory according to claim 1, characterized in that, The step of obtaining the second data based on the embedded mask further includes: Repeat the process of selecting other bits as the at least one misplaced bit in the misplaced mask until all specific bits of the misplaced mask have been selected.

3. The verification method for the error correction circuit of the static random access memory according to claim 2, characterized in that, Repeating the step of selecting other bits as the at least one misplaced bit in the misplaced mask includes: Starting from the at least one misplaced position and offset by a first incremental distance, a new at least one misplaced position is obtained.

4. The verification method for the error correction circuit of the static random access memory according to claim 2, characterized in that, Repeating the step of selecting other bits as the at least one misplaced bit in the misplaced mask includes: Randomly select other bits in the misplaced mask that have not been selected before to obtain a new misplaced bit.

5. The verification method for the error correction circuit of the static random access memory according to claim 1, 2, 3 or 4, characterized in that, The step of writing the third data into the test target area in the static memory to become the fourth data includes: Select a memory address from the static memory; and The memory address is used as a starting address of the test target area, and the bit length of the test target area is the same as the bit length of the third data.

6. The verification method for the error correction circuit of the static random access memory according to claim 5, characterized in that, The step of writing the third data into the test target area in the static memory to become the fourth data further includes: Select an address segment from the test target area, wherein the bit length of the address segment is the same as the bit length of the third data; and The third data is written into the address segment to become the fourth data.

7. The verification method for the error correction circuit of the static random access memory according to claim 1, 2, 3 or 4, characterized in that, The step of writing the third data into the test target area in the static memory to become the fourth data further includes: Obtain a start address and an end address of the static memory; and The starting address to the ending address is taken as the test target area, and the bit length of the test target area is greater than or equal to the bit length of the third data.

8. The verification method for the error correction circuit of the static random access memory according to claim 6, characterized in that, The step of writing the third data into the test target area in the static memory to become the fourth data further includes: Repeat the process of selecting another address segment at a different location within the test target area until all specific addresses within the test target area have been selected.

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