fusible link programming unit, programming circuit, control circuit and array

Abstract

The application discloses a fuse programming unit, a programming circuit, a control circuit and an array, comprising two efuse units and a mode control tube; the first efuse unit comprises a first fuse, a first end of the first fuse constituting a first bit line of the fuse programming unit, a second end of the first fuse being connected with a drain end of a first MOS; a source end of the first MOS being connected with a ground, and a gate end of the first MOS constituting a first word line of the fuse programming unit; the second efuse unit comprises a second fuse, a first end of the second fuse constituting a second bit line of the fuse programming unit, a second end of the second fuse being connected with a drain end of a second MOS; a source end of the second MOS being connected with the ground, and a gate end of the second MOS constituting a second word line of the fuse programming unit; and the mode control tube, a drain end of the mode control tube being connected with the bit line of the first efuse unit, a source end of the mode control tube being connected with the bit line of the second efuse unit, and a gate end of the mode control tube constituting a correction signal of the fuse programming unit. The application improves the use flexibility of the fuse programming unit array, and realizes the redundancy correction function of each storage bit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a fuse programming unit. It also includes a fuse programming circuit, a control circuit for the fuse programming unit, and an array of fuse programming units. Background Technology

[0002] eFuse is based on the principle of electromigration (EM) and achieves programming functionality by blowing a fuse. Essentially, the internal read module of eFuse converts the fuse resistance value into a corresponding logic value. Specifically, a comparator circuit compares the fuse resistance before and after the fuse blown with a reference resistance to generate different logic levels. However, during programming, unexpected events may occur, such as the fuse not blowing or the resistance being too low after programming, leading to the read module outputting incorrect logic values.

[0003] A typical efuse unit consists of one fuse link and one NMOS control select transistor, such as... Figure 1 As shown.

[0004] An array composed of conventional efuse cells, such as Figure 2 As shown, the array consists of bit lines BL and word lines WL. Each column of bit lines in the array is connected to an SA module via an NMOS read select transistor Nsa, with the gate control signal of Nsa being RD. Each word line in the array is connected to the gate of the control select transistor of the efuse cell in the same row, while each column of bit lines is connected to the fuse of the efuse cell in the same column. Each column of bit lines in the array is connected to the programming power supply VDDQ via a PMOS power select transistor Mpn, with its gate controlled by a BLC signal.

[0005] During programming, in a standard efuse cell array, RD=0 disables the path from all bit lines BL to the SA module. One bit line control signal BLC in the array is 0, opening the path from VDDQ to that bit line BL, making the voltage of BL VDDQ. Other bit line control signals BLC are VDDQ, disabling the path from VDDQ to BL. One word line WL in the array is selected, with a voltage of VDDQ, turning on the NMOS select transistors of all efuse cells in that row. Other word lines WL are not selected, with a voltage of 0, turning off the NMOS select transistors of all efuse cells in that row. A VDDQ-to-ground path is formed in the efuse cell between the bit line BL and the word line WL (both with VDDQ). Programming current flows through the fuse link, programming the cell by blowing the fuse. Other efuse cells do not have a VDDQ-to-ground path and remain in a non-programmable state.

[0006] To correct the output of the efuse cell during programming, the conventional method is to add redundant correction bits in addition to the normal storage bits. By programming these redundant correction bits, the address information of the bit to be corrected and the correct value are recorded in the redundant area. During a read operation, if the input address contains an error, the system ignores the error value stored at that address and reads the preset correct value from the redundant area, effectively correcting the error. This correction method uses indirect correction, meaning that to correct one error bit, it requires a dozen or so bits to store the address and correct value information of that error bit. Therefore, it occupies a large amount of redundant area, has a very limited correction range, and results in complex circuit and layout design and low reliability. Summary of the Invention

[0007] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0008] The first technical problem to be solved by the present invention is to provide a novel fuse programming unit.

[0009] In addition, a fuse programming circuit, a control circuit for the fuse programming unit, and an array of fuse programming units.

[0010] To solve the above-mentioned technical problems, the present invention provides a fuse programming unit, comprising:

[0011] Two efuse units and one mode control tube Nsw;

[0012] The first efuse unit includes:

[0013] The first fuse link1 has its first end forming the first connection terminal of the fuse programming unit, which is connected to the first bit line BL1, and its second end is connected to the drain terminal of the first MOSN1.

[0014] The first MOSN1 has its source end connected to ground and its gate end forming the second connection terminal of the fuse programming unit. The second connection terminal is connected to the first word line WLo.

[0015] The second efuse unit includes:

[0016] The second fuse link2 has its first end forming the third connection terminal of the fuse programming unit. The third connection terminal is connected to the second bit line BL2, and its second end is connected to the drain terminal of the second MOSN2.

[0017] The second MOSN2, whose source end is connected to ground, and whose gate end constitutes the second word line WLe of the fuse programming unit;

[0018] The mode control transistor Nsw has its drain connected to the bit line BL1 of the first efuse unit, its source connected to the bit line BL2 of the second efuse unit, and its gate constitutes the correction signal REWL of the fuse programming unit.

[0019] Among them, the first MOSN1, the second MOSN2 and the mode control transistor Nsw are NMOS.

[0020] The fuse programming unit provided by this invention consists of two efuse units and one NMOS transistor, forming a 5-port device BL1, BL2, REWL, WLo, WLe, as shown below. Figure 3 As shown. The first efuse unit consists of fuse link1 and control transistor N1, and the second efuse unit consists of fuse link2 and control transistor N2. One end of fuse link1 forms the BL1 port of the unit, and one end of fuse link2 forms the BL2 port of the unit. Between BL1 and BL2, the drain and source terminals of the NMOS transistor Nsw (used for mode control) are connected, and its gate terminal forms the REWL port of the unit. The other end of fuse link1 is connected to the drain terminal of control transistor N1, and the source terminal of N1 is grounded. The other end of fuse link2 is connected to the drain terminal of control transistor N2, and the source terminal of N2 is grounded. The gate terminal of control transistor N1 forms the WLo port of the unit, and the gate terminal of control transistor N2 forms the WLe port of the unit.

[0021] To solve the above-mentioned technical problems, the present invention provides a fuse programming circuit for the fuse programming unit, further comprising:

[0022] The first power control transistor Mp1 has its drain terminal connected to the first bit line BL1 of the fuse programming unit, its gate terminal connected to the first programming control signal BLC1, and its source terminal connected to the programming power supply VDDQ.

[0023] The first read control transistor Mn1 has its drain end connected to the first bit line BL1 of the fuse programming unit, its gate end connected to the first read control signal RDR, and its source end connected to the first SA module SA1.

[0024] The second power control transistor Mp2 has its drain end connected to the second bit line BL2 of the fuse programming unit, its gate end connected to the second programming control signal BLC2, and its source end connected to the programming power supply VDDQ.

[0025] The second read control transistor Mn2 has its drain end connected to the second bit line BL2 of the fuse programming unit, its gate end connected to the second read control signal RD, and its source end connected to the second SA module SA2.

[0026] Among them, the first power control transistor Mp1 and the second power control transistor Mp2 are PMOS, and the first read control transistor Mn1 and the second read control transistor Mn2 are NMOS.

[0027] The present invention provides a fuse programming circuit, such as... Figure 4 As shown, by Figure 3 The port BL1 of the shown fuse programming unit is connected to the drain of the power control transistor Mp1 and the drain of the read control transistor Mn1, respectively. The source of Mp1 is connected to the programming power supply VDDQ, and the source of Mn1 is grounded. The gate of Mp1 is connected to the programming control signal BLC1, and the gate of Mn1 is connected to the read control signal RDR. The port BL2 of the basic unit is connected to the drain of the power control transistor Mp2 and the drain of the read control transistor Mn2, respectively. The source of Mp2 is connected to the programming power supply VDDQ, and the source of Mn2 is grounded. The gate of Mp2 is connected to the programming control signal BLC2, and the gate of Mn2 is connected to the read control signal RD. The REWL, WLo, and WLe ports of the basic unit are connected to their respective control signals.

[0028] To solve the above technical problems, the present invention provides a control circuit for the programming circuit of the fuse, comprising:

[0029] An AND gate and an inverter;

[0030] An inverter, whose input terminal serves as the first input terminal of the control circuit, is connected to the correction signal REWL and the correction control signal RE of the fuse programming unit.

[0031] The AND gate has its second input terminal as the second input terminal of the control circuit. The second input terminal is connected to the second word line WLe and the word control signal WL of the fuse programming unit, and its output terminal is connected to the first word line WLo of the fuse programming unit.

[0032] The correction control signal RE is used to control the switching between correction mode and normal mode.

[0033] When the correction control signal RE is 1, the correction mode is entered, the correction signal REWL input of the fuse programming unit is 1, and the first word line WLo input of the fuse programming unit is 0.

[0034] When the correction control signal RE is 0, the system enters the normal mode. The correction signal REWL input of the fuse programming unit is 0, the first word line WLo input of the fuse programming unit is the word control signal WL, and the second word line WLe input of the fuse programming unit is always the word control signal WL.

[0035] This invention provides a control circuit such as Figure 5As shown, it consists of an AND gate and an inverter, with input signals WL (word control) and RE (correction control). Signal RE controls the switching between correction mode and normal mode. When RE=1, it enters correction mode, with REWL outputting 1 and WLo outputting 0; when RE=0, it enters normal mode, with REWL outputting 0 and WLo outputting WL. WLe remains WL in all modes.

[0036] To solve the above-mentioned technical problems, the present invention provides a fuse programming unit array, which consists of n rows of fuse programming circuits and n control circuits, each row including at least two fuse programming circuits and each row including one control circuit, where n≥1.

[0037] The first read operation mode includes: when the nth programming control signal BLCn is 1, disconnecting all programming power supplies VDDQ and the power control transistor MPn between bit lines BL1~BLn;

[0038] When the REWL signal of each fuse programming unit is 0, the efuse units on all odd-column bit lines in the array are disconnected from the even-column bit lines, and the efuse units in both odd and even columns are valid.

[0039] The first word line WLon signal of the nth efuse unit pair is 1, the second word line WLen signal of the nth efuse unit pair is 1, the first read control signal RDR is 1, the second read control signal RD is 1, and the first SA module to the 2nSA module SA1 to SA2n read the efuse unit information of all columns in this row.

[0040] The second read operation mode includes: when the nth programming control signal BLCn is 1, disconnecting all programming power supplies VDDQ and the power control transistor MPn between bit lines BL1~BLn;

[0041] When the nth correction signal REWLn is 1, the efuse cells on the odd-numbered column lines and the efuse cells on the even-numbered column lines of the row containing the nth correction signal REWLn in the array are short-circuited.

[0042] When the second read control signal RD is 0, the grounding path of all even-numbered SA modules is turned off. When the first word line WLon signal of the odd-numbered column of the selected fuse programming unit row is 0, and the second word line WLen signal of the even-numbered column of the selected fuse programming unit row is 1, the control tube of the even-numbered column of the selected fuse programming unit row is turned on, and other control tubes are turned off.

[0043] When the first read control signal RDR is 1, the current selection mode control transistor Nsw of the odd column SA module of the selected fuse programming unit row and the even column efuse unit are grounded. The selected fuse programming unit row odd column SA module converts the fuse resistance value of the even column unit in the same row into a logic value.

[0044] That is, the odd-numbered columns of efuse cells in each row are used as storage bits, and the adjacent even-numbered columns of efuse cells are used as redundancy for that storage bit.

[0045] The fuse programming unit array provided by this invention includes a cell array and a control circuit, as shown below. Figure 6 As shown. The cell array consists of odd / even bit lines BLn and odd / even word lines WLon / WLen, mode control line REWL, efuse basic cells, and PMOS power control transistor Mpn and NMOS read function control transistor Mnn. The control circuit consists of AND gates and inverters. The input control signals are mode control RE and word control WLn, and the output signals are REWL, WLen, and WLon. The cell control signals for each row are WLo1~n and WLe1~n. The cells in each column are connected to the same bit lines BLn-1 and BLn. The bit lines are connected to VDDQ via the power control transistor Mp controlled by the BLC, and connected to the SA2n module via the read control transistor Mn controlled by RDR and RD.

[0046] The fuse programming unit array of the present invention includes two read operation modes: normal mode and redundant mode.

[0047] The present invention describes the read operation of the fuse programming unit array in conventional mode, such as... Figure 8a As shown. BLCn=1, disconnects the power control transistors between all VDDQ and bit lines BLn; REWL=0, disconnects the efuse cells on all odd-column bit lines from the even-column bit lines in the array, making the efuse cells on both odd and even columns valid. WLne=1, WLno=1, RDR=1, RD=1, SA1~n reads the efuse cell information of all columns in this row.

[0048] The present invention describes the read operation of the fuse programming unit array in conventional mode, such as... Figure 8bAs shown, BLCn=1, disconnecting all power control transistors between VDDQ and BLn; REWL = 1, shorting the odd-column bit line BL2n-1 and the even-column bit line BL2n in the array; RD=0, turning off all even-column SA paths to ground; in the selected WL row, odd-column WLno=0, even-column WLne=1, turning on the control transistors in the even-column of that row, and turning off other control transistors; RDR=1, the current selection transistor Nsw of the odd-column SA and the fuse cell of the even-column SA are connected to ground, and the odd-column SA converts the fuse resistance value of the even-column cell in the same row into a logic value, that is, the odd-column SA of each row... The efuse unit of the sequence is used as a storage bit, and the efuse unit of the adjacent even-numbered sequence is used as a redundancy for the storage bit. That is, before programming, the two units of the odd and even columns are both 0, and the odd column SA outputs the odd column unit (which is 0); after programming, the odd column unit becomes 1, and SA outputs 1; if the odd column unit fails (still 0), after programming the even column units in the same row, when the odd column SA corrects the read mode, it will output the even column unit as 1. Therefore, the present invention can realize the redundancy backup of the even column for the odd column.

[0049] The fuse programming unit, programming circuit, control circuit, and array provided by this invention improve the flexibility of the efuse cell array by modifying the circuit and adding mode control, based on the traditional array. The cell array can perform read and write operations on all bits of the storage area, or it can use half of the physical storage area as the actual storage capacity and the other half as the redundant area of ​​the former, and has the ability to directly correct all bits.

[0050] Taking an 8192-bit capacity, 32-bit output width efuse as an example, under conventional redundancy correction methods, correcting one bit requires 16 bits of capacity to store the address and correction value information of that bit. Therefore, for an 8192-bit capacity, to achieve correction of all stored bits, the actual effective capacity of this efuse is only 482 bits, with the remaining capacity used as a redundancy correction storage area, which is 482 (actual) + 482 x 16 (redundancy) = 8194 bits (closest to the total capacity of 8192 bits). However, using the array scheme of this invention, an 8K efuse of the same capacity can achieve redundancy correction capability for all storage capacity with an actual storage space of 4096 bits, which is much higher than the 482 bits designed using conventional redundancy schemes. Attached Figure Description

[0051] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

[0052] Figure 1 This is a schematic diagram of a standard efuse unit.

[0053] Figure 2 This is a schematic diagram of a conventional efuse cell array.

[0054] Figure 3 This is a schematic diagram of the fuse programming unit of the present invention.

[0055] Figure 4 This is a schematic diagram of the fuse programming circuit of the present invention.

[0056] Figure 5 This is a schematic diagram of the control circuit of the present invention.

[0057] Figure 6 This is a schematic diagram of the fuse programming unit array of the present invention.

[0058] Figure 7a This is a schematic diagram of the programming state of the efuse unit on the odd column during the programming operation of the fuse programming unit array of the present invention.

[0059] Figure 7b This is a schematic diagram of the programming state of the efuse unit on the even column during the programming operation of the fuse programming unit array of the present invention.

[0060] Figure 8a This is a schematic diagram of the read operation of the fuse programming unit array in the conventional mode of the present invention.

[0061] Figure 8b This is a schematic diagram of the read operation in the redundant mode of the fuse programming unit array of the present invention. Detailed Implementation

[0062] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements.

[0063] First embodiment;

[0064] refer to Figure 3 As shown, the present invention provides a fuse programming unit, characterized in that it includes: two efuse units and a mode control transistor Nsw;

[0065] The first efuse unit includes:

[0066] The first fuse link1 has its first end forming the first connection terminal of the fuse programming unit, which is connected to the first bit line BL1, and its second end is connected to the drain terminal of the first MOSN1.

[0067] The first MOSN1 has its source end connected to ground and its gate end forming the second connection terminal of the fuse programming unit. The second connection terminal is connected to the first word line WLo.

[0068] The second efuse unit includes:

[0069] The second fuse link2 has its first end forming the third connection terminal of the fuse programming unit. The third connection terminal is connected to the second bit line BL2, and its second end is connected to the drain terminal of the second MOSN2.

[0070] The second MOSN2, whose source end is connected to ground, and whose gate end constitutes the second word line WLe of the fuse programming unit;

[0071] The mode control transistor Nsw has its drain connected to the bit line BL1 of the first efuse unit, its source connected to the bit line BL2 of the second efuse unit, and its gate constitutes the correction signal REWL of the fuse programming unit.

[0072] Among them, the first MOSN1, the second MOSN2 and the mode control transistor Nsw are NMOS.

[0073] Furthermore, it should be understood that although the terms "first," "second," etc., may be used herein to describe different elements, parameters, components, regions, layers, and / or portions, these elements, parameters, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, parameter, component, region, layer, or portion from another element, parameter, component, region, layer, or portion. Therefore, without departing from the teachings of exemplary embodiments according to the present invention, the first element, parameter, component, region, layer, or portion discussed below may also be referred to as the second element, parameter, component, region, layer, or portion.

[0074] Second embodiment;

[0075] refer to Figure 4 As shown, the present invention provides a fuse programming circuit having the fuse programming unit described in the first embodiment, and further includes:

[0076] The first power control transistor Mp1 has its drain terminal connected to the first bit line BL1 of the fuse programming unit, its gate terminal connected to the first programming control signal BLC1, and its source terminal connected to the programming power supply VDDQ.

[0077] The first read control transistor Mn1 has its drain end connected to the first bit line BL1 of the fuse programming unit, its gate end connected to the first read control signal RDR, and its source end connected to the first SA module SA1.

[0078] The second power control transistor Mp2 has its drain end connected to the second bit line BL2 of the fuse programming unit, its gate end connected to the second programming control signal BLC2, and its source end connected to the programming power supply VDDQ.

[0079] The second read control transistor Mn2 has its drain end connected to the second bit line BL2 of the fuse programming unit, its gate end connected to the second read control signal RD, and its source end connected to the second SA module SA2.

[0080] Among them, the first power control transistor Mp1 and the second power control transistor Mp2 are PMOS, and the first read control transistor Mn1 and the second read control transistor Mn2 are NMOS.

[0081] Third embodiment;

[0082] refer to Figure 5 As shown, the present invention provides a control circuit for the programming circuit of the fuse wire, comprising:

[0083] An AND gate and an inverter;

[0084] An inverter, whose input terminal serves as the first input terminal of the control circuit, is connected to the correction signal REWL and the correction control signal RE of the fuse programming unit.

[0085] The AND gate has its second input terminal as the second input terminal of the control circuit. The second input terminal is connected to the second word line WLe and the word control signal WL of the fuse programming unit, and its output terminal is connected to the first word line WLo of the fuse programming unit.

[0086] Among them, the correction control signal RE is used to control the switching between correction mode and normal mode;

[0087] When the correction control signal RE is 1, the correction mode is entered, the correction signal REWL input of the fuse programming unit is 1, and the first word line WLo input of the fuse programming unit is 0.

[0088] When the correction control signal RE is 0, the system enters the normal mode. The correction signal REWL input of the fuse programming unit is 0, the first word line WLo input of the fuse programming unit is the word control signal WL, and the second word line WLe input of the fuse programming unit is always the word control signal WL.

[0089] Fourth embodiment;

[0090] refer to Figure 6 As shown, the present invention provides a fuse programming unit array, which consists of n rows of fuse programming circuits as described in the second embodiment and n control circuits as described in the third embodiment. Each row includes at least two fuse programming circuits and each row includes one control circuit, where n≥1.

[0091] It consists of n rows of fuse programming circuits as described in the second embodiment and n control circuits as described in the third embodiment, with each row including at least two of the fuse programming circuits and each row including one of the control circuits, and n≥1.

[0092] For example, the fuse programming circuit described in n rows is illustrated, with each row having n fuse programming units. This should not be construed as limiting the number of fuse programming units per row.

[0093] In the nth row, the first terminal of the nth fuse programming unit is connected to the nth first bit line BL1n, the second terminal is connected to the nth first word line WLon, the third terminal is connected to the nth second bit line BL2n, the fourth terminal is connected to the nth second word line WLen, and the fifth terminal is connected to the nth correction signal REWLn.

[0094] The nth first power control transistor Mp1n has its drain connected to the nth first bit line BL1n, its gate connected to the nth programming control signal BLC1n, and its source connected to the programming power supply VDDQ.

[0095] The nth second power control transistor Mp2n has its drain connected to the nth second bit line BL2n, its gate connected to the nth programming control signal BLC2n, and its source connected to the programming power supply VDDQ.

[0096] The nth first read control transistor Mn1n has its drain connected to the nth first bit line BL1n, its gate connected to the first read control signal RDR, and its source connected to the nth first SA module SA1n.

[0097] The nth second read control transistor Mn2n has its drain connected to the nth second bit line BL2, its gate connected to the second read control signal RD, and its source connected to the nth second SA module SA2n.

[0098] The nth mode control transistor Nswn has its drain connected to the nth first bit line BL1n, its source connected to the nth second bit line BL2n, and its gate connected to the nth correction signal REWLn.

[0099] The nth inverter has its input connected to the nth correction signal REWLn and the nth correction control signal REn, and its output connected to the first input of the nth AND gate.

[0100] The nth AND gate has its second input connected to the nth second word line WLen and the nth word control signal WLn, and its output connected to the nth first word line WLon.

[0101] The first read operation mode includes: BLCn=1, disconnecting the power control transistors between all VDDQ and bit lines BLn; REWL=0, disconnecting the efuse cells on all odd-numbered bit lines and even-numbered bit lines in the array, making efuse cells on both odd and even columns valid; WLne=1, WLno=1, RDR=1, RD=1, SA1~n reads the efuse cell information of all columns in that row.

[0102] The second read operation mode includes: BLCn=1, disconnecting all power control transistors between VDDQ and BLn; REWL=1, shorting the odd-numbered column bit line BL2n-1 and the even-numbered column bit line BL2n in the array; RD=0, turning off all even-numbered column SA to ground; in the selected WL row, odd-numbered column WLno=0, even-numbered column WLne=1, turning on the control transistor located in the even-numbered column of that row, and turning off other control transistors; RDR=1, the current selection Nsw transistor of the odd-numbered column SA and the efuse cell of the even-numbered column are connected to ground, and the odd-numbered column SA converts the fuse resistance value of the even-numbered column cell in the same row into a logic value, that is, the odd-numbered column of each row... The efuse unit of the sequence is used as a storage bit, and the efuse unit of the adjacent even-numbered sequence is used as a redundancy for the storage bit. That is, before programming, the two units of the odd and even columns are both 0, and the odd column SA outputs the odd column unit (which is 0); after programming, the odd column unit becomes 1, and SA outputs 1; if the odd column unit fails (still 0), after programming the even column units in the same row, when the odd column SA corrects the read mode, it will output the even column unit as 1. Therefore, the present invention can realize the redundancy backup of the even column for the odd column.

[0103] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0104] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A fuse programming unit, characterized in that... It includes: two efuse units and one mode control tube (Nsw); The first efuse unit includes: The first fuse (link1) has its first end forming the first connection terminal of the fuse programming unit, which is connected to the first bit line (BL1), and its second end is connected to the drain terminal of the first MOS (N1). The first MOS (N1) has its source terminal connected to ground and its gate terminal forming the second connection terminal of the fuse programming unit, which is connected to the first word line (WLo). The second efuse unit includes: The second fuse (link2) has its first end forming the third connection terminal of the fuse programming unit. The third connection terminal is connected to the second bit line (BL2), and its second end is connected to the drain terminal of the second MOS (N2). The second MOS (N2) has its source terminal connected to ground and its gate terminal forming the fourth connection terminal of the fuse programming unit, which is connected to the second word line (WLe). The mode control transistor (Nsw) has its drain connected to the bit line (BL1) of the first efuse unit, its source connected to the bit line (BL2) of the second efuse unit, and its gate forming the fifth connection terminal of the fuse programming unit. This fifth connection terminal is connected to the correction signal (REWL).

2. The fuse programming unit as described in claim 1, characterized in that: The first MOS (N1), the second MOS (N2), and the mode control transistor (Nsw) are NMOS transistors.

3. A fuse programming circuit having the fuse programming unit as described in claim 1, characterized in that, Also includes: The first power control transistor (Mp1) has its drain terminal connected to the first bit line (BL1) of the fuse programming unit, its gate terminal connected to the first programming control signal (BLC1), and its source terminal connected to the programming power supply (VDDQ). The first read control transistor (Mn1) has its drain terminal connected to the first bit line (BL1) of the fuse programming unit, its gate terminal connected to the first read control signal (RDR), and its source terminal connected to the first SA module (SA1). The second power control transistor (Mp2) has its drain terminal connected to the second bit line (BL2) of the fuse programming unit, its gate terminal connected to the second programming control signal (BLC2), and its source terminal connected to the programming power supply (VDDQ). The second read control transistor (Mn2) has its drain end connected to the second bit line (BL2) of the fuse programming unit, its gate end connected to the second read control signal (RD), and its source end connected to the second SA module (SA2).

4. The fuse programming circuit as described in claim 3, characterized in that: The first power control transistor (Mp1) and the second power control transistor (Mp2) are PMOS, and the first read control transistor (Mn1) and the second read control transistor (Mn2) are NMOS.

5. A control circuit for the programmable circuit of the fuse as described in claim 3, characterized in that, include: An AND gate and an inverter; The inverter has its input terminal as the first input terminal of the control circuit. The first input terminal is connected to the correction signal (REWL) and correction control signal (RE) of the fuse programming unit. Its output terminal is the first input terminal of the AND gate. The AND gate has its second input terminal as the second input terminal of the control circuit. The second input terminal is connected to the second word line (WLe) and word control signal (WL) of the fuse programming unit, and its output terminal is connected to the first word line (WLo) of the fuse programming unit. The correction control signal (RE) is used to control the switching between correction mode and normal mode.

6. The control circuit of the fuse programming circuit as described in claim 5, characterized in that: When the correction control signal (RE) is 1, the correction mode is entered, the correction signal (REWL) input of the fuse programming unit is 1, and the first word line (WLo) input of the fuse programming unit is 0; When the correction control signal (RE) is 0, the normal mode is entered. The correction signal (REWL) input of the fuse programming unit is 0, the first word line (WLo) input of the fuse programming unit is the word control signal (WL), and the second word line (WLe) input of the fuse programming unit is always the word control signal (WL).

7. A fuse programming unit array, characterized in that: It consists of n rows of the fuse programming circuits described in claim 3 and n control circuits described in claim 5, with each row including at least two of the fuse programming circuits and each row including one of the control circuits, where n ≥ 1.

8. The fuse programming unit array as described in claim 7, characterized in that: Each row includes n of the aforementioned fuse programming circuits; The first read operation mode includes: when the first to second programming control signals (BLC1 to BLC2n) are 1, disconnect the power control transistors (MP1 to MP2n) between all programming power supplies (VDDQ) and bit lines (BL1 to BL2n). When the correction signal (REWL) of each fuse programming unit is 0, the efuse units on all odd-numbered columns and even-numbered columns in the array are disconnected, and the efuse units on both odd and even columns are valid. The word control signal of the fuse programming unit in row i is 1, the first word line signal of the fuse programming unit in row i is 1, the second word line signal of the fuse programming unit in row i is 1, the first read control signal (RDR) is 1, the second read control signal (RD) is 1, and the first SA module to the 2n SA modules (SA1 to SA2n) read the efuse unit information in all columns of this row.

9. The fuse programming unit array as described in claim 7, characterized in that: Each row includes n of the aforementioned fuse programming circuits; The second read operation mode includes: when the first to second programming control signals (BLC1 to BLC2n) are 1, disconnect the power control transistors (MP1 to MP2n) between all programming power supplies (VDDQ) and bit lines (BL1 to BL2n). The correction signal (REWL) of each fuse programming unit is 1, and the efuse units on the odd-numbered and even-numbered columns of the array are shorted; the word control signal of the fuse programming unit in the i-th row is 1, and the fuse programming unit in the i-th row is selected. When the second read control signal (RD) is 0, the grounding path of all even-numbered SA modules is turned off. When the first word line signal of the odd-numbered column of the selected fuse programming unit row is 0, and the second word line signal of the even-numbered column of the selected fuse programming unit row is 1, the control tube of the even-numbered column of the selected fuse programming unit row is turned on, and the other control tubes are turned off. When the first read control signal (RDR) is 1, the current selection mode control transistor (Nsw) of the odd-numbered column SA module of the selected fuse programming unit row and the even-numbered column efuse unit are grounded. The selected fuse programming unit row odd-numbered column SA module converts the fuse resistance value of the even-numbered column unit in the same row into a logic value. That is, the odd-numbered columns of efuse cells in each row are used as storage bits, and the adjacent even-numbered columns of efuse cells are used as redundancy for that storage bit.

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