A semiconductor device, a DRAM and a manufacturing method thereof

Abstract

This invention relates to a semiconductor device, DRAM, and its manufacturing method, belonging to the field of semiconductor technology. It addresses the problems of uneven chamfering or the formation of barriers in existing dual-damascene etching schemes for through-holes. The device includes: a metal component disposed in a semiconductor substrate; a first interconnect disposed in a first opening of an ILD layer and in contact with the top surface of the first metal component; and a second interconnect disposed in a second opening of the ILD layer, including a main body and a first branch and a second branch located below the main body. The first and second branches are in contact with the top surfaces of a second and a third metal component, respectively. The sum of the width of the first branch, the width of the second branch, and the width of a protrusion in the ILD layer between the first and second branches is less than or equal to the width of the main body. The protrusion in the ILD layer has rounded chamfers. The cavity significantly increases the trench etching process window, enabling effective rounding of the chamfers and improving device reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a semiconductor device, a DRAM and a manufacturing method thereof. BACKGROUND

[0002] Memory is a device or component used to store a large amount of information in a digital system, and is an important component in a computer and a digital device. Memory can be divided into two categories: random access memory (RAM) and read-only memory (ROM). RAM includes DRAM, PRAM, MRAM, etc., and semiconductor devices such as interconnects are key components for manufacturing these RAMs.

[0003] In the trench etching, the via fill is etched. At the same time, in the trench etching, the oxide of ILD (interlevel dielectric, also known as interlayer dielectric) or SiCOH is generally minimized by using low-selectivity etching, but the process window of this etching method is relatively small. The cost of changing the structure used by the first trench metal hard mask and the etching scheme thereof is high.

[0004] Spin-on hard mask SOH (Spin-on Hard Mask) and spin-on carbon SOC (Spin on Carbon) and other organic materials are filled in the via. In the case of a via dual damascene etching scheme, it is difficult to control the via fence and the chamfer during the trench etching, so the via chamfer is uneven or the fence is prone to be generated, and therefore such a profile will reduce the yield or affect the reliability of the device. SUMMARY

[0005] In view of the above analysis, the embodiments of the present application aim to provide a semiconductor device, a DRAM and a manufacturing method thereof, to solve the problem of uneven via chamfer or easy fence generation in the existing via dual damascene etching scheme.

[0006] In one aspect, embodiments of the present application provide a semiconductor device, comprising: a metal component disposed in a semiconductor substrate and having a top surface flush with a top surface of the semiconductor substrate, comprising a first metal component, a second metal component, and a third metal component; a first interconnect disposed in a first opening of an ILD layer and in contact with the top surface of the first metal component, wherein the first interconnect comprises an upper portion, a lower portion, and an intermediate portion between the lower portion and the upper portion, the upper portion having a second width, the lower portion having a first width, and the intermediate portion gradually increasing in width from the first width to the second width from bottom to top; and a second interconnect disposed in a second opening of the ILD layer, comprising a main body portion and first and second branch portions below the main body portion, the first and second branch portions in contact with the top surfaces of the second and third metal components, respectively, wherein a sum of a width of the first branch portion, a width of the second branch portion, and a width of a raised portion of the ILD layer between the first and second branch portions is a third width, the third width being less than or equal to a width of the main body portion, the first and second branch portions each having the first width, and the raised portion of the ILD layer having a rounded corner.

[0007] The above technical solution has the following beneficial effects: in the semiconductor device according to embodiments of the present application, the width of the upper portion of the interconnect is greater than or equal to the sum of the width of the first branch portion, the width of the second branch portion, and the width of the raised portion of the ILD layer between the first and second branch portions, greatly increasing the trench etching process window, effectively rounding the corner, and improving the reliability of the device.

[0008] Based on the further improvement of the above device, the main body portion comprises an upper main body portion, a lower main body portion, and an intermediate main body portion between the upper and lower main body portions, wherein the width of the lower main body portion is equal to the third width, the width of the upper main body portion is greater than the third width, and the width of the intermediate main body portion gradually increases from the third width to the width of the upper main body portion from bottom to top.

[0009] Based on the further improvement of the above device, the first opening comprises an upper portion and a first lower portion, the width of the upper portion being greater than the width of the first lower portion, wherein the interface between the first and second openings has a rounded corner.

[0010] Based on the further improvement of the above device, the second opening includes a second lower opening, a third lower opening and a cavity, wherein the cavity is located above the second lower opening, a protrusion of the ILD layer and the third lower opening and communicates with the second lower opening and the third lower opening, wherein the opposite sidewalls of the cavity have a round chamfer at the interface between the second lower opening and the third lower opening.

[0011] Based on the further improvement of the above device, the semiconductor device further includes a fourth metal component between the first interconnect and the second interconnect, which has a width of the first width and a bottom surface in contact with the ILD layer.

[0012] Based on the further improvement of the above device, the first interconnect, the fourth metal component and the second interconnect include a metal barrier layer and a copper layer above the metal barrier layer, wherein the material of the metal barrier layer includes TaN or TiN.

[0013] Based on the further improvement of the above device, the top surfaces of the first interconnect, the fourth metal component and the second interconnect are flush with the top surface of the ILD layer, and the material of the ILD layer includes SiOF, TEOS, oxide of SiCOH or a combination of multiple layers thereof.

[0014] In another aspect, an embodiment of the present application provides a DRAM including the semiconductor device according to the above embodiments.

[0015] In yet another aspect, an embodiment of the present application provides a manufacturing method of a semiconductor device, including: providing a semiconductor substrate, wherein the semiconductor substrate includes a metal component; sequentially forming a diffusion barrier layer, an ILD layer and a cover hard mask layer above the semiconductor substrate; etching the cover hard mask layer and the ILD layer to form a plurality of lower openings corresponding to the metal component; sequentially forming an organic hard mask layer, a top mask layer and a photoetch mask layer pattern above the plurality of lower openings; transferring the photoetch mask layer pattern to the cover hard mask layer and the ILD layer via the top mask layer and the organic hard mask layer to form a cover hard mask layer pattern and an ILD layer pattern while removing part of the organic hard mask layer in the plurality of lower openings to form a plurality of openings including an opening fence in the openings; etching the plurality of openings to remove the opening fence and form a round chamfer; removing the cover hard mask layer pattern and removing part of the ILD layer and part of the diffusion barrier layer below in the plurality of lower openings to expose the metal component; and forming a metal material in the plurality of openings to form a metal interconnect.

[0016] Based on the further improvement of the above method, the metal components include a first metal component, a second metal component, and a third metal component, and the width of the metal components is greater than the width of the plurality of lower openings, wherein etching the cover hard mask layer and the ILD layer to form a plurality of lower openings vertically aligned with the metal components further comprises: sequentially etching the cover hard mask layer and the ILD layer to form a plurality of lower openings, wherein the bottom surface of the plurality of lower openings and the metal components include a portion of the ILD layer and a diffusion barrier layer, and the plurality of lower openings include a first lower opening, a second lower opening, and a third lower opening vertically aligned with the first metal component, the second metal component, and the third metal component, respectively.

[0017] Based on the further improvement of the above method, after forming the top mask layer, further comprising: sequentially forming an anti-reflective layer and a photolithography mask layer above the top mask layer; and performing photolithography on the photolithography mask layer to form the photolithography mask layer pattern and a plurality of recesses, the plurality of recesses including a first recess and a second recess, wherein the first recess is vertically aligned with the first metal component; and the second recess is vertically aligned with the second metal component, the third metal component, and the protrusion of the ILD layer between the second metal component and the third metal component.

[0018] Based on the further improvement of the above method, transferring the photolithography mask layer pattern to the cover hard mask layer and the ILD layer via the top mask layer and the organic hard mask layer to form a cover hard mask layer pattern and an ILD layer pattern while removing the portion of the organic hard mask layer in the plurality of lower openings to form a plurality of openings further comprises: etching the top mask layer and the organic hard mask layer to form a top mask layer pattern and an organic hard mask layer pattern, with the photolithography mask layer pattern as a mask; etching the cover hard mask layer and the ILD layer to form the cover hard mask layer pattern and the ILD layer pattern to form an upper opening and a cavity and simultaneously remove the portion of the organic hard mask layer in the plurality of lower openings to form a plurality of openings, with the top mask layer pattern and the organic hard mask layer pattern as a mask, wherein the plurality of openings include a first opening and a second opening, the first opening includes an upper opening and a first lower opening, the width of the upper opening is greater than the width of the first lower opening; and the second opening includes a cavity, a second lower opening, and a third lower opening, the width of the cavity is greater than or equal to the sum of the width of the second lower opening, the width of the third lower opening, and the width of the protrusion of the ILD layer between the second lower opening and the third lower opening.

[0019] In further improvement of the above method, etching the plurality of openings to remove the opening fence and form the rounded chamfer further comprises: using reactive ion etching of the openings with a mixed gas containing carbon-rich CxFy-based, as a mask of the cover hard mask layer pattern, to remove the opening fence and form the rounded chamfer, wherein the mixed gas comprises C4F6, O2 and Ar; or C4F8, O2 and Ar.

[0020] In further improvement of the above method, CO, CO2, COS or O2 is added in the mixed gas to selectively etch part of the diffusion barrier layer located below the lower opening.

[0021] In further improvement of the above method, forming a metal material in the plurality of openings to form a metal connector further comprises: depositing a metal barrier layer above the plurality of openings by PVD or CVD; plating a copper layer above the metal barrier layer to overfill the plurality of openings; and removing part of the metal barrier layer and the copper layer outside the plurality of openings by a planarization process until the top surface of the ILD layer is exposed, wherein the top surface of the metal barrier layer and the copper layer is flush with the top surface of the ILD layer.

[0022] In further improvement of the above method, the material of the cover hard mask layer and the diffusion barrier layer comprises: nitride of SiN, SiCN or SiON.

[0023] In further improvement of the above method, the ILD layer comprises oxide of SiOF, TEOS, SiCOH or combination of multiple layers thereof.

[0024] In yet another aspect, an embodiment of the present application provides a manufacturing method of a DRAM, comprising: a manufacturing method of a semiconductor device according to the above embodiments.

[0025] Compared with the prior art, the present application can achieve at least one of the following beneficial effects:

[0026] 1. The width of the upper body part of the interconnect is greater than or equal to the sum of the width of the first branch, the width of the second branch and the width of the protruding part of the ILD layer between the first branch and the second branch, which greatly increases the trench etching process window, effectively rounds the chamfer and improves the reliability of the device, such as electromigration (EM).

[0027] 2. In the second etching process, the RIE (Reactive Ion Etching) process using C4F6, O2 and Ar, or C4F8, O2 and Ar can effectively remove the fence and round the chamfer.

[0028] 3. Adding CO, CO2, COS, or O2 to the gas mixture (e.g., C4F6, O2, and Ar, or C4F8, O2, and Ar), which has a high selectivity ratio for etching the barrier layer, so that the etching can stop at the portion of the diffusion barrier layer under the lower opening.

[0029] In the present application, each of the above technical solutions can be combined with each other to realize more preferred combination solutions. Other features and advantages of the present application will be set forth in the subsequent description, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the present application. The objects and other advantages of the present application can be realized and attained by the structure particularly pointed out in the description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings:

[0031] Figure 1 A cross-sectional view of an intermediate stage of a manufacturing method of a semiconductor device according to an embodiment of the present application.

[0032] Figure 2 A cross-sectional view of an intermediate stage of a manufacturing method of a semiconductor device according to an embodiment of the present application.

[0033] Figure 3 A cross-sectional view of an intermediate stage of a manufacturing method of a semiconductor device according to an embodiment of the present application.

[0034] Figure 4 A cross-sectional view of an intermediate stage of a manufacturing method of a semiconductor device according to an embodiment of the present application.

[0035] Figure 5 A cross-sectional view of a semiconductor device according to an embodiment of the present application.

[0036] REFERENCE NUMERALS:

[0037] 100 - semiconductor substrate; 102a - first metal feature; 102b - second metal feature; 102c - third metal feature; 102d - other metal feature; 104 - diffusion barrier layer; 106 - ILD layer; 108 - blanket hardmask layer; 110 - organic hardmask layer; 112 - top mask layer; 114 - antireflective layer; 116 - photoresist mask layer pattern; 118a - first lower opening; 118b - second lower opening; 118c - third lower opening; 120a - first lower opening; 120b - second lower opening; 120c - third lower opening; 122 - upper opening; 124 - cavity; 126 - opening fence; 128 - third opening; 130 - hardmask layer pattern; 132 - rounded corner; 134 - body portion; 136 - lower connector; 138 - upper connector; 140 - middle connector; 142 - fourth metal feature; 144 - second leg; 146 - metal barrier layer; 148 - first leg DETAILED DESCRIPTION

[0038] The preferred embodiments of the present application will be described in detail with reference to the drawings, where:

[0039] One embodiment of the present application discloses a semiconductor device. Referring to Figure 5 The semiconductor device will be described in detail. The semiconductor device includes a metal feature, a first interconnect, a first interconnect, a diffusion barrier layer 104, an ILD layer 106, and a fourth metal feature 142.

[0040] The metal feature is disposed in the semiconductor substrate 100 and a top surface of the metal feature is flush with a top surface of the semiconductor substrate 100. The metal feature includes a first metal feature 102a, a second metal feature 102b, and a third metal feature 102c, wherein the first metal feature 102a, the second metal feature 102b, and the third metal feature 102c have a same width. In addition, the metal feature further includes an other metal feature between the second metal feature 102b and the third metal feature 102c, wherein the other metal feature has a width smaller than the width of the first metal feature 102a, the second metal feature 102b, or the third metal feature 102c.

[0041] The first interconnect is disposed in the first opening of the diffusion barrier layer 104 and the ILD layer 106 and in contact with the top surface of the first metal component 102a, wherein the first interconnect includes an upper connector 138, a lower connector 136, and an intermediate connector 140 between the lower connector 136 and the upper connector 138, the upper connector 138 has a second width, the lower connector 136 has a first width, and the width of the intermediate connector 140 gradually increases from the first width to the second width from bottom to top. The first opening includes an upper opening 122 and a first lower opening 120a, the width of the upper opening 122 is greater than the width of the first lower opening 120a, and the interface between the first opening and the second opening has a round chamfer. The first interconnect includes a metal barrier layer 146 and a copper layer above the metal barrier layer 146, wherein the material of the metal barrier layer 146 includes TaN or TiN.

[0042] The second interconnect is disposed in the second opening of the diffusion barrier layer 104 and the ILD layer 106, and includes a main body 134 and first and second branch parts 148 and 144 below the main body 134, the first and second branch parts 148 and 144 are in contact with the top surfaces of the second and third metal components 102b and 102c, respectively; wherein the sum of the width of the first branch part 148, the width of the second branch part 144, and the width of the raised part of the ILD layer 106 between the first and second branch parts 148 and 144 is a third width, the third width is less than or equal to the width of the main body 134, the widths of the first and second branch parts 148 and 144 are both the first width, and the raised part of the ILD layer 106 has a round chamfer. The main body 134 includes an upper main body, a lower main body, and an intermediate main body between the upper and lower main bodies, wherein the width of the lower main body is equal to the third width, the width of the upper main body is greater than the third width, and the width of the intermediate main body gradually increases from the third width to the width of the upper main body from bottom to top. The second opening includes a second lower opening 120b, a third lower opening 120c, and a cavity 124, wherein the cavity 124 is above the second lower opening 120b, the raised part of the ILD layer 106, and the third lower opening 120c and communicates with the second and third lower openings 120b and 120c, and the opposite side walls of the cavity 124 have a round chamfer at the interface between the second and third lower openings 120b and 120c. The second interconnect includes a metal barrier layer 146 and a copper layer above the metal barrier layer 146, wherein the material of the metal barrier layer 146 includes TaN or TiN.

[0043] A fourth metal component 142 is located between the first interconnect and the second interconnect, and has a width of the first width and a bottom surface in contact with the ILD layer 106. The fourth metal component includes a metal barrier layer 146 and a copper layer above the metal barrier layer 146, wherein the material of the metal barrier layer 146 includes TaN or TiN.

[0044] The first interconnect, the fourth metal component 142 and the second interconnect are embedded in the ILD layer 106. The top surfaces of the first interconnect, the fourth metal component and the second interconnect are flush with the top surface of the ILD layer 106, and the material of the ILD layer 106 includes SiOF, TEOS, oxide of SiCOH or a combination of multiple layers thereof. In addition, the diffusion barrier layer 104 is located between the semiconductor substrate 100 and the ILD layer 106. The first interconnect and the second interconnect pass through the ILD layer 106 and the diffusion barrier layer 104.

[0045] Compared with the prior art, in the semiconductor device according to the embodiment of the present application, the width of the upper main body part of the interconnect is greater than or equal to the sum of the width of the first branch part, the width of the second branch part and the width of the protruding part of the ILD layer between the first branch part and the second branch part, which greatly increases the trench etching process window, effectively rounds the chamfer and improves the reliability of the device.

[0046] Another specific embodiment of the present application discloses a DRAM, which includes the semiconductor device described in the above embodiments.

[0047] Still another specific embodiment of the present application discloses a manufacturing method of a semiconductor device. Hereinafter, each step of the manufacturing method of the semiconductor device is described in detail. Figures 1 to 5

[0048] Referring to Figure 1 , a semiconductor substrate 100 is provided, wherein the semiconductor substrate 100 includes metal components embedded in the semiconductor substrate. The metal components include a first metal component 102a, a second metal component 102b and a third metal component 102c. The metal components further include other metal components 102d between the second metal component 102b and the third metal component 102c, wherein the width of the other metal components 102d is less than the width of the first metal component 102a, the second metal component 102b or the third metal component 102c. The top surfaces of the first metal component 102a, the second metal component 102b, the third metal component 102c and the other metal components 102d are flush with the top surface of the semiconductor substrate 100. The material of the metal components includes metal such as W, Cu, etc.

[0049] Referring to Figure 1 ​A diffusion barrier layer 104, an ILD layer 106, and a cover hard mask layer 108 are sequentially formed over the semiconductor substrate 100. In an embodiment, the diffusion barrier layer 104 can also be used as an etch stop layer. The material of the cover hard mask layer 108 and the diffusion barrier layer 104 includes a nitride of SiN, SiCN, or SiON. The material of the ILD layer 106 includes an oxide, such as SiOF, TEOS (Tetraethyl orthosilicate, also known as tetraethyl orthosilicate), SiCOH. In an optional embodiment, the ILD layer 106 can include a multi-layer combination of SiOF layer, TEOS layer, SiCOH layer, etc.

[0050] Referring to Figure 1 The cover hard mask layer 108 and the ILD layer 106 are etched (i.e., under-etch) to form a plurality of lower openings 118a, 118b, and 118c corresponding to the metal features. Specifically, etching the cover hard mask layer 108 and the ILD layer 106 to form a plurality of lower openings vertically aligned with the metal features further includes sequentially etching the cover hard mask layer 108 and the ILD layer 106 to form a plurality of lower openings, wherein the bottom surface of the plurality of lower openings and the metal features include a portion of the ILD layer 106 and the diffusion barrier layer 104 therebetween, and wherein the plurality of lower openings include a first lower opening 118a, a second lower opening 118b, and a third lower opening 118c vertically aligned with the first metal feature 102a, the second metal feature 102b, and the third metal feature 102c, respectively. The metal features and the bottom surface of the lower openings include the portion of the ILD layer 106 and the portion of the diffusion barrier layer 104 directly below the lower openings therebetween. The width of the metal features is greater than the width of the lower openings, in other words, the width of the lower openings is less than the width of the metal features. Specifically, the width of the lower openings is less than the width of the first metal feature 102a, the second metal feature 102b, or the third metal feature 102c.

[0051] Referring to Figure 1The organic hard mask layer 110, the top mask layer 112, the anti-reflective layer 114, and the photoresist layer 116 are sequentially formed over the plurality of lower openings 118a, 118b, and 118c. The photoresist layer is patterned by photolithography to form the photoresist layer pattern 116 and the plurality of recesses including the first recess and the second recess, wherein the first recess is vertically aligned with the first metal component 102a; and the second recess is vertically aligned with the second metal component 102b, the third metal component 102c, and the protrusion of the ILD layer 106 between the second metal component 102b and the third metal component 102c. The organic hard mask layer 110 includes SOH (Spin on Hard Mask), SOC (Spin on Carbon), and any other material containing C x H y .

[0052] Referring to Figure 2transferring the photoetching mask layer pattern 116 to the cover hard mask layer 108 and the ILD layer 106 via the top mask layer 112 and the organic hard mask layer 110 to form the cover hard mask layer pattern and the ILD layer pattern, and simultaneously removing the portions of the organic hard mask layer 110 located in the plurality of lower openings to form the plurality of openings further comprises the following steps: etching the top mask layer 112 and the organic hard mask layer 110 as a mask to form the top mask layer pattern and the organic hard mask layer pattern; etching the cover hard mask layer 108 and the ILD layer 106 as a mask to form the cover hard mask layer pattern 130 and the ILD layer pattern to form the upper opening 122 and the cavity 124 and simultaneously remove the portions of the organic hard mask layer 110 located in the plurality of lower openings to form the plurality of openings. The plurality of openings comprises a first opening and a second opening. In an embodiment, the first opening comprises the upper opening 122 and the first lower opening 120a, and the width of the upper opening 122 is greater than the width of the first lower opening 120a. A vertical inner chamfer is included at the interface between the upper opening 122 and the first lower opening 120a. The second opening comprises the cavity 124, the second lower opening 120b and the third lower opening 120c, and the width of the cavity 124 is greater than or equal to the sum of the width of the second lower opening 120b, the width of the third lower opening 120c and the width of the protrusion of the ILD layer 106 between the second lower opening 120b and the third lower opening 120c. The opposite side walls of the cavity 124 comprise a vertical inner chamfer, and the protrusion of the ILD layer 106 comprises a vertical outer chamfer. In addition, the plurality of openings further comprises a third opening 128. The bottom surface of the upper opening 122, the bottom surface of the cavity 124 and the bottom surface of the third opening 128 are flush. The vertical inner chamfer and the vertical outer chamfer are not conducive to the filling of the subsequent film layer, and are prone to cause sharp end discharge, thereby affecting the device performance. Therefore, in the following, the vertical inner chamfer and the vertical outer chamfer are etched to form a circular inner chamfer and a circular outer chamfer.

[0053] REFERENCE Figure 3The plurality of openings are etched (second etching) to remove the opening fences 126 and form the rounded chamfers 132. Specifically, etching the plurality of openings to remove the opening fences 126 and form the rounded chamfers 132 further comprises: using reactive ion etching (also referred to as second etching) with a mixed gas containing carbon-rich CxFy (etching chemical) to the openings to remove the opening fences 126 and form the rounded chamfers 132, wherein the mixed gas comprises C4F6, O2 and Ar; or C4F8, O2 and Ar, with the hard mask layer pattern 130 as a mask. In an embodiment, the vertical inner chamfer between the upper opening 122 and the first lower opening 120a is changed to a rounded inner chamfer. The vertical inner chamfer of the opposite sidewall of the cavity 124 is changed to a rounded inner chamfer, and the vertical outer chamfer of the protrusion of the ILD layer 106 is changed to a rounded outer chamfer.

[0054] Compared with the prior art, the rounded inner chamfer and the rounded outer chamfer are beneficial to the filling of the subsequent film layer, can improve the gapless filling, and can avoid causing the tip discharge, thereby improving the device reliability.

[0055] Reference Figure 4 The hard mask layer pattern 130 is removed and part of the ILD layer 106 and the underlying part of the diffusion barrier layer 104 in the plurality of lower openings are removed to form a diffusion barrier layer pattern and expose the metal component, specifically, expose the top surface of the metal component. CO, CO2, COS or O2 is added to the mixed gas to selectively etch the hard mask layer pattern 130.

[0056] Reference Figure 5The metal material is formed in the plurality of openings to form the plurality of metal connectors. Specifically, the forming the metal material in the plurality of openings to form the plurality of metal connectors further comprises: depositing a metal barrier layer 146 over the plurality of openings in a PVD or CVD manner; plating a copper layer over the metal barrier layer 146 to overfill the plurality of openings; and removing portions of the metal barrier layer 146 and the copper layer outside the plurality of openings by a planarization process until a top surface of the ILD layer 106 is exposed, wherein the top surface of the metal barrier layer 146 and the copper layer is flush with the top surface of the ILD layer 106. The metal connectors include a first interconnect, a second interconnect, and the metal component 142. The first interconnect includes the upper connector 138, the lower connector 136, and the intermediate connector 140 between the lower connector 136 and the upper connector 138, the upper connector 138 has the second width, the lower connector 136 has the first width, and the width of the intermediate connector 140 gradually increases from the first width to the second width from bottom to top. The second interconnect includes the main body 134 and the first branch 148 and the second branch 144 below the main body 134. The first branch 148 and the second branch 144 are in contact with the top surfaces of the second metal component 102b and the third metal component 102c, respectively. The sum of the width of the first branch 148, the width of the second branch 144, and the width of the raised portion of the ILD layer 106 between the first branch 148 and the second branch 144 is the third width, the third width is less than or equal to the width of the main body 134, and the width of the first branch 148 and the width of the second branch 144 are both the first width.

[0057] In yet another embodiment of the present application, a method for manufacturing a DRAM is disclosed, comprising: the method for manufacturing a semiconductor device as described in the above embodiments.

[0058] Compared with the prior art, the present application can achieve at least one of the following beneficial effects:

[0059] 1. The width of the upper main body of the interconnect is greater than or equal to the sum of the width of the first branch 148, the width of the second branch 144, and the width of the raised portion of the ILD layer 106 between the first branch 148 and the second branch 144, which greatly increases the trench etching process window, effectively rounds the chamfer, and improves the reliability of the device, such as electromigration EM.

[0060] 2. In the second etching process, the RIE (Reactive Ion Etching) process using C4F6, O2, and Ar, or C4F8, O2, and Ar can effectively remove the fence and round the chamfer.

[0061] 3. Adding CO, CO2, COS, or O2 to the gas mixture (e.g., C4F6, O2, and Ar, or C4F8, O2, and Ar), which has a high selectivity ratio for etching the barrier layer, so that the etching can stop at the portion of the diffusion barrier layer under the lower opening.

[0062] Those skilled in the art can understand that all or part of the processes of the above-mentioned embodiments can be completed by instructing the relevant hardware by a computer program, and the program can be stored in a computer readable storage medium. The computer readable storage medium is a disk, an optical disk, a read-only memory, a random access memory, etc.

[0063] The above description is merely preferred specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any changes or replacements easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered within the protection scope of the present application.

Claims

1. A semiconductor device, characterized by, Comprising: a metal component disposed in a semiconductor substrate and a top surface of the metal component flush with a top surface of the semiconductor substrate, including a first metal component, a second metal component, and a third metal component; a first interconnect disposed in a first opening of an ILD layer and in contact with a top surface of the first metal component, wherein the first interconnect includes an upper connector, a lower connector, and an intermediate connector between the lower connector and the upper connector, the upper connector having a second width, the lower connector having a first width, and the intermediate connector gradually increasing in width from the first width to the second width from bottom to top; a second interconnect disposed in a second opening of the ILD layer, including a main body and first and second branches below the main body, the first and second branches in contact with top surfaces of the second and third metal components, respectively, wherein a sum of a width of the first branch, a width of the second branch, and a width of a raised portion of the ILD layer between the first and second branches is a third width, the third width less than or equal to a width of the main body, the first and second branches each having the first width, and the raised portion of the ILD layer having a rounded corner.

2. The semiconductor device according to claim 1, wherein the main body includes an upper main body, a lower main body, and an intermediate main body between the upper and lower main bodies, wherein the lower main body has a width equal to the third width, the upper main body has a width greater than the third width, and the intermediate main body gradually increases in width from the third width to the width of the upper main body from bottom to top.

3. The semiconductor device of claim 1, wherein the first opening includes an upper portion and a first lower portion, the upper portion having a width greater than a width of the first lower portion, wherein an interface between the first opening and the second opening has a rounded corner.

4. The semiconductor device of claim 1, wherein the second opening includes a second lower portion, a third lower portion, and a cavity, wherein the cavity is above and in communication with the second lower portion and the third lower portion, and opposite sidewalls of the cavity have rounded corners at an interface between the second lower portion and the third lower portion.

5. The semiconductor device of claim 1, wherein a fourth metal component is disposed between the first interconnect and the second interconnect, having a width of the first width and a bottom surface in contact with the ILD layer.

6. The semiconductor device according to claim 5, wherein the first interconnect, the fourth metal component, and the second interconnect include a metal barrier layer and a copper layer above the metal barrier layer, wherein a material of the metal barrier layer includes TaN or TiN.

7. The semiconductor device of claim 6, wherein, top surfaces of the first interconnect, the fourth metal component, and the second interconnect are flush with a top surface of the ILD layer, and a material of the ILD layer includes SiOF, TEOS, an oxide of SiCOH, or a combination of multiple layers thereof.

8. A DRAM, comprising: Comprising:

9. A method of manufacturing a semiconductor device, characterized by providing a semiconductor substrate, wherein the semiconductor substrate includes a metal component; ​ forming a diffusion barrier layer, an ILD layer, and a cover hard mask layer sequentially over the semiconductor substrate; performing etching on the cover hard mask layer and the ILD layer to form a plurality of lower openings corresponding to the metal features; forming an organic hard mask layer, a top mask layer, and a photoresist mask layer pattern sequentially over the plurality of lower openings; transferring the photoresist mask layer pattern to the cover hard mask layer and the ILD layer via the top mask layer and the organic hard mask layer to form a cover hard mask layer pattern and an ILD layer pattern while removing portions of the organic hard mask layer in the plurality of lower openings to form a plurality of openings including an opening fence in the openings, with the photoresist mask layer pattern as a mask; performing etching on the plurality of openings to remove the opening fence and form a round chamfer; removing the cover hard mask layer pattern and removing portions of the ILD layer and the underlying portions of the diffusion barrier layer in the plurality of lower openings to expose the metal features; and forming a metal material in the plurality of openings to form a metal connector.

10. The method of manufacturing a semiconductor device according to Claim 9, wherein the metal features include a first metal feature, a second metal feature, and a third metal feature, and a width of the metal features is greater than a width of the plurality of lower openings, wherein performing etching on the cover hard mask layer and the ILD layer to form the plurality of lower openings vertically aligned with the metal features further includes: performing sequential etching on the cover hard mask layer and the ILD layer to form the plurality of lower openings, wherein a bottom surface of the plurality of lower openings and the metal features include portions of the ILD layer and the diffusion barrier layer, and wherein the plurality of lower openings include a first lower opening, a second lower opening, and a third lower opening vertically aligned with the first metal feature, the second metal feature, and the third metal feature, respectively.

11. The method of manufacturing a semiconductor device according to Claim 10, wherein after forming the top mask layer, further comprising: forming an anti-reflective layer and a photoresist mask layer sequentially over the top mask layer; and performing photolithography on the photoresist mask layer to form the photoresist mask layer pattern and a plurality of recesses including a first recess and a second recess, wherein the first recess is vertically aligned with the first metal feature; and the second recess is vertically aligned with the second metal feature, the third metal feature, and a protrusion of the ILD layer between the second metal feature and the third metal feature.

12. The method of manufacturing a semiconductor device according to Claim 11, wherein transferring the photoresist mask layer pattern to the cover hard mask layer and the ILD layer via the top mask layer and the organic hard mask layer to form a cover hard mask layer pattern and an ILD layer pattern while removing portions of the organic hard mask layer in the plurality of lower openings to form a plurality of openings further includes: performing etching on the top mask layer and the organic hard mask layer to form a top mask layer pattern and an organic hard mask layer pattern with the photoresist mask layer pattern as a mask; forming a plurality of openings including a first opening and a second opening by etching the plurality of openings to remove the opening fence and form a round chamfer further comprises: the first opening includes an upper portion opening and a first lower portion opening, the width of the upper portion opening is greater than the width of the first lower portion opening; and the second opening includes a cavity, a second lower portion opening and a third lower portion opening, the width of the cavity is greater than or equal to the sum of the width of the second lower portion opening, the width of the third lower portion opening and the width of a protrusion of the ILD layer between the second lower portion opening and the third lower portion opening.

13. The method of manufacturing a semiconductor device according to Claim 9, wherein forming a plurality of openings including a first opening and a second opening by etching the plurality of openings to remove the opening fence and form a round chamfer further comprises: reactive ion etching the openings using a mixed gas containing carbon-rich CxFy as a mask to remove the opening fence and form a round chamfer, wherein the mixed gas includes C4F6, O2 and Ar; or C4F8, O2 and Ar.

14. The method of claim 13, wherein: adding CO, CO2, COS or O2 in the mixed gas to selectively etch a portion of the diffusion barrier layer under the lower portion opening.

15. The method of manufacturing a semiconductor device according to Claim 9, wherein forming a metal material in the plurality of openings to form a metal connector further comprises: depositing a metal barrier layer over the plurality of openings by PVD or CVD; plating a copper layer over the metal barrier layer to overfill the plurality of openings; and removing a portion of the metal barrier layer and the copper layer outside the plurality of openings by a planarization process until the top surface of the ILD layer is exposed, wherein the top surface of the metal barrier layer and the copper layer is flush with the top surface of the ILD layer.

16. The method of manufacturing a semiconductor device according to Claim 9, wherein the material of the cap hard mask layer and the diffusion barrier layer includes nitride of SiN, SiCN or SiON.

17. The method of manufacturing a semiconductor device according to Claim 9, wherein the ILD layer includes oxide of SiOF, TEOS, SiCOH or a combination of multiple layers thereof.

18. A method of manufacturing a DRAM, characterized by, the method of manufacturing a semiconductor device according to any one of claims 9 to 17. the method of manufacturing a semiconductor device according to any one of claims 9 to 17.

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