Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: providing a substrate; performing a first ion implantation process on the substrate to form a first ion implantation region; the first ion implantation region extends from the upper surface of the substrate to the inside of the substrate; etching the substrate to form a word line groove; the word line groove penetrates the first ion implantation region and extends below the first ion implantation region; the word line groove comprises a first part and a second part which is integrally connected with the first part; the first part is located in the first ion implantation region; the second part is located below the first ion implantation region; during the etching of the substrate to form the word line groove, the etching rate of the second part is greater than that of the first part, so that the width of the second part is greater than that of the first part. The preparation method of the semiconductor structure provided by the application can increase the cross-sectional area of the bottom of the word line groove, reduce the resistance of the word line formed in the subsequent process, and avoid the increase of device power consumption and the deterioration of RC delay.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and its preparation method. Background Technology

[0002] As semiconductor memory devices (such as Dynamic Random Access Memory, or DRAM) become highly integrated, the area of ​​a single cell on a semiconductor substrate gradually decreases, and the channel length contained in a metal-oxide-semiconductor (MOS) transistor also gradually decreases. The reduction in channel length easily leads to the generation of short-channel effects.

[0003] In order to maintain the high integration of semiconductor memory devices, the current mainstream DRAM process uses buried wordline (BW) MOS transistors for memory cells, which can reduce the short-channel effect to a certain extent and thus reduce device leakage.

[0004] However, as the size of memory cells shrinks, the size of the BW trench also shrinks, which in turn reduces the cross-sectional area of ​​the metal filling the BW trench. This leads to an increase in word line (WL) resistance, resulting in more power consumption and exacerbating signal delay (RC delay) caused by the charging and discharging process of resistor (R) and parasitic capacitance (C). Summary of the Invention

[0005] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the shortcomings of existing technologies.

[0006] On one hand, this application provides a method for fabricating a semiconductor structure, comprising:

[0007] Provide substrate;

[0008] A first ion implantation process is performed on the substrate to form a first ion implantation region within the substrate; the first ion implantation region extends from the upper surface of the substrate into the interior of the substrate.

[0009] The substrate is etched to form word line trenches; the word line trenches penetrate the first ion implantation region and extend below the first ion implantation region; the word line trenches include a first portion and a second portion integrally connected to the first portion, the first portion being located within the first ion implantation region and the second portion being located below the first ion implantation region;

[0010] During the etching process of the substrate to form word line trenches, the etching rate of the second portion is greater than the etching rate of the first portion, so that the width of the second portion is greater than the width of the first portion.

[0011] In one embodiment, the method for fabricating the semiconductor structure prior to forming the first ion implantation region further includes:

[0012] A second ion implantation process is performed on the substrate to form a second ion implantation region within the substrate; the second ion implantation region is located below the first ion implantation region.

[0013] Both the second ion implantation region and the first ion implantation region are P-type, and the ion concentration in the second ion implantation region is lower than the ion concentration in the first ion implantation region.

[0014] In one embodiment, the implanted ions in both the first ion implantation region and the second ion implantation region include boron ions.

[0015] In one embodiment, the first ion implantation region is P-type;

[0016] Before forming the first ion implantation region, the method for fabricating the semiconductor structure further includes:

[0017] A second ion implantation process is performed on the substrate to form a second ion implantation region within the substrate; the second ion implantation region is located below the first ion implantation region.

[0018] The second ion implantation region is N-type.

[0019] In one embodiment, the implanted ions in the first ion implantation region include boron ions; and the implanted ions in the second ion implantation region include phosphorus ions.

[0020] In one embodiment, the word line trench is formed in the substrate using dry etching.

[0021] In one embodiment, after forming the word line trench, the method for fabricating the semiconductor structure further includes:

[0022] A third ion implantation process is performed on the substrate to eliminate the first ion implantation region and form a first doped region of a first conductivity type within the substrate; the first doped region extends from the upper surface of the substrate into the substrate; a fourth ion implantation process is performed on the substrate to eliminate the second ion implantation region and form a second doped region of a second conductivity type within the substrate; the second doped region extends downward from the lower surface of the first doped region into the substrate; the word line trench penetrates the first doped region and extends into the second doped region;

[0023] A gate oxide layer is formed on the sidewalls and bottom of the word line groove;

[0024] A word line conductive layer is formed on the surface of the gate oxide layer; the top of the word line conductive layer is lower than the top of the word line trench.

[0025] In one embodiment, the first conductivity type is N-type; the second conductivity type is P-type.

[0026] In one embodiment, after forming a word line conductive layer on the surface of the gate oxide layer, the method for fabricating the semiconductor structure further includes:

[0027] A filling dielectric layer is formed within the word line trench; the filling dielectric layer is located on top of the word line conductive layer and at least fills the word line trench.

[0028] On the other hand, this application also provides a semiconductor structure, characterized in that it includes:

[0029] A substrate; a first ion implantation region is provided within the substrate; the first ion implantation region extends from the upper surface of the substrate into the interior of the substrate;

[0030] The word line groove penetrates the first ion implantation region and extends below the first ion implantation region; the word line groove includes a first part and a second part integrally connected to the first part, the first part is located within the first ion implantation region, the second part is located below the first ion implantation region, and the width of the second part is greater than the width of the first part.

[0031] In one embodiment, the substrate further includes a second ion implantation region located below the first ion implantation region;

[0032] Both the second ion implantation region and the first ion implantation region are P-type, and the ion concentration in the second ion implantation region is lower than the ion concentration in the first ion implantation region.

[0033] In one embodiment, the implanted ions in both the first ion implantation region and the second ion implantation region include boron ions.

[0034] In one embodiment, the first ion implantation region is P-type;

[0035] The substrate also includes a second ion implantation region, located below the first ion implantation region;

[0036] The second ion implantation region is N-type.

[0037] In one embodiment, the implanted ions in the first ion implantation region include boron ions; and the implanted ions in the second ion implantation region include phosphorus ions.

[0038] In one embodiment, the depth of the first ion implantation region is 100 nm to 150 nm;

[0039] The ion concentration in the first ion implantation region is 1×10⁻⁶. 19 cm 3 ~1×10 21 cm 3 .

[0040] The semiconductor structure and its fabrication method described in this application have at least the following beneficial effects:

[0041] The semiconductor structure fabrication method provided in this application, by forming a first ion implantation region in the substrate, enables the etching rate of the second part to be greater than the etching rate of the first part during the etching process of forming word line trenches on the substrate, thereby forming a word line trench with a width greater than that of the first part. In this way, the bottom of the formed word line trench is wider, which can increase the cross-sectional area of ​​the bottom of the word line trench, reduce the resistance of the word lines formed in subsequent processes, and avoid the increase of device power consumption and the deterioration of RC delay.

[0042] The semiconductor structure provided in this application has word line trenches with a large bottom cross-sectional area, which can reduce the resistance of word lines formed in subsequent processes and avoid increased device power consumption and deterioration of RC delay. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1This is a schematic diagram of the cross-sectional structure of the embedded character line after the mountain-shaped groove of the embedded character line is formed by dry etching in an embedded character line process.

[0045] Figure 2 This is a schematic diagram of the cross-sectional structure of the structure obtained after forming the character line structure in an embedded character line process.

[0046] Figure 3 A flowchart illustrating a method for fabricating a semiconductor structure according to one embodiment of this application;

[0047] Figure 4 A schematic diagram of the cross-sectional structure of the structure obtained in step S1 in a method for preparing a semiconductor structure according to one embodiment of this application;

[0048] Figure 5 A schematic diagram of the cross-sectional structure of the structure obtained in step S2 in the method for preparing a semiconductor structure according to one embodiment of this application;

[0049] Figure 6 A schematic diagram of the cross-sectional structure of the structure obtained in step S3 in the method for preparing a semiconductor structure according to one embodiment of this application; Figure 6 This is also a schematic cross-sectional view of a semiconductor structure provided in one embodiment of this application;

[0050] Figure 7 A schematic diagram of the cross-sectional structure of the structure obtained in step S4 in a method for fabricating a semiconductor structure according to one embodiment of this application;

[0051] Figure 8 A schematic diagram of the cross-sectional structure of the structure obtained in step S5 in the method for preparing a semiconductor structure according to one embodiment of this application;

[0052] Figure 9 This is a schematic cross-sectional view of the structure obtained in step S6 of the method for preparing a semiconductor structure according to one embodiment of this application.

[0053] Explanation of reference numerals in the attached figures:

[0054] 1', Substrate; 132', Gate oxide layer; 133', Metal; 134', Filling dielectric layer; 1, Substrate; 13, Word line trench; 132, Gate oxide layer; 133, Word line conductive layer; 134, Filling dielectric layer; 135, First portion; 136, Second portion; 141, First ion implantation region; 142, Second ion implantation region; 143, First doped region; 144, Second doped region. Detailed Implementation

[0055] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0057] It should be understood that when an element or layer is referred to as being "above" other elements or layers, it may be directly on those other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are used merely to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, a first doped region may be referred to as a second doped region, and similarly, a second doped region may be referred to as a first doped region; the first doped region and the second doped region are different doped regions, for example, the first doped region may be a doped region of a first conductivity type and the second doped region may be a doped region of a second conductivity type; or the first doped region may be a doped region of a second conductivity type and the second doped region may be a doped region of a first conductivity type.

[0058] Spatial relation terms such as "below" or "above" are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that spatial relation terms include not only the orientation shown in the figure, but also different orientations of the device in use and operation. For example, if the device in the figure is flipped, the description "below other elements" would be oriented "above" other elements or features. Therefore, the exemplary term "above" can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0059] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0060] Embodiments of the invention are described herein with reference to cross-sectional views illustrating preferred embodiments (and intermediate structures) of this application, thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Consequently, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of this application.

[0061] In order to maintain the high integration of semiconductor memory devices, the current mainstream DRAM process uses buried word lines for memory cell transistors, which can reduce the short-channel effect to a certain extent and thus reduce device leakage.

[0062] In DRAM buried word line technology, such as Figure 1 As shown, typically, dry etching is first used to form an island-like structure within the substrate 1'; then, dry etching is used to form buried word line trenches; subsequently, a thermal oxidation process is performed to form a gate oxide layer 132', followed by the deposition of metal 133' and a filling dielectric layer 134' from bottom to top to form the word line structure, as shown. Figure 2 As shown.

[0063] However, as memory cell size shrinks, the size of embedded word line trenches also shrinks, which in turn reduces the cross-sectional area of ​​the metal filling the embedded word line trenches; this leads to increased word line resistance, resulting in more power consumption and exacerbating RC delay.

[0064] In view of the shortcomings of the prior art, this application provides a method for preparing a semiconductor structure according to some embodiments.

[0065] Please refer to Figure 3 In one embodiment, the preparation method may include the following steps:

[0066] S1: Provide substrate.

[0067] S2: Perform a first ion implantation process on the substrate to form a first ion implantation region within the substrate; the first ion implantation region extends from the upper surface of the substrate into the interior of the substrate.

[0068] S3: Etch the substrate to form word line trenches.

[0069] In step S3, the word line trench formed should penetrate the first ion implantation region and extend below it. Specifically, the word line trench may include a first portion and a second portion integrally connected to the first portion; the first portion is located within the first ion implantation region, and the second portion is located below the first ion implantation region. During the etching process of the substrate to form the word line trench, the etching rate of the second portion is greater than the etching rate of the first portion, so that the width of the second portion is greater than the width of the first portion.

[0070] The semiconductor structure fabrication method in the above embodiments, by forming a first ion implantation region in the substrate, enables the etching rate of the second part to be greater than the etching rate of the first part during the etching process of forming word line trenches on the substrate, thereby forming a word line trench with a width greater than that of the first part. In this way, the bottom of the formed word line trench is wider, which can increase the cross-sectional area of ​​the bottom of the word line trench and reduce the word line resistance formed in subsequent processes. Therefore, it can reduce device power consumption and reduce RC delay.

[0071] The following is combined Figures 4 to 9 The method for fabricating the semiconductor structure involved in this application will be described in more detail.

[0072] For step S1, as follows Figure 4 As shown, substrate 1 is provided.

[0073] The method for fabricating the semiconductor structure provided in this application does not specifically limit the material of the substrate 1. As an example, the substrate 1 may be any one or more of the following: silicon substrate, sapphire substrate, glass substrate, silicon carbide substrate, gallium nitride substrate, or gallium arsenide substrate; that is, the material of the substrate 1 may be any one or more of the following: silicon, sapphire, glass, silicon carbide, gallium nitride, or gallium arsenide.

[0074] In some possible embodiments, prior to step S1, the fabrication method may further include etching the initial substrate to form, as shown in the figure. Figure 4 The steps for creating the island-like structure are shown. This application does not specifically limit the method of etching the initial substrate; as an example, the initial substrate can be etched using, but is not limited to, dry etching.

[0075] For step S2, please refer to Figure 5 A first ion implantation process is performed on substrate 1 to form a first ion implantation region 141 within substrate 1.

[0076] Specifically, the first ion implantation region 141 extends from the upper surface of the substrate 1 into the interior of the substrate 1.

[0077] The method for fabricating the semiconductor structure provided in this application does not limit the depth of the first ion implantation region 141. As an example, the depth of the first ion implantation region 141 can be 100nm to 150nm; for example, the depth of the first ion implantation region 141 can be 100nm, 110nm, 120nm, 130nm, 140nm or 150nm, etc.

[0078] In one embodiment, the first ion implantation region 141 formed in step S2 has a depth of 130 nm.

[0079] The semiconductor structure fabrication method provided in this application does not limit the ion concentration of the first ion implantation region 141. As an example, the ion concentration of the first ion implantation region 141 can be 1 × 10⁻⁶. 19 cm 3 ~1×10 21 cm 3 For example, the ion concentration in the first ion implantation region 141 can be 1 × 10⁻⁶. 19 cm 3 1×10 20 cm 3 Or 1×10 21 cm 3 etc.

[0080] This preparation method can form a second ion implantation region before forming the first ion implantation region. Please continue reading. Figure 5 In one embodiment, the step of forming the second ion implantation region may specifically include: performing a second ion implantation process on the substrate 1 to form a second ion implantation region 142 in the substrate 1.

[0081] Specifically, the second ion implantation region 142 should be located below the first ion implantation region 141.

[0082] As an example, an intrinsic region may be present below the first ion implantation region 141. Please refer to [further details]. Figure 5 ,Right now Figure 5 The second ion implantation region 142 in the text can be replaced with an intrinsic region.

[0083] As an example, in the preparation method provided in this application, the first ion implantation region 141 and the second ion implantation region 142 can both be P-type; in this case, the ion concentration of the second ion implantation region 142 should be less than the ion concentration of the first ion implantation region 141.

[0084] During the etching process, holes trap electrons, thus inhibiting the etching process. The semiconductor structure fabrication method in the above embodiments utilizes the characteristic that regions with different hole concentrations have different etching rates to form a wider word line trench at the bottom. Since the ion concentration of the second ion implantation region 142 is lower than that of the first ion implantation region 141, and the first ion implantation region 141 has more holes than the second ion implantation region 142, these holes trap electrons generated during the etching reaction, inhibiting the etching process and reducing the etching rate. Therefore, the etching rate of the second ion implantation region 142 is greater than that of the first ion implantation region 141, resulting in a wider word line trench being formed in the second ion implantation region 142.

[0085] In the semiconductor structure fabrication method described in the above embodiments, there is no specific limitation on the ion concentration of the second ion implantation region 142. The ion concentration of the second ion implantation region 142 can be selected according to actual needs, as long as the ion concentration of the second ion implantation region 142 is less than the ion concentration of the first ion implantation region 141.

[0086] Based on the above embodiments, as an example, in the preparation method provided in this application, the implanted ions in the first ion implantation region 141 may include, but are not limited to, boron (B) ions. As an example, the implanted ions in the second ion implantation region 142 may include, but are not limited to, boron ions.

[0087] As an example, the step of performing a first ion implantation process on substrate 1 to form a first ion implantation region 141 in substrate 1 can be performed in the following manner, for example: using boron ions (B+) generated by the ionization of boron trifluoride (BF3) as an ion source, and through multiple ion implantation processes with different energies, a high concentration of boron element is doped into a region of 100nm to 150nm from the upper surface of substrate 1 in substrate 1 to form a P-type first ion implantation region 141.

[0088] As an example, in the preparation method provided in this application, the second ion implantation region 142 can also be N-type; in this case, the first ion implantation region 141 should be P-type.

[0089] In the above embodiment, since the second ion implantation region 142 is N-type, which is a region where the electron concentration is much greater than the hole concentration, it can have a greater etching rate than the P-type first ion implantation region 141. Thus, the etching rate of the second ion implantation region 142 is greater than that of the first ion implantation region 141, thereby enabling the formation of a wider word line trench in the second ion implantation region 142.

[0090] Based on the above embodiments, as an example, in the preparation method provided in this application, the implanted ions in the first ion implantation region 141 may include, but are not limited to, boron ions, and the implanted ions in the second ion implantation region 142 may include, but are not limited to, phosphorus (P) ions.

[0091] For step S3, please refer to Figure 6 The substrate 1 is etched to form word line trenches 13.

[0092] This application does not specifically limit the method of etching the substrate 1 to form the word line trench 13 in step S3. As an example, the word line trench 13 can be formed in the substrate 1 by, but is not limited to, dry etching.

[0093] As an example, the step of forming word line trenches 13 in a silicon substrate can be performed as follows: For instance, dry etching of the silicon substrate is performed using carbon tetrafluoride (CF4) as the etching gas. The carbon tetrafluoride dissociates into trifluoromethyl (CF3) and fluorine (F) neutral groups in capacitively coupled plasma (CCP) or inductively coupled plasma (ICP). These fluorine neutral groups have high reactivity due to their electron unsaturation, and therefore react very readily with the silicon substrate to form volatile silicon tetrafluoride (SiF4), ultimately forming the word line trenches 13.

[0094] Please combine Figures 7 to 9 Continue reading Figure 3 In one embodiment, after forming the word line trench 13, the method for fabricating the semiconductor structure may further include the following steps:

[0095] S4: Perform a third ion implantation process on substrate 1 to eliminate the first ion implantation region 141 and form a first doped region 143 of the first conductivity type in substrate 1; perform a fourth ion implantation process on substrate 1 to eliminate the second ion implantation region 142 and form a second doped region 144 of the second conductivity type in substrate 1.

[0096] like Figure 7 As shown, the first doped region 143 extends from the upper surface of the substrate 1 into the interior of the substrate 1; the second doped region 144 extends downward from the lower surface of the first doped region 143 into the interior of the substrate 1. Based on this, the word line trench 13 should penetrate the first doped region 143 and extend into the second doped region 144.

[0097] S5: As Figure 8 As shown, a gate oxide layer 132 is formed on the sidewall and bottom of the character line groove 13.

[0098] S6: As Figure 9 As shown, a word line conductive layer 133 is formed on the surface of the gate oxide layer 132.

[0099] Specifically, the top of the word line conductive layer 133 should be lower than the top of the word line trench 13.

[0100] This application does not specifically limit the method of forming the gate oxide layer 132. As an example, the gate oxide layer 132 can be formed on the sidewalls and bottom of the word line trench 13 by any of the following methods, including but not limited to free radical oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), flowable chemical vapor deposition (FCVD), high density plasma deposition (HDP), plasma-enhanced deposition, or atomic layer deposition.

[0101] Furthermore, this application does not specifically limit the material of the gate oxide layer 132. As an example, the gate oxide layer 132 may be any one or more of silicon dioxide, high-k dielectric material, or other dielectric material layers, etc.; that is, the material of the gate oxide layer 132 may be any one or more of silicon dioxide, high-k dielectric material, or other dielectric material, etc.

[0102] As an example, the gate oxide layer 132 can be formed using a free radical oxidation process at 850℃ to 1050℃; for instance, the gate oxide layer 132 can be formed using free radical oxidation processes at 850℃, 900℃, 950℃, 1000℃, or 1050℃, etc. Oxygen-neutral free radicals (O*) or hydroxyl-neutral free radicals (OH*) are intermediate products in the reaction of hydrogen (H2) and oxygen (O2) to produce water. Due to their unsaturated outer electrons, they possess stronger chemical reactivity. Free radicals can break weaker chemical bonds and then form stronger chemical bonds, thus enabling the acquisition of a higher quality gate oxide layer 132.

[0103] As an example, during the formation of the gate oxide layer 132 using a free radical oxidation process, the reaction pressure can be controlled below 20 Torr; for instance, during the formation of the gate oxide layer 132 using a free radical oxidation process, the reaction pressure can be controlled to 18 Torr, 16 Torr, 14 Torr, 12 Torr, or 10 Torr, etc. Lower pressure allows for a longer mean free path of gas molecules. In this way, a longer free radical lifetime can be obtained.

[0104] This application does not specifically limit the method of forming the word line conductive layer 133. As an example, the word line conductive layer 133 can be formed on the surface of the gate oxide layer 132 by any one or more of the following processes, including but not limited to chemical vapor deposition, fluid chemical vapor deposition, high-density plasma deposition, plasma-enhanced deposition, or atomic layer deposition.

[0105] As an example, the step of forming a word line conductive layer 133 on the surface of the gate oxide layer 132 can be performed in the following manner, such as: forming a word line conductive material layer on the surface of the gate oxide layer 132; etching back a portion of the word line conductive material layer to form the word line conductive layer 133.

[0106] Furthermore, this application does not specifically limit the material of the word line conductive layer 133. As an example, the word line conductive layer 133 may be any one or more of titanium nitride (TiN) layer, titanium (Ti) layer, tungsten silicide (Si2W) layer, or tungsten (W) layer; that is, the material of the word line conductive layer 133 may be any one or more of titanium nitride, titanium, tungsten silicide, or tungsten.

[0107] As an example, the step of forming the word line conductive layer 133 on the surface of the gate oxide layer 132 can also be performed in the following manner, such as: depositing tungsten metal as a word line conductive material layer using a chemical vapor deposition process with good step coverage, wherein the reaction gas in this process can include, but is not limited to, silane (SiH4) and tungsten hexafluoride (WF6); and then etching back the word line conductive material layer using a dry etching method, wherein the etching gas in this process can be, but is not limited to, sulfur hexafluoride.

[0108] This application does not specifically limit the ion concentration in the first doped region 143 or the ion concentration in the second doped region 144. As an example, the ion concentration in the first doped region 143 can be 1 × 10⁻⁶. 16 cm 3 ~1×10 20 cm 3 For example, the ion concentration in the first doped region 143 can be 1×10⁻⁶. 16 cm 3 1×10 17 cm 3 1×10 18 cm 3 1×10 19 cm 3 Or 1×10 20 cm 3 And so on. As an example, the ion concentration within the second doped region 144 can be 1 × 10⁻⁶. 15 cm3 ~1×10 19 cm 3 For example, the ion concentration in the second doped region 144 can be 1×10⁻⁶. 15 cm 3 1×10 16 cm 3 1×10 17 cm 3 1×10 18 cm 3 Or 1×10 19 cm 3 etc.

[0109] In this application, the first conductivity type can be N-type; in this case, the second conductivity type should be P-type.

[0110] As an example, the step of forming the first N-type doped region 143 can be carried out in the following manner, for example: using boron ions generated by the ionization of boron trifluoride as an ion source, and forming the first N-type doped region 143 doped with boron ions by an ion implantation process.

[0111] As an example, the step of forming the second doped region 144 of the P type can be carried out in the following manner, for example: using phosphorus ions (P+) generated by phosphorus vapor ionization as the ion source, the second doped region 144 of the P type doped with phosphorus ions is formed above the first doped region 143 of the N type by an ion implantation process.

[0112] Please combine Figure 9 Continue reading Figure 3 In one embodiment, after forming a word line conductive layer 133 on the surface of the gate oxide layer 132, the method for fabricating the semiconductor structure may further include the following steps:

[0113] S7: A filling medium layer 134 is formed within the character line groove 13.

[0114] Specifically, the filling dielectric layer 134 is located on top of the word line conductive layer 133 and should at least completely fill the word line trench 13.

[0115] This application does not specifically limit the form in which the filling dielectric layer 134 is formed. As an example, the filling dielectric layer 134 can be formed in the word line trench 13 by, but is not limited to, chemical vapor deposition (CVD) or any of the CVD processes.

[0116] This application does not specifically limit the material of the filling dielectric layer 134. As an example, the filling dielectric layer 134 may include, but is not limited to, one or more of silicon dioxide, silicon nitride (Si3N4), or silicon oxynitride (SiON); that is, the material of the filling dielectric layer 134 may include, but is not limited to, one or more of silicon dioxide, silicon nitride, or silicon oxynitride.

[0117] As an example, the step of forming a filling dielectric layer 134 in the word line groove 13 can be performed in the following manner, for example: using chemical vapor deposition, hexachlorosilane (Si2Cl6, abbreviated as HCD) or dichlorosilane (SiH2Cl2, abbreviated as DCS) reacts with ammonia (NH3) to form silicon nitride as a filling dielectric material layer; and then chemical mechanical polishing (CMP) is performed to form the filling dielectric layer 134.

[0118] It should be understood that, although Figure 3 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 3 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0119] On the other hand, this application also provides a semiconductor structure according to some embodiments.

[0120] Please continue reading. Figure 6 In one embodiment, the semiconductor structure may include a substrate 1 and word line trenches 13.

[0121] The substrate 1 includes a first ion implantation region 141, which extends from the upper surface of the substrate 1 into the interior of the substrate 1. A word line trench 13 penetrates the first ion implantation region 141 and extends below it.

[0122] Specifically, the word line groove 13 may include a first portion 135 and a second portion 136 integrally connected to the first portion 135. The first portion 135 is located within the first ion implantation region 141, the second portion 136 is located below the first ion implantation region 141, and the width of the second portion 136 is greater than the width of the first portion 135.

[0123] The semiconductor structure in the above embodiment has a word line trench 13 with a large bottom cross-sectional area, which can reduce the resistance of the word lines formed in subsequent processes and avoid increased device power consumption and deterioration of RC delay.

[0124] The semiconductor structure provided in this application does not specifically limit the material of the substrate 1. As an example, the substrate 1 may be any one or more of the following: silicon substrate, sapphire substrate, glass substrate, silicon carbide substrate, gallium nitride substrate, or gallium arsenide substrate; that is, the material of the substrate 1 may be any one or more of the following: silicon, sapphire, glass, silicon carbide, gallium nitride, or gallium arsenide.

[0125] The semiconductor structure provided in this application does not limit the depth of the first ion implantation region 141. As an example, the depth of the first ion implantation region 141 can be 100nm to 150nm; for example, the depth of the first ion implantation region 141 can be 100nm, 110nm, 120nm, 130nm, 140nm or 150nm, etc.

[0126] In one embodiment, the depth of the first ion implantation region 141 is 130 nm.

[0127] The semiconductor structure provided in this application does not limit the ion concentration of the first ion implantation region 141. As an example, the ion concentration of the first ion implantation region 141 can be 1 × 10⁻⁶. 19 cm 3 ~1×10 21 cm 3 For example, the ion concentration in the first ion implantation region 141 can be 1 × 10⁻⁶. 19 cm 3 1×10 20 cm 3 Or 1×10 21 cm 3 etc.

[0128] In one embodiment, a second ion implantation region 142 may also be provided within the substrate 1. Please continue reading. Figure 6 The second ion implantation region 142 is located below the first ion implantation region 141.

[0129] As an example, in the semiconductor structure provided in this application, the first ion implantation region 141 and the second ion implantation region 142 can both be P-type; based on this, the ion concentration of the second ion implantation region 142 should be less than the ion concentration of the first ion implantation region 141.

[0130] In the semiconductor structure described above, there is no specific limitation on the ion concentration of the second ion implantation region 142. The ion concentration of the second ion implantation region 142 can be selected according to actual needs, as long as the ion concentration of the second ion implantation region 142 is less than the ion concentration of the first ion implantation region 141.

[0131] The semiconductor structure in the above embodiments can utilize the characteristic that regions with different hole concentrations have different etching rates in subsequent processes to form word line trenches with a wider bottom. Since the ion concentration of the second ion implantation region 142 is lower than that of the first ion implantation region 141, and the first ion implantation region 141 has more holes than the second ion implantation region 142, it captures electrons generated during the etching reaction, inhibiting etching and reducing the etching rate. Thus, the etching rate of the second ion implantation region 142 is greater than that of the first ion implantation region 141, allowing the second ion implantation region 142 to form a wider word line trench in subsequent processes.

[0132] Based on the above embodiments, as an example, in the semiconductor structure provided in this application, the implanted ions in the first ion implantation region 141 may include, but are not limited to, boron ions. As an example, in the semiconductor structure provided in this application, the implanted ions in the second ion implantation region 142 may include, but are not limited to, boron ions.

[0133] As an example, in the semiconductor structure provided in this application, the second ion implantation region 142 can also be N-type; in this case, the first ion implantation region 141 should be P-type.

[0134] Based on the above embodiments, as an example, in the semiconductor structure provided in this application, the implanted ions in the first ion implantation region 141 may include, but are not limited to, boron ions, and the implanted ions in the second ion implantation region 142 may include, but are not limited to, phosphorus ions.

[0135] It should be noted that the methods for preparing the semiconductor structures in the embodiments of this application can all be used to prepare the corresponding semiconductor structures. Therefore, the technical features between the method embodiments and the structure embodiments can be substituted and supplemented for each other without conflict, so that those skilled in the art can understand the technical content of this application.

[0136] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0137] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A first ion implantation process is performed on the substrate to form a first ion implantation region within the substrate; The first ion implantation region extends from the upper surface of the substrate into the interior of the substrate; The substrate is etched to form word line trenches; The word line groove penetrates the first ion implantation region and extends below the first ion implantation region; The word line groove includes a first part and a second part integrally connected to the first part. The first part is located within the first ion implantation region, and the second part is located below the first ion implantation region. During the etching process of the substrate to form word line trenches, the etching rate of the second portion is greater than the etching rate of the first portion, so that the width of the second portion is greater than the width of the first portion.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, Before forming the first ion implantation region, the method for fabricating the semiconductor structure further includes: A second ion implantation process is performed on the substrate to form a second ion implantation region within the substrate; the second ion implantation region is located below the first ion implantation region; Both the second ion implantation region and the first ion implantation region are P-type, and the ion concentration in the second ion implantation region is lower than the ion concentration in the first ion implantation region.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, Both the implanted ions in the first ion implantation region and the implanted ions in the second ion implantation region include boron ions.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first ion implantation region is P-type; Before forming the first ion implantation region, the method for fabricating the semiconductor structure further includes: A second ion implantation process is performed on the substrate to form a second ion implantation region within the substrate; The second ion implantation region is located below the first ion implantation region; The second ion implantation region is N-type.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The implanted ions in the first ion implantation region include boron ions; the implanted ions in the second ion implantation region include phosphorus ions.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 5, characterized in that, The word line trenches are formed in the substrate using dry etching.

7. The method for preparing a semiconductor structure according to claim 2, characterized in that, After forming the word line trench, the method for fabricating the semiconductor structure further includes: A third ion implantation process is performed on the substrate to eliminate the first ion implantation region and form a first doped region of a first conductivity type within the substrate; the first doped region extends from the upper surface of the substrate into the substrate; a fourth ion implantation process is performed on the substrate to eliminate the second ion implantation region and form a second doped region of a second conductivity type within the substrate; the second doped region extends downward from the lower surface of the first doped region into the substrate; the word line trench penetrates the first doped region and extends into the second doped region; A gate oxide layer is formed on the sidewalls and bottom of the word line groove; A word line conductive layer is formed on the surface of the gate oxide layer; the top of the word line conductive layer is lower than the top of the word line trench.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The first conductivity type is N-type; the second conductivity type is P-type.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, After forming a word line conductive layer on the surface of the gate oxide layer, the method for fabricating the semiconductor structure further includes: A filling dielectric layer is formed within the word line trench; the filling dielectric layer is located on top of the word line conductive layer and at least fills the word line trench.

10. A semiconductor structure, formed using the method for fabricating a semiconductor structure as described in any one of claims 1-9, characterized in that, include: Substrate; the substrate has a first ion implantation region; The first ion implantation region extends from the upper surface of the substrate into the interior of the substrate; Character line groove; The word line groove penetrates the first ion implantation region and extends below the first ion implantation region; The word line groove includes a first part and a second part integrally connected to the first part. The first part is located within the first ion implantation region, and the second part is located below the first ion implantation region, with the width of the second part being greater than the width of the first part.

11. The semiconductor structure according to claim 10, characterized in that, The substrate also includes a second ion implantation region, located below the first ion implantation region; Both the second ion implantation region and the first ion implantation region are P-type, and the ion concentration in the second ion implantation region is lower than the ion concentration in the first ion implantation region.

12. The semiconductor structure according to claim 11, characterized in that, Both the implanted ions in the first ion implantation region and the implanted ions in the second ion implantation region include boron ions.

13. The semiconductor structure according to claim 10, characterized in that, The first ion implantation region is P-type; The substrate also includes a second ion implantation region, located below the first ion implantation region; The second ion implantation region is N-type.

14. The semiconductor structure according to claim 13, characterized in that, The implanted ions in the first ion implantation region include boron ions; the implanted ions in the second ion implantation region include phosphorus ions.

15. The semiconductor structure according to any one of claims 10 to 14, characterized in that, The depth of the first ion implantation region is 100nm~150nm; The ion concentration in the first ion implantation region is 1×10⁻⁶. 19 cm 3 ~1×10 21 cm 3 .

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